S1D13701F00A100 - EPCOS

MF1213-02

S1D13705F00A Technical Manual

Technical Manual

S1D13705F00A

Technical Manual

Embedded Memory LCD Controller

S1D13705F00A

EPSON Electronic Devices Website

ELECTRONIC DEVICES MARKETING DIVISION

http://www.epson.co.jp/device/

First issue August, 1999 D

Printed July, 2001 in Japan C B

This manual was made with recycle papaer,

and printed using soy-based inks.

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written

permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material

or due to its application or use in any product or circuit and, further, there is no representation that this material

is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any

intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that

anything made in accordance with this material will be free from any patent or copyright infringement of a third

party. This material or portions thereof may contain technology or the subject relating to strategic products under

the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from

the Ministry of International Trade and Industry or other approval from another government agency.

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PC-DOS, PC/AT, VGA, EGA and IBM are registered trademarks of International Business Machines Corporation, U.S.A.

All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners.

Comparison table between new and previous number of Evaluation Boards

S5U 13705 P00C

Specification

Corresponding model number (13705: for S1D13705)

Product classification (S5U: development tool for semiconductor)

S1 D 13706 F 00A0 00

The information of the product number change

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales

representative.

Devices

Configuration of product number

Comparison table between new and previous number

Packing specification

Specification

Package (B: CSP, F: QFP)

Corresponding model number

Model name (D: driver, digital products)

Product classification (S1: semiconductor)

Evaluation Board

Previous No.

SED1335 Series

SED1335D0A

SED1335F0A

SED1335F0B

S1D13305 Series

S1D13305D00A

S1D13305F00A

S1D13305F00B

New No.

Previous No.

SED135x Series

SED1353D0A

SED1353F0A

SED1353F1A

SED1354F0A

SED1354F1A

SED1354F2A

SED1355F0A

SED1356F0A

S1D1350x Series

S1D13503D00A

S1D13503F00A

S1D13503F01A

S1D13504F00A

S1D13504F01A

S1D13504F02A

S1D13505F00A

S1D13506F00A

New No.

Previous No.

SED137x Series

SED1374F0A

SED1375F0A

SED1376B0A

SED1376F0A

SED1378 Series

S1D1370x Series

S1D13704F00A

S1D13705F00A

S1D13706B00A

S1D13706F00A

S1D13708 Series

New No.

Previous No.

SED13Ax Series

SED13A3F0A

SED13A3B0B

SED13A4B0B

S1D13A0x Series

S1D13A03F00A

S1D13A03B00B

S1D13A04B00B

New No.

Previous No.

SED138x Series

SED1386F0A S1D1380x Series

S1D13806F00A

New No.

• S1D1350x Series

• S1D13305 Series • S1D1370x Series

• S1D13A0x Series

• S1D1380x Series

• S1D1350x Series

• S1D1370x Series • S1D1380x Series

• S1D13A0x Series

Previous No.

SDU1353#0C

SDU1354#0C

SDU1355#0C

SDU1356#0C

S5U13503P00C

S5U13504P00C

S5U13505P00C

S5U13506P00C

New No. Previous No.

SDU1374#0C

SDU1375#0C

SDU1376#0C

SDU1376BVR

SDU1378#0C

S5U13704P00C

S5U13705P00C

S5U13706P00C

S5U1370632R

S5U13708P00C

New No. Previous No.

SDU1386#0C S5U13806P00C

New No.

Previous No.

SDU13A3#0C

SDU13A4#0C S5U13A03P00C

S5U13A04P00C

New No.

S1D13705F00A Technical Manual

HARDWARE FUNCTIONAL SPECIFICATION

PROGRAMMING NOTES AND EXAMPLES

UTILITIES

S5U13705B00C ISA BUS EVALUATION

BOARD USER’S MANUAL

APPLICATION NOTES

WINDOWS

CE DISPLAY DRIVERS

Tobira.fm Page 1 Tuesday, July 24, 2001 10:52 PM

S1D13705F00A

Embedded Memory LCD Controller

Hardware Functional

Specification

 
CONTENTS
 
S1D13705F00A HARDWARE FUNCTIONAL 
 
EPSON
 
1-i
 
SPECIFICATION
 
CONTENTS
1I
 
NTRODUCTION
 
.........................................................................................................................1-1
 
1.1 Scope ............................................................................................................................................1-1
1.2 Overview Description ....................................................................................................................1-1
 
2F
 
EATURES
 
...............................................................................................................................1-2
 
2.1 Integrated Frame Buffer ................................................................................................................1-2
2.2 CPU Interface................................................................................................................................1-2
2.3 Display Support.............................................................................................................................1-2
2.4 Display Modes...............................................................................................................................1-2
2.5 Clock Source.................................................................................................................................1-3
2.6 Miscellaneous................................................................................................................................1-3
2.7 Package ........................................................................................................................................1-3
 
3T
 
YPICAL
 
 S
 
YSTEM
 
 I
 
MPLEMENTATION
 
 D
 
IAGRAMS
 
...........................................................................1-4
4F
 
UNCTIONAL
 
 B
 
LOCK
 
 D
 
IAGRAM
 
..................................................................................................1-7
 
4.1 Functional Block Descriptions .......................................................................................................1-7
4.1.1 Host Interface................................................................................................................1-7
4.1.2 Memory Controller ........................................................................................................1-7
4.1.3 Sequence Controller .....................................................................................................1-7
4.1.4 Look-Up Table ..............................................................................................................1-7
4.1.5 LCD Interface................................................................................................................1-8
4.1.6 Power Save...................................................................................................................1-8
 
5P
 
INS
 
.......................................................................................................................................1-9
 
5.1 Pinout Diagram..............................................................................................................................1-9
5.2 Pin Description ............................................................................................................................1-10
5.2.1 Host Interface..............................................................................................................1-10
5.2.2 LCD Interface..............................................................................................................1-12
5.2.3 Clock Input..................................................................................................................1-12
5.2.4 Miscellaneous ............................................................................................................1-12
5.2.5 Power Supply..............................................................................................................1-12
5.3 Summary of Configuration Options .............................................................................................1-13
5.4 Host Bus Interface Pin Mapping..................................................................................................1-13
5.5 LCD Interface Pin Mapping .........................................................................................................1-14
 
6 D.C. C
 
HARACTERISTICS
 
.........................................................................................................1-15
7 A.C. C
 
HARACTERISTICS
 
.........................................................................................................1-17
 
7.1 Bus Interface Timing ...................................................................................................................1-17
7.1.1 SH-4 Interface Timing.................................................................................................1-17
7.1.2 SH-3 Interface Timing.................................................................................................1-19
7.1.3 Motorola MC68K #1 Interface Timing .........................................................................1-20
7.1.4 Motorola MC68K #2 Interface Timing .........................................................................1-21
7.1.5 Generic #1 Interface Timing........................................................................................1-22
7.1.6 Generic #2 Interface Timing........................................................................................1-23
7.2 Clock Input Requirements...........................................................................................................1-24
7.3 Display Interface..........................................................................................................................1-25
7.3.1 Power On/Reset Timing..............................................................................................1-25
7.3.2 Power Down/Up Timing ..............................................................................................1-26
7.3.3 4-Bit Single Monochrome Panel Timing......................................................................1-27
7.3.4 8-Bit Single Monochrome Panel Timing......................................................................1-29
7.3.5 4-Bit Single Color Panel Timing..................................................................................1-31
7.3.6 8-Bit Single Color Panel Timing (Format 1) ................................................................1-33
7.3.7 8-Bit Single Color Panel Timing (Format 2) ................................................................1-35
7.3.8 8-Bit Dual Monochrome Panel Timing ........................................................................1-37
7.3.9 8-Bit Dual Color Panel Timing.....................................................................................1-39
7.3.10 12-Bit TFT/D-TFD Panel Timing .................................................................................1-41

 
CONTENTS
 
1-ii
 
EPSON
 
S1D13705F00A HARDWARE FUNCTIONAL
SPECIFICATION 
 
8R
 
EGISTERS
 
............................................................................................................................1-44
 
8.1 Register Mapping........................................................................................................................1-44
8.2 Register Descriptions..................................................................................................................1-44
 
9F
 
RAME
 
 R
 
ATE
 
 C
 
ALCULATION
 
....................................................................................................1-56
10 D
 
ISPLAY
 
 D
 
ATA
 
 F
 
ORMATS
 
........................................................................................................1-57
11 L
 
OOK
 
-U
 
P
 
 T
 
ABLE
 
 A
 
RCHITECTURE
 
.............................................................................................1-58
 
11.1 Monochrome Modes ...................................................................................................................1-58
11.1.1 1 Bit-per-pixel Monochrome Mode..............................................................................1-58
11.1.2 2 Bit-per-pixel Monochrome Mode..............................................................................1-58
11.1.3 4 Bit-per-pixel Monochrome Mode..............................................................................1-59
11.2 Color Modes................................................................................................................................1-60
11.2.1 1 Bit-per-pixel Color Mode..........................................................................................1-60
11.2.2 2 Bit-per-pixel Color Mode..........................................................................................1-61
11.2.3 4 Bit-per-pixel Color Mode..........................................................................................1-62
11.2.4 8 Bit-per-pixel Color Mode..........................................................................................1-63
 
12 S
 
WIVEL
 
V
 
IEW
 
 M
 
ODE
 
................................................................................................................1-64
 
12.1 Default SwivelView Mode............................................................................................................1-64
12.1.1 How to Set Up Default SwivelView Mode...................................................................1-65
12.2 Alternate SwivelView Mode.........................................................................................................1-66
12.2.1 How to Set Up Alternate SwivelView Mode................................................................1-67
12.3 Comparison Between Default and Alternate SwivelView Modes................................................1-68
12.4 SwivelView Mode Limitations......................................................................................................1-68
 
13 P
 
OWER
 
 S
 
AVE
 
 M
 
ODES
 
.............................................................................................................1-69
 
13.1 Software Power Save Mode........................................................................................................1-69
13.2 Hardware Power Save Mode......................................................................................................1-69
13.3 Power Save Mode Function Summary........................................................................................1-69
13.4 Panel Power Up/Down Sequence...............................................................................................1-70
13.5 Turning Off BCLK Between Accesses ........................................................................................1-70
13.6 Clock Requirements....................................................................................................................1-71
 
14 M
 
ECHANICAL
 
 D
 
ATA
 
................................................................................................................1-72

 
CONTENTS
 
S1D13705F00A HARDWARE FUNCTIONAL 
 
EPSON
 
1-iii
 
SPECIFICATION
 
List of Figures
 
Figure 3-1 Typical System Diagram (SH-4 Bus)....................................................................................1-4
Figure 3-2 Typical System Diagram (SH-3 Bus)....................................................................................1-4
Figure 3-3 Typical System Diagram (M68K #1 Bus) .............................................................................1-5
Figure 3-4 Typical System Diagram (M68K #2 Bus) .............................................................................1-5
Figure 3-5 Typical System Diagram (Generic #1 Bus)..........................................................................1-6
Figure 3-6 Typical System Diagram (Generic #2 Bus - e.g. ISA Bus)...................................................1-6
Figure 4-1 System Block Diagram Showing Data Paths .......................................................................1-7
Figure 5-1 Pinout Diagram.....................................................................................................................1-9
Figure 7-1 SH-4 Timing .......................................................................................................................1-17
Figure 7-2 SH-3 Bus Timing................................................................................................................1-19
Figure 7-3 MC68K #1 Bus Timing (MC68000) ....................................................................................1-20
Figure 7-4 MC68K #2 Timing (MC68030)............................................................................................1-21
Figure 7-5 Generic #1 Timing..............................................................................................................1-22
Figure 7-6 Generic #2 Timing..............................................................................................................1-23
Figure 7-7 Clock Input Requirements..................................................................................................1-24
Figure 7-8 LCD Panel Power On/Reset Timing...................................................................................1-25
Figure 7-9 Power Down/Up Timing......................................................................................................1-26
Figure 7-10 4-Bit Single Monochrome Panel Timing.............................................................................1-27
Figure 7-11 4-Bit Single Monochrome Panel A.C. Timing.....................................................................1-28
Figure 7-12 8-Bit Single Monochrome Panel Timing.............................................................................1-29
Figure 7-13 8-Bit Single Monochrome Panel A.C. Timing.....................................................................1-30
Figure 7-14 4-Bit Single Color Panel Timing .........................................................................................1-31
Figure 7-15 4-Bit Single Color Panel A.C. Timing .................................................................................1-32
Figure 7-16 8-Bit Single Color Panel Timing (Format 1)........................................................................1-33
Figure 7-17 8-Bit Single Color Panel A.C. Timing (Format 1)................................................................1-34
Figure 7-18 8-Bit Single Color Panel Timing (Format 2)........................................................................1-35
Figure 7-19 8-Bit Single Color Panel A.C. Timing (Format 2)................................................................1-36
Figure 7-20 8-Bit Dual Monochrome Panel Timing................................................................................1-37
Figure 7-21 8-Bit Dual Monochrome Panel A.C. Timing........................................................................1-38
Figure 7-22 8-Bit Dual Color Panel Timing............................................................................................1-39
Figure 7-23 8-Bit Dual Color Panel A.C. Timing....................................................................................1-40
Figure 7-24 12-Bit TFT/D-TFD Panel Timing.........................................................................................1-41
Figure 7-25 TFT/D-TFD A.C. Timing .....................................................................................................1-42
Figure 8-1 Screen-Register Relationship.............................................................................................1-52
Figure 10-1 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization...................................................1-57
Figure 11-1 1 Bit-per-pixel Monochrome Mode Data Output Path ........................................................1-58
Figure 11-2 2 Bit-per-pixel Monochrome Mode Data Output Path ........................................................1-58
Figure 11-3 4 Bit-per-pixel Monochrome Mode Data Output Path ........................................................1-59
Figure 11-4 1 Bit-per-pixel Color Mode Data Output Path.....................................................................1-60
Figure 11-5 2 Bit-per-pixel Color Mode Data Output Path.....................................................................1-61
Figure 11-6 4 Bit-per-pixel Color Mode Data Output Path.....................................................................1-62
Figure 11-7 8 Bit-per-pixel Color Mode Data Output Path.....................................................................1-63
Figure 12-1 Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Default 
Mode1-64
Figure 12-2 Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Alternate 
Mode1-66
Figure 13-1 Panel On/Off Sequence .....................................................................................................1-70
Figure 14-1 Mechanical Drawing QFP14...............................................................................................1-72

 
CONTENTS
 
1-iv
 
EPSON
 
S1D13705F00A HARDWARE FUNCTIONAL
SPECIFICATION 
 
List of Tables
 
Table 5-1 Host Interface Pin Descriptions..........................................................................................1-10
Table 5-2 LCD Interface Pin Descriptions..........................................................................................1-12
Table 5-3 Clock Input Pin Description................................................................................................1-12
Table 5-4 Miscellaneous Pin Descriptions .........................................................................................1-12
Table 5-5 Power Supply Pin Descriptions..........................................................................................1-12
Table 5-6 Summary of Power On/Reset Options...............................................................................1-13
Table 5-7 Host Bus Interface Pin Mapping ........................................................................................1-13
Table 5-8 LCD Interface Pin Mapping................................................................................................1-14
Table 6-1 Absolute Maximum Ratings ...............................................................................................1-15
Table 6-2 Recommended Operating Conditions for Core VDD = 3.3V ± 10%...................................1-15
Table 6-3 Input Specifications............................................................................................................1-15
Table 6-4 Output Specifications.........................................................................................................1-16
Table 7-1 SH-4 Timing.......................................................................................................................1-18
Table 7-2 SH-3 Bus Timing................................................................................................................1-19
Table 7-3 MC68K #1 Bus Timing (MC68000)....................................................................................1-20
Table 7-4 MC68K #2 Timing (MC68030) ...........................................................................................1-21
Table 7-5 Generic #1 Timing..............................................................................................................1-22
Table 7-6 Generic #2 Timing..............................................................................................................1-23
Table 7-7 Clock Input Requirements..................................................................................................1-24
Table 7-8 LCD Panel Power On/Reset Timing ..................................................................................1-25
Table 7-9 Power Down/Up Timing .....................................................................................................1-26
Table 7-10 4-Bit Single Monochrome Panel A.C. Timing.....................................................................1-28
Table 7-11 8-Bit Single Monochrome Panel A.C. Timing.....................................................................1-30
Table 7-12 4-Bit Single Color Panel A.C. Timing.................................................................................1-32
Table 7-13 8-Bit Single Color Panel A.C. Timing (Format 1) ...............................................................1-34
Table 7-14 8-Bit Single Color Panel A.C. Timing (Format 2) ...............................................................1-36
Table 7-15 8-Bit Dual Monochrome Panel A.C. Timing .......................................................................1-38
Table 7-16 8-Bit Dual Color Panel A.C. Timing....................................................................................1-40
Table 7-17 TFT/D-TFD A.C. Timing.....................................................................................................1-43
Table 8-1 Panel Data Format.............................................................................................................1-45
Table 8-2 Gray Scale/Color Mode Selection......................................................................................1-45
Table 8-3 High Performance Selection ..............................................................................................1-46
Table 8-4 Inverse Video Mode Select Options...................................................................................1-46
Table 8-5 Hardware Power Save/GPIO0 Operation ..........................................................................1-47
Table 8-6 Software Power Save Mode Selection...............................................................................1-47
Table 8-7 Selection of Portrait Mode..................................................................................................1-54
Table 8-8 Selection of PCLK and MCLK in Portrait Mode .................................................................1-54
Table 12-1 Default and Alternate SwivelView Mode Comparison........................................................1-68
Table 13-1 Power Save Mode Selection..............................................................................................1-69
Table 13-2 Software Power Save Mode Summary..............................................................................1-69
Table 13-3 Hardware Power Save Mode Summary.............................................................................1-69
Table 13-4 Power Save Mode Function Summary ..............................................................................1-69
Table 13-5 S1D13705 Internal Clock Requirements............................................................................1-71

1: INTRODUCTION

S1D13705F00A HARDWARE FUNCTIONAL

EPSON

1-1

SPECIFICATION (X27A-A-001-06)

NTRODUCTION

1.1 Scope

This is the Hardware Functional Speciﬁcation for the S1D13705 Embedded Memory LCD

Controller Chip. Included in this document are timing diagrams, AC and DC characteristics, re gister

descriptions, and power management descriptions. This document is intended for two audiences:

Video Subsystem Designers and Software Developers.

1.2 Overview Description

The S1D13705 is a color / monochrome LCD graphics controller with an embedded 80K byte

SRAM display buffer. The high integration of the S1D13705 provides a low cost, low power, single

chip solution to meet the requirements of embedded markets such as Ofﬁce Automation equipment,

Mobile Communications devices, and Hand-Held PCs where board size and battery life are major

concerns.

Products requiring a “Portrait” display can take adv antage of the Hardw are Portrait Mode feature of

the S1D13705. Virtual and Split Screen are just some of the display modes supported. The above

features, combined with the Operating System independence of the S1D13705, make it the ideal

solution for a wide variety of applications.

2: FEATURES

1-2

EPSON

S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

EATURES

2.1 Integrated Frame Buffer

• Embedded 80K byte SRAM display buffer.

2.2 CPU Interface

• Direct support of the following interfaces:

Hitachi SH-3.

Hitachi SH-4.

Motorola M68K.

MPU bus interface using WAIT# signal.

• Direct memory mapping of internal registers.

• Single level CPU write buffer.

• Registers are mapped into upper 32 bytes of 128K byte address space.

• The complete 80K byte display buffer is directly and contiguously available through the 17-bit

address bus.

2.3 Display Support

• 4/8-bit monochrome LCD interface.

• 4/8-bit color LCD interface.

• Single-panel, single-drive passive displays.

• Dual-panel, dual-drive passive displays.

• Active Matrix TFT / D-TFD interface

• Register level support for EL panels.

• Example resolutions:

640

480 at a color depth of 2 bpp

640

240 at a color depth of 4 bpp

320

240 at a color depth of 8 bpp

2.4 Display Modes

• SwivelView™: direct 90˚ hardware rotation of display image for portrait mode display

• 1/2/4 bit-per-pixel (bpp), 2/4/16-level grayscale display.

• 1/2/4/8 bit-per-pixel, 2/4/16/256-level color display.

• Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 256

4 Look-Up Table

is used to map 1/2/4 bpp modes into these shades.

• 256 simultaneous of 4096 colors on color passive and active matrix LCD panels; three 256

Look-Up Tables are used to map 1/2/4/8 bpp modes into these colors.

• Split screen display for all landscape panel modes allows two different images to be simulta-

neously displayed.

• Virtual display support (displays images larger than the panel size through the use of panning).

2: FEATURES

S1D13705F00A HARDWARE FUNCTIONAL

EPSON

1-3

SPECIFICATION (X27A-A-001-06)

2.5 Clock Source

• Maximum operating clock (CLK) frequency of 25MHz.

• Operating clock (CLK) is derived from CLKI input.

CLK = CLKI

CLK = CLKI/2

• Pixel Clock (PCLK) and Memory Clock (MCLK) are derived from CLK.

2.6 Miscellaneous

• Hardware/Software Video In vert.

• Software Power Save mode.

• Hardware Power Save mode.

• LCD power-down sequencing.

• 5 General Purpose Input/Output pins are available.

GPIO0 is available if Hardware Power Save is not required.

GPIO[4:1] are available if upper LCD data pins (FPDAT[11:8]) are not required for TFT/D-

TFD support or hardware inverse video.

• Core operates from 2.7 volts to 3.6 volts.

• IO Operates from the core voltage up to 5.5 volts.

2.7 Package

• 80 pin QFP14 package.

3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS

1-4

EPSON

S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

YPICAL

YSTEM

MPLEMENTATION

IAGRAMS

Figure 3-1 Typical System Diagram (SH-4 Bus)

Figure 3-2 Typical System Diagram (SH-3 Bus)

S1D13705 FPFRAME

FPSHIFT

FPLINE

DRDY

FPDAT[7:0]

CLKI

Oscillator

FPFRAME

FPSHIFT

FPLINE

MOD

D[7:0]

8-bit

LCD

Display

SH-4

BUS

RESET#

WE0#

D[15:0]

BS#

RD/WR#

RD#

RDY#

A[16:0]

CKIO

WE0#

RD/WR#

AB[16:0]

DB[15:0]

WE1#

BS#

RD#

CS#

BCLK

WAIT#

RESET#

CSn#

WE1#

LCDPWR

S1D13705 FPFRAME

FPSHIFT

FPLINE

DRDY

FPDAT[7:4]

CLKI

Oscillator

FPFRAME

FPSHIFT

FPLINE

MOD

D[3:0]

4-bit

LCD

Display

SH-3

BUS

RESET#

WE0#

D[15:0]

BS#

RD/WR#

RD#

WAIT#

A[16:0]

CKIO

WE0#

RD/WR#

AB[16:0]

DB[15:0]

WE1#

BS#

RD#

CS#

BCLK

WAIT#

RESET#

CSn#

WE1#

LCDPWR

3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS

S1D13705F00A HARDWARE FUNCTIONAL

EPSON

1-5

SPECIFICATION (X27A-A-001-06)

Figure 3-3 Typical System Diagram (M68K #1 Bus)

Figure 3-4 Typical System Diagram (M68K #2 Bus)

S1D13705 FPFRAME

FPSHIFT

FPLINE

DRDY

FPDAT[7:4]

CLKI

Oscillator

FPFRAME

FPSHIFT

FPLINE

MOD

D[3:0]

4-bit

LCD

Display

MC68000

BUS

RESET#

LDS#

D[15:0]

AS#

R/W#

DTACK#

A[16:1]

CLK

AB0

RD/WR#

AB[16:1]

DB[15:0]

WE1#

BS#

CS#

BCLK

WAIT#

RESET#

A[23:17]

FC0, FC1, FC2 Decoder

UDS#

LCDPWR

S1D13705 FPFRAME

FPSHIFT

FPLINE

DRDY

FPDAT[7:0]

CLKI

Oscillator

FPFRAME

FPSHIFT

FPLINE

MOD

D[7:0]

8-bit

LCD

Display

MC68030

BUS

RESET#

SIZ0

D[31:16]

AS#

R/W#

SIZ1

DSACK1#

A[16:0]

CLK

WE0#

RD/WR#

AB[16:0]

DB[15:0]

WE1#

BS#

RD#

CS#

BCLK

WAIT#

RESET#

A[31:17]

FC0, FC1, FC2 Decoder

DS#

LCDPWR

3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS

1-6 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 3-5 Typical System Diagram (Generic #1 Bus)

Figure 3-6 Typical System Diagram (Generic #2 Bus - e.g. ISA Bus)

S1D13705 FPFRAME

FPSHIFT

FPLINE

DRDY

FPDAT[11:0]

CLKI

Oscillator

FPFRAME

FPSHIFT

FPLINE

DRDY

D[11:0]

12-bit

TFT

Display

GENERIC #1

BUS

RESET#

D[15:0]

RD0#

WAIT#

A[16:0]

BCLK

RD/WR#

AB[16:0]

DB[15:0]

WE1#

CS#

BCLK

WAIT#

RESET#

CSn#

WE1#

LCDPWR

WE0#

BS#

RD1#

S1D13705 FPFRAME

FPSHIFT

FPLINE

DRDY

FPDAT[8:0]

CLKI

Oscillator

FPFRAME

FPSHIFT

FPLINE

DRDY

D[8:0]

9-bit

TFT

Display

ISA

BUS

RESET

SD[15:0]

SMEMR#

IOCHRDY

SA[16:0]

BCLK

AB[16:0]

DB[15:0]

WE1#

RD#

BCLK

WAIT#

RESET#

LCDPWR

WE0#

SMEMW#

BS#

Decoder CS#

SA[19:17]

REFRESH

SBHE#

4: FUNCTIONAL BLOCK DIAGRAM

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-7

SPECIFICATION (X27A-A-001-06)

4FUNCTIONAL BLOCK DIAGRAM

Figure 4-1 System Block Diagram Showing Data Paths

4.1 Functional Block Descriptions

4.1.1 Host Interface

The Host Interface provides the means for the CPU/MPU to communicate with the display buffer

and internal registers.

4.1.2 Memory Controller

The Memory Controller arbitrates between CPU accesses and display refresh accesses. It also

generates the necessary signals to control the SRAM frame buffer.

4.1.3 Sequence Controller

The Sequence Controller controls data ﬂo w from the Memory Controller through the Look-Up Table

and to the LCD Interface. It also generates memory addresses for display refresh accesses.

4.1.4 Look-Up Table

The Look-Up Table contains three 256 × 4 Look-Up Tables or palettes, one for each primary color.

In monochrome mode only the green Look-Up Table is used.

LCD

Memory

Controller

40k × 16-bit SRAM

LCD

Clocks

Power Save

Sequence Controller

Look-Up

I/F

Generic MPU

MC68K

SH-3 Host

I/F

Bus Clock Memory Clock Pixel Clock

Table

SH-4

4: FUNCTIONAL BLOCK DIAGRAM

1-8 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

4.1.5 LCD Interface

The LCD Interface performs frame rate modulation for passive LCD panels. It also generates the

correct data format and timing control signals for various LCD and TFT/D-TFD panels.

4.1.6 Power Save

Power Save contains the power save mode circuitry.

5: PINS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-9

SPECIFICATION (X27A-A-001-06)

5PINS

5.1 Pinout Diagram

Figure 5-1 Pinout Diagram

Note: Package type: 80 pin surface mount QFP14

1234567891011121314151617181920

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

S1D13705

IOVDD

DB6

DB5

DB4

DB3

DB2

DB0

DB1

COREVDD

DB8

DRDY

FPDAT7

COREVDD

GPIO0

AB3

VSS

AB4

AB5

AB6

AB11

AB14

FPDAT11

FPDAT10

FPDAT9

VSS

FPSHIFT

IOVDD

FPDAT5

FPDAT4

FPDAT3

FPDAT2

FPDAT1

FPDAT0

FPLINE

FPFRAME

VSS

CNF2

DB12

DB9

DB10

DB11

DB13

DB14

DB15

WAIT#

VSS

RD/WR#

WE1#

WE0#

RD#

BS#

CS#

RESET#

AB0

AB1

AB2

COREVDD

LCDPWR

AB9

AB10

VSS

AB8

VSS

FPDAT8

FPDAT6

TESTEN

CNF3

CNF1

CNF0

CLKI

IOVDD

AB15

AB12

BCLK

AB13

VSS

AB7

AB16

DB7

5: PINS

1-10 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

5.2 Pin Description

Key:

5.2.1 Host Interface

I = Input

O = Output

IO = Bi-Directional (Input/Output)

P = Power pin

C = CMOS level input

CS = CMOS level Schmitt input

COx = CMOS output driver , x denotes driver type (see IOL/IOH in Table 6-4: “Output Speciﬁcations,” on page 1-16)

TSx = Tri-state CMOS output driver, x denotes driver type (see IOL/IOH in Table 6-4: “Output Speciﬁcations,” on

page 1-16)

CNx = CMOS low-noise output driver, x denotes driver type (see IOL/IOH in Table 6-4: “Output Speciﬁcations,” on

page 1-16)

TEST = CMOS level test input with pull down resistor

Table 5-1 Host Interface Pin Descriptions

Pin Names Type Pin # Cell RESET#

State Description

AB0 I 70 CS Input

This pin has multiple functions.

• For SH-3/SH-4 mode, this pin inputs system address bit 0 (A0).

• For MC68K #1, this pin inputs the lower data strobe (LDS#).

• For MC68K #2, this pin inputs system address bit 0 (A0).

• For Generic #1, this pin inputs system address bit 0 (A0).

• For Generic #2, this pin inputs system address bit 0 (A0).

See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for

summary.

AB[16:1] I

45, 53, 54,

55, 56, 57,

58, 59, 62,

63, 64, 65,

66, 67, 68,

C Input

These pins input the system address bits 16 through 1 (A[16:1]).

DB[15:0] IO

3, 4, 5, 6, 7,

8, 9, 11, 12,

13, 14, 15,

16, 17, 18,

C/TS2 Hi-Z

These pins have multiple functions.

• For SH-3/SH-4 mode, these pins are connected to [D15:0].

• For MC68K #1, these pins are connected to D[15:0].

• For MC68K #2, these pins are connected to D[31:16] for a 32-bit

device (e.g. MC68030) or D[15:0] for a 16-bit device (e.g.

MC68340).

• For Generic #1, these pins are connected to D[15:0].

• For Generic #2, these pins are connected to D[15:0].

See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for

summary.

WE0# I 77 CS Input

This pin has multiple functions.

• For SH-3/SH-4 mode, this pin inputs the write enable signal for the

lower data byte (WE0#).

• For MC68K #1, this pin must be tied to IO VDD

• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).

• For Generic #1, this pin inputs the write enable signal for the lo wer

data byte (WE0#).

• For Generic #2, this pin inputs the write enable signal (WE#)

See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for

summary.

5: PINS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-11

SPECIFICATION (X27A-A-001-06)

WE1# I 78 CS Input

This pin has multiple functions.

• For SH-3/SH-4 mode, this pin inputs the write enable signal for the

upper data byte (WE1#).

• For MC68K #1, this pin inputs the upper data strobe (UDS#).

• For MC68K #2, this pin inputs the data strobe (DS#).

• For Generic #1, this pin inputs the write enable signal for the upper

data byte (WE1#).

• For Generic #2, this pin inputs the byte enable signal for the high

data byte (BHE#).

See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for

summary.

CS# I 74 C Input This pin inputs the chip select signal.

BCLK I 71 C Input This pin inputs the system bus clock.

BS# I 75 CS Input

This pin has multiple functions.

• For SH-3/SH-4 mode, this pin inputs the bus start signal (BS#).

• For MC68K #1, this pin inputs the address strobe (AS#).

• For MC68K #2, this pin inputs the address strobe (AS#).

• For Generic #1, this pin must be tied to VSS.

• For Generic #2, this pin must be tied to IO VDD.

See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for

summary.

RD/WR# I 79 CS Input

This pin has multiple functions.

• For SH-3/SH-4 mode, this pin inputs the RD/WR# signal. The

S1D13705 needs this signal for early decode of the bus cycle.

• For MC68K #1, this pin inputs the R/W# signal.

• For MC68K #2, this pin inputs the R/W# signal.

• For Generic #1, this pin inputs the read command for the upper

data byte (RD1#).

• For Generic #2, this pin must be tied to IO VDD.

See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for

summary.

RD# I 76 CS Input

This pin has multiple functions.

• For SH-3/SH-4 mode, this pin inputs the read signal (RD#).

• For MC68K #1, this pin must be tied to IO VDD.

• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).

• For Generic #1, this pin inputs the read command for the lower

data byte (RD0#).

• For Generic #2, this pin inputs the read command (RD#).

See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for

summary.

WAIT# O 2 TS2 Hi-Z

This pin has multiple functions.

• For SH-3 mode, this pin outputs the wait request signal (WAIT#).

• For SH-4 mode, this pin outputs the device ready signal (RDY#).

• For MC68K #1, this pin outputs the data transfer acknowledge sig-

nal (DTACK#).

• For MC68K #2, this pin outputs the data transfer and size ackno wl-

edge bit 1 (DSACK1#).

• For Generic #1, this pin outputs the wait signal (WAIT#).

• For Generic #2, this pin outputs the wait signal (WAIT#).

See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for

summary.

RESET# I 73 CS 0 Activ e lo w input to set all internal re gisters to the def ault state and to

force all signals to their inactive states.

Table 5-1 Host Interface Pin Descriptions

Pin Names Type Pin # Cell RESET#

State Description

5: PINS

1-12 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

5.2.2 LCD Interface

5.2.3 Clock Input

5.2.4 Miscellaneous

5.2.5 Power Supply

Table 5-2 LCD Interface Pin Descriptions

Pin Name Type Pin # Cell RESET#

State Description

FPDAT[7:0] O 30, 31, 32,

33, 34, 35,

36, 37 CN3 0 Panel Data

FPDAT[10:8] O,

IO 24, 25, 26 CN3 Input

These pins have multiple functions.

• Panel Data bits [10:8] for TFT/D-TFD panels.

• General Purpose Input/Output pins GPIO[3:1].

These pins should be connected to IO VDD when unused. See

Table 5-8, “LCD Interface Pin Mapping,” on page 1-14 for

summary.

FPDAT11 O,

IO 23 CN3 Input

This pin has multiple functions.

• Panel Data bit 11 for TFT/D-TFD panels.

• General Purpose Input/Output pin GPIO4.

• Inverse Video select pin.

This pin should be connected to IO VDD when unused. See

Table 5-8, “LCD Interface Pin Mapping,” on page 1-14 for

summary.

FPFRAME O 39 CN3 0 Frame Pulse

FPLINE O 38 CN3 0 Line Pulse

FPSHIFT O 28 CN3 0 Shift Clock

LCDPWR O 43 CO1 0 Active high LCD Power Control

DRDY O 42 CN3 0

This pin has multiple functions.

• TFT/D-TFD Display Enable (DRDY).

• LCD Backplane Bias (MOD).

• Second Shift Clock (FPSHIFT2).

See Table 5-8, “LCD Interface Pin Mapping,” on page 1-14 for

summary.

Table 5-3 Clock Input Pin Description

Pin Name Type Pin # Driver Description

CLKI I 51 C Input Clock

Table 5-4 Miscellaneous Pin Descriptions

Pin Name Type Pin # Cell RESET#

State Description

CNF[3:0] I 46, 47,

48, 49 CAs set by

hardware

These inputs are used to conﬁgure the S1D13705 - see Table 5-

6, “Summary of Power On/Reset Options,” on page 1-13.

Must be connected directly to IO VDD or VSS.

GPIO0 IO,

I22 CS/

TS1 Input This pin has multiple functions - see REG[03h] bit 2.

General Purpose Input/Output pin.

Hardware Power Save.

TESTEN I 44 TEST Pulled low Test Enable input. This input must be connected to VSS.

Table 5-5 Power Supply Pin Descriptions

Pin Name Type Pin # Driver Description

COREVDD P1, 21, 41,

61 PCore VDD

IOVDD P 10, 29, 52 P IO VDD

VSS P20, 27, 40,

50, 60, 72,

80 PCommon VSS

5: PINS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-13

SPECIFICATION (X27A-A-001-06)

5.3 Summary of Conﬁguration Options

5.4 Host Bus Interface Pin Mapping

Table 5-6 Summary of Power On/Reset Options

Conﬁguration

Pin Power On/Reset State

CNF3 Big Endian Little Endian

CNF[2:0] Select host bus interface as follows:

CNF2 CNF1 CNF0 BS# Host Bus

0 0 0 X SH-4 interface

0 0 1 X SH-3 interface

0 1 0 X reserved

0 1 1 X MC68K #1, 16-bit

1 0 0 X reserved

1 0 1 X MC68K #2, 16-bit

1100 reserved

1101 reserved

1110 Generic #1, 16-bit

1111 Generic #2, 16-bit

Table 5-7 Host Bus Interface Pin Mapping

S1D13705

Pin Names SH-3 SH-4 MC68K #1 MC68K #2 Generic #1 Generic #2

AB[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1]

AB0 A0 A0 LDS# A0 A0 A0

DB[15:0] D[15:0] D[15:0] D[15:0] D[31:16] D[15:0] D[15:0]

WE1# WE1# WE1# UDS# DS# WE1# BHE#

CS# CSn# CSn# External Decode External Decode External Decode External Decode

BCLK CKIO CKIO CLK CLK BCLK BCLK

BS# BS# BS# AS# AS# connect to VSS connect to IO VDD

RD/WR# RD/WR# RD/WR# R/W# R/W# RD1# connect to IO VDD

RD# RD# RD# connect to IO VDD SIZ1 RD0# RD#

WE0# WE0# WE0# connect to IO VDD SIZ0 WE0# WE#

WAIT# WAIT# RDY# DTACK# DSACK1# WAIT# WAIT#

RESET# RESET# RESET# RESET# RESET# RESET# RESET#

5: PINS

1-14 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

5.5 LCD Interface Pin Mapping

Note: 1.Unused GPIO pins must be connected to IO VDD.

2.Hardware Video Invert is enabled on FPDAT11 by REG[02h] bit 1.

Table 5-8 LCD Interface Pin Mapping

S1D13705

Pin Name

Monochrome Passive Panel Color Passive Panel Color TFT/D-TFD

4-bit Single 8-bit Single 8-bit Dual 4-bit Single 8-bit Single

Format 1 8-bit Single

Format 2 8-bit Dual 9-bit 12-bit

FPFRAME FPFRAME

FPLINE FPLINE

FPSHIFT FPSHIFT

DRDY MOD MOD MOD MOD FPSHIFT2 MOD MOD DRDY

FPDAT0 driven 0 D0 LD0 driven 0 D0 D0 LD0 R2 R3

FPDAT1 driven 0 D1 LD1 driven 0 D1 D1 LD1 R1 R2

FPDAT2 driven 0 D2 LD2 driven 0 D2 D2 LD2 R0 R1

FPDAT3 driven 0 D3 LD3 driven 0 D3 D3 LD3 G2 G3

FPDAT4 D0 D4 UD0 D0 D4 D4 UD0 G1 G2

FPDAT5 D1 D5 UD1 D1 D5 D5 UD1 G0 G1

FPDAT6 D2 D6 UD2 D2 D6 D6 UD2 B2 B3

FPDAT7 D3 D7 UD3 D3 D7 D7 UD3 B1 B2

FPDAT8 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 B0 B1

FPDAT9 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 R0

FPDAT10 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 G0

FPDAT11

GPIO4/

Hardware

Video

Invert

GPIO4/

Hardware

Video

Invert

GPIO4/

Hardware

Video

Invert

GPIO4/

Hardware

Video

Invert

GPIO4/

Hardware

Video

Invert

GPIO4/

Hardware

Video

Invert

GPIO4/

Hardware

Video

Invert

GPIO4 B0

6: D.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-15

SPECIFICATION (X27A-A-001-06)

6 D.C. CHARACTERISTICS

Table 6-1 Absolute Maximum Ratings

Symbol Parameter Rating Units

Core VDD Supply Voltage VSS - 0.3 to 4.0 V

IO VDD Supply Voltage Core VDD to 7.0 V

VIN Input Voltage VSS - 0.3 to IO VDD + 0.5 V

VOUT Output Voltage VSS - 0.3 to IO VDD + 0.5 V

TSTG Storage Temperature -65 to 150 °C

TSOL Solder Temperature/Time 260 for 10 sec. Max. at lead °C

Table 6-2 Recommended Operating Conditions for Core VDD = 3.3V ± 10%

Symbol Parameter Condition Min. Typ. Max. Units

Core VDD Supply Voltage VSS = 0 V 2.7 3.0/3.3 3.6 V

IO VDD Supply Voltage VSS = 0 V, IO VDD ≥ Core VDD 2.7 3.0/3.3/5.0 5.5 V

VIN Input Voltage VSS IO VDD V

TOPR Operating Temperature -40 25 85 °C

Table 6-3 Input Speciﬁcations

Symbol Parameter Condition Min. Typ. Max. Units

VIL Low Level Input Voltage

CMOS inputs

IO VDD = 3.0

3.3

5.0

0.8

1.0

VIH High Level Input Voltage

CMOS inputs

IO VDD = 3.0

3.3

5.0

1.9

2.0

3.5

VT+ Positiv e-going Threshold

CMOS Schmitt inputs

IO VDD = 3.0

3.3

5.0

1.0

1.1

2.0

2.3

2.4

4.0

VT- Negati v e-going Threshold

CMOS Schmitt inputs

IO VDD = 3.0

3.3

5.0

0.5

0.6

0.8

1.7

1.8

3.1

IIZ Input Leakage Current

VDD = Max.

VIH = VDD

VIL = VSS

-1 1 µA

CIN Input Pin Capacitance 10 pF

6: D.C. CHARACTERISTICS

1-16 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Table 6-4 Output Speciﬁcations

Symbol Parameter Condition Min. Typ. Max. Units

IOL(3.0V) Low Level Output Current

IO VDD = 3.0V

VO = 0.4V, Type = 1

1.8

IOL(3.3V) Low Level Output Current

IO VDD = 3.3V

VO = 0.4V, Type = 1

IOL(5.0V) Low Level Output Current

IO VDD = 5.0V

VO = 0.4V, Type = 1

IOH(3.0V) High Level Output Current

IO VDD = 3.0V

VO = IO VDD - 0.4V,Type =1

-1.8

-5

-10

IOH(3.3V) High Level Output Current

IO VDD = 3.3V

VO = IO VDD - 0.4V,Type =1

-2

-6

-12

IOH(5.0V) High Level Output Current

IO VDD = 5.0V

VO = IO VDD - 0.4V,Type =1

-3

-8

-12

VOL Low Level Output Voltage I = IOL 0.4 V

VOH High Level Output Voltage I = IOH IO VDD - 0.4 V

IOZ Output Leakage Current

VDD = Max.

VOH = VDD

VOL = VSS

-1 1 µA

COUT Output Pin Capacitance 10 pF

CBID Bidirectional Pin Capaci-

tance 10 pF

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-17

SPECIFICATION (X27A-A-001-06)

7 A.C. CHARACTERISTICS

Conditions: IO VDD = 2.7 V to 5.0 V

TA = -40°C to 85°C

Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%)

CL = 60pF (Bus/MPU Interface)

CL = 60pF (LCD Panel Interface)

7.1 Bus Interface Timing

7.1.1 SH-4 Interface Timing

Figure 7-1 SH-4 Timing

Note: The SH-4 Wait State Control Register for the area in which the S1D13705 resides must be set to a

non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value

(with reference to BUSCLK).

RDY#

TCKIO t2 t3

t11

t12

t17

t6 t7

t13

t18

t15 t16

CKIO

A[16:0], M/R#

CSn#

RD/WR#

RD#

D[15:0]

BS#

WEn#

D[15:0] Hi-Z Hi-Z

Hi-Z

Hi-Z VALID

(write)

(read)

t10

t14

7: A.C. CHARACTERISTICS

1-18 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Note: CKIO may be turned off (held low) between accesses - see Section 13.5 “Turning Off BCLK Between

Accesses” on page 1-70.

Table 7-1 SH-4 Timing

Symbol Parameter Min. Max. Units

fCKIO Bus Clock frequency 50 MHz

TCKIO Bus Clock period 1/fCKIO

t2 Bus Clock pulse width low 8 ns

t3 Bus Clock pulse width high 8 ns

t4 A[16:0], RD/WR# setup to CKIO 0 ns

t5 A[16:0], RD/WR# hold from CS# 0 ns

t6 BS# setup 5 ns

t7 BS# hold 5 ns

t8 CSn# setup 0 ns

t9 Falling edge RD# to DB[15:0] driven 25 ns

t10 CKIO to WE#, RD# high 1.5 TCKIO

t11 Rising edge CSn# to RDY# high impedance TCKIO

t12 Falling edge CSn# to RDY# driven 20 ns

t13 CKIO to RDY# low 20 ns

t14 Rising edge CSn# to RDY# high 16 ns

t15 DB[15:0] setup to 2nd CKIO after BS# (write cycle) 0ns

t16 DB[15:0] hold (write cycle) 0 ns

t17 DB[15:0] valid to RDY# falling edge setup time (read cycle) 0 ns

t18 Rising edge RD# to DB[15:0] high impedance (read cycle) 10 ns

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-19

SPECIFICATION (X27A-A-001-06)

7.1.2 SH-3 Interface Timing

Figure 7-2 SH-3 Bus Timing

Note: The SH-3 Wait State Control Register for the area in which the S1D13705 resides must be set to a

non-zero value.

Note: CKIO may be turned off (held low) between accesses - see Section 13.5 “Turning Off BCLK Between

Accesses” on page 1-70.

Table 7-2 SH-3 Bus Timing

Symbol Parameter Min. Max. Units

fCKIO Bus Clock frequency 50 MHz

TCKIO Bus Clock period 1/fCKIO

t2 Bus Clock pulse width low 8 ns

t3 Bus Clock pulse width high 8 ns

t4 A[16:0], RD/WR# setup to CKIO 0 ns

t5 A[16:0], RD/WR# hold from CS# 0 ns

t6 BS# setup 5 ns

t7 BS# hold 5 ns

t8 CSn# setup 0 ns

t9 Falling edge RD# to DB[15:0] driven 25 ns

t10 CKIO to WEn#, RD#high 1.5 TCKIO

t11 Rising edge CSn# to WAIT# high impedance 10 ns

t12 Falling edge CSn# to WAIT# driven 15 ns

t13 CKIO to WAIT# delay 20 ns

t14 DB[15:0] setup to 2nd CKIO after BS# (write cycle) 0ns

t15 DB[15:0] hold from rising edge of WEn# (write cycle) 0 ns

t16 DB[15:0] valid to WAIT# rising edge setup time (read cycle) 0 ns

t17 Rising edge RD# to DB[15:0] high impedance (read cycle) 10 ns

TCKIO t2 t3

t11

t12

t16

t6 t7

t13

t17

t14 t15

CKIO

A[16:0], M/R#

CSn#

RD/WR#

RD#

D[15:0]

BS#

WAIT#

WEn#

D[15:0]

Hi-Z

Hi-Z Hi-Z

Hi-Z

Hi-Z VALID

(write)

(read)

t10

7: A.C. CHARACTERISTICS

1-20 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

7.1.3 Motorola MC68K #1 Interface Timing

Figure 7-3 MC68K #1 Bus Timing (MC68000)

Note: CKIO may be turned off (held low) between accesses - see Section 13.5 “Turning Off BCLK Between

Accesses” on page 1-70.

Table 7-3 MC68K #1 Bus Timing (MC68000)

Symbol Parameter Min. Max. Units

fCLK Bus Clock Frequency 33 MHz

TCLK Bus Clock period 1/fCLK

t1 A[16:1], CS# valid before AS# falling edge 0 ns

t2 A[16:1], CS# hold from AS# rising edge 0 ns

t3 AS# low to DTACK# driven high 16 ns

t4 CLK to DTACK# low 15 ns

t5 CLK to AS#, UDS#, LDS# high 1 TCLK

t6 AS# high to DTACK# high 20 ns

t7 AS# high to DTACK# high impedance TCLK

t8 UDS#, LDS# falling edge to D[15:0] valid (write cycle) TCLK

t9 D[15:0] hold from AS# rising edge (write cycle) 0 ns

t10 UDS#, LDS# falling edge to D[15:0] driven (read cycle) 15 ns

t11 D[15:0] valid to DTACK# falling edge (read cycle) 0 ns

t12 UDS#, LDS# rising edge to D[15:0] high impedance 10 ns

A[16:1]

AS#

UDS#, LDS#

VALID

R/W#

Hi-Z Hi-Z

INVALID

DTACK# Hi-Z

Hi-Z

CLK

TCLK

CS#

t10 t11

Hi-Z VALID Hi-Z

D[15:0]

t12

(write

(read)

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-21

SPECIFICATION (X27A-A-001-06)

7.1.4 Motorola MC68K #2 Interface Timing

Figure 7-4 MC68K #2 Timing (MC68030)

Note: CKIO may be turned off (held low) between accesses - see Section 13.5 “Turning Off BCLK Between

Accesses” on page 1-70.

Table 7-4 MC68K #2 Timing (MC68030)

Symbol Parameter Min. Max. Units

fCLK Bus Clock frequency 33 MHz

TCLK Bus Clock period 1/fCLK

t1 A[16:0], CS#, SIZ0, SIZ1 valid before AS# falling edge 0 ns

t2 A[16:0], CS#, SIZ0, SIZ1 hold from AS#, DS# rising edge 0 ns

t3 AS# low to DSACK1# driven high 22 ns

t4 CLK to DSACK1# low 18 ns

t5 CLK to AS#, DS# high 1 TCLK ns

t6 AS# high to DSACK1# high 20 ns

t7 AS# high to DSACK1# high impedance TCLK

t8 DS# falling edge to D[31:16] valid (write cycle) TCLK/2

t9 AS#, DS# rising edge to D[31:16] invalid (write cycle) 0 ns

t10 D[31:16] valid to DSACK1# low (read cycle) 0 ns

t11 AS#, DS# rising edge to D[31:16] high impedance 20 ns

A[16:0]

AS#

DS#

VALID

R/W#

Hi-Z

CS#

SIZ0, SIZ1

CLK

t3 t4

DSACK1# Hi-Z

Hi-Z

TCLK

t10

VALID

Hi-Z Hi-Z

D[31:16]

VALID Hi-Z

t11

(write)

(read)

7: A.C. CHARACTERISTICS

1-22 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

7.1.5 Generic #1 Interface Timing

Figure 7-5 Generic #1 Timing

Note: CKIO may be turned off (held low) between accesses - see Section 13.5 “Turning Off BCLK Between

Accesses” on page 1-70.

Table 7-5 Generic #1 Timing

Symbol Parameter Min. Max. Units

fBCLK Bus Clock frequency 50 MHz

TBCLK Bus Clock period 1/fBCLK MHz

t1 A[16:0], CS# valid to WE0#, WE1# low (write cycle) or RD0#, RD1#

low (read cycle) 0ns

t2 WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to

A[16:0], CS# invalid 0ns

t3 WE0#, WE1# low to D[15:0] valid (write cycle) TBCLK

t4 RD0#, RD1# low to D[15:0] driven (read cycle) 17 ns

t5 WE0#, WE1# high to D[15:0] invalid (write cycle) 0 ns

t6 D[15:0] valid to WAIT# high (read cycle) 0 ns

t7 RD0#, RD1# high to D[15:0] high impedance (read cycle) 10 ns

t8 WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) to

WAIT# driven low 16 ns

t9 BCLK to WAIT# high 16 ns

t10 WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to

WAIT# high impedance 16 ns

t11 WAIT# high to WE0#, WE1#, RD0#, RD1# high 1 TBCLK

TBCLK

t10

BCLK

A[16:0]

CS#

WE0#,WE1#

WAIT#

VALID

Hi-Z

VALID

t6 t7

VALID

Hi-Z Hi-Z

D[15:0]

RD0#, RD1#

(write)

(read)

t11

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-23

SPECIFICATION (X27A-A-001-06)

7.1.6 Generic #2 Interface Timing

Figure 7-6 Generic #2 Timing

Note: CKIO may be turned off (held low) between accesses - see Section 13.5 “Turning Off BCLK Between

Accesses” on page 1-70.

Table 7-6 Generic #2 Timing

Symbol Parameter Min. Max. Units

fBCLK Bus Clock frequency 50 MHz

TBCLK Bus Clock period 1/fBCLK

t1 A[16:0], BHE#, CS# valid to WE#, RD# low 0 ns

t2 WE#, RD# high to A[16:0], BHE#, CS# invalid 0ns

t3 WE# low to D[15:0] valid (write cycle) TBCLK

t4 WE# high to D[15:0] invalid (write cycle) 0 ns

t5 RD# low to D[15:0] driven (read cycle) 16 ns

t6 D[15:0] valid to WAIT# high (read cycle) 0 ns

t7 RD# high to D[15:0] high impedance (read cycle) 10 ns

t8 WE#, RD# low to WAIT# driven low 14 ns

t9 BCLK to WAIT# high 10 ns

t10 WE#, RD# high to WAIT# high impedance 11 ns

t11 WAIT# high to WE#, RD# high 1 TBCLK

t10

BCLK

A[16:0]

CS#

WE#,RD#

WAIT#

VALID

Hi-Z

VALID

TBCLK

t6 t7

VALID

Hi-Z Hi-Z

D[15:0]

BHE#

(write)

(read)

t11

7: A.C. CHARACTERISTICS

1-24 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

7.2 Clock Input Requirements

Figure 7-7 Clock Input Requirements

Note: When CLKI is > 25MHz it must be divided by 2 (REG[02h] bit 4 = 1).

Table 7-7 Clock Input Requirements

Symbol Parameter Min. Max. Units

fCLKI Input Clock Frequency (CLKI) 0 50 MHz

TCLKI Input Clock period (CLKI) 1/fCLKI

tPWH Input Clock Pulse Width High (CLKI) 8 ns

tPWL Input Clock Pulse Width Low (CLKI) 8 ns

tfInput Clock Fall Time (10% - 90%) 5 ns

trInput Clock Rise Time (10% - 90%) 5 ns

tPWL

tPWH

Clock Input Waveform

TCLKI

VIH

VIL

10%

90%

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-25

SPECIFICATION (X27A-A-001-06)

7.3 Display Interface

7.3.1 Power On/Reset Timing

Figure 7-8 LCD Panel Power On/Reset Timing

Note: Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock.

Table 7-8 LCD Panel Power On/Reset Timing

Symbol Parameter Min. Typ. Max. Units

t1 REG[03h] to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active TFPFRAME ns

t2 FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active to LCDPWR 0 Frames

RESET#

REG[03h] bits [1:0]

LCDPWR

FPLINE

FPSHIFT

FPDAT

DRDY t1 t2

00 11

FPFRAME

ACTIVE

7: A.C. CHARACTERISTICS

1-26 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

7.3.2 Power Down/Up Timing

Figure 7-9 Power Down/Up Timing

Table 7-9 Power Down/Up Timing

Symbol Parameter Min. Typ. Max. Units

t1 HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY

inactive - LCDPWR Override = 1 1 Frame

t2 HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY

active - LCDPWR Override = 1 1 Frame

t3 HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY

inactive - LCDPWR Override = 0 1 Frame

t4 LCDPWR low to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY inactive

- LCDPWR Override = 0 127 Frame

t5 HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY,

LCDPWR active - LCDPWR Override = 0 0 Frame

t6 LCDPWR Override active (1) to LCDPWR inactive 1 Frame

t7 LCDPWR Override inactive (1) to LCDPWR active 1 Frame

Active Inactive Active Inactive Active

LCDPWR Override

(REG[03h] bit 3)

HW Power Save

FP Signals

LCDPWR

Software Power Save 11 00 11 00 11

t5 t6 t7

REG[03h] bits [1:0]

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-27

SPECIFICATION (X27A-A-001-06)

7.3.3 4-Bit Single Monochrome Panel Timing

Figure 7-10 4-Bit Single Monochrome Panel Timing

VDP = Vertical Displa y P eriod = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines

VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8Ts

HNDP = Horizontal Non-Display Period = (REG[08h] + 4) × 8Ts

VDP

FPLINE

FPSHIFT

LINE1 LINE2 LINE3 LINE4 LINE239 LINE240

FPFRAME

LINE1 LINE2

FPLINE

DRDY (MOD)

1-2 1-6 1-318

1-3 1-7 1-319

1-4 1-8 1-320

1-1 1-5 1-317

DRDY (MOD)

VNDP

HDP HNDP

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 320 × 240 panel

FPDAT[7:4]]

FPDAT6

FPDAT5

FPDAT4

FPDAT7

For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

7: A.C. CHARACTERISTICS

1-28 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 7-11 4-Bit Single Monochrome Panel A.C. Timing

1.Ts = pixel clock period

2.t1min = t3min - 9Ts

3.t3min = [((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0) + 4) × 8]Ts

4.t6min = [(REG[08h] bits 4-0) × 8 + 2]Ts

5.t7min = [(REG[08h] bits 4-0) × 8 + 11]Ts

Table 7-10 4-Bit Single Monochrome Panel A.C. Timing

Symbol Parameter Min. Typ. Max. Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)

t2 Frame Pulse hold from Line Pulse falling edge 9 Ts

t3 Line Pulse period note 3

t4 Line Pulse pulse width 9 Ts

t5 MOD delay from Line Pulse rising edge 1 Ts

t6 Shift Pulse falling edge to Line Pulse rising edge note 4

t7 Shift Pulse falling edge to Line Pulse falling edge note 5

t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 2 Ts

t9 Shift Pulse period 4 Ts

t10 Shift Pulse pulse width low 2 Ts

t11 Shift Pulse pulse width high 2 Ts

t12 FPDAT[7:4] setup to Shift Pulse falling edge 2 Ts

t13 FPDAT[7:4] hold to Shift Pulse falling edge 2 Ts

t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

Frame Pulse

Line Pulse

DRDY (MOD)

Sync Timing

Line Pulse

Shift Pulse

FPDAT[7:4]

Data Timing

t12 t13

t14 t10t11

t1 t2

t8 t9

Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-29

SPECIFICATION (X27A-A-001-06)

7.3.4 8-Bit Single Monochrome Panel Timing

Figure 7-12 8-Bit Single Monochrome Panel Timing

VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines

VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8Ts

HNDP = Horizontal Non-Display Period = (REG[08h] + 4) × 8Ts

HNDP

VDP

FPLINE

FPSHIFT

LINE1 LINE2 LINE3 LINE4 LINE479 LINE480

FPFRAME

LINE1 LINE2

FPLINE

DRDY (MOD)

1-2 1-10 1-634

1-3 1-11 1-635

1-4 1-12 1-636

1-5 1-13 1-637

1-6 1-14 1-638

1-7 1-15 1-639

1-8 1-16 1-640

1-1 1-9 1-633

DRDY (MOD)

VNDP

HDP

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640 × 480 panel

FPDAT[7:0]

FPDAT6

FPDAT5

FPDAT4

FPDAT7

FPDAT2

FPDAT1

FPDAT0

FPDAT3

For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

7: A.C. CHARACTERISTICS

1-30 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 7-13 8-Bit Single Monochrome Panel A.C. Timing

1. Ts = pixel clock period

2. t1min = t3min - 9Ts

3. t3min = [((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0) + 4) × 8]Ts

4. t6min = [(REG[08h] bits 4-0) × 8 + 4]Ts

5. t7min = [(REG[08h] bits 4-0) × 8 + 13]Ts

Table 7-11 8-Bit Single Monochrome Panel A.C. Timing

Symbol Parameter Min. Typ. Max. Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)

t2 Frame Pulse hold from Line Pulse falling edge 9 Ts

t3 Line Pulse period note 3

t4 Line Pulse pulse width 9 Ts

t5 MOD delay from Line Pulse rising edge 1 Ts

t6 Shift Pulse falling edge to Line Pulse rising edge note 4

t7 Shift Pulse falling edge to Line Pulse falling edge note 5

t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 4 Ts

t9 Shift Pulse period 8 Ts

t10 Shift Pulse pulse width low 4 Ts

t11 Shift Pulse pulse width high 4 Ts

t12 FPDAT[7:0] setup to Shift Pulse falling edge 4 Ts

t13 FPDAT[7:0] hold to Shift Pulse falling edge 4 Ts

t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

t12 t13

Frame Pulse

Line Pulse

DRDY (MOD)

Sync Timing

Line Pulse

Shift Pulse

FPDAT[7:0]

Data Timing

t1 t2

t14 t8 t9 t10t11

Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-31

SPECIFICATION (X27A-A-001-06)

7.3.5 4-Bit Single Color Panel Timing

Figure 7-14 4-Bit Single Color Panel Timing

VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines

VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8Ts

HNDP = Horizontal Non-Display Period = (REG[08h] + 4) × 8Ts

VDP

FPLINE

FPDAT[7:4] LINE1 LINE2 LINE3 LINE4 LINE239 LINE240

FPFRAME

LINE1 LINE2

FPLINE

DRDY (MOD)

FPDAT6

FPDAT5

FPDAT4

FPDAT7

DRDY (MOD)

VNDP

1-R1

1-G1

1-B1

1-R2

1-G2

1-B2

1-R3

1-G3

1-B3

1-R4

1-G4

1-B4

1-B319

1-R320

1-G320

1-B320

HDP HNDP

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 320 × 240 panel

FPSHIFT

7: A.C. CHARACTERISTICS

1-32 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 7-15 4-Bit Single Color Panel A.C. Timing

1. Ts = pixel clock period

2. t1min = t3min - 9Ts

3. t3min = [((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0) + 4) × 8]Ts

4. t6min = [(REG[08h] bits 4-0) × 8 + 0.5]Ts

5. t7min = [(REG[08h] bits 4-0) × 8 + 9.5]Ts

Table 7-12 4-Bit Single Color Panel A.C. Timing

Symbol Parameter Min. Typ. Max. Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)

t2 Frame Pulse hold from Line Pulse falling edge 9 Ts

t3 Line Pulse period note 3

t4 Line Pulse pulse width 9 Ts

t5 MOD delay from Line Pulse rising edge 1 Ts

t6 Shift Pulse falling edge to Line Pulse rising edge note 4

t7 Shift Pulse falling edge to Line Pulse falling edge note 5

t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 0.5 Ts

t9 Shift Pulse period 1 Ts

t10 Shift Pulse pulse width low 0.5 Ts

t11 Shift Pulse pulse width high 0.5 Ts

t12 FPDAT[7:4] setup to Shift Pulse falling edge 0.5 Ts

t13 FPDAT[7:4] hold to Shift Pulse falling edge 0.5 Ts

t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

Frame Pulse

Line Pulse

DRDY (MOD)

Sync Timing

Line Pulse

Shift Pulse

FPDAT[7:4]

Data Timing

t14

t1 t2

t8 t9

t10t11

t12 t13

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-33

SPECIFICATION (X27A-A-001-06)

7.3.6 8-Bit Single Color Panel Timing (Format 1)

Figure 7-16 8-Bit Single Color Panel Timing (Format 1)

VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines

VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8Ts

HNDP = Horizontal Non-Display Period = (REG[08h] + 4) × 8Ts

VDP

FPLINE

FPSHIFT 2

LINE1 LINE2 LINE3 LINE4 LINE479 LINE480

FPFRAME

LINE1 LINE2

FPLINE

FPDAT6

FPDAT5

FPDAT4

FPDAT3

FPDAT2

FPDAT1

FPDAT0

FPDAT7

HDP

VNDP

1-R1

1-B1

1-G2

1-R3

1-B3

1-G4

1-R5

1-B5

1-G1

1-R2

1-B2

1-G3

1-R4

1-B4

1-G5

1-R6

1-G6

1-R7

1-B7

1-G8

1-R9

1-B9

1-G10

1-R11

1-B6

1-G7

1-R8

1-B8

1-G9

1-R10

1-B10

1-G11

1-R636

1-B636

1-G637

1-R638

1-B638

1-G639

1-R640

1-B640

FPSHIFT

1-B11

1-G12

1-R13

1-B13

1-G14

1-R15

1-B15

1-G16

1-R12

1-B12

1-G13

1-R14

1-B14

1-G15

1-R16

1-B16

HNDP

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640 × 480 panel

FPDAT[7:0]

7: A.C. CHARACTERISTICS

1-34 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 7-17 8-Bit Single Color Panel A.C. Timing (Format 1)

1. Ts = pixel clock period

2. t1min = t3min - 9Ts

3. t3min = [((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0) + 4) × 8]Ts

4. t6amin = [(REG[08h] bits 4-0) × 8 + t13 - t10]Ts

5. t6bmin = [(REG[08h] bits 4-0) × 8 + t13]Ts

6. t7amin = [(REG[08h] bits 4-0) × 8 + 11]Ts

7. t7bmin = [(REG[08h] bits 4-0) × 8 + 11] - t10]Ts

Table 7-13 8-Bit Single Color Panel A.C. Timing (Format 1)

Symbol Parameter Min. Typ. Max. Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)

t2 Frame Pulse hold from Line Pulse falling edge 9 Ts

t3 Line Pulse period note 3

t4 Line Pulse pulse width 9 Ts

t6a Shift Pulse falling edge to Line Pulse rising edge note 4

t6b Shift Pulse 2 falling edge to Line Pulse rising edge note 5

t7a Shift Pulse 2 falling edge to Line Pulse falling edge note 6

t7b Shift Pulse falling edge to Line Pulse falling edge note 7

t8 Line Pulse falling edge to Shift Pulse rising, Shift Pulse 2 falling edge t14 + 2 Ts

t9 Shift Pulse 2, Shift Pulse period 4 Ts

t10 Shift Pulse 2, Shift Pulse pulse width low 2 Ts

t11 Shift Pulse 2, Shift Pulse pulse width high 2 Ts

t12 FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge 1 Ts

t13 FPDAT[7:0] hold from Shift Pulse 2, Shift Pulse falling edge 1 Ts

t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

Frame Pulse

Line Pulse

Sync Timing

Line Pulse

Shift Pulse 2

FPDAT[7:0]

Data Timing

t14

t1 t2

t8 t9

t10t11

t12 t13

t7a

t6b

Shift Pulse

t6a

t7b

t12 t13

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-35

SPECIFICATION (X27A-A-001-06)

7.3.7 8-Bit Single Color Panel Timing (Format 2)

Figure 7-18 8-Bit Single Color Panel Timing (Format 2)

VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines

VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8Ts

HNDP = Horizontal Non-Display Period = (REG[08h] + 4) × 8Ts

VDP

FPLINE

FPDAT[7:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480

FPFRAME

LINE1 LINE2

FPLINE

DRDY (MOD)

FPDAT6

FPDAT5

FPDAT4

FPDAT3

FPDAT2

FPDAT1

FPDAT0

FPDAT7

DRDY (MOD)

VNDP

1-R1

1-G1

1-B1

1-R2

1-G2

1-B2

1-R3

1-G3

1-B3

1-R4

1-G4

1-B4

1-R5

1-G5

1-B5

1-R6

1-G6

1-B6

1-R7

1-G7

1-B7

1-R8

1-G8

1-B8

1-G638

1-B638

1-R639

1-G639

1-B639

1-R640

1-G640

1-B640

HDP HNDP

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640 × 480 panel

FPSHIFT

7: A.C. CHARACTERISTICS

1-36 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 7-19 8-Bit Single Color Panel A.C. Timing (Format 2)

1. Ts = pixel clock period

2. t1min = t3min - 9Ts

3. t3min = [((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0) + 4) × 8]Ts

4. t6min = [(REG[08h] bits 4-0) × 8 + 1]Ts

5. t7min = [(REG[08h] bits 4-0) × 8 + 10]Ts

Table 7-14 8-Bit Single Color Panel A.C. Timing (Format 2)

Symbol Parameter Min. Typ. Max. Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)

t2 Frame Pulse hold from Line Pulse falling edge 9 Ts

t3 Line Pulse period note 3

t4 Line Pulse pulse width 9 Ts

t5 MOD delay from Line Pulse rising edge 1 Ts

t6 Shift Pulse falling edge to Line Pulse rising edge note 4

t7 Shift Pulse falling edge to Line Pulse falling edge note 5

t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 2 Ts

t9 Shift Pulse period 2 Ts

t10 Shift Pulse pulse width low 1 Ts

t11 Shift Pulse pulse width high 1 Ts

t12 FPDAT[7:0] setup to Shift Pulse falling edge 1 Ts

t13 FPDAT[7:0] hold to Shift Pulse falling edge 1 Ts

t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts

t14 t10t11

t12 t13

Data Timing

Frame Pulse

t1 t2

Line Pulse

DRDY (MOD)

Sync Timing

Line Pulse

Shift Pulse

t8 t9

FPDAT[7:0]

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-37

SPECIFICATION (X27A-A-001-06)

7.3.8 8-Bit Dual Monochrome Panel Timing

Figure 7-20 8-Bit Dual Monochrome Panel Timing

VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines

VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8Ts

HNDP = Horizontal Non-Display Period = (REG[08h] + 4) × 8Ts

VDP

FPLINE

FPSHIFT

FPDAT[7:0]

FPFRAME

FPLINE

DRDY (MOD)

FPDAT6 1-2 1-6 1-638

FPDAT5 1-3 1-7 1-639

FPDAT4 1-4 1-8 1-640

FPDAT3 241-1 241-5 241-637

FPDAT2 241-638

FPDAT1 241-639

FPDAT0 241-640

FPDAT7 1-1 1-5 1-637

HDP

DRDY (MOD)

241-2 241-6

241-3 241-7

241-4 241-8

VNDP

HNDP

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640 × 480 panel

LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242

7: A.C. CHARACTERISTICS

1-38 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 7-21 8-Bit Dual Monochrome Panel A.C. Timing

1. Ts = pixel clock period

2. t1min = t3min - 9Ts

3. t3min = [(((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0) + 4) × 8) × 2]Ts

5. t6min = [((REG[08h] bits 4-0) x 2) × 8 + 20]Ts

6. t7min = [((REG[08h] bits 4-0) x 2) × 8 + 29]Ts

Table 7-15 8-Bit Dual Monochrome Panel A.C. Timing

Symbol Parameter Min. Typ. Max. Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)

t2 Frame Pulse hold from Line Pulse falling edge 9 Ts

t3 Line Pulse period note 3

t4 Line Pulse pulse width 9 Ts

t5 MOD delay from Line Pulse falling edge 1 Ts

t6 Shift Pulse falling edge to Line Pulse rising edge note 5

t7 Shift Pulse falling edge to Line Pulse falling edge note 6

t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 4 Ts

t9 Shift Pulse period 8 Ts

t10 Shift Pulse pulse width low 4 Ts

t11 Shift Pulse pulse width high 4 Ts

t12 FPDAT[7:0] setup to Shift Pulse falling edge 4 Ts

t13 FPDAT[7:0] hold to Shift Pulse falling edge 4 Ts

t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts

t14 t10t11

t12 t13

Data Timing

Frame Pulse

t1 t2

Line Pulse

DRDY (MOD)

Sync Timing

Line Pulse

Shift Pulse

t8 t9

FPDAT[7:0]

Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-39

SPECIFICATION (X27A-A-001-06)

7.3.9 8-Bit Dual Color Panel Timing

Figure 7-22 8-Bit Dual Color Panel Timing

VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines

VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8Ts

HNDP = Horizontal Non-Display Period = (REG[08h] + 4) × 8Ts

VDP

FPLINE

FPDAT[7:0]

FPFRAME

FPLINE

DRDY (MOD)

VNDP

1-R1

1-G1

1-B1

1-R2

1-G2

1-B2

1-R3

1-G3

1-B3

1-R4

1-G4

1-B4

1-R5

1-G5

1-B5

1-R6

1-G6

1-B6

1-R7

1-G7

1-R8

1-G8

1-B8

1-B639

1-R640

1-G640

1-B640

241-

B639

241-

R640

241-

G640

241-

B640

241-R1

241-G1

241-B1

241-R2

241-G2

241-B2

241-R3

241-G3

241-B3

241-R4

241-G4

241-B4

241-R5

241-G5

241-B5

241-R6

241-G6

241-B6

241-R7

241-G7

241-B7

241-R8

241-G8

241-B8

1-B7

FPSHIFT

HDP HNDP

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640 × 480 panel

LINE 1/241 LINE 2/242 LINE 239/479 LINE 240/480 LINE 1/241

FPDAT6

FPDAT5

FPDAT4

FPDAT3

FPDAT2

FPDAT1

FPDAT0

FPDAT7

7: A.C. CHARACTERISTICS

1-40 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 7-23 8-Bit Dual Color Panel A.C. Timing

1. Ts = pixel clock period

2. t1min = t3min - 9Ts

3. t3min = [(((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0) + 4) × 8) × 2]Ts

5. t6min = [((REG[08h] bits 4-0) × 2) × 8 + 17]Ts

6. t7min = [((REG[08h] bits 4-0) × 2) × 8 + 26]Ts

Table 7-16 8-Bit Dual Color Panel A.C. Timing

Symbol Parameter Min. Typ. Max. Units

t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)

t2 Frame Pulse hold from Line Pulse falling edge 9 Ts

t3 Line Pulse period note 3

t4 Line Pulse pulse width 9 Ts

t5 MOD delay from Line Pulse falling edge 1 Ts

t6 Shift Pulse falling edge to Line Pulse rising edge note 5

t7 Shift Pulse falling edge to Line Pulse falling edge note 6

t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 1 Ts

t9 Shift Pulse period 2 Ts

t10 Shift Pulse pulse width low 1 Ts

t11 Shift Pulse pulse width high 1 Ts

t12 FPDAT[7:0] setup to Shift Pulse falling edge 1 Ts

t13 FPDAT[7:0] hold to Shift Pulse falling edge 1 Ts

t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts

t14 t10t11

t12 t13

Data Timing

Frame Pulse

t1 t2

Line Pulse

DRDY (MOD)

Sync Timing

Line Pulse

Shift Pulse

t8 t9

FPDAT[7:0]

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-41

SPECIFICATION (X27A-A-001-06)

7.3.10 12-Bit TFT/D-TFD Panel Timing

Figure 7-24 12-Bit TFT/D-TFD Panel Timing

VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines

VNDP = Vertical Non-Display Period = VNDP1 + VNDP2 = (REG[0Ah] bits 5-0) Lines

VNDP1 =Vertical Non-Display Period 1 = REG[09h] bits 5-0 Lines

VNDP2 =Vertical Non-Display Period 2 = (REG[0Ah] bits 5-0) - (REG[09Ah] bits 5-0) Lines

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8Ts

HNDP = Horizontal Non-Display Period = HNDP1 + HNDP2 = (REG[08h] + 4) × 8Ts

HNDP1= Horizontal Non-Display Period 1= ((REG[07h] bits4-0) × 8) +16Ts

HNDP2= Horizontal Non-Display P eriod 2 = (((REG[08h] bits4-0) - (REG[07h] bits 4-0))

8)+16Ts

FPFRAME

FPLINE

LINE1 LINE480

1-1

1-2

1-640

FPLINE

FPSHIFT

DRDY

FPDAT[11:0]

FPDAT[9]

FPDAT[10]

FPDAT[11]

VDP

DRDY

Note: DRDY is used to indicate the first pixel

Example Timing for 12-bit 640 × 480 panel

VNDP2

HDP

HNDP2HNDP1

LINE480

VNDP1

FPDAT[8:6]

FPDAT[4:3]

FPDAT[2:0]

7: A.C. CHARACTERISTICS

1-42 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 7-25 TFT/D-TFD A.C. Timing

t12

Line Pulse

Frame Pulse

DRDY

Shift Pulse

640

Line Pulse

21 639

t13

t2 t3 t16

t4 t5

t14

t15

t1 t11

t10

FPDAT[11:0]

Note: DRDY is used to indicate the first pixel

t17

7: A.C. CHARACTERISTICS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-43

SPECIFICATION (X27A-A-001-06)

1. Ts = pixel clock period

2. t6min = [((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0)+4) × 8] Ts

3. t8min = [((REG[06h] bits 1-0, REG[05h] bits 7-0)+1) + (REG[0Ah] bits 6-0)] Lines

4. t10min = [((REG[04h] bits 6-0)+1) × 8] Ts

5. t14min = [((REG[04h] bits 6-0)+1) × 8] Ts

6. t15min = [(REG[07h] bits 4-0) × 8 + 16] Ts

7. t17min = [(REG[08h] bits 4-0) - (REG[07]) × 8 + 16] Ts

Table 7-17 TFT/D-TFD A.C. Timing

Symbol Parameter Min. Typ. Max. Units

t1 Shift Pulse period 1 (note 1)

t2 Shift Pulse pulse width high 0.5 Ts

t3 Shift Pulse pulse width low 0.5 Ts

t4 Data setup to Shift Pulse falling edge 0.5 Ts

t5 Data hold from Shift Pulse falling edge 0.5 Ts

t6 Line Pulse cycle time note 2

t7 Line Pulse pulse width low 9 Ts

t8 Frame Pulse cycle time note 3

t9 Frame Pulse pulse width low 2t6

t10 Horizontal display period note 4

t11 Line Pulse setup to Shift Pulse falling edge 0.5 Ts

t12 Frame Pulse falling edge to Line Pulse falling edge

phase difference t6 - 18Ts

t13 DRDY to Shift Pulse falling edge setup time 0.5 Ts

t14 DRDY pulse width note 5

t15 DRDY falling edge to Line Pulse falling edge note 6

t16 DRDY hold from Shift Pulse falling edge 0.5 Ts

t17 Line Pulse Falling edge to DRDY active note 7 250

8: REGISTERS

1-44 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

8REGISTERS

8.1 Register Mapping

The S1D13705 registers are located in the upper 32 bytes of the 128K byte S1D13705 address

range. The registers are accessible when CS# = 0 and AB[16:0] are in the range 1FFE0h through

1FFFFh.

8.2 Register Descriptions

Unless speciﬁed otherwise, all register bits are reset to 0 during power up.

All bits marked n/a should be programmed 0.

bits 7-2 Product Code

This is a read-only register that indicates the product code of the chip. The product code is

001001.

bits 1-0 Revision Code

This is a read-only register that indicates the revision code of the chip. The revision code

is 00.

bit 7 TFT/STN

When this bit = 0, STN (passive) panel mode is selected. When this bit = 1, TFT/D-TFD

panel mode is selected. If TFT/D-TFD panel mode is selected, Dual/Single (REG[01h]

bit 6) and Color/Mono (REG[01h] bit5) are ignored. See Table 8-1 for a comprehensive

description of panel selection.

bit 6 Dual/Single

When this bit = 0, Single LCD panel dri ve is selected. When this bit = 1, Dual LCD panel

drive is selected. See Table 8-1 for a comprehensive description of panel selection.

bit 5 Color/Mono

When this bit = 0, Monochrome LCD panel drive is selected. When this bit = 1, Color

LCD panel drive is selected. See Table 8-1 for a comprehensive description of panel

selection.

bit 4 FPLINE Polarity

This bit controls the polarity of FPLINE in TFT/D-TFD mode (no effect in passive panel

mode). When this bit = 0, FPLINE is activ e low. When this bit = 1, FPLINE is acti ve high.

bit 3 FPFRAME Polarity

This bit controls the polarity of FPFRAME in TFT/D-TFD mode (no effect in passive

panel mode). When this bit = 0, FPFRAME is activ e lo w. When this bit = 1, FPFRAME is

active high.

REG[00h] Revision Code Register

Address = 1FFE0h Read Only.

Product Code

Bit 5 Product Code

Bit 4 Product Code

Bit 3 Product Code

Bit 2 Product Code

Bit 1 Product Code

Bit 0 Revision Code

Bit 1 Revision Code

Bit 0

REG[01h] Mode Register 0

Address = 1FFE1h Read/Write.

TFT/STN Dual/Single Color/Mono FPLine Polar-

ity FPFrame

Polarity Mask

FPSHIFT Data W idth

Bit 1 Data Width

Bit 0

8: REGISTERS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-45

SPECIFICATION (X27A-A-001-06)

bit 2 Mask FPSHIFT

FPSHIFT is masked during non-display periods if either of the following two criteria is

met: 1. Color passive panel is selected (REG[01h] bit 5 = 1)

2. This bit (REG[01h] bit 2) = 1

bits 1-0 Data Width Bits [1:0]

These bits select the display data format. See Table 8-1 below for a comprehensive

description of panel selection.

bits 7-6 Bit-Per-Pixel Bits [1:0]

These bits select the color or gray-scale depth (Display Mode).

Table 8-1 Panel Data Format

TFT/STN

REG[01h] bit 7 Color/Mono

REG[01h] bit 5 Dual/Single

REG[01h] bit 6

Data Width

Bit 1

REG[01h] bit 1

Data Width

Bit 0

REG[01h] bit 0 Function

000 Mono Single 4-bit passive LCD

1 Mono Single 8-bit passive LCD

10 reserved

1 reserved

100 reserved

1 Mono Dual 8-bit passive LCD

10 reserved

1 reserved

000 Color Single 4-bit passive LCD

1 Color Single 8-bit passive LCD format 1

10 reserved

1 Color Single 8-bit passive LCD format 2

100 reserved

1 Color Dual 8-bit passive LCD

10 reserved

1 reserved

1 X (don’t care) 0 9-bit TFT/D-TFD panel

1 12-bit TFT/D-TFD panel

REG[02h] Mode Register 1

Address = 1FFE2h Read/Write.

Bit-Per-Pixel

Bit 1 Bit-Per-Pixel

Bit 0 High Perfor-

mance

Input Clock

divide

(CLKI/2) Display Blank Frame Repeat Hardware

Video Invert

Enable

Software Video

Invert

Table 8-2 Gray Scale/Color Mode Selection

Color/Mono

REG[01h] bit 6 Bit-Per-Pixel Bit 1

REG[02h] bit 7 Bit-Per-Pixel Bit 0

REG[02h] bit 6 Display Mode

000 2 Gray scale 1 bit-per-pixel

1 4 Gray scale 2 bit-per-pixel

10 16 Gray scale 4 bit-per-pixel

1 reserved

100 2 Colors 1 bit-per-pixel

1 4 Colors 2 bit-per-pixel

10 16 Colors 4 bit-per-pixel

1 256 Colors 8 bit-per-pixel

8: REGISTERS

1-46 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

bit 5 High Performance (Landscape Modes Only)

When this bit = 0, the internal Memory Clock (MCLK) is a divided-down version of the

Pixel Clock (PCLK). The denominator is dependent on the bit-per-pixel mode - see the

table below.

When this bit = 1, MCLK is ﬁxed to the same frequency as PCLK for all bit-per-pixel

modes. This pro vides a faster screen update performance in 1/2/4 bit-per -pixel modes, b ut

also increases power consumption. This bit can be set to 1 just before a major screen

update, then set back to 0 to save power after the update. This bit has no effect in portrait

mode. Refer to “REG[1Bh] Portrait Mode Register” on page 1-54 for portrait mode

clock selection.

bit 4 Input Clock Divide

When this bit = 0, the Operating Clock(CLK) is the same as the Input Clock (CLKI).

When this bit = 1, CLK = CLKI/2.

In landscape mode PCLK=CLK and MCLK is selected as per Table 8-3 .

In portrait mode, MCLK and PCLK are deri ved from CLK as shown in Table 8-8, “Selec-

tion of PCLK and MCLK in Portrait Mode,” on page 1-54.

bit 3 Display Blank

This bit blanks the display image. When this bit = 1, the display is blanked (FPDAT lines

to the panel are driven low). When this bit = 0, the display is enabled.

bit 2 Frame Repeat (EL support)

This feature is used to improve Frame Rate Modulation of EL panels. When this bit = 1,

an internal frame counter runs from 0 to 3FFFFh. When the frame counter rolls over, the

modulated image pattern is repeated (every 1 hour when the frame rate is 72Hz). When

this bit = 0, the modulated image pattern is never repeated.

bit 1 Hardware Video Invert Enable

In passive panel modes (REG[01h] bit 7 = 0) FPDAT11 is available as either GPIO4 or

hardware video invert. When this bit = 1, Hardware Video Invert is enabled via the

FPDAT11 pin. When this bit = 0, FPDAT11 operates as GPIO4. See Table 8-4 below.

Note: Video data is inverted after the Look-Up Table.

bit 0 Software Video Invert

When this bit = 1, Inverse Video Mode is selected. When this bit = 0, Standard Video

Mode is selected. See Table 8-4 below.

Note: Video data is inverted after the Look-Up Table.

Table 8-3 High Performance Selection

High Performance BPP Bit 1 BPP Bit 0 Display Modes

000 MClk = PClk/8 1 bit-per-pixel

1 MClk = PClk/4 2 bit-per-pixel

10 MClk = PClk/2 4 bit-per-pixel

1 MClk = PClk 8 bit-per-pixel

1 X X MClk = PClk

Table 8-4 Inverse Video Mode Select Options

Hardware Video Inv ert

Enable Softw are Video Invert

(Passive and Active Panels) FPDAT11

(Passive Panels Only) Video Data

0 0 X Normal

0 1 X Inverse

1 X 0 Normal

1 X 1 Inverse

8: REGISTERS

S1D13705F00A HARDWARE FUNCTIONAL

EPSON

1-47

SPECIFICATION (X27A-A-001-06)

bit 3 LCDPWR Override

When this bit = 1, LCDPWR is forced inactive, by-passing the LCD power sequencing.

The 127 frame delay between Hardware Po wer Sa ve and the LCD panel control signals is

reduced to a single line. When this bit = 0, LCDPWR is controlled by the power sequenc-

ing logic within the S1D13705. See Figure 7-9,

“Power Down/Up Timing,”

on page 1-26

for further information.

bit 2 Hardware Power Save Enable

When this bit = 1 GPIO0 is used as the Hardware Power Save input pin. When this bit =

0, GPIO0 operates normally.

bits 1-0 Software Power Save Bits [1: 0]

These bits select the Power Save Mode as shown in the following table.

Refer to Section 13 “Power Save Modes” on page 1-69 for a complete description of the

power save modes.

bits 6-0 Horizontal Panel Size Bits [6:0]

This register determines the horizontal resolution of the panel. This register must be pro-

grammed with a value calculated as follows:

Note:

This register must not be set to a value less than 03h.

REG[03h] Mode Register 2

Address = 1FFE3h Read/Write

n/a n/a n/a n/a LCDPWR

Override

Hardware

Power Save

Enable

Software

Power Save Bit

Software

Power Save Bit

Table 8-5 Hardware Power Save/GPIO0 Operation

RESET#

State

Hardware Power

Save Enable

REG[03h] bit 2

GPIO0 Conﬁg

REG[18h] bit 0

GPIO0 Status/

Control

REG[19h] bit 0

GPIO0 Operation

0XXX

1 0 0 reads pin status GPIO0 Input

(high impedance)

1 0 1 0 GPIO0 Output = 0

1 0 1 1 GPIO0 Output = 1

11 X X

Hardware Power Save Input

(active high)

Table 8-6 Software Power Save Mode Selection

Bit 1 Bit 0 Mode

0 0 Software Power Save

0 1 reserved

1 0 reserved

1 1 Normal Operation

REG[04h] Horizontal Panel Size Register

Address = 1FFE4h Read/Write

n/a Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal

Panel Size Bit

Horizontal Panel Size Register Horizontal Panel Resolution (pixels)

---------------------------------------------------------------------------------------





1–=

8: REGISTERS

1-48

EPSON

S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

REG[05h] bits 7-0 Vertical Panel Size Bits [9:0]

REG[06h] bits 1-0 This 10-bit register determines the vertical resolution of the panel. This regis-

ter must be programmed with a value calculated as follows.:

3FFh is the maximum value of this register for a vertical resolution of 1024

lines.

bits 4-0 FPLINE Start Position

These bits are used in TFT/D-TFD mode to specify the position of the FPLINE pulse.

These bits specify the delay, in 8-pixel resolution, from the end of a line of display data

(FPDAT) to the leading edge of FPLINE. This register is effective in TFT/D-TFD mode

only (REG[01h] bit 7 = 1). This register is programmed as follows:

The following constraint must be satisﬁed:

bits 4-0 Horizontal Non-Display Period

These bits specify the horizontal non-display period in 8-pixel resolution.

REG[05h] Vertical Panel Size Register (LSB)

Address = 1FFE5h Read/Write

Vertical Panel

Size

Bit 7

Vertical Panel

Size

Bit 6

Vertical Panel

Size

Bit 5

Vertical Panel

Size

Bit 4

Vertical Panel

Size

Bit 3

Vertical Panel

Size

Bit 2

Vertical Panel

Size

Bit 1

Vertical Panel

Size

Bit 0

REG[06h] Vertical Panel Size Register (MSB)

Address = 1FFE6h Read/Write

n/a n/a n/a n/a n/a n/a Vertical Panel

Size

Bit 9

Vertical Panel

Size

Bit 8

REG[07h] FPLINE Start Position

Address = 1FFE7h Read/Write

n/a n/a n/a FPLINE Start

Position Bit 4 FPLINE Start

Position Bit 3 FPLINE Start

Position Bit 2 FPLINE Start

Position Bit 1 FPLINE Start

Position Bit 0

REG[08h] Horizontal Non-Display Period

Address = 1FFE8h Read/Write

n/a n/a n/a Horizontal

Non-Display

Period Bit 4

Horizontal

Non-Display

Period Bit 3

Horizontal

Non-Display

Period Bit 2

Horizontal

Non-Display

Period Bit 1

Horizontal

Non-Display

Period Bit 0

Vertical Panel Size Register Vertical Panel Resolution (lines) 1–=

FPLINEposition pixels()REG 07h[]2+()8×=

REG 07h[]REG 08h[]≤

Horizontal Non-Display Period (pixels) REG 08h[]4+()8×=

8: REGISTERS

S1D13705F00A HARDWARE FUNCTIONAL

EPSON

1-49

SPECIFICATION (X27A-A-001-06)

bits 5-0 FPFRAME Start Position

These bits are used in TFT/D-TFD mode to specify the position of the FPFRAME pulse.

These bits specify the number of lines between the last line of display data (FPDAT) and

the leading edge of FPFRAME. This register is effective in TFT/D-TFD mode only

(REG[01h] bit 7 = 1). This register is programmed as follows:

The contents of this register must be greater than zero and less than or equal to the Verti-

cal Non-Display Period Register, i.e.

bit 7 Vertical Non-Display Status

This bit =1 during the Vertical Non-Display period.

bits 5-0 Vertical Non-Display Period

These bits specify the vertical non-display period. This register is programmed as fol-

lows:

Note:

This register should be set only once, on power-up during initialization.

bits 5-0 MOD Rate Bits [5:0]

When the v alue of this register is 0, the MOD output signal toggles e very FPFRAME. F or

a non-zero value, the value in this register + 1 speciﬁes the number of FPLINEs between

toggles of the MOD output signal. These bits are for passive LCD panels only.

REG[09h] FPFRAME Start Position

Address = 1FFE9h Read/Write

n/a n/a FPFRAME

Start Position

Bit 5

FPFRAME

Start Position

Bit 4

FPFRAME

Start Position

Bit 3

FPFRAME

Start Position

Bit 2

FPFRAME

Start Position

Bit 1

FPFRAME

Start Position

Bit 0

REG[0Ah] Vertical Non-Display Period

Address = 1FFEAh Read/Write

Vertical Non-

Display Status n/a Vertical Non-

Display Period

Bit 5

Vertical Non-

Display Period

Bit 4

Vertical Non-

Display Period

Bit 3

Vertical Non-

Display Period

Bit 2

Vertical Non-

Display Period

Bit 1

Vertical Non-

Display Period

Bit 0

REG[0Bh] MOD Rate Register

Address = 1FFEBh Read/Write

n/a n/a MOD Rate

Bit 5 MOD Rate

Bit 4 MOD Rate

Bit 3 MOD Rate

Bit 2 MOD Rate

Bit 1 MOD Rate

Bit 0

FPFRAMEposition lines()REG 09h[]=

1 REG 09h[]REG 0Ah[]≤≤

Vertical Non-Display Period (lines) REG[0Ah] bits [5:0]=

8: REGISTERS

1-50

EPSON

S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

REG[0Dh] bits 7-0 Screen 1 Start Address Bits [15:0]

REG[0Ch] bits 7-0 These bits determine the

word addr ess

of the start of Screen 1 in Landscape

modes or the

byte address

of the start of Screen 1 in Portrait modes.

Note:

For Portrait mode the most significant bit (bit 16) is located in REG[10h].

REG[0Fh] bits 7-0 Screen 2 Start Address Bits [15:0]

REG[0Eh] bits 7-0 These bits determine the

word addr ess

of the start of Screen 2 in Landscape

modes only and has no effect in Portrait modes.

bit 0 Screen 1 Start Address Bit 16

This bit is the most signiﬁcant bit of Screen 1 Start Address for Portrait mode. This bit has

no effect in Landscape mode.

REG[0Ch] Screen 1 Start Address Register (LSB)

Address = 1FFECh Read/Write

Screen 1 Start

Address

Bit 7

Screen 1 Start

Address

Bit 6

Screen 1 Start

Address

Bit 5

Screen 1 Start

Address

Bit 4

Screen 1 Start

Address

Bit 3

Screen 1 Start

Address

Bit 2

Screen 1 Start

Address

Bit 1

Screen 1 Start

Address

Bit 0

REG[0Dh] Screen 1 Start Address Register (MSB)

Address = 1FFEDh Read/Write

Screen 1 Start

Address

Bit 15

Screen 1 Start

Address

Bit 14

Screen 1 Start

Address

Bit 13

Screen 1 Start

Address

Bit 12

Screen 1 Start

Address

Bit 11

Screen 1 Start

Address

Bit 10

Screen 1 Start

Address

Bit 9

Screen 1 Start

Address

Bit 8

REG[0Eh] Screen 2 Start Address Register (LSB)

Address = 1FFEEh Read/Write

Screen 2 Start

Address

Bit 7

Screen 2 Start

Address

Bit 6

Screen 2 Start

Address

Bit 5

Screen 2 Start

Address

Bit 4

Screen 2 Start

Address

Bit 3

Screen 2 Start

Address

Bit 2

Screen 2 Start

Address

Bit 1

Screen 2 Start

Address

Bit 0

REG[0Fh] Screen 2 Start Address Register (MSB)

Address = 1FFEFh Read/Write

Screen 2 Start

Address

Bit 15

Screen 2 Start

Address

Bit 14

Screen 2 Start

Address

Bit 13

Screen 2 Start

Address

Bit 12

Screen 2 Start

Address

Bit 11

Screen 2 Start

Address

Bit 10

Screen 2 Start

Address

Bit 9

Screen 2 Start

Address

Bit 8

REG[10h] Screen Start Address Overﬂow Register

Address = 1FFF0h Read/Write

n/a n/a n/a n/a n/a n/a n/a Screen 1 Start

Address

Bit 16

8: REGISTERS

S1D13705F00A HARDWARE FUNCTIONAL

EPSON

1-51

SPECIFICATION (X27A-A-001-06)

bits 7-0 Memory Address Offset Bits [7:0] (Landscape Modes Only)

This register is used to create a virtual image by setting a word offset between the last

address of one line and the ﬁrst address of the follo wing line. If this register is not equal to

zero, then a virtual image is formed. The displayed image is a window into the larger vir-

tual image. See Figure 8-1,

“Screen-Register Relationship,”

on page 1-52.

This register has no effect in portrait modes. See

“ REG[1Ch] Line Byte Count Register

for Portrait Mode”

on page 1-55.

REG[13h] bits 1-0 Screen 1 Vertical Size Bits [9:0]

REG[12h] bits 7-0 These bits determine the height (in lines) of Screen 1.

In landscape modes, if this register is programmed with a v alue, n, where n is less than the

Vertical Panel Size (REG[06h], REG[05h]), then lines 0 to n of the panel contain Screen 1

and lines n+1 to REG[06h], REG[05h] of the panel contain Screen 2. See Figure 8-1,

“Screen-Register Relationship,”

on page 1-52.

In portrait modes this register must be programmed greater than, or equal to the Vertical

Panel Size, REG[06h] and REG[05h]. See

“12 SwivelView Mode”

on page 1-64.

REG[11h] Memory Address Offset Register

Address = 1FFF1h Read/Write

Memory

Address Offset

Bit 7

Memory

Address Off-

set Bit 6

Memory

Address Off-

set Bit 5

Memory

Address Off-

set Bit 4

Memory

Address Off-

set Bit 3

Memory

Address Off-

set Bit 2

Memory

Address Off-

set Bit 1

Memory

Address Off-

set Bit 0

REG[12h] Screen 1 Vertical Size Register (LSB)

Address = 1FFF2h Read/Write

Screen 1 Verti-

cal Size Bit 7 Screen 1 Verti-

cal Size

Bit 6 Screen 1 Verti-

cal Size

Bit 5 Screen 1 Verti-

cal Size

Bit 4 Screen 1 Verti-

cal Size

Bit 3 Screen 1 Verti-

cal Size

Bit 2 Screen 1 Verti-

cal Size

Bit 1 Screen 1 Verti-

cal Size

Bit 0

REG[13h] Screen 1 Vertical Size Register (MSB)

Address = 1FFF3h Read/Write

n/a n/a n/a n/a n/a n/a Screen 1 Verti-

cal Size

Bit 9 Screen 1 Verti-

cal Size

Bit 8

8: REGISTERS

1-52

EPSON

S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

Figure 8-1 Screen-Register Relationship

Consider an example where REG[13h], REG[12] = 0CEh for a 320x240 display system.

The upper 207 lines (CEh + 1) of the panel show an image from the Screen 1 Start Word

Address. The remaining 33 lines show an image from the Screen 2 Start Word Address.

bits 7-0 LUT Address Bits [7:0]

These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13705 has three

256-position, 4-bit wide LUTs, one for each of red, green, and blue – refer to Section 11

“Look-Up Table Architecture” on page 1-58 for details.

This register selects which LUT entry is read/write accessible through the LUT Data Re g-

ister (REG[17h]). Writing the LUT Address Register automatically sets the pointer to the

Red LUT. Accesses to the LUT Data Register automatically increment the pointer.

For example, writing a value 03h into the LUT Address Register sets the pointer to R[3].

A subsequent access to the LUT Data Register accesses R[3] and moves the pointer onto

G[3]. Subsequent accesses to the LUT Data Register move the pointer onto B[3], R[4],

G[4], B[4], R[5], etc.

Note:

The RGB data is inserted into the LUT after the Blue data is written, i.e. all three

colors must be written before the LUT is updated.

REG[15h] Look-Up Table Address Register

Address = 1FFF5h Read/Write

LUT Address

Bit 7 LUT Address

Bit 6 LUT Address

Bit 5 LUT Address

Bit 4 LUT Address

Bit 3 LUT Address

Bit 2 LUT Address

Bit 1 LUT Address

Bit 0

Line 0

Line 1

(REG[0Dh], REG[0Ch]) Words

Line 0 Last Pixel Address + REG[11h] Words Line 0 Last Pixel Address=((REG[0Dh], REG[0Ch]) +

(8(REG[04h]+1) × BPP/16))

8(REG[04h]+1) Pixels

Virtual Image

REG[11h] Words

Line=(REG[13h], REG[12h])

((REG[06h], REG[05])+1) Lines

Image 1

Image 2 (REG[0Fh], REG[0Eh]) Words

Where:

(REG[0Dh], REG[0Ch]) is the Screen 1 Start Word Address

BPP is Bits-per-Pixel as set by REG[02h] bits 7:6

REG[11h] is the Address Pitch Adjustment in Words

(REG[0Fh], REG[0Eh]) is the Screen 2 Start Word Address

(REG[13h], REG[12h]) is the Screen 1 Vertical Size

(REG[06h], REG[05h]) is the Vertical Panel Size

Words

8: REGISTERS

S1D13705F00A HARDWARE FUNCTIONAL

EPSON

1-53

SPECIFICATION (X27A-A-001-06)

bits 7-4 LUT Data Bits [3:0]

This register is used to read/write the RGB Look-Up Tables. This register accesses the

entry at the pointer controlled by the Look-Up Table Address Register (REG[15h]).

Accesses to the Look-Up Table Data Register automatically increment the pointer.

Note:

The RGB data is inserted into the LUT after the Blue data is written, i.e. all three

colors must be written before the LUT is updated.

bits 4-0 GPIO[4:0] Pin IO Conﬁguration

These bits determine the direction of the GPIO[4:0] pins.

When the GPIOn Pin IO Conﬁguration bit = 0, the corresponding GPIOn pin is conﬁg-

ured as an input. The input can be read at the GPIOn Status/Control Register bit. See

“REG[19h] GPIO Status/Control Register”.

When the GPIOn Pin IO Conﬁguration bit = 1, the corresponding GPIOn pin is conﬁg-

ured as an output. The output can be controlled by writing the GPIOn Status/Control Re g-

ister bit.

Note:

These bits have no effect when the GPIOn pin is configured for a specific function

(i.e. as FPDAT[11:8] for TFT/D-TFD operation).

When configured as IO, all unused pins must be tied to IO V

bits 4-0 GPIO[4:0] Status

When the GPIOn pin is conﬁgured as an input, the corresponding GPIO Status bit is used

to read the pin input. See REG[18h] above.

When the GPIOn pin is conﬁgured as an output, the corresponding GPIO Status bit is

used to control the pin output.

bits 7-0 Scratch Pad Register

This register contains general use read/write bits. These bits have no effect on hardware.

REG[17h] Look-Up Table Data Register

Address = 1FFF7h Read/Write

LUT Data

Bit 3 LUT Data

Bit 2 LUT Data

Bit 1 LUT Data

Bit 0 n/a n/a n/a n/a

REG[18h] GPIO Conﬁguration Control Register

Address = 1FFF8h Read/Write

n/a n/a n/a GPIO4 Pin IO

Conﬁguration GPIO3 Pin IO

Conﬁguration GPIO2 Pin IO

Conﬁguration GPIO1 Pin IO

Conﬁguration GPIO0 Pin IO

Conﬁguration

REG[19h] GPIO Status/Control Register

Address = 1FFF9h Read/Write

n/a n/a n/a GPIO4 Pin IO

Status GPIO3 Pin IO

Status GPIO2 Pin IO

Status GPIO1 Pin IO

Status GPIO0 Pin IO

Status

REG[1Ah] Scratch Pad Register

Address = 1FFFAh Read/Write

Scratch bit 7 Scratch bit 6 Scratch bit 5 Scratch bit 4 Scratch bit 3 Scratch bit 2 Scratch bit 1 Scratch bit 0

8: REGISTERS

1-54 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

bit 7 Portrait Mode Enable

When this bit = 1, Portrait Mode is enabled. When this bit = 0, Landscape Mode is

enabled.

bit 6 Portrait Mode Select

When this bit = 0, Default Portrait Mode is selected. When this bit = 1, Alternate Portrait

Mode is selected. See Section 12 “SwivelView Mode” on page 1-64 for further informa-

tion on Portrait Mode.

The following table shows the selection of Portrait Mode.

bit 2 reserved

reserved bits must be set to 0.

bits 1-0 Portrait Mode Pixel Clock Select Bits [1:0]

These two bits select the Pix el Clock (PCLK) source in Portrait Mode - these bits hav e no

effect in Landscape Mode. The following table shows the selection of PCLK and MCLK

in Portrait Mode - see Section 12 “SwivelView Mode” on page 1-64 for details.

Where CLK is CLKI (REG[02h] bit 4 = 0) or CLKI/2 (REG[02h] bit 4 = 1)

REG[1Bh] Portrait Mode Register

Address = 1FFFBh Read/Write

Portrait Mode

Enable Portrait Mode

Select n/a n/a n/a reserved Portrait Mode

Pixel Clock

Select Bit 1

Portrait Mode

Pixel Clock

Select Bit 0

Table 8-7 Selection of Portrait Mode

Portrait Mode

Enable

(REG[1Bh] bit 7)

Portrait Mode

Select

(REG[1Bh] bit 6) Mode

0 X Landscape

1 0 Default Portrait

1 1 Alternate Portrait

Table 8-8 Selection of PCLK and MCLK in Portrait Mode

Portrait Mode

Enable

(REG[1Bh] bit 7)

Portrait Mode

Select

(REG[1Bh] bit 6)

Pixel Clock (PCLK) Select

(REG[1Bh] bits [1:0] PCLK = MCLK =

Bit 1 Bit 0

0 X X X CLK See Reg[02h] bit 5

1 0 0 0 CLK CLK

1 0 0 1 CLK/2 CLK/2

1 0 1 0 CLK/4 CLK/4

1 0 1 1 CLK/8 CLK/8

1 1 0 0 CLK/2 CLK

1 1 0 1 CLK/2 CLK

1 1 1 0 CLK/4 CLK/2

1 1 1 1 CLK/8 CLK/4

8: REGISTERS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-55

SPECIFICATION (X27A-A-001-06)

bits 7-0 Line Byte Count Bits [7:0]

This register is the byte count from the beginning of one line to the beginning of the next

consecutive line (commonly called “stride” by programmers). This register may be used

to create a virtual image in portrait mode.

When this register = 00 the “stride” = 256 bytes. This value is used for 240×320 8 bpp

default portrait mode

When the Line Byte Count Register = n, where 1 ≤ n ≤ FFh, the “stride” = n bytes.

REG[1Eh] and REG[1Fh]

REG[1Eh] and REG[1Fh] are reserved for f actory S1D13705 testing and should not be written. Any

v alue written to these registers may result in damage to the S1D13705 and/or any panel connected to

the S1D13705.

REG[1Ch] Line Byte Count Register for Portrait Mode

Address = 1FFFCh Read/Write

Line Byte

Count bit 7 Line Byte

Count bit 6 Line Byte

Count bit 5 Line Byte

Count bit 4 Line Byte

Count bit 3 Line Byte

Count bit 2 Line Byte

Count bit 1Line Byte

Count bit 0

9: FRAME RATE CALCULATION

1-56 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

9FRAME RATE CALCULATION

The following formulae are used to calculate the display frame rate.

TFT/D-TFD and Passive Single-Panel modes

Where: fPCLK = PCLK frequency (Hz)

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8 Pixels

HNDP = Horizontal Non-Display Period = ((REG[08h] bits 4-0) + 4) × 8 Pixels

VDP = Vertical Display Period = ((REG[06h] bits 1-0, REG[05h] bits 7-0) + 1) Lines

VNDP = Vertical Non-Display Period = (REG[0Ah] bits 5-0) Lines

Passive Dual-Panel mode

Where: fPCLK = PCLK frequency (Hz)

HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) × 8 Pixels

HNDP = Horizontal Non-Display Period = ((REG[08h] bits 4-0) + 4) × 8 Pixels

VDP = Vertical Display Period = ((REG[06h] bits 1-0, REG[05h] bits 7-0) + 1) Lines

VNDP = Vertical Non-Display Period = (REG[0Ah] bits 5-0) Lines

FrameRate fPCLK

HDP HNDP+()VDP VNDP+()×

-----------------------------------------------------------------------------------------=

FrameRate fPCLK

2 HDP HNDP+()×VDP

------------ VNDP+





---------------------------------------------------------------------------------------------------=

10: DISPLAY DATA FORMATS

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-57

SPECIFICATION (X27A-A-001-06)

10DISPLAY DATA FORMATS

Figure 10-1 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization

1-bpp:

A0A1A2A3A4A5A6A7

Host Address Display Memory

Panel Display

P0P1P2P3P4P5P6P7

2-bpp:

A0B0A1B1A2B2A3B3

Host Address Display Memory

A4B4A5B5A6B6A7B7

bit 7 bit 0

4-bpp:

A0B0C0D0A1B1C1D1

Host Address Display Memory

A2B2C2D2A3B3C3D3

bit 7 bit 0

A4B4C4D4A5B5C5D5

Host Address Display Memory

bit 7 bit 0

8-bpp:

A0B0C0D0E0F0G0H0

A1B1C1D1E1F1G1H1

A2B2C2D2E2F2G2H2

Byte 0

Byte 1

Byte 0

Byte 1

Byte 2

Byte 0

Byte 1

Byte 2

Panel Display

P0P1P2P3P4P5P6P7

Panel Display

P0P1P2P3P4P5P6P7

Panel Display

P0P1P2P3P4P5P6P7

Pn = (An)

Pn = (An, Bn)

Pn = (An, Bn, Cn, Dn)

Pn = (An, Bn, Cn, Dn, En, Fn, Gn, Hn)

11: LOOK-UP TABLE ARCHITECTURE

1-58 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

11LOOK-UP TABLE ARCHITECTURE

The following ﬁgures are intended to show the display data output path only.

Note: When Video Data Invert is enabled the video data is inverted after the Look-Up Table.

11.1 Monochrome Modes

The green Look-Up Table (LUT) is used for all monochrome modes.

11.1.1 1 Bit-per-pixel Monochrome Mode

Figure 11-1 1 Bit-per-pixel Monochrome Mode Data Output Path

11.1.2 2 Bit-per-pixel Monochrome Mode

Figure 11-2 2 Bit-per-pixel Monochrome Mode Data Output Path

Green Look-Up Table 256×4

1 bit-per-pixel data

4-bit Gray Data

from Display Buffer

= unused Look-Up Table entries

Green Look-Up Table 256×4

2 bit-per-pixel data

4-bit Gray Data

from Display Buffer

= unused Look-Up Table entries

11: LOOK-UP TABLE ARCHITECTURE

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-59

SPECIFICATION (X27A-A-001-06)

11.1.3 4 Bit-per-pixel Monochrome Mode

Figure 11-3 4 Bit-per-pixel Monochrome Mode Data Output Path

Green Look-Up Table 256×4

0000

0001

4 bit-per-pixel data

4-bit Gray Data

from Display Buffer

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

= unused Look-Up Table entries

11: LOOK-UP TABLE ARCHITECTURE

1-60 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

11.2 Color Modes

11.2.1 1 Bit-per-pixel Color Mode

Figure 11-4 1 Bit-per-pixel Color Mode Data Output Path

Red Look-Up Table 256×4

1 bit-per-pixel data

from Display Buffer

Green Look-Up Table 256×4

Blue Look-Up Table 256×4

4-bit Red Data

4-bit Green Data

4-bit Blue Data

= unused Look-Up Table entries

11: LOOK-UP TABLE ARCHITECTURE

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-61

SPECIFICATION (X27A-A-001-06)

11.2.2 2 Bit-per-pixel Color Mode

Figure 11-5 2 Bit-per-pixel Color Mode Data Output Path

Red Look-Up Table 256×4

2 bit-per-pixel data

4-bit Red Data

from Display Buffer

Green Look-Up Table 256×4

01 4-bit Green Data

Blue Look-Up Table 256×4

01 4-bit Blue Data

= unused Look-Up Table entries

11: LOOK-UP TABLE ARCHITECTURE

1-62 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

11.2.3 4 Bit-per-pixel Color Mode

Figure 11-6 4 Bit-per-pixel Color Mode Data Output Path

Red Look-Up Table 256×4

0000

0001

4 bit-per-pixel data

4-bit Red Data

from Display Buffer

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Green Look-Up Table 256×4

0000

0001

4-bit Green Data

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Blue Look-Up Table 256×4

0000

0001

4-bit Blue Data

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

= unused Look-Up Table entries

11: LOOK-UP TABLE ARCHITECTURE

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-63

SPECIFICATION (X27A-A-001-06)

11.2.4 8 Bit-per-pixel Color Mode

Figure 11-7 8 Bit-per-pixel Color Mode Data Output Path

Red Look-Up Table 256×4

0000 0000

0000 0001

8 bit-per-pixel data

4-bit Red Data

from Display Buffer

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

1111 1000

1111 1001

1111 1010

1111 1011

1111 1100

1111 1101

1111 1110

1111 1111

Green Look-Up Table 256×4

0000 0000

0000 0001

4-bit Green Data

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

1111 1000

1111 1001

1111 1010

1111 1011

1111 1100

1111 1101

1111 1110

1111 1111

Blue Look-Up Table 256×4

0000 0000

0000 0001

4-bit Blue Data

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

1111 1000

1111 1001

1111 1010

1111 1011

1111 1100

1111 1101

1111 1110

1111 1111

12: SWIVELVIEW MODE

1-64 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

12SWIVELVIEW MODE

Many of todays applications use the LCD panel in a portrait orientation. In this case it becomes

necessary to “rotate” the displayed image by 90˚. This rotation can be done by software at the

expense of performance or, it can be done by the S1D13705 hardware with no CPU penalty.

There are two SwivelView modes: Default SwivelView Mode and Alternate SwivelView Mode.

12.1 Default SwivelView Mode

Default Swi v elView Mode requires the portrait image width be a power of two, e.g. a 240-line panel

requires a minimum virtual image width of 256. This mode should be used whenever the required

virtual image can be contained within the integrated display buffer (i.e. virtual image size ≤ 80K

bytes), as it consumes less power than the Alternate SwivelView Mode.

For example, the panel size is 320x240 and the display mode is 8 bit-per-pixel. The virtual image

size is 320x256 which can be contained within the 80K Byte display buffer.

Default SwivelView Mode also requires Memory Clock (MCLK) ≥ Pixel Clock (PCLK).

The following ﬁgure shows how the programmer sees a 240x320 image and how the image is

displayed. The application image is written to the S1D13705 in the following sense:

A–B–C–D. The display is refreshed by the S1D13705 in the following sense: B-D-A-C.

Figure 12-1 Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Default Mode

256

image seen by programmer

= image in display buffer

320

SwivelView

window

320

240

start

address

SwivelView

window

display

image refreshed by S1D13705

start

address

physical

memory

12: SWIVELVIEW MODE

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-65

SPECIFICATION (X27A-A-001-06)

12.1.1 How to Set Up Default SwivelView Mode

The following describes the register settings needed to set up Default SwivelView Mode for a

240×320×8 bpp image:

• Select Default SwivelView Mode: REG[1Bh] bit 7 = 1 and bit 6 = 0

• The display refresh circuitry starts at pixel “B”, therefore the Screen 1 Start Address register must

be programmed with the address of pixel “B”, i.e.

• The Line Byte Count Register for SwivelView Mode must be set to the virtual-image width in

bytes, i.e.

• Panning is achieved by changing the Screen 1 Start Address register:

• Increment the register by 1 to pan horizontally by one byte, e.g. one pixel in 8 bpp mode

• Increment the register by twice the ef fecti ve v alue of the Line Byte Count re gister to pan vertically

by two lines, e.g. add 200h to pan by two lines in the example above.

Note: Vertical panning by a single line is not supported in Default SwivelView Mode.

REG[10h], REG[0Dh], REG[0Ch] AddressOfPixelB=

AddressOfPixelA ByteOffset+()=

AddressOfPixelA 240pixels 8bpp×

8bpb

--------------------------------------------





1–+=

AddressOfPixelA EFh+=

Where bpp is bits-per-pixel and bpb is bits-per-byte.

REG 1Ch[] 256

8bpb()8bpp()÷

------------------------------------------256

--------- 256 00h : see REG[1Ch] for explanation====

Where bpb is bits-per-byte and bpp is bits-per-pixel.

12: SWIVELVIEW MODE

1-66 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

12.2 Alternate SwivelView Mode

Alternate Swi v elView Mode may be used when the virtual image size of Default SwivelView Mode

cannot be contained in the 80K byte integrated frame b uffer. For example, the panel size is 480 ×320

and the display mode is 4 bit-per-pixel. The minimum virtual image size for Default SwivelView

Mode would be 480×512 which requires 122,880 bytes. Alternate SwivelView Mode requires a

panel size of only 480×320 which needs only 76,800 bytes.

Alternate Swi v elView Mode requires the Memory Clock (MCLK) to be at least twice the frequency

of the Pixel Clock (PCLK), i.e. MCLK ≥ 2 x PCLK. This makes the po wer consumption in Alternate

SwivelView Mode higher than in Default SwivelView Mode.

The follo wing ﬁgure shows ho w the programmer sees a 480×320 image and how the image is being

displayed. The application image is written to the S1D13705 in the follo wing sense: A–B–C–D. The

display is refreshed by the S1D13705 in the following sense: B-D-A-C.

Figure 12-2 Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Alternate Mode

image seen by programmer

= image in display buffer

480

SwivelView

window

480

320

start

address

SwivelView

window

display

image refreshed by S1D13705

start

address

physical

memory

12: SWIVELVIEW MODE

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-67

SPECIFICATION (X27A-A-001-06)

12.2.1 How to Set Up Alternate SwivelView Mode

The following describes the register settings needed to set up Alternate SwivelView Mode for a

320×480×4 bpp image.

• Select Alternate SwivelView Mode:

REG[1Bh] bit 7 = 1 and bit 6 = 1

• The display refresh circuitry startsP at pixel “B”, therefore the Screen 1 Start Address register

must be programmed with the address of pixel “B”, or

• The Line Byte Count Register for SwivelView Mode must be set to the image width in bytes, i.e.

• Panning is achieved by changing the Screen 1 Start Address register:

• Increment the register by 1 to pan horizontally by one byte, e.g. two pixels in 4 bpp mode

• Increment the register by the value in the Line Byte Count register to pan vertically by one line,

e.g. add A0h to pan by one line in the example above

REG[10h], REG[0Dh], REG[0Ch] Address Of Pixel B=

Address Of Pixel A Byte Offset+()=

Address Of Pixel A 320pixels 4bpp×

8bpb

--------------------------------------------





1–+=

Address Of Pixel A 9Fh+=

Where bpp is bits-per-pixel and bpb is bits-per-byte.

REG 1Ch[] 320

8bpb()4bpp()÷

------------------------------------------320

--------- 160 A0h====

Where bpb is bits-per-byte and bpp is bits-per-pixel.

12: SWIVELVIEW MODE

1-68 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

12.3 Comparison Between Default and Alternate SwivelView Modes

12.4 SwivelView Mode Limitations

The only limitation to using Swi v elView mode on the S1D13705 is that split screen operation is not

supported.

Table 12-1 Default and Alternate SwivelView Mode Comparison

Item Default SwivelView Mode Alternate SwivelView Mode

Memory Requirements

The width of the rotated image must be a power of

2. In most cases, a virtual image is required where

the right-hand side of the virtual image is unused

and memory is wasted. For example, a 320 × 480 ×

4bpp image would normally require only 76,800

bytes - possible within the 80K byte address space,

but the virtual image is 512 × 480 × 4bpp which

needs 122,880 bytes - not possible.

Does not require a virtual image.

Clock Requirements CLK need only be as fast as the required PCLK.

MCLK, and hence CLK, need to be 2x PCLK. For

example, if the panel requires a 3MHz PCLK, then

CLK must be 6MHz. Note that 25MHz is the maxi-

mum CLK, so PCLK cannot be higher than

12.5MHz in this mode.

Power Consumption Lowest power consumption. Higher than Default Mode.

Panning Vertical panning in 2 line increments. Vertical panning in 1 line increments.

Performance Nominal performance. Higher performance than Default Mode.

13: POWER SAVE MODES

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-69

SPECIFICATION (X27A-A-001-06)

13POWER SAVE MODES

Two Power Save Modes have been incorporated into the S1D13705 to accommodate the need for

power reduction in the hand-held devices market. These modes are enabled as follows:

13.1 Software Power Save Mode

Software Power Save Mode saves power by powering down the panel and stopping display refresh

accesses to the display buffer.

13.2 Hardware Power Save Mode

Hardware Power Save Mode saves power by powering down the panel, stopping accesses to the

display buffer and registers, and disabling the Host Bus Interface.

13.3 Power Save Mode Function Summary

Note: When FPDAT[11:8] are designated as GPIO these pins are not forced low. Unused GPIO pins must

be tied to IO VDD - see Table 5-8, “LCD Interface Pin Mapping,” on page 1-14.

Table 13-1 Power Save Mode Selection

Hardware Power Save Software Power Save

Bit 1 Software Power Save

Bit 0 Mode

Not Conﬁgured or 0 0 0 Software Power Save Mode

Not Conﬁgured or 0 0 1 reserved

Not Conﬁgured or 0 1 0 reserved

Not Conﬁgured or 0 1 1 Normal Operation

Conﬁgured and 1 X X Hardware Power Save Mode

Table 13-2 Software Power Save Mode Summary

• Registers read/write accessible

• Memory read/write accessible

• Look-Up Table registers not accessible

• LCD outputs are forced low

Table 13-3 Hardware Power Save Mode Summary

• Host Interface not accessible

• Memory read/write not accessible

• Look-Up Table registers not accessible

• LCD outputs are forced low

Table 13-4 Power Save Mode Function Summary

Hardware Power

Save Software Power

Save Normal

IO Access Possible? No Yes Yes

Memory Access Possible? No Yes Y es

Look-Up Table Registers Access Possible? No No Yes

Sequence Controller Running? No No Yes

Display Activ e? No No Yes

LCDPWR Inactive Inactive Active

FPDAT[11:0], FPSHIFT (see note) Forced Low Forced Low Active

FPLINE, FPFRAME, DRDY Forced Low Forced Low Active

13: POWER SAVE MODES

1-70 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

13.4 Panel Power Up/Down Sequence

After chip reset or when entering/exiting a power save mode, the Panel Interface signals follow a

po wer on/of f sequence sho wn belo w. This sequence is essential to pre vent damage to the LCD panel.

Figure 13-1 Panel On/Off Sequence

After chip reset, LCDPWR is inactive and the rest of the panel interface output signals are held

“low”. Software initializes the chip (i.e. programs all registers except the Look-Up Table registers)

and then programs REG[03h] bits [1:0] to 11b. This starts the power-up sequence as shown. The

power-up/power-down sequence delay is 127 frames. The Look-Up Table registers may be

programmed any time after REG[03h] bits[1:0] = 11b.

The po wer -up/power -down sequence also occurs when exiting/entering Softw are Power Save Mode.

13.5 Turning Off BCLK Between Accesses

BCLK may be turned off (held low) between accesses if the following rules are observed:

1. BCLK must be turned off/on in a glitch free manner

2. BCLK must continue for a period equal to [8TBCLK + 12TMCLK] after the end of the access

(RDY# asserted or WAIT# deasserted).

3. BCLK must be present for at least one TBCLK before the start of an access.

RESET#

LCDPWR

Panel Interface

Output Signals

(except LCDPWR)

0 frame 127 frames 0 frame

Power Save Mode

power-down power-uppower-up

Software Power Save 00 11 00 11

Hardware Power Save

REG[03h] bits [1:0]

13: POWER SAVE MODES

S1D13705F00A HARDWARE FUNCTIONAL EPSON 1-71

SPECIFICATION (X27A-A-001-06)

13.6 Clock Requirements

The following table shows what clock is required for which function in the S1D13705.

Table 13-5 S1D13705 Internal Clock Requirements

Function BCLK CLKI

Is required during register accesses. BCLK

can be shut down between accesses: allow

eight BCLK pulses plus 12 MCLK pulses

(8TBCLK + 12TMCLK) after the last access

before shutting BCLK off. Allow one BCLK

pulse after starting up BCLK before the next

access.

Not Required

Memory Read/Write

Is required during memory accesses. BCLK

can be shut down between accesses: allow

eight BCLK pulses plus 12 MCLK pulses

(8TBCLK + 12TMCLK) after the last access

before shutting BCLK off. Allow one BCLK

pulse after starting up BCLK before the next

access.

Requied

Look-Up Table Register

Read/Write

Is required during LUT register accesses.

BCLK can be shut down between accesses:

allow eight BCLK pulses plus 12 MCLK

pulses (8TBCLK + 12 TMCLK) after the last

access before shutting BCLK off. Allow one

BCLK pulse after starting up BCLK before

the next access.

Not Required

Software Power Save Required Can be stopped after 128 frames from

entering Software Power Save, i.e. after

REG[03h] bits 1-0 = 11.

Hardware Power Save Not Required Can be stopped after 128 frames from

entering Hardware Power Save.

14: MECHANICAL DATA

1-72 EPSON S1D13705F00A HARDWARE FUNCTIONAL

SPECIFICATION (X27A-A-001-06)

14MECHANICAL DATA

Figure 14-1 Mechanical Drawing QFP14

QFP14 - 80 pin Unit: mm

120

60 41

Index

0~10˚

12.0 ± 0.1

14.0 ± 0.4

0.5 0.18

1.4 ± 0.1

0.125

1.0

0.5 ± 0.2

0.1

- 0.05

+ 0.1

- 0.025

+ 0.05

S1D13705F00A

Embedded Memory LCD Controller

Programming Notes

and Examples

 
CONTENTS
 
S1D13705F00A PROGRAMMING NOTES 
 
EPSON
 
2-i
 
AND EXAMPLES
 
CONTENTS
1I
 
NTRODUCTION
 
.........................................................................................................................2-1
2I
 
NITIALIZATION
 
..........................................................................................................................2-2
 
2.1 Display Buffer Location .................................................................................................................2-2
2.2 Register Values.............................................................................................................................2-2
2.3 Frame Rate Calculation.................................................................................................................2-3
 
3M
 
EMORY
 
 M
 
ODELS
 
....................................................................................................................2-5
 
3.1 1 Bit-Per-Pixel (2 Colors/Gray Shades).........................................................................................2-5
3.2 2 Bit-Per-Pixel (4 Colors/Gray Shades).........................................................................................2-5
3.3 4 Bit-Per-Pixel (16 Colors/Gray Shades).......................................................................................2-6
3.4 Eight Bit-Per-Pixel (256 Colors).....................................................................................................2-6
 
4L
 
OOK
 
-U
 
P
 
 T
 
ABLE
 
 (LUT)...........................................................................................................2-7
 
4.1 Look-Up Table Registers...............................................................................................................2-8
4.2 Look-Up Table Organization .........................................................................................................2-8
Color Modes...............................................................................................................................2-8
Gray Shade Modes..................................................................................................................2-12
 
5A
 
DVANCED
 
 T
 
ECHNIQUES
 
.........................................................................................................2-15
 
5.1 Virtual Display .............................................................................................................................2-15
Registers..................................................................................................................................2-15
Examples .................................................................................................................................2-16
5.2 Panning and Scrolling .................................................................................................................2-16
Registers  ................................................................................................................................2-17
Examples .................................................................................................................................2-18
5.3 Split Screen.................................................................................................................................2-20
Registers..................................................................................................................................2-20
Examples .................................................................................................................................2-22
 
6 LCD P
 
OWER
 
 S
 
EQUENCING
 
 
 
AND
 
 P
 
OWER
 
 S
 
AVE
 
 M
 
ODES
 
..............................................................2-23
 
6.1 LCD Power Sequencing..............................................................................................................2-23
6.2 Registers .....................................................................................................................................2-23
6.3 LCD Enable/Disable....................................................................................................................2-24
 
7H
 
ARDWARE
 
 R
 
OTATION
 
............................................................................................................2-25
 
7.1 Introduction To Hardware Rotation .............................................................................................2-25
7.2 Default Portrait Mode ..................................................................................................................2-25
7.3 Alternate Portrait Mode ...............................................................................................................2-26
7.4 Registers .....................................................................................................................................2-27
7.5 Limitations ...................................................................................................................................2-28
7.6 Examples.....................................................................................................................................2-28
 
8I
 
DENTIFYING
 
 
 
THE
 
 S1D13705 ..................................................................................................2-31
9H
 
ARDWARE
 
 A
 
BSTRACTION
 
 L
 
AYER
 
 (HAL).................................................................................2-32
 
9.1 Introduction..................................................................................................................................2-32
9.2 Contents of the HAL_STRUCT ...................................................................................................2-32
9.3 Using the HAL library ..................................................................................................................2-32
9.4 API for 13705HAL .......................................................................................................................2-33
Initialization ..............................................................................................................................2-34
General HAL Support...............................................................................................................2-35
Advanced HAL Functions ........................................................................................................2-37
Register / Memory Access.......................................................................................................2-40
Power Save..............................................................................................................................2-41
Drawing....................................................................................................................................2-42
LUT Manipulation.....................................................................................................................2-43
9.5 Porting LIBSE to a new target platform.......................................................................................2-44
Building the LIBSE library for SH3 target example ..................................................................2-44

CONTENTS

2-ii

EPSON

S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES

Building the HAL library for the target example.......................................................................2-45

10 S

AMPLE

ODE

.......................................................................................................................2-46

10.1 Sample code using the S1D13705 HAL API...............................................................................2-46

10.2 Sample code without using the S1D13705 HAL API ..................................................................2-48

10.3 Header Files................................................................................................................................2-54

 
CONTENTS
 
S1D13705F00A PROGRAMMING NOTES 
 
EPSON
 
2-iii
 
AND EXAMPLES
 
List of Figures
 
Figure 3-1 Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer ..................2-5
Figure 3-2 Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer ..................2-5
Figure 3-3 Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer ................2-6
Figure 3-4 Pixel Storage for 8 Bpp (256 Colors) in One Byte of Display Buffer ....................................2-6
Figure 5-1 Viewport Inside a Virtual Display........................................................................................2-15
Figure 5-2 320
 
×
 
240 Single Panel For Split Screen .............................................................................2-20
Figure 7-1 Relationship Between the Default Mode Screen Image and the Image Refreshed by 
S1D13705 ..........................................................................................................................2-25
Figure 7-2 Relationship Between the Alternate Mode Screen Image and the Image Refreshed by
S1D13705 ..........................................................................................................................2-26
 
List of Tables
 
Table 2-1 S1D13705 Initialization Sequence .......................................................................................2-3
Table 4-1 Recommended LUT Values for 1 Bpp Color Mode..............................................................2-8
Table 4-2 Example LUT Values for 2 Bpp Color Mode ........................................................................2-9
Table 4-3 Suggested LUT Values to Simulate VGA Default 16 Color Palette....................................2-10
Table 4-4 Suggested LUT Values to Simulate VGA Default 256 Color Palette..................................2-11
Table 4-5 Recommended LUT Values for 1 Bpp Gray Shade ...........................................................2-12
Table 4-6 Suggested Values for 2 Bpp Gray Shade ..........................................................................2-13
Table 4-7 Suggested LUT Values for 4 Bpp Gray Shade...................................................................2-14
Table 5-1 Number of Pixels Panned Using Start Address..................................................................2-17
Table 7-1 Default and Alternate Portrait Mode Comparison...............................................................2-28
Table 9-1 HAL Functions....................................................................................................................2-33

1: INTRODUCTION

S1D13705F00A PROGRAMMING NOTES

EPSON

2-1

AND EXAMPLES (X27A-G-002-01)

NTRODUCTION

This guide demonstrates ho w to program the S1D13705 Embedded Memory Color LCD Controller.

The guide presents the basic concepts of the LCD controller and provides methods to directly

program the registers. It explains some of the advanced techniques used and the special features of

the S1D13705.

The guide also introduces the Hardware Abstraction Layer (HAL), which is designed to make

programming the S1D13705 as easy as possible. Future S1D1370x products will support the HAL

allowing OEMs the ability to upgrade to future chips with relative ease.

2: INITIALIZATION

2-2

EPSON

S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

NITIALIZATION

Prior to doing anything else with the S1D13705 the controller must be initialized. Initialization is

the process of setting up the control registers to a known state in order to generate proper display

signals.

2.1 Display Buffer Location

Before we can perform the initialization we have to know where to ﬁnd the S1D13705 display

memory and control registers.

The S1D13705 contains 80 kilobytes of internal display memory. External support logic must be

employed to decode the starting address for this display memory in CPU address space. On the

S5U13705B00C PC platform evaluation boards the address is usually ﬁxed at F00000h.

Alternatively the address can be set to D0000h.

The control registers are located by adding 1FFE0h (128 Kb less 32 bytes) to the base memory

address. Thus, on the typical PC platform, we access control re gister 0 at address F1FFE0h. Control

2.2 Register Values

This section describes the register settings and sequence of setting the registers. In addition to these

setting the Look-Up Table must be programmed with appropriate colors. Look-Up Table setup is not

covered here. See “Section” 4 on page 2-7 of this manual for Look-Up Table programming details.

The following initialization, presented in table form, shows the sequences and values to set the

registers. The notes column comments the reason for the particular value being written.

This example writes to all the necessary registers. Initially, when the S1D13705 is powered up, all

registers, unless noted otherwise in the speciﬁcation, are set to zero. This example programs these

registers to zero to establish a kno wn state. In practice, it may be possible to write to only a subset of

the registers.

The example initializes a S1D13705 to control a panel with the following speciﬁcations:

• 320

240 color single passive LCD panel at 70Hz.

• Color Format 2, 8-bit data interface.

• 8 bit-per-pixel (256 colors).

• 6 MHz input clock (CLKI).

 
2: INITIALIZATION
 
S1D13705F00A PROGRAMMING NOTES 
 
EPSON
 
2-3
 
AND EXAMPLES (X27A-G-002-01)
 
2.3 Frame Rate Calculation
 
Frame rate speciﬁes the number of complete frame which are drawn on the display in one second. 
Conﬁguring a frame rate that is too high or too low adversely effects the quality of the displayed 
image.
System conﬁguration imposes certain non-v ariable limitations. For instance the width and height of 
the display panel are ﬁxed as is, typically, the input clock to the S1D13705. From the following 
formula it is evident that the two variables the programmer can use to adjust frame rate are 
horizontal and vertical non-display periods.
 
Table 2-1  S1D13705 Initialization Sequence 
Register Value (hex) Notes See Also
 
[01] 0010 0011 (23) Select a passive, Single, Color panel with an 8-bit data width
[02] 1100 0000 (C0) Select 8-bit per pixel color depth
[03] 0000 0011 (03) Select normal power operation
[04] 0010 0111 (27) Horizontal display size = (Reg[04]+1)*8 = (39+1) * 8 = 320 pixels
[05] 1110 1111 (EF) Vertical display size = Reg[06][05] + 1 
= 0000 0000 1110 1111 + 1 = 239 +1 = 240 lines[06] 0000 0000 (00)
[07] 0000 0000 (00) FPLINE start position (only required for TFT conﬁguration)
[08] 0000 0000 (00) Horizontal non-display period = (Reg[08] + 4) * 8
                                                     = 4 * 8  =  32 pixels Frame Rate Calculation
[09] 0000 0000 (00) FPFRAME start position (only required for TFT conﬁguration)
[0A] 0000 0011 (03) Vertical non-display period = REG[0A] = 3 lines Frame Rate Calculation
[0B] 0000 0000 (00) MOD rate is only required by some monochrome panels
[0C] 0000 0000 (00) Screen 1 Start Address - set to 0 for initialization
 
“5.3 Split Screen”
 
 on 
page 2-20[0D] 0000 0000 (00)
[0E] 0000 0000 (00) Screen 2 Start Address - set to 0 for initialization
 
“5.3 Split Screen”
 
 on 
page 2-20[0F] 0000 0000 (00)
[10] 0000 0000 (00) Screen 1 / Screen 2 Start Address MSB - set to 0
[11] 0000 0000 (00) Memory Address offset - not virtual setup - so set to 0
 
“5.1 Virtual Display”
 
 on 
page 2-15
[12] 1111 1111 (FF) Set the vertical size to the maximum value.
 
“5.3 Split Screen”
 
 on 
page 2-20[13] 0000 0011 (03)
[15] Leave the LUT alone for now
 
“4 Look-Up Table (LUT)”
 
 
on page 2-7[17]
[18] 0000 0000 (00) GPIO control and status registers - set to “0”.
[19] 0000 0000 (00)
[1A] 0000 0000 (00) Set the scratch pad bits to “0”.
[1B] 0000 0000 (00) This is not portrait mode so set this register to “0”.
 
“7.1 Introduction To Hard-
ware Rotation”
 
 on page 2-
25
[1C] 0000 0000 (00) Line Byte Count is only required for portrait mode.

2: INITIALIZATION

2-4

EPSON

S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

The following are the formulae for determining the frame rate of a panel. The formula for a single

passive or TFT panel is calculated as follows:

for a dual passive panel the formula is:

where : PCLK = Pixel clock (in Hz)

HDP = Horizontal Display Period (in pixels)

HNDP = Horizontal Non-Display Period (in pixels)

VDP = Vertical Display Period (in lines)

VNDP = Vertical Non-Display Period (in lines)

In addition to varying the HNDP and VNDP times we can also select divider values which will

reduce CLKi to one half, one quarter up to one eight of the CLKi value. The example below is a

portion of a ’C’ routine to calculate HNDP and VNDP from a desired frame rate.

for (int loop = 0; loop < 2; loop++)

{for (VNDP = 2; VNDP < 0x3F; VNDP += 3)

{// Solve for HNDP

HNDP = (PCLK / (FrameRate * (VDP + VNDP))) - HDP;

if ((HNDP >= 32) && (HNDP <= 280))

{

// Solve for VNDP.

VNDP = (PCLK / (FrameRate * (HDP + HNDP))) - VDP;

// If we have satisfied VNDP then we're done.

if ((VNDP >= 0) && (VNDP <= 0x3F))

goto DoneCalc;

}

// Divide ClkI and try again.

// (Reg[02] allows us to dived CLKI by 2)

PCLK /= 2;

}

// If we still can't hit the frame rate - throw an error.

if ((VNDP < 0) || (VNDP > 0x3F) || (HNDP < 32) || (HNDP > 280))

{sprintf("ERROR: Unable to set the desired frame rate.\n");

exit(1);

}

This routine ﬁrst performs a formula rearrangement so that HNDP or VNDP can be solved. Start

with VNDP set to a small value. Loop increasing VNDP and solving the equation for HNDP until

satisfactory HNDP and VNDP values are found. If no satisfactory values are found then divide

CLKI and repeat the process. If a satisfactory frame rate still can’t be reached - return an error.

Note:

Most passive (STN) panels are tolerant of nearly any combination of HNDP and VNDP values,

however panel specifications generally specify only a few lines of vertical non-display period.

The S1D13705 is capable of generating a vertical non-display period of up to sixty-three lines.

This amount of VNDP is far too great a non-display period and will likely degrade display qual-

ity. Similarly, setting a large HNDP value may cause a degrade in image quality.

If possible the system should be designed such that VNDP values of 7 or less lines and HNDP

values of 20 or less characters can be selected.

FrameRate PCLK

HDP HNDP+()VDP VNDP+()×

-----------------------------------------------------------------------------------------=

FrameRate PCLK

2 HDP HNDP+()

VDP

------------ VNDP+





××

---------------------------------------------------------------------------------------------------=

3: MEMORY MODELS

S1D13705F00A PROGRAMMING NOTES

EPSON

2-5

AND EXAMPLES (X27A-G-002-01)

EMORY

ODELS

The S1D13705 is capable of operating at four different color depths. For each color depth the data

format is packed pixel. S1D13705 packed pixel modes can range from one byte containing eight

adjacent pixels (1-bpp) to one byte containing just one pixel (8-bpp).

Packed pixel data may be envisioned as a stream of pixels. In this stream, pixels are packed in

adjacent to each other. If a pixel requires four bits then it will be located in the four most signiﬁcant

bits of a byte. The pixel to the immediate right on the display will occupy the lower four bits of the

same byte. The next two pixels to the immediate right are located in the following byte, etc.

3.1 1 Bit-Per-Pixel (2 Colors/Gray Shades)

1-bit pixels support two color/gray shades. In this memory format each byte of display buffer

contains eight adjacent pixels. Setting or resetting any pixel requires reading the entire byte,

masking out appropriate bits and, if necessary, setting bits to “1”.

When using a color panel the two colors are derived by indexing into positions 0 and 1 of the Look-

Up Table. If the ﬁrst two LUT elements are set to black (RGB = 0 0 0) and white (RGB = F F F) then

each “0” bit of display memory will display as a black pixel and each “1” bit will display as a white

pixel. The two LUT entries can be set to any desired colors, for instance red and green or cyan and

yellow.

For monochrome panels the two displayed gray shades are generated by indexing into the ﬁrst two

elements of the green component of the Look-Up Table (LUT). Thus, by manipulating the green

LUT components we can set either of the two gray shades to any of sixteen possible levels.

Figure 3-1 Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer

3.2 2 Bit-Per-Pixel (4 Colors/Gray Shades)

2-bit pixels support four color/gray shades. In this memory format each byte of display buffer

contains four adjacent pixels. Setting or resetting an y pixel requires reading the entire byte, masking

out the appropriate bits and, if necessary, setting bits to “1”.

Color panels derive their four colors by indexing into positions 0 through 3 of the Look-Up Table.

These four LUT entries can be set to any of the 4096 possible color combinations.

Monochrome panels derive four gray shades by indexing into the ﬁrst four elements of the green

component of the Look-Up Table. Any of the four LUT entries can be set to any of the sixteen

possible gray shades.

Figure 3-2 Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Pixel 0

Bit 1 Pixel 0

Bit 0 Pixel 1

Bit 1 Pixel 1

Bit 0 Pixel 2

Bit 1 Pixel 2

Bit 0 Pixel 3

Bit 1 Pixel 3

Bit 0

3: MEMORY MODELS

2-6

EPSON

S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

3.3 4 Bit-Per-Pixel (16 Colors/Gray Shades)

Four bit pixels support 16 color/gray shades. In this memory format each byte of display buffer

contains two adjacent pix els. Setting or resetting an y pix el requires reading the entire byte, masking

out the upper or lower nibble (4 bits) and setting the appropriate bits to “1”.

Color panels can display up to sixteen colors simultaneously. These sixteen colors are derived by

indexing into the ﬁrst sixteen elements of the Look-Up Table. Each of these colors may be selected

from the 4096 possible available colors.

On a monochrome panel the gray shades are generated by indexing into the ﬁrst sixteen green

components of the LUT. Each of these sixteen possible gray shades can be adjusted to any of the

sixteen possible gray shades. For instance, one could program the ﬁrst eight green LUT entries to be

0 and the second green LUT entries to be FFh. This would result in nibble values of 0 through 7

displaying as black and nibble values 8 through 0Fh displaying as white.

Figure 3-3 Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer

3.4 Eight Bit-Per-Pixel (256 Colors)

In eight bit-per-pixel mode one byte of display buffer represents one pixel on the display. At this

color depth the read-modify-write cycles, required by the lessor pixel depths, are eliminated.

When using a color panel, each byte of display memory acts as and index to one element of the LUT.

The displayed color is arrived at by taking the display memory value as an index into the LUT.

Eight bit per pixel is not supported for monochrome display modes. The reason is that each element

of the LUT supports a 4-bit (sixteen value) level for red, green and blue. In monochrome display

modes on the green v alue is used to set the gray intensity. Thus we ha v e sixteen possible grey values

but, because of the color.

Figure 3-4 Pixel Storage for 8 Bpp (256 Colors) in One Byte of Display Buffer

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Pixel 0

Bit 3 Pixel 0

Bit 2 Pixel 0

Bit 1 Pixel 0

Bit 0 Pixel 1

Bit 3 Pixel 1

Bit 2 Pixel 1

Bit 1 Pixel 1

Bit 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Red bit 2 Red bit 1 Red bit 0 Green bit 2 Green bit 1 Green bit 0 Blue bit 1 Blue bit 0

4: LOOK-UP TABLE (LUT)

S1D13705F00A PROGRAMMING NOTES

EPSON

2-7

AND EXAMPLES (X27A-G-002-01)

OOK

-U

ABLE (LUT)

This section is supplemental to the description of the Look-Up Table architecture found in the

S1D13705 Hardware Functional Speciﬁcation. Covered here is a review of the LUT registers,

recommendations for the color and gray shade LUT values, and additional programming

considerations for the LUT. Refer to the “S1D13705 Hardware Functional Speciﬁcation”,

document number X27A-A-001-01 for more detail.

The S1D13705 Look-Up Table consists of 256 indexed red/green/blue entries. Each entry is 4 bits

wide. Two registers, REG[15h] and REG[17h], control access to the LUT.

Each Look-Up Table entry consists of a red, green, and blue component. Each component consisting

of four bits, or sixteen intensity le vels. Any Look-Up Table element can be selected from a palette of

4096 (16×16×16) colors.

In color display modes, pixel values are used as an index to an RGB value stored in the Look-Up

Table. In monochrome modes, pixel v alues still inde x into the LUT, b ut only the green component is

used to determine display intensity.

The selected color depth determines how many index positions are used for image display. For

example at one bit-per -pixel (bpp) only index positions 0 and 1 of the Look-Up Table are used. At 4-

bpp the ﬁrst 16 index positions of the Look-Up Table are used and at 8-bpp all 256 Look-Up Table

index positions are used.

The Look-Up Table mechanism itself consists of an index register and a data register. The index, or

address, register determines which element of the Look-Up Table will be accessed. After setting the

index the LUT may be read or written through the data re gister . The ﬁrst data element read or written

is the red component of the entry. Subsequent read/write operations access the green and then the

blue elements of the Look-Up Table.The S1D13705 LUT architecture is designed to provide a high

degree of similarity in operation to a standard VGA RAMDAC. However, there are two

considerations which must be kept in mind.

• The S1D13705 Look-Up Table has four bits (16 levels) of intensity per primary color. The

standard VGA RAMDAC has six bits (64 levels). This four to one difference must be taken into

consideration when converting from a VGA palette to a LUT palette. One suggestion is to divide

the VGA intensity level by four to arrive at the LUT intensity.

Ho we v er, most applications specify the red, green and blue components as eight bit intensities. To

determine the appropriate S1D13705 Look-Up Table value we recomend using the four most

signiﬁcant bits.

4: LOOK-UP TABLE (LUT)

2-8 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

4.1 Look-Up Table Registers

LUT Address

The LUT address register selects which of the 256 LUT entries will be accessed. After three

successive reads/writes to the data register this register is automatically incremented to point to the

next address.

LUT Data

This register is where the 4-bit red/green/blue data value is written/read. Immediately after setting

the LUT index with re gister [15h] this register accesses the red element of the Look-Up Table. With

each successive write/read the internal bank select is incremented. Thus the second access is from

the green element and the third is from the blue element.

After the third access the LUT Address is incremented by one, then next access to this register will

be the red element of the next Look-Up Table index.

4.2 Look-Up Table Organization

Color Modes

1 bpp color

When the S1D13705 is conﬁgured for 1 bpp color mode, the LUT is limited to selecting colors from

the ﬁrst two entries. The two LUT entries can be any two RGB values but are typically set to black-

and-white.

Each byte in the display buffer contains eight adjacent pixels. If a bit has a value of “0” then the

color in LUT 0 index is displayed. A bit value of “1” results in the color in LUT 1 index being

displayed.

The following table shows the recommended values for obtaining a black-and-white mode while in

1 bpp on a color panel.

REG[15h] Look-Up Table Address Registe Read/Write

LUT Address

Bit 7 LUT Address

Bit 6 LUT Address

Bit 5 LUT Address

Bit 4 LUT Address

Bit 3 LUT Address

Bit 2 LUT Address

Bit 1 LUT Address

Bit 0

REG[17h] Look-Up Table Data Register Read/Write

LUT Data

Bit 3 LUT Data

Bit 2 LUT Data

Bit 1 LUT Data

Bit 0 n/a n/a n/a n/a

Table 4-1 Recommended LUT Values for 1 Bpp Color Mode

Index Red Green Blue

00 00 00 00

01 F0 F0 F0

02 00 00 00

... 00 00 00

FF 00 00 00

unused entries

4: LOOK-UP TABLE (LUT)

S1D13705F00A PROGRAMMING NOTES EPSON 2-9

AND EXAMPLES (X27A-G-002-01)

2 bpp color

When the S1D13705 is conﬁgured for 2 bpp color mode, the displayed colors are selected from the

ﬁrst four entries of the Look-Up Table. The LUT entries may be set to any of the 4096 possible

colors.

Each byte in the display buf fer contains four adjacent pix els. If a bit combination has a v alue of “00”

then the color in LUT index 0 is displayed. A bit value of “01” results in the color in LUT index 1

being displayed. Likewise the bit combination of “10” displays from the third LUT entry and “11”

displays a color from the fourth LUT entry.

The following table shows the example values for 2 bit-per-pixel display mode.

Table 4-2 Example LUT Values for 2 Bpp Color Mode

Index Red Green Blue

00 00 00 00

01 70 70 70

02 A0 A0 A0

03 F0 F0 F0

04 00 00 00

... 00 00 00

FF 00 00 00

indicates unused entries

4: LOOK-UP TABLE (LUT)

2-10 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

4 bpp color

When the S1D13705 is conﬁgured for 4 bpp color mode, the displayed colors are selected from the

ﬁrst sixteen entries of the Look-Up Table. The LUT entries may be set to any of the 4096 possible

colors.

Each byte in the display buffer contains two adjacent pixels. If a nibble has a value of “0000” then

the color in LUT index 0 is displayed. A nibble value of “0001” results in the color in LUT index 1

being displayed. The pattern continues to the nibble pattern of “1111” which results in the sixteenth

color of the Look-Up Table being displayed.

The following table shows the example values for 4 bit-per-pixel display mode. These colors

simulate the colors used by the sixteen color modes of a VGA.

Table 4-3 Suggested LUT Values to Simulate VGA Default 16 Color Palette

Index Red Green Blue

00 00 00 00

01 00 00 A0

02 00 A0 00

03 00 A0 A0

04 A0 00 00

05 A0 00 A0

06 A0 A0 00

07 A0 A0 A0

08 00 00 00

09 00 00 F0

0A 00 F0 00

0B 00 F0 F0

0C F0 00 00

0D F0 00 F0

0E F0 F0 00

0F F0 F0 F0

10 00 00 00

... 00 00 00

FF 00 00 00

indicates unused entries

4: LOOK-UP TABLE (LUT)

S1D13705F00A PROGRAMMING NOTES EPSON 2-11

AND EXAMPLES (X27A-G-002-01)

8 bpp color

When the S1D13705 is conﬁgured for 8 bpp color mode the entire Look-Up Table is used to display

images. Each of the LUT entries may be set to any of the 4096 possible colors.

Each byte in the display buf fer represents one pix els. The byte v alue is used directly as an inde x into

one of the 256 LUT entries. A display memory byte with a value of 00h will display the color

contained in the ﬁrst Look-Up Table entry while a display memory byte of FFh will display a color

formed byte the two hundred and ﬁfty sixth Look-Up Table entry.

The following table depicts LUT values which approximate the VGA default 256 color palette.

Table 4-4 Suggested LUT Values to Simulate VGA Default 256 Color Palette

Index R G B Index R G B Index R G B Index R G B

00 00 00 00 40 F0 70 70 80 30 30 70 C0 00 40 00

01 00 00 A0 41 F0 90 70 81 40 30 70 C1 00 40 10

02 00 A0 00 42 F0 B0 70 82 50 30 70 C2 00 40 20

03 00 A0 A0 43 F0 D0 70 83 60 30 70 C3 00 40 30

04 A0 00 00 44 F0 F0 70 84 70 30 70 C4 00 40 40

05 A0 00 A0 45 D0 F0 70 85 70 30 60 C5 00 30 40

06 A0 50 00 46 B0 F0 70 86 70 30 50 C6 00 20 40

07 A0 A0 A0 47 90 F0 70 87 70 30 40 C7 00 10 40

08 50 50 50 48 70 F0 70 88 70 30 30 C8 20 20 40

09 50 50 F0 49 70 F0 90 89 70 40 30 C9 20 20 40

0A 50 F0 50 4A 70 F0 B0 8A 70 50 30 CA 30 20 40

0B 50 F0 F0 4B 70 F0 D0 8B 70 60 30 CB 30 20 40

0C F0 50 50 4C 70 F0 F0 8C 70 70 30 CC 40 20 40

0D F0 50 F0 4D 70 D0 F0 8D 60 70 30 CD 40 20 30

0E F0 F0 50 4E 70 B0 F0 8E 50 70 30 CE 40 20 30

0F F0 F0 F0 4F 70 90 F0 8F 40 70 30 CF 40 20 20

10 00 00 00 50 B0 B0 F0 90 30 70 30 D0 40 20 20

11 10 10 10 51 C0 B0 F0 91 30 70 40 D1 40 20 20

12 20 20 20 52 D0 B0 F0 92 30 70 50 D2 40 30 20

13 20 20 20 53 E0 B0 F0 93 30 70 60 D3 40 30 20

14 30 30 30 54 F0 B0 F0 94 30 70 70 D4 40 40 20

15 40 40 40 55 F0 B0 E0 95 30 60 70 D5 30 40 20

16 50 50 50 56 F0 B0 D0 96 30 50 70 D6 30 40 20

17 60 60 60 57 F0 B0 C0 97 30 40 70 D7 20 40 20

18 70 70 70 58 F0 B0 B0 98 50 50 70 D8 20 40 20

19 80 80 80 59 F0 C0 B0 99 50 50 70 D9 20 40 20

1A 90 90 90 5A F0 D0 B0 9A 60 50 70 DA 20 40 30

1B A0 A0 A0 5B F0 E0 B0 9B 60 50 70 DB 20 40 30

1C B0 B0 B0 5C F0 F0 B0 9C 70 50 70 DC 20 40 40

1D C0 C0 C0 5D E0 F0 B0 9D 70 50 60 DD 20 30 40

1E E0 E0 E0 5E D0 F0 B0 9E 70 50 60 DE 20 30 40

1F F0 F0 F0 5F C0 F0 B0 9F 70 50 50 DF 20 20 40

20 00 00 F0 60 B0 F0 B0 A0 70 50 50 E0 20 20 40

21 40 00 F0 61 B0 F0 C0 A1 70 50 50 E1 30 20 40

22 70 00 F0 62 B0 F0 D0 A2 70 60 50 E2 30 20 40

23 B0 00 F0 63 B0 F0 E0 A3 70 60 50 E3 30 20 40

24 F0 00 F0 64 B0 F0 F0 A4 70 70 50 E4 40 20 40

25 F0 00 B0 65 B0 E0 F0 A5 60 70 50 E5 40 20 30

26 F0 00 70 66 B0 D0 F0 A6 60 70 50 E6 40 20 30

27 F0 00 40 67 B0 C0 F0 A7 50 70 50 E7 40 20 30

28 F0 00 00 68 00 00 70 A8 50 70 50 E8 40 20 20

29 F0 40 00 69 10 00 70 A9 50 70 50 E9 40 30 20

2A F0 70 00 6A 30 00 70 AA 50 70 60 EA 40 30 20

2B F0 B0 00 6B 50 00 70 AB 50 70 60 EB 40 30 20

2C F0 F0 00 6C 70 00 70 AC 50 70 70 EC 40 40 20

4: LOOK-UP TABLE (LUT)

2-12 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

Gray Shade Modes

Gray shade modes are monochrome display modes. Monochrome display modes use the Look-Up

Table in a very similar fashion to the color modes. This most signiﬁcant difference is that the

monochrome display modes use only the intensity of the green element of the Look-Up Table to

form the gray level.

One side ef fect of using only green for intensity selection is that in gray shade modes there are only

sixteen possible intensities. 8 bit-per-pixel is not supported for gray shade modes.

1 bpp gray shade

When the S1D13705 is conﬁgured for 1 bpp gray shade mode, the LUT is limited to selecting colors

from the ﬁrst two green entries. The two LUT entries can be set to any of sixteen possible intensities.

Typically they would be set to 0h (black) and Fh (white).

Each byte in the display buffer contains eight adjacent pixels. If a bit has a value of “0” then the

color in the green LUT 0 index is displayed. A bit value of “1” results in the color in green LUT 1

index being displayed.

The following table shows the recommended values 1 bpp gray shade display mode

2D B0 F0 00 6D 70 00 50 AD 50 60 70 ED 30 40 20

2E 70 F0 00 6E 70 00 30 AE 50 60 70 EE 30 40 20

2F 40 F0 00 6F 70 00 10 AF 50 50 70 EF 30 40 20

30 00 F0 00 70 70 00 00 B0 00 00 40 F0 20 40 20

31 00 F0 40 71 70 10 00 B1 10 00 40 F1 20 40 30

32 00 F0 70 72 70 30 00 B2 20 00 40 F2 20 40 30

33 00 F0 B0 73 70 50 00 B3 30 00 40 F3 20 40 30

34 00 F0 F0 74 70 70 00 B4 40 00 40 F4 20 40 40

35 00 B0 F0 75 50 70 00 B5 40 00 30 F5 20 30 40

36 00 70 F0 76 30 70 00 B6 40 00 20 F6 20 30 40

37 00 40 F0 77 10 70 00 B7 40 00 10 F7 20 30 40

38 70 70 F0 78 00 70 00 B8 40 00 00 F8 00 00 00

39 90 70 F0 79 00 70 10 B9 40 10 00 F9 00 00 00

3A B0 70 F0 7A 00 70 30 BA 40 20 00 FA 00 00 00

3B D0 70 F0 7B 00 70 50 BB 40 30 00 FB 00 00 00

3C F0 70 F0 7C 00 70 70 BC 40 40 00 FC 00 00 00

3D F0 70 D0 7D 00 50 70 BD 30 40 00 FD 00 00 00

3E F0 70 B0 7E 00 30 70 BE 20 40 00 FE 00 00 00

3F F0 70 90 7F 00 10 70 BF 10 40 00 FF 00 00 00

Table 4-5 Recommended LUT Values for 1 Bpp Gray Shade

Address Red Green Blue

00 00 00 00

01 00 F0 00

02 00 00 00

... 00 00 00

FF 00 00 00

unused entries

Table 4-4 Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued)

Index R G B Index R G B Index R G B Index R G B

4: LOOK-UP TABLE (LUT)

S1D13705F00A PROGRAMMING NOTES EPSON 2-13

AND EXAMPLES (X27A-G-002-01)

2 bpp gray shade

When the S1D13705 is conﬁgured for 2 bpp gray shade, the displayed colors are selected from the

ﬁrst four green entries in the Look-Up Table. The remaining entries of the LUT are unused. Each of

the four entries can be set to any of the sixteen possible colors.

Each byte in the display buf fer contains four adjacent pix els. If a bit combination has a v alue of “00”

then the intensity in the green LUT index 0 is displayed. A bit value of “01” results in the intensity

represented by the green in LUT index 1 being displayed. Likewise the bit combination of “10”

displays from the third LUT entry and “11” displays a from the fourth LUT entry.

The following table shows the example values for 2 bit-per-pixel display mode.

Table 4-6 Suggested Values for 2 Bpp Gray Shade

Index Red Green Blue

0 00 00 00

1 00 50 00

2 00 A0 00

3 00 F0 00

4 00 00 00

... 00 00 00

FF 00 00 00

indicates unused entries

4: LOOK-UP TABLE (LUT)

2-14 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

4 bpp gray shade

When the S1D13705 is conﬁgured for 4 bpp gray shade mode the displayed colors are selected from

the green values of the ﬁrst sixteen entries of the Look-Up Table. Each of the sixteen entries can be

set to any of the sixteen possible intensity levels.

Each byte in the display buffer contains two adjacent pixels. If a nibble pattern is “0000” then the

green intensity of LUT index 0 is displayed. A nibble value of “0001” results in the green intensity

in LUT index 1 being displayed. The pattern continues to the nibble pattern of “1111” which results

in the sixteenth intensity of Look-Up Table being displayed.

The following table shows the example values for 4 bit-per-pixel display mode.

Table 4-7 Suggested LUT Values for 4 Bpp Gray Shade

Index Red Green Blue

00 00 00 00

01 00 10 00

02 00 20 00

03 00 30 00

04 00 40 00

05 00 50 00

06 00 60 00

07 00 70 00

08 00 80 00

09 00 90 00

0A 00 A0 00

0B 00 B0 00

0C 00 C0 00

0D 00 D0 00

0E 00 E0 00

0F 00 F0 00

10 00 00 00

... 00 00 00

FF 00 00 00

indicates unused entries

5: ADVANCED TECHNIQUES

S1D13705F00A PROGRAMMING NOTES EPSON 2-15

AND EXAMPLES (X27A-G-002-01)

5ADVANCED TECHNIQUES

This section contains programming suggestions for the following:

• virtual display

• panning and scrolling

• split screen display

5.1 Virtual Display

Virtual display refers to the situation where the image to be viewed is larger than the physical

display. The difference can be in the horizontal, vertical or both dimensions. To view the image, the

display is used as a windo w into the display buffer. At any given time only a portion of the image is

visible. Panning and scrolling are used to view the full image.

The Memory Address Offset register determines the number of horizontal pixels in the virtual

image. The offset register can be used to specify from 0 to 255 additional words for each scan line.

At 1 bpp, 255 words span an additional 4,080 pixels. At 8 bpp, 255 words span an additional 510

pixels.

The maximum vertical size of the virtual image is the result of dividing 81920 bytes of display

memory by the number of bytes on each line (i.e. at 1 bpp with a 320 × 240 panel set for a virtual

width of 640 × 480 there is enough memory for 1024 lines).

Figure 5-1 “Viewport Inside a V irtual Display,” depicts a typical use of a virtual display. The display

panel is 320 × 240 pixels, an image of 640 × 480 pixels can be viewed by navigating a 320 × 240

pixel viewport around the image using panning and scrolling.

Figure 5-1 Viewport Inside a Virtual Display

Registers

Memory Address Offset Register

REG[11h] forms an 8-bit value called the Memory Address Offset. This offset is the number of

additional words on each line of the display. If the offset is set to zero there is no virtual width.

This value does not represent the number of words to be shown on the display. The display width is

set in the Horizontal Display Width register.

Note: This value does not represent the number of words to be shown on the display. The display

width is set in the Horizontal Display Width register.

REG[11h] Memory Address Offset Register

Memory

Address Offset

Bit 7

Memory

Address Offset

Bit 6

Memory

Address Offset

Bit 5

Memory

Address Offset

Bit 4

Memory

Address Offset

Bit 3

Memory

Address Offset

Bit 2

Memory

Address Offset

Bit 1

Memory

Address Offset

Bit 0

320 × 240

Viewport

640 × 480

“Virtual” Display

5: ADVANCED TECHNIQUES

2-16 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

Examples

Example 1

In this example we go thr ough the calculations to displa y a 640 × 480 image on a 320

× 240 panel at 2 bpp.

Step 1: Calculate the number of pixels per word for this color depth.

At 2 bpp each byte is comprised of 4 pixels, therefore each word contains 8 pixels.

pixels_per_word = 16 / bpp = 16 / 2 = 8

Step 2: Calculate the Memory Address Offset register value

We require a total of 640 pixels. The horizontal display re gister will account for 320 pixels,

this leaves 320 pixels for the Memory Address Offset register to account for.

offset = pixels / pixels_per_word = 320 / 8 = 40 = 28h

The Memory Address Offset register, REG[11h], will have to be set to 28h to satisfy the

above condition.

Example 2

From the above, what is the maximum number of lines our image can contain?

Step 1: Calculate the number of bytes on each line.

bytes_per_line = pixels_per_line / pixels_per_byte = 640 / 4 = 160

Each line of the display requires 160 bytes.

Step 2: Calculate the number of lines the S1D13705 is capable of.

total_lines = memory / bytes_per_line = 81920 / 160 = 512

We can display a maximum of 512 lines. Our example image requires 480 lines so this

example can be done.

5.2 Panning and Scrolling

Panning and scrolling describe the operation of moving a physical display viewport about a virtual

image in order to view the entire image a portion at time. For example, after setting up the previous

example (virtual display) and dra wing an image into it we would only be able to view one quarter of

the image. Panning and scrolling are used to reveal the rest of the image.

Panning describes the horizontal (side to side) motion of the vie wport. When panning to the right the

image in the viewport appears to slide to the left. When panning to the left the image to appears to

slide to the right. Scrolling describes the vertical (up and down) motion of the viewport. Scrolling

down causes the image to appear to slide up and scrolling up causes the image to appear to slide

down.

Both panning and scrolling are performed by modifying the start address register. The start address

registers in the S1D13705 are a word offset to the data to be displayed in the top left corner of a

frame. Changing the start address by one means a change on the display of the number of pixels in

one word. The number of pixels in word varies according to the color depth. At 1 bit-per-pixel a

word contains sixteen pix els. At 2 bit-per-pixel there are eight pix els, at 4 bit-per -pixel there are four

pixels and at 8 bit-per-pixel there is two pixels in each word. The number of pixels in each word

represent the ﬁnest step we can pan to the left or right.

When portrait mode (see “7 Har dwar e Rotation” on page 2-25) is enabled the start address registers

become of fsets to bytes. In this mode the step rate for the start address registers if halv ed making for

smoother panning.

5: ADVANCED TECHNIQUES

S1D13705F00A PROGRAMMING NOTES EPSON 2-17

AND EXAMPLES (X27A-G-002-01)

Registers

Screen 1 Start Address Registers

These three registers form the seventeen bit screen 1 start address. Screen 1 is displayed starting at

the top left corner of the display.

In landscape mode these registers form the word offset to the ﬁrst byte in display memory to be

displayed in the upper left corner of the screen. Changing these registers by one will shift the display

image 2 to 16 pixels, depending on the current color depth.

In portrait mode these registers form the offset to the display memory byte where screen 1 will start

displaying. Changing these registers in portrait mode will result in a shift of 1 to 8 pix els depending

on the color depth.

Refer to Table 5-1 to see the minimum number of pixels affected by a change of one to these

registers

REG[0Ch] Screen 1 Display Start Address 0 (LSB)

Start Addr

Bit 7 Start Addr

Bit 6 Start Addr

Bit 5 Start Addr

Bit 4 Start Addr

Bit 3 Start Addr

Bit 2 Start Addr

Bit 1 Start Addr

Bit 0

REG[0Dh] Screen 1 Display Start Address 1 (MSB)

Start Addr

Bit 15 Start Addr

Bit 14 Start Addr

Bit 13 Start Addr

Bit 12 Start Addr

Bit 11 Start Addr

Bit 10 Start Addr

Bit 9 Start Addr

Bit 8

REG[10h] Screen 1 Display Start Address 2 (MSB)

n/a n/a n/a n/a n/a n/a n/a Start Addr

Bit 16

Table 5-1 Number of Pixels Panned Using Start Address

Color Depth (bpp) Pixels per Word Landscape Mode

Number of Pixels Panned Pixels Per Byte Portrait Mode

Number of Pixels Panned

116 16 8 8

28 8 4 4

44 4 2 2

82 2 1 1

5: ADVANCED TECHNIQUES

2-18 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

Examples

For the follo wing e xamples we base our calculations on a 4 bit-per -pixel image displayed on a 256w

× 64h panel. We have set up a virtual size of 320w × 240h. Width is greater than height so we are in

landscape display mode. Refer to Section 2, “Initialization” on page 2-2 and Section 5.1, “Virtual

Display” on page 2-15 for assistance with these settings.

These examples are shown using a C-like syntax.

Example 3

Panning (Right and Left)

To pan to the right increase the start address value by one. To pan to the left decrease the start

address value. Keep in mind that, with the exception of 8 bit-per-pixel portrait display mode, the

display will jump by more than one pixel as a result of changing the start address registers.

Panning to the right.

StartWord = GetStartAddress();

StartWord ++;

SetStartAddress(StartWord);

Panning to the left.

StartWord = GetStartAddress();

StartWord --;

if (StartWord < 0)

StartWord = 0;

SetStartAddress(StartWord);

The routine GetStartAddress() is one which will read the start address registers and return the start

address as a long value. It would be written similar to:

long GetStartAddress()

{return ((REG[10] & 1) * 65536) + (REG[0D] * 256) + (REG[0C]);

}

The routine SetStartAddress() break up its long integer ar gument into three re gister values and store

the values.

void SetStartAddress(long SA)

{REG[0C] = SA & 0xFF;

REG[0D] = (SA >> 8) & 0xFF;

Reg[10] = (SA >> 16) & 0xFF;

}

5: ADVANCED TECHNIQUES

S1D13705F00A PROGRAMMING NOTES EPSON 2-19

AND EXAMPLES (X27A-G-002-01)

Example 4

Scrolling (Up and Down)

To scroll down, increase the value in the Screen 1 Display Start Address Register by the number of

words in one virtual scan line. To scroll up, decrease the value in the Screen 1 Display Start Address

number of bytes required by the physical display and any extra bytes that may be being used for

creating a virtual width on the display.

The previous dimensions are still in effect for this example (i.e. 320w × 240h virtual size, 256h ×

64w physical size at 4 bpp)

Step 1: Determine the number of words in one virtual scanline.

bytes_per_line = pixels_per_line / pixels_per_byte = 320 / 2 = 160

words_per_line = bytes_per_line / 2 = 160 /2 = 80

Step 2: Scroll up or down

To scroll up.

StartWord = GetStartAddress();

StartWord -= words_per_line;

if (StartWord < 0)

StartWord = 0;

SetStartAddress(StartWord);

To scroll down.

StartWord = GetStartAddress();

StartWord += words_per_line;

SetStartAddress(StartWord);

}

5: ADVANCED TECHNIQUES

2-20 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

5.3 Split Screen

Occasionally the need arises to display two different but related images. Take, for example, a game

where the main play area requires rapid updates and game status, displayed at the bottom of the

screen, requires infrequent updates.

The Split Screen feature of the S1D13705 allows a programmer to setup a display in such a manor.

When correctly conﬁgured the programmer has only to update the main area on a regular basis.

Occasionally, as the need arises, the secondary area is updated.

The ﬁgure below illustrates how a 320×240 panel may be conﬁgured to have one image displaying

from scan line 0 to scan line 199 and image 2 displaying from scan line 200 to scan line 239.

Although this example picks speciﬁc values, the split between image 1 and image 2 may occur at

any line of the display.

Figure 5-2 320×240 Single Panel For Split Screen

In split screen operation “Image 1" is taken from the display memory location pointed to by the

Screen 1 Start Address registers and is always located at the top of the screen. “Image 2" is taken

from the display memory location pointed to by the Screen 2 Start Address registers. The line where

“Image 1" end and “Image 2" begins is determined by the Screen 1 Vertical Size register.

Registers

Split screen operation is performed primarily by manipulating three register sets. Screen 1 Start

Address and Screen 2 Start Address determine from where in display memory the ﬁrst and second

images will be taken from. The Vertical Size registers determine how many lines Screen 1 will use.

The following is a description of the registers used to do split screen.

Screen 1 Vertical Size

These two re gisters form a ten bit value which determines the size of screen 1. When the vertical size

is equal to or greater than the physical number of lines being displayed there is no visible effect on

the display. When the vertical size value is less than the number of physical display lines, operation

is like this:

1. From the beginning of a frame to the number of lines indicated by vertical size the display data

will come from the memory area pointed to by the Screen 1 Display Start Address.

2. After vertical size lines have been displayed the system will begin displaying data from the

memory area pointed to by Screen 2 Display Start Address.

Scan Line 0

Image 1...

Scan Line 199

Scan Line 200 Image 2...

Scan Line 239

Screen 1 Vertical Size Registers = 199 lines

REG[13] Screen 1 Vertical Size (LSB)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

REG[14] Screen 1 Vertical Size (MSB)

n/a n/a n/a n/a n/a n/a Bit 9 Bit 8

5: ADVANCED TECHNIQUES

S1D13705F00A PROGRAMMING NOTES EPSON 2-21

AND EXAMPLES (X27A-G-002-01)

On thing that must be pointed out here is that Screen 1 memory is always displayed at the top of the

screen followed by screen 2 memory. This relationship holds true regardless of where in display

memory Screen 1 Start Address and Screen 2 Start Address are pointing. For instance, Screen 2 Start

Address may point to offset zero of display memory while Screen 1 Start Address points to a

location several thousand bytes higher. Screen 1 will still be shown ﬁrst on the display. While not

particularly useful, it is even possible to set screen 1 and screen 2 to the same address.

Screen 2 Start Address Registers

These two registers form the sixteen bit Screen 2 Start Address. Screen 2 is always displayed

immediately follo wing the screen 1 data and will begin at the left-most pix el on a line. K eep in mind

that if the Screen 1 Vertical Size is equal to or greater than the physical display then Screen 2 will

not be shown.

In landscape mode these registers form the word offset to the ﬁrst byte in display memory to be

displayed. Changing these registers by one will shift the display image 2 to 16 pixels, depending on

the current color depth.

The S1D13705 does not support split screen operation in portrait mode. Screen 2 will ne v er be used

if portrait mode is selected.

Refer to Table 5-1 to see the minimum number of pixels affected by a change of one to these

registers

Screen 1 Start Address registers, REG[0C], REG[0D] and REG[10] are discussed in “Section” on

page 2-17.

REG[0Eh] Screen 2 Display Start Address 0 (LSB)

Start Addr

Bit 7 Start Addr

Bit 6 Start Addr

Bit 5 Start Addr

Bit 4 Start Addr

Bit 3 Start Addr

Bit 2 Start Addr

Bit 1 Start Addr

Bit 0

REG[0Fh] Screen 2 Display Start Address 1 (MSB)

Start Addr

Bit 15 Start Addr

Bit 14 Start Addr

Bit 13 Start Addr

Bit 12 Start Addr

Bit 11 Start Addr

Bit 10 Start Addr

Bit 9 Start Addr

Bit 8

5: ADVANCED TECHNIQUES

2-22 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

Examples

Example 5

Display 200 scanlines of ima ge 1 and 40 scanlines of image 2. Ima ge 2 is located ﬁrst

(offset 0) in the display buffer followed immediately by image 1. Assume a 320 × 240

display and a color depth of 4 bpp.

1. Calculate the Scre en 1Vertical Size register values.

vertical_size = 200 = C8h

Write the Vertical Size LSB, REG[13h], with C8h and Vertical Size MSB, REG[14h], with a

00h.

2. Calculate the Screen 1 Start Word Address register values.

Screen 2 is located ﬁrst in display memory, therefore we must calculate the number of bytes

taken up by the screen 2 data.

bytes_per_line = pixels_per_line / pixels_per_byte = 320 / 2 = 160

total bytes = bytes_per_line × lines = 160 × 40 = 6400.

Screen 2 requires 6400 bytes (0 to 6399) therefore the start address offset for screen 1 must be

6400 bytes. (6400 bytes = 3200 words = C80h words)

Set the Screen 1 Start Word Address MSB, REG[0Dh], to 0Ch and the Screen 1 Start Word

Address LSB, REG[0Ch], to 80h.

3. Calculate the Screen 2 Start Word Address register values.

Screen 2 display data is coming from the very be ginning of the display b uffer. All there is to do here

is ensure that both the LSB and MSB of the Screen 2 Start Word Address registers are set to zero.

6: LCD POWER SEQUENCING AND POWER SAVE MODES

S1D13705F00A PROGRAMMING NOTES EPSON 2-23

AND EXAMPLES (X27A-G-002-01)

6 LCD POWER SEQUENCING AND POWER

SAVE MODES

6.1 LCD Power Sequencing

Correct power sequencing is required to prevent long term damage to LCD panels and to avoid

unsightly" lines" during power-up and power-down. Power Sequencing allows the LCD power

supply to discharge prior to shutting down the LCD logic signals.

Proper LCD power sequencing dictates there must be a time delay between the LCD power being

disabled and the LCD signals being shut down. During power-up the LCD signals must be active

prior to or when power is applied to the LCD. The time intervals vary depending on the power

supply design.

The S1D13705 performs automatic power sequencing in response to both software power save

(REG[03h]) or in response to a hardware power save. One frame after a power save mode is set, the

S1D13705 disables LCD power, and the LCD logic signals continue for one hundred and twenty

seven frames allowing the LCD power supply to completely discharge. For most applications the

internal power sequencing is the appropriate choice.

There may be situations where the internal time delay is insufﬁcient to discharge the LCD power

supply before the LCD signals are shut down, or the delay is too long and the designer wishes to

shorten it. This section details the sequences to manually power-up and power-down the LCD

interface.

6.2 Registers

The LCD Po wer (LCDPWR) Override bit forces LCD po wer inacti ve one frame after being toggled.

As long as this bit is "1" LCD power will be disabled.

The Hardware Power Save Enable bit must be set in order to activate hardware power save through

GPIO0.

The Software Po wer Sa v e bits set and reset the softw are po wer sa v e mode. These bits are set to "11"

for normal opertion and set to "00" for power save mode.

LCD logic signals to the display panel are active for 128 frames after setting either hardware or

software power save modes. Power sequencing overide is performed by setting the LCDPWR

Override bit some time before setting a po wer sa ve mode for po wer of f sequences. During po wer on

sequences the power save mode is reset some time before the LCDPWR Override is reset resulting

in the LCD logic signals being active before power is applied to the panel.

REG[03h] Mode Register 2

LCDPWR

Override

Hardware

Power Save

Enable

Software

Power Save

bit 1

Software

Power Save

bit 0

6: LCD POWER SEQUENCING AND POWER SAVE MODES

2-24 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

6.3 LCD Enable/Disable

The descriptions below cover manually powering the LCD panel up and down. Use the sequences

described in this section if the po wer supply connected to the panel requires more than 127 frames to

discharge on po wer -down, or if the panel requires starting the LCD logic well in adv ance of enabling

LCD power. Currently there are no known circumstances where the LCD logic must be active well

in advance of LCD power.

Note: If 127 frame period is to long, blank the display, then reprogram the Horizontal and Vertical siz-

es to produce a shorter frame period before using these methods.

Power On/Enable Sequence

The following is a sequence for manually powering-up an LCD panel if LCD power had to be

applied later than LCD logic.

1. Set REG[03h] bit 3 (LCDPWR Override) to “1”. This ensures that LCD power will be held dis-

abled.

2. Enable LCD logic. This is done by either setting the GPIO0 pin low to disable hardware power

save mode and/or by setting REG[03h] bits 1-0 to "11" to disable software power save.

3. Count “x” Vertical Non-Display Periods (OPTIONAL).

“x” corresponds the length of time LCD logic must be enabled before LCD po wer -up, converted

to the equivalent vertical non-display periods. For example, at 72 HZ counting 36 non-display

periods results in a one half second delay.

4. Set REG[03h] bit 3 to “0” to enable LCD Power.

Power Off/Disable Sequence

The follo wing is a sequence for manually po wering-do wn an LCD panel. These steps w ould be used

if the power supply discharge requirements are larger than the default 127 frames.

1. Set REG[03h] bit 3 (LCDPWR Override) to “1” which will disable LCD Power.

2. Count “x” Vertical Non-Display Periods.

“x” corresponds to the power supply discharge time converted to the equivalent vertical non-dis-

play periods. (see the previous example)

3. Disable the LCD logic by setting the software power save in REG[03h] or setting hardware

power save via GPIO0. Keep in mind that after setting the power save mode there will be 127

frames before the LCD logic signals are disabled.

7: HARDWARE ROTATION

S1D13705F00A PROGRAMMING NOTES EPSON 2-25

AND EXAMPLES (X27A-G-002-01)

7HARDWARE ROTATION

7.1 Introduction To Hardware Rotation

Many of todays applications use the LCD panel in a SwivelView orientation (typically LCD panels

are landscape oriented) . In this case it becomes necessary to “rotate” the displayed image. This

rotation can be done by software at the expense of performance or, as with the S1D13705, it can be

done by hardware with no performance penalty.

This discussion of display rotation is intended to augment the excellent description of the hardware

functionality found in the Hardware Functional Speciﬁcation.

The S1D13705 supports two SwivelView modes: Default SwivelView Mode and Alternate

SwivelView Mode.

7.2 Default SwivelView Mode

Default SwivelView mode was designed to reduce power consumption for SwivelView mode use.

The reduced power consumption comes with certain trade offs.

The most obvious difference between the two modes is that Default Portrait Mode requires the

SwivelView width be a power of two, e.g. a 240-line panel, used in SwivelView mode, requires

setting a virtual width of 256 pixels. Also default SwivelView mode is only capable of scrolling the

display in two line increments.

The beneﬁts to using default SwivelView mode lies in the ability to use a slower input clock and in

reduced power consumption.

The following ﬁgure depicts the ways to envision memory layouts for the S1D13705 in default

SwivelView mode. This example uses a 320 × 240 panel.

Figure 7-1 Relationship Between the Default Mode Screen Image and the Image Refreshed by S1D13705

From the programmers perspecti ve the memory is laid out as shown on the left. The programmer

accesses memory exactly as for a panel of with the dimensions of 240 × 320 setup to hav e a 256 pix el

horizontal stride. The programmer sees memory addresses increasing from A->B and from C->D.

From a hardware perspective the S1D13705 always refreshes the LCD panel in the order B->D and

down to do A->C.

256

image seen by programmer

= image in display buffer

320

SwivelView

window

320

240

start

address

SwivelView

window

display

image refreshed by S1D13705

start

address

physical

memory

7: HARDWARE ROTATION

2-26 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

7.3 Alternate SwivelView Mode

Alternate SwivelView mode does not impose the power of two line width. To rotated the image on

240 line panel requires a portrait stride of 240 pixels. Alternate SwivelView mode is capable of

scrolling by one line at a time in response to changes to the Start Address Registers. However, to

achieve the same frame rate requires a 2 x faster input clock, therefore using more power.

The following ﬁgure depicts the ways to envision memory layouts for the S1D13705 in alternate

SwivelView mode. This example also uses a 480 × 320 panel. Notice that in alternate SwivelView

mode the stride may be as little as 240 pixels.

Figure 7-2 Relationship Between the Alternate Mode Screen Image and the Image Refreshed by S1D13705

From the programmers perspective the memory is laid out as shown on the left. The programmer

accesses memory exactly as for a panel of with the dimensions of 480 × 320. The programmer sees

memory addresses increasing from A->B and from C->D.

From a hardware perspective the S1D13705 always refreshes the LCD panel in the order B->D and

down to do A->C

The greatest factor in selecting alternate Swi v elView mode o v er default Swi v elView mode w ould be

for the ability to obtain an area of contiguous of f screen memory. For example: A 640 × 480 panel in

default SwivelView mode at two bit-per-pixel requires 81920 bytes (80 Kb). There is unused

memory but it is not contiguous. The same situation using alternate SwivelView mode requires

76800 bytes leaving 5120 bytes of contiguous memory available to the application. In fact the

change in memory usage may make the difference between being able to run certain panels in

SwivelView mode or not being able to do so.

image seen by programmer

= image in display buffer

480

SwivelView

window

480

320

start

address

SwivelView

window

display

image refreshed by S1D13705

start

address

physical

memory

7: HARDWARE ROTATION

S1D13705F00A PROGRAMMING NOTES EPSON 2-27

AND EXAMPLES (X27A-G-002-01)

7.4 Registers

This section describes the registers used to set SwivelView mode operation.

The Screen 1 Start Address registers must be set correctly for SwivelView mode. In SwivelView

mode the Start Address registers form a byte offset, as opposed to a word offset, into display

memory.

The initial required offset is the SwivelView mode stride (in bytes) less one.

The line byte count register informs the S1D13705 of the stride, in bytes, between two consecutive

lines of display in SwivelView mode. The Line Byte Count register only affects SwivelView mode

operation and are ignored when the S1D13705 is in landscape display mode.

The SwivelView mode register contains several items for SwivelView mode support.

The ﬁrst is the SwivelView Mode Enable bit. When this bit is “0” the S1D13705 is in landscape

mode and the remainder of the settings in this register as well as the Line Byte Count in REG[1Ch]

are ignored. Set this bit to “1” to enable SwivelView mode.

The SwivelView mode select bit selects between the “Default Mode” and the “Alternate Mode”.

Setting this bit to “0” selects the default SwivelView mode while setting this bit to “1” enables the

alternate SwivelView mode.

SwivelView Mode Memory Clock Select is another power saving measure which can be enabled if

the ﬁnal MCLK value is less than or equal to 25 MHz. Memory Clock Select results in the

S1D13705 temporarily increasing the memory clock circuitry on CPU access and resuming the

slower speed when the access is complete. This results in better performance while using the least

power.

In SwivelView display mode the CLKI (input clock) is routed to the SwivelView section of the

S1D13705 as CLK. From the CLK signal the MCLK v alue can be determined from table 8-8 of the

Hardware Functional Speciﬁcation, document number X27A-A-001-xx. If MCLK is determined to

be less than or equal to 25 MHz then SwivelView Mode Memory Clock Select may be enabled.

REG[0Ch] Screen 1 Start Word Address LSB

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

REG[0Dh] Screen 1 Start Word Address MSB

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8

REG[0Eh] Screen 1 Start Word Address MSB

n/a n/a n/a n/a n/a n/a n/a bit 16

REG[1Ch] Line Byte Count Register

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

REG[1Bh] SwivelView Mode Register

SwivelView

Mode Enable SwivelView

Mode Select n/a n/a n/a SwivelView

Mode Memory

Clock Select

SwivelView

Mode Pixel Clock

Select Bit 1

SwivelView

Mode Pixel Clock

Select Bit 0

7: HARDWARE ROTATION

2-28 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

7.5 Limitations

The only limitation to using Swi v elView mode on the S1D13705 is that split screen operation is not

supported.

A comparison of the two SwivelView modes is as follows:

7.6 Examples

Example 6

Enable default SwivelView mode for a 320×240 panel at 4 bpp.

Before switching to SwivelView mode from landscape mode, display memory should be cleared to

make the user perceived transition smoother. Images in display memory are not rotated

automatically by hardware and a garbled image would be visible for a short period of time if video

memory is not cleared.

If alternate Swi velView is used then the CLK signal is divided in half to get the PCLK signal. If the

Input Clock Divide bit, in register[02] is set we can simply reset the divider. The result of this is a

PCLK of exactly the same frequency as we used for landscape mode and we can use the current

horizontal and vertical non-display periods. If the Input Clock Divide bit is not set then we must

recalculate the frame rate based on the a PCLK value. In this example we will bypass recalculation

of the horizontal and vertical non-display times (frame rate) by selecting the default SwivelView

mode scheme.

1. Calculate and set the Screen 1 Start Word Address register.

OffsetBytes = (Width × BitsPerPixel / 8) - 1 = (256 × 4 / 8) -1 = 127 = 007Fh

(“Width” is the width of the SwivelView mode display - in this case the next power of two

greater than 240 pixels or 256.)

Set Screen1 Display Start Word Address LSB (REG [0Ch]) to 7Fh and Screen1 Display Start

Word Address MSB (REG[0Dh]) to 00h.

2. Calculate the Line Byte Count

The Line Byte Count also must be based on the power of two width.

Table 7-1 Default and Alternate SwivelView Mode Comparison

Item Default SwivelView Mode Alternate SwivelView Mode

Memory Requirements

The width of the rotated image must be a power

of 2. In most cases, a virtual image is required

where the right-hand side of the virtual image is

unused and memory is wasted. For example, a

320 × 480 × 4bpp image would normally

require only 76,800 bytes - possible within the

80K byte address space, but the virtual image is

512 × 480 × 4bpp which needs 122,880 bytes -

not possible.

Does not require a virtual image.

Clock Requirements CLK need only be as fast as the required

PCLK.

MCLK, and hence CLK, need to be 2x PCLK. For

example, if the panel requires a 3MHz PCLK, then

CLK must be 6MHz. Note that 25MHz is the

maximum CLK, so PCLK cannot be higher than

12.5MHz in this mode.

Power Consumption Lowest power consumption. Higher than Default Mode.

Panning Vertical panning in 2 line increments. Vertical panning in 1 line increments.

Performance Nominal performance. Note that performance

can be increased by increasing CLK and setting

MCLK = CLK (REG[1Bh] bit 2 = 1).

Higher performance than Default Mode. Note that

performance can be increased by increasing CLK

and setting MCLK = CLK (REG[1Bh] bit 2 = 1).

7: HARDWARE ROTATION

S1D13705F00A PROGRAMMING NOTES EPSON 2-29

AND EXAMPLES (X27A-G-002-01)

LineByteCount = Width × BitsPerPixel / 8 = 256 × 4 / 8 = 128 = 80h.

Set the Line Byte Count (REG[1C]) to 80h.

3. Enable SwivelView mode.

This example uses the default SwivelView mode scheme. If we do not change the SwivelView

Mode Pixel Clock Select bits then we will not have to recalculate the non-display timings to

correct the frame rate.

Write 80h to the SwivelView Mode Register (REG[1Bh]).

The display is now conﬁgured for SwivelView mode use. Offset zero into display memory will

corresponds to the upper left corner of the display. The only item to keep in mind is that the count

from the ﬁrst pixel of one line to the ﬁrst pixel of the next line (referred to as the “stride”) is 128

bytes.

Example 7

Enable alternate SwivelView mode for a 320x240 panel at 4 bpp.

Note: As we have to perform a frame rate calculation for this mode we need to know the following

panel characteristics: 320 × 240 8-bit color to be run at 80 Hz with a 16 MHz input clock.

As in the previous example, before switching to SwivelView mode, display memory should be

cleared. Images in display memory are not rotated automatically by hardware and the garbled image

would be visible for a short period of time if video memory is not cleared.

1. Calculate and set the Screen 1 Start Word Address register.

OffsetBytes = (Width × BitsPerPixel / 8) - 1 = (240 × 4 / 8) - 1 = 119 = 0077h

Set Screen1 Display Start Word Address LSB (REG [0Ch]) to 77h and Screen1 Display Start

Word Address MSB (REG[0Dh]) to 00h.

2. Calculate the Line Byte Count.

LineByteCount = Width × BitsPerPixel / 8 = 240 × 4 / 8 = 120 = 78h.

Set the Line Byte Count (REG[1C]) to 78h.

3. Enable SwivelView mode.

This example uses the alternate SwivelView mode scheme. We will not change the MCLK

Autoswitch or Pixel Clock Select settings.

Write C0h to the SwivelView Mode register (REG[1Bh])

4. Recalculate the frame rate dependents.

This example assumes the alternate Swi v elVie w mode scheme. In this scheme, without touching the

Pixel Clock Select bits the PCLK value will be equal to CLK/2.

These examples don’t use the Pixel Clock Select bits. The ability to divide the PCLK value down

further than the default values was added to the S1D13705 to support hardware SwivelView mode

on very small panels.

The Pixel Clock v alue has changed so we must calculate horizontal and vertical non-display times to

reach the desired frame rate. Rather than perform the frame rate calculations here I will refer the

reader to the frame rate calculations in “2.3 Frame Rate Calculation” on page 2-3 and simply

“arrive” at the following:

Horizontal Non-Display Period = 88h

Vertical Non-Display Period = 03h

Plugging the values into the frame rate calculations yields:

7: HARDWARE ROTATION

2-30

EPSON

S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

For this example the Horizontal Non-Display register [REG[08h]) needs to be set to 07h and the

Vertical Non-Display register (REG[0Ah]) needs to be set to 03h.

The 16,000,000/2 in the formula above represents the input clock being divided by two when this

alternate SwivelView mode is selected. With the values given for this example we must ensure the

Input Clock Divide bit (REG[02h] b4) is reset (with the given values it was likely set as a result of

the frame rate calculations for landscape display mode).

No other registers need to be altered.

The display is now conﬁgured for SwivelView mode use. Offset zero of display memory

corresponds to the upper left corner of the display. Display memory is accessed exactly as it was for

landscape mode.

As this is the alternate Swi velView mode the power of two stride issue encountered with the default

SwivelView mode is no longer an issue. The stride is the same as the SwivelView mode width. In

this case 120 bytes.

Example 8

Pan the above SwivelView mode image to the right by 4 pixels then scroll it up by 6

pixels.

To pan by four pixels the start address needs to be advanced.

1. Calculate the number of bytes to change start address by.

Bytes = Pixels

BitsPerPixel / 8 = 4

4 / 8 = 2 bytes

2. Increment the start address registers by the just calculated value.

In this case the value write to the start address register will be 81h (7Fh + 2 = 81h)

To scroll by 4 lines we have to change the start address by the offset of four lines of display.

1. Calculate the number of bytes to change start address by.

BytesPerLine = LineByteCount = 128

Bytes = Lines

BytesPerLine = 4

128 = 512 = 200h

2. Increment the start address registers by the just calculated value

In this case 281h (81h + 200h) will be written to the Screen 1 Start Address register set.

Set Screen1 Display Start Word Address LSB (REG[0Ch]) to 81h and Screen1 Display Start

Word Address MSB (REG[0Dh]) to 02h.

FrameRate PCLK

HDP HNDP+()VDP VNDP+()×

-----------------------------------------------------------------------------------------=

FrameRate

16 000 000,,

------------------------------

320 88+()240 3+()×

------------------------------------------------------- 80.69==

8: IDENTIFYING THE S1D13705

S1D13705F00A PROGRAMMING NOTES

EPSON

2-31

AND EXAMPLES (X27A-G-002-01)

DENTIFYING

THE

S1D13705

There are se veral similar products in the 1350x and 1370x LCD controller families. Products which

can share signiﬁcant portions of a generic code base. It may be important for a program to identify

between products at run time.

Identiﬁcation of the S1D13705 can be performed any time after the system has been powered up by

reading REG[00h], the Revision Code register. The six most signiﬁcant bits form the product

identiﬁcation code and the two least signiﬁcant bits form the product revision.

From reset (power on) the steps to identifying the S1D13705 are as follows:

1. Read REG[00h]. Mask off the lower two bits, the revision code, to obtain the product code.

2. The product code for the S1D13705 is 024h.

9: HARDWARE ABSTRACTION LAYER (HAL)

2-32

EPSON

S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

ARDWARE

BSTRACTION

AYER

(HAL)

9.1 Introduction

The HAL is a processor independent programming library provided by Epson. The HAL was

developed to aid the implementation of internal test programs, and provides an easy, consistent

method of programming the S1D13705 on different processor platforms. The HAL also allows for

easier porting of programs between S1D1370x products. Integral to the HAL is an information

structure (HAL_STRUCT) that contains conﬁguration data on clocks, display modes, and default

of a program for a new target display or environment.

Using the HAL keeps sample code simpler, although some programmers may ﬁnd the HAL

functions to be limited in their scope, and may wish to program the S1D13705 without using the

HAL.

9.2 Contents of the HAL_STRUCT

The HAL_STRUCT below is contained in the ﬁle “hal.h” and is required to use the HAL library.

typedef struct tagHalStruct

{

char szIdString[16];

WORD wDetectEndian;

WORD wSize;

BYTE Regs [MAX_REG + 1];

DWORD dwClkI; /* Input Clock Frequency (in kHz) */

DWORD dwDispMem; /* Starting address of display buffer memory */

WORD wFrameRate; /* Desired panel frame rate */

} HAL_STRUCT;

Within the Regs array ia a structure which deﬁnes all the registers described in the

S1D13705

Hardware Functional Speciﬁcation

, document number X27A-A-001-xx. Using the 1375CFG.EXE

utility you can adjust the content of the registers contained in HAL_STRUCT to allow for different

LCD panel timing values and other default settings used by the HAL. In the simplest case, the

program only calls a few basic HAL functions and the contents of the HAL_STRUCT are used to

setup the S1D13705 for operation.

9.3 Using the HAL library

To utilize the HAL library, the programmer must include two “.h” ﬁles in their code. “Hal.h”

contains the HAL library function prototypes and structure deﬁnitions, and “appcfg.h” contains the

instance of the HAL_STRUCT that is deﬁned in “Hal.h” and conﬁgured by 1375CFG.EXE. For a

more thorough example of using the HAL see Section 10.1, “Sample code using the S1D13705

HAL API” on page 2-46.

Note:

Many of the HAL library functions have pointers as parameters. The programmer should be

aware that little validation of these pointers is performed, so it is up to the

programmer to ensure that they adhere to the interface and use valid pointers.

Programmers are recommended to use the highest warning levels of their compiler in

order to verify the parameter types.

9: HARDWARE ABSTRACTION LAYER (HAL)

S1D13705F00A PROGRAMMING NOTES

EPSON

2-33

AND EXAMPLES (X27A-G-002-01)

9.4 API for 13705HAL

This section is a description of the HAL library Application Programmers Interface (API). Updates

and revisions to the HAL may include new functions not included in this documentation.

Table 9-1 HAL Functions

Function Description

Initialization:

seRegisterDevice Registers the S1D13705 parameters with the HAL, calls seInitHal if necessary. seRegisterDevice

MUST be the ﬁrst HAL function called by an application.

seSetInit Programs the S1D13705 for use with the default settings, calls seSetDisplayMode to do the work,

clears display memory. Note: either seSetInit or seSetDisplayMode must be called AFTER calling

seRegisterDevice

General HAL Support:

seGetId Interpret the revision code register to determine chip id

seGetHalVersion Return version information on the HAL library

seGetLastUsableByte Determine the offset of the last unreserved usable byte in the display buffer

seGetBytesPerScanline Determine the number of bytes or memory consumed per scan line in current mode

seGetScreenSize Determine the height and width of the display surface in pixels

seDelay Use the frame rate timing to delay for required seconds (requires registers to be initialized)

seSetHighPerformance Used in color modes less than 8-bpp to toggle the high performance bit on or off

Advanced HAL Functions:

seSplitInit Initialize split screen variables and setup start addresses

seSplitScreen Set the size of either the top or bottom screen

seVirtInit Initialize virtual screen mode setting x and y sizes

seVirtMove pan/scroll the virtual screen surface(s)

Hardware Rotate:

seSetHWRotate Set the hardware rotation to either Portrait or Landscape

seSetPortraitMethod Call before setting hardware portrait mode to set either Default or Alternate Portrait Mode

seSetReg Write a Byte value to the speciﬁed S1D13705 register

seGetReg Read a Byte value from the speciﬁed S1D13705 register

seWriteDisplayBytes Write one or more bytes to the display buffer at the speciﬁed offset

seWriteDisplayWords Write one or more words to the display buffer at the speciﬁed offset

seWriteDisplayDwords Write one or more dwords to the display buffer at the speciﬁed offset

seReadDisplayByte Read a byte from the display buffer from the speciﬁed offset

seReadDisplayWord Read a word from the display buffer from the speciﬁed offset

seReadDisplayDword Read a dword from the display buffer from the speciﬁed offset

Color Manipulation:

seSetLut Write to the Look-Up Table (LUT) entries starting at index 0

seGetLut Read from the LUT starting at index 0

seSetLutEntry Write one LUT entry (red, green, blue) at the speciﬁed index

seGetLutEntry Read one LUT entry (red, green, blue) from the speciﬁed index

seSetBitsPerPixel Set the color depth

seGetBitsPerPixel Determine the current color depth

Drawing:

seSetPixel Draw a pixel at (x,y) in the speciﬁed color

seGetPixel Read pixel’s color at (x,y)

seDrawLine Draw a line from (x1,y1) to (x2,y2) in speciﬁed color

seDrawRect Draw a rectangle from (x1,y1) to (x2,y2) in speciﬁed color

Power Save:

seSetPowerSaveMode Control S1D13705 SW power save mode (enable/disable)

9: HARDWARE ABSTRACTION LAYER (HAL)

2-34 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

Initialization

The follo wing section describes the HAL functions dealing with S1D13705 initialization. Typically

a programmer has only to concern themselves with calls to seRegisterDevice() and seSetInit().

int seRegisterDevice(const LPHAL_STRUC lpHalInfo)

Description: This function registers the S1D13705 device parameters with the HAL library. The

de vice parameters include address range, register values, desired frame rate, etc., and

are stored in the HAL_STRUCT structure pointed to by lpHalInfo. Additionally this

routine allocates system memory as address space for accessing registers and the dis-

play buffer.

Parameters: lpHalInfo - pointer to HAL_STRUCT information structure

Return Value: ERR_OK - operation completed with no problems

ERR_UNKNOWN_DEVICE - the HAL was unable to ﬁnd an S1D13705.

Note: seRegisterDevice() MUST be called before any other HAL functions.

No S1D13705 registers are changed by calling seRegisterDevice().

seSetInit()

Description: Conﬁgures the S1D13705 for operation. This function sets all the S1D13705 control

registers to their default values.

Initialization of the S1D13705 is a two step process to accommodate those programs

(e.g. 1375PLAY.EXE) which do not initialize the S1D13705 on start-up.

Parameters: None

Return Value: ERR_OK - operation completed with no problems

Note: After this call the Look-Up Table will be set to a default state appropriate to the display type.

Unlike S1D1350x HAL versions, this function does not call seSetDisplayMode as this function

does not exist in the 13705 HAL.

9: HARDWARE ABSTRACTION LAYER (HAL)

S1D13705F00A PROGRAMMING NOTES EPSON 2-35

AND EXAMPLES (X27A-G-002-01)

General HAL Support

Functions in this group do not ﬁt into any speciﬁc cate gory of support. The y provide a miscellaneous

range of support for working with the S1D13705.

int seGetId(int * pId)

Description: Reads the S1D13705 revision code register to determine the chip product and revi-

sions. The interpreted value is returned in pID.

Parameters: pId - pointer to an integer which will receive the

controller ID.

S1D13705 values returned in pID are:

- ID_S1D13705_REV0

- ID_UNKNOWN

Other HAL libraries will return their respective controller IDs upon detection of

their controller.

Return Value: ERR_OK - operation completed with no problems

ERR_UNKNOWN_DEVICE - the HAL was unable to identify the display

cotroller. Returned when pID returnsID_UNKNOWN.

void seGetHalVersion(const char ** pVersion, const char ** pStatus, const char **pSta-

tusRevision)

Description: Retrieves the HAL library version. The return pointers are all to ASCII strings. A

typical return would be: *pVersion == “1.01” (HAL version 1.01),*pStatus == “B”

(The 'B' is the beta designator), *pStatusRevision == “5”. The programmer need

only create pointers of const char type to pass as parameters (see Example below).

Parameters: pVersion - Pointer to string to return the version in.

- must point to an allocated string of size VER_SIZE

pStatus - Pointer to a string to return the release status in.

- must point to an allocated string of size

STATUS_SIZE

pStatusRevision - Pointer to return the current revision of status.

- must point to an allocated string of size

STAT_REV_SIZE

Return Value: None

Example: const char *pVersion, *pStatus, *pStatusRevision;

seGetHalVersion( &pVersion, &pStatus, &pStatusRevision);

9: HARDWARE ABSTRACTION LAYER (HAL)

2-36 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

int seSetBitsPerPixel(int BitsPerPixel)

Description: This routine sets the display color depth.

After performing validity checks to ensure the requested video mode can be set the

appropriate registers are changed and the Look-Up Table is set its default values

appropriate to the color depth.

This call is similar to a mode set call on a standard VGA.

Parameter: BitsPerPixel - desired color depth in bits per pixel.

- Valid arguments are: 1, 2, 4, and 8.

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED - possible causes for this error include:

1) the desired frame rate may not be attainable with the speciﬁed input clock

2) the combination of width, height and color depth may require more memory than

is available on the S1D13705.

int seGetBitsPerPixel(int * pBitsPerPixel)

Description: This function reads the S1D13705 re gisters to determine the current color depth and

returns the result in pBitsPerPixel.

Parameters: pBitsPerPixel - pointer to an integer to receive current color depth.

- return values will be: 1, 2, 4, or 8.

Return Value: ERR_OK - operation completed with no problems

int seGetBytesPerScanline(int * pBytes)

Description: Determines the number of bytes per scan line of current display mode. It is assumed

that the registers have already been correctly initialized before seGetBytesPerScan-

line() is called (i.e. after initializing the HAL, setting the Display mode and adjusting

the bits per pixel or other values).

The number of bytes per scanline will include non-displayed bytes if the screen

width is greater the display width, or in Default SwivelView Mode.

Parameters: pBytes - pointer to an integer to receive the number of bytes per scan line

Return Value: ERR_OK - operation completed with no problems

int seGetScreenSize(int * Width, int * Height)

Description: Retrie v es the width and height in pix els of the display surf ace. The width and height

are derived by reading the horizontal and vertical size registers and calculating the

dimensions. Virtual dimensions are not taken into account for this calculation.

When the display is in SwivelView mode the dimensions will be swapped. (i.e. a

640×480 display in SwivelView mode will return a width of 480 and height of 640).

Parameters: Width - pointer to an integer to receive the display width

Height - pointer to an integer to receive the display height

Return value: ERR_OK - the operation completed successfully

9: HARDWARE ABSTRACTION LAYER (HAL)

S1D13705F00A PROGRAMMING NOTES EPSON 2-37

AND EXAMPLES (X27A-G-002-01)

int seDelay(int MilliSeconds)

Description: This function will delay for the length of time speciﬁed in “MilliSeconds” before

returning to the caller.

This function was originally intended for non-PC platforms. Information about how

to access the timers was not always available however we do know frame rate and

can use that for timing calculations.

The S1D13705 registers must be initialized for this function to work correctly. On

the PC platform this is simply a call to the C timing functions and is therefore inde-

pendent of the register settings.

Parameters: MilliSeconds - time to delay in seconds

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED - returned on non-PC platforms when the S1D13705 registers have

not bee initialized

int seGetLastUsableByte(long * plLastByte)

Description: This functions returns a pointer, as a long integer, to the last byte of usable display

memory.

The returned value never changes for the S1D13705.

Parameters: plLastByte - pointer to a long integer to receive the offset to the last byte of

display memory

Return Value: ERR_OK - operation completed with no problems

int seSetHighPerformance(BOOL OnOff)

Description: This function call enables or disable the high performance bit of the S1D13705.

When high performance is enabled then MClk equals PClk for all video display res-

olutions. In the high performance state CPU to video memory performance is

improved at the cost of higher power consumption.

When high performance is disabled then MClk ranges from PClk/1 at 8 bit-per-pix el

to PClk/8 at 1 bit-per-pix el. W ithout high performance CPU to video memory speeds

are slower and the S1D13705 uses less power.

Parameters: OnOff - a boolean value (deﬁned in HAL.H) to indicate whether to

enable of disable high performance.

Return Value: ERR_OK- operation completed with no problems

Advanced HAL Functions

Advanced HAL functions include the functions to support split, virtual and rotated displays. While

the concept for using these features is advanced the HAL makes actually using them easy.

int seSetSwivelViewMethod( int Style )

Description: This selects the SwivelView mode method to be used when seSetHWRotate() is

called to put the S1D13705 into SwivelView mode.

Parameters: Style - call with style set to DEFAULT (-1) to select

Default SwivelView Mode

- call with style set to any other value to select

Alternate SwivelView Mode.

9: HARDWARE ABSTRACTION LAYER (HAL)

2-38 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED - the operation failed.

int seSetHWRotate(int Rotate)

Description: This function sets the rotation scheme according to the value of 'Rotate'. When por-

trait mode is selected as the display rotation the scheme selected is the 'non-X2'

scheme.

Parameters: Rotate - the direction to rotate the display

- Valid arguments for Rotate are: LANDSCAPE

and SwivelView.

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED - the operation failed to complete.

The most likely reason for failing to set a rotate mode is an inability to set the

desired frame rate when setting portrait mode. Other factors which can cause a fail-

ure include having a 0 Hz frame rate or specifying a value other than LANDSCAPE

or SwivelView for the rotation scheme.

int seSplitInit(WORD Scrn1Addr, WORD Scrn2Addr)

Description: This function prepares the system for split screen operation. In order for split screen

to function the starting address in the display buffer for the upper portion(screen 1)

and the lower portion (screen 2) must be speciﬁed. Screen 1 is always displayed

above screen 2 on the display regardless of the location of their start addresses.

Parameters: Scrn1Addr - offset, in bytes, to the start of screen 1

Scrn2Addr - offset, in bytes, to the start of screen 2

Return Value: ERR_OK - operation completed with no problems

Note: It is assumed that the system has been initialized prior to calling seSplitInit().

int seSplitScreen(int Screen, int VisibleScanlines)

Description: Changes the relevant registers to adjust the split screen according to the number of

visible lines requested. 'WhichScreen' determines which screen, 1 or 2, to base the

changes on.

The smallest surface screen 1 can display is one line. This is due to the way the

S1D13705 operates. Setting Screen 1 Vertical Size to zero results in one line of

screen 1 being displayed. The remainder of the display will be screen 2 image.

Parameters: Screen - must be set to 1 or 2 (or use the constants

SCREEN1 or SCREEN2)

VisibleScanlines- number of lines to display for the selected screen

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - argument VisibleScanlines is negative or is greater than

vertical panel size or WhichScreen

is not SCREEN 1 or SCREEN 2.

Note: Changing the number of lines for one screen will also change the number of lines for the other

screen.

seSplitInit() must be called before calling seSplitScreen().

9: HARDWARE ABSTRACTION LAYER (HAL)

S1D13705F00A PROGRAMMING NOTES EPSON 2-39

AND EXAMPLES (X27A-G-002-01)

int seVirtInit(DWORD VirtX, DWORD * VirtY)

Description: This function prepares the system for virtual screen operation. The programmer

passes the desired virtual width in pixels. When the routine returns VirtY will contain

the maximum number of line that can be displayed at the requested virtual width.

Parameter: VirtX - horizontal size of virtual display in pixels.

(Must be greater or equal to physical size of display)

VirtY - pointer to an integer to receive the maximum

number of displayable lines of 'VirtX' width.

Return Value: ERR_OK -operation completed with no problems

ERR_HAL_BAD_ARG - returned in three situations:

1) the virtual width (VirtX) is greater than

the largest possible width

(VirtX varies with color depth and ranges

from 4096 pixels wider than the panel

at 1 bit-per-pixel down to 512 pixels wider than

the panel at 8 bit-per-pixel)

2) the virtual width is less than the physical width or

3) the maximum number of lines becomes less than the

physical number of lines

Note: The system must have been initialized prior to calling seVirtInit()

int seVirtMove(int Screen, int x, int y)

Description: This routine pans and scrolls the display. In the case where split screen operation is

being used, the Screen argument speciﬁes which screen to mo v e. The x and y param-

eters specify, in pixels, the starting location in the virtual image for the top left cor-

ner of the applicable display.

Parameter: Screen - must be set to 1 or 2, or use the constants

SCREEN1 or SCREEN2,

to identify which screen to base calculations on

x - new starting X position in pixels

y - new starting Y position in pixels

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - there are several reasons for this return value:

1) WhichScreen is not SCREEN1 or SCREEN2.

2) the y argument is greater than the last available line

less the screen height.

Note: seVirtInit() must be been called before calling seVirtMove().

9: HARDWARE ABSTRACTION LAYER (HAL)

2-40 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

The Register/Memory Access functions provide access to the S1D13705 re gisters and display buf fer

through the HAL.

int seGetReg(int Index, BYTE * pValue)

Description: Reads the value in the register speciﬁed by index.

Parameters: Index - register index to read

pValue - pointer to a BYTE to receive the register value.

Return Value: ERR_OK - operation completed with no problems

int seSetReg(int Index, BYTE Value)

Description: Writes value speciﬁed in Value to the register speciﬁed by Index.

Parameters: Index - register index to set

Value - value to write to the register

Return Value: ERR_OK - operation completed with no problems

int seReadDisplayByte(DWORD Offset, BYTE *pByte)

Description: Reads a byte from the display buffer at the speciﬁed offset and returns the value in

pByte.

Parameters: Offset - offset, in bytes from start

of the display buffer, to read from

pByte - pointer to a BYTE to return the value in

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - if the value for Addr is greater 80 kb

int seReadDisplayWord(DWORD Offset, WORD *pWord)

Description: Reads a word from the display buffer at the speciﬁed offset and returns the value in

pWord.

Parameters: Offset - offset, in bytes from start of the display buffer, to read

from

pWord - pointer to a WORD to return the value in

Return Value: ERR_OK - operation completed with no problems.

ERR_HAL_BAD_ARG - if the value for Addr is greater than 80 kb.

int seReadDisplayDword(DWORD Offset, DWORD *pDword)

Description: Reads a dword from the display b uffer at the speciﬁed of fset and returns the value in

pDword.

Parameters: Offset - offset from start of the display buffer to read from

pDword - pointer to a DWORD to return the value in

Return Value: ERR_OK - operation completed with no problems.

ERR_HAL_BAD_ARG - if the value for Addr is greater than 80 kb.

9: HARDWARE ABSTRACTION LAYER (HAL)

S1D13705F00A PROGRAMMING NOTES EPSON 2-41

AND EXAMPLES (X27A-G-002-01)

int seWriteDisplayBytes(DWORD Offset, BYTE Value, DWORD Count)

Description: This routine writes one or more bytes to the display buffer at the offset speciﬁed by

Offset. If a count greater than one is speciﬁed all bytes will have the same value.

Parameters: Offset - offset from start of the display buffer to start writing at

Value - BYTE value to write

Count - number of bytes to write

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - if the value for Addr or the value of Addr plus Count is

greater than 80 kb.

Note: There are slight functionality differences between the S1D1370x and the S1D1350x HAL.

int seWriteDisplayWords(DWORD Offset, WORD Value, DWORD Count)

Description: Writes one or more WORDS to the display b uf fer at the of fset speciﬁed by Addr . If a

count greater than one is speciﬁed all WORDS will have the same value.

Parameters: Offset - offset from start of the display buffer

Value - WORD value to write

Count - number of words to write

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - if the value for Addr or if Addr plus Count is greater than

80 kb.

Note: There are slight functionality differences between the S1D1370x and the S1D1350x HAL.

int seWriteDisplayDwords(DWORD Offset, DWORD Value, DWORD Count)

Description: Writes one or more D WORDS to the display b uf fer at the offset speciﬁed by Addr. If

a count greater than one is speciﬁed all DWORDSs will have the same value.

Parameters: Offset - offset from start of the display buffer

Value - DWORD value to write

Count - number of dwords to write

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - if the value for Addr or if Addr plus Count is greater than

80 kb.

Note: There are slight functionality differences between the S1D1370x and the S1D1350x HAL.

Power Save

This section covers the HAL functions dealing with the Power Save features of the S1D13705.

int seSetPowerSaveMode(int PwrSaveMode)

Description: This function sets on the S1D13705’s software selectable power save modes.

Parameters: PwrSaveMode - integer value specifying the desired power save mode.

Acceptable values for PwrSaveMode are:

0 - (software power save mode) in this mode registers and memory are

read/writable. LCD output is forced low.

3 - (normal operation) all outputs function normally.

Return Value: ERR_OK- operation completed with no problems

9: HARDWARE ABSTRACTION LAYER (HAL)

2-42 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

Drawing

The Drawing routines cover HAL functions that deal with displaying pixels, lines and shapes.

int seSetPixel(long x, long y, DWORD Color)

Description: Draws a pixel at coordinates (x,y) in the requested color. This routine can be used for

any color depth.

Parameters: x - horizontal coordinate of the pixel (starting from 0)

y - vertical coordinate of the pixel (starting from 0)

Color - at 1, 2, 4, and 8 bpp Color is an index into the LUT.

At 15 and 16 bpp Color deﬁnes the color directly

(i.e. rrrrrggggggbbbbb for 16 bpp)

Return Value: ERR_OK - operation completed with no problems.

int seGetPixel(long x, long y, DWORD *pColor)

Description: Reads the pixel color at coordinates (x,y). This routine can be used for any color

depth.

Parameters: x - horizontal coordinate of the pixel (starting from 0)

y - vertical coordinate of the pixel (starting from 0)

pColor - at 1, 2, 4, and 8 bpp pColor points to an index into the LUT.

At 15 and 16 bpp pColor points to the color directly

(i.e. rrrrrggggggbbbbb for 16 bpp)

Return Value: ERR_OK - operation completed with no problems.

int seDrawLine(int x1, int y1, int x2, int y2, DWORD Color)

Description: This routine draws a line on the display from the endpoints deﬁned by x1,y1 to the

endpoint x2,y2 in the requested 'Color'.

Currently seDrawLine() only draws horizontal and vertical lines.

Parameters: (x1, y1)- ﬁrst endpoint of the line in pixels

(x2, y2) - second endpoint of the line in pixels (see note below)

Color - color to draw with. 'Color' is an index into the LUT.

Return Value: ERR_OK - operation completed with no problems

Note: Functionality differs from the 1350x HAL.

int seDrawRect(long x1, long y1, long x2, long y2, DWORD Color,

BOOL SolidFill)

Description: This routine draws and optionally ﬁlls a rectangular area of display b uf fer . The upper

right corner is deﬁned by x1,y1 and the lower right corner is deﬁned by x2,y2. The

color, deﬁned by Color, applies both to the border and to the optional ﬁll.

Parameters: x1, y1 - top left corner of the rectangle (in pixels)

x2, y2 - bottom right corner of the rectangle (in pixels)

Color - The color to draw the rectangle outline and ﬁll with

- Color is an index into the Look-Up Table.

SolidFill - Flag whether to ﬁll the rectangle or simply draw the border.

- Set to 0 for no ﬁll, set to non-0 to ﬁll the inside of the rectangle

Return Value: ERR_OK - operation completed with no problems.

9: HARDWARE ABSTRACTION LAYER (HAL)

S1D13705F00A PROGRAMMING NOTES EPSON 2-43

AND EXAMPLES (X27A-G-002-01)

LUT Manipulation

These functions deal with altering the color values in the Look-Up Table.

int seSetLut(BYTE *pLut, int Count)

Description: This routine writes one or more LUT entries. The writes always start with Look-Up

Table index 0 and continue for 'Count' entries.

A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.

The color information is stored in the four most signiﬁcant bits of each byte.

Parameters: pLut - pointer to an array of BYTE lut[16][3]

lut[x][0] == RED component

lut[x][1] == GREEN component

lut[x][2] == BLUE component

Count - the number of LUT entries to write.

Return Value: ERR_OK - operation completed with no problems

int seGetLut(BYTE *pLUT, int Count)

Description: This routine reads one or more LUT entries and puts the result in the byte array

pointed to by pLUT.

A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.

The color information is stored in the four most signiﬁcant bits of each byte.

Parameters: pLUT - pointer to an array of BYTE lut[16][3]

- pLUT must point to enough memory to hold 'Count' x 3 bytes of data.

Count - the number of LUT elements to read.

Return Value: ERR_OK - operation completed with no problems

int seSetLutEntry(int Index, BYTE *pEntry)

Description: This routine writes one LUT entry. Unlike seSetLut, the LUT entry indicated by

'Index' can be any value from 0 to 255.

A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.

The color information is stored in the four most signiﬁcant bits of each byte.

Parameters: Index - index to LUT entry (0 to 255)

pLUT - pointer to an array of three bytes.

Return Value: ERR_OK - operation completed with no problems

int seGetLutEntry(int index, BYTE *pEntry)

Description: This routine reads one LUT entry from any index.

A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.

The color information is stored in the four most signiﬁcant bits of each byte.

Parameters: Index - index to LUT entry (0 to 255)

pEntry - pointer to an array of three bytes

Return Value: ERR_OK - operation completed with no problems

9: HARDWARE ABSTRACTION LAYER (HAL)

2-44 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

9.5 Porting LIBSE to a new target platform

Building Epson Research and Development applications like a simple HelloApp for a new target

platform requires 3 things, the HelloApp code, the 13705 HAL library, and a some standard C

functions (portable ones are encapsulated in our mini C library LIBSE).

Components needed to build 13705 HAL application

For example, when building HELLOAPP.EXE for the Intel 16-bit platform, you need the

HELLOAPP source ﬁles, the 13705 HAL library and its include ﬁles, and some Standard C library

functions (which in this case would be supplied by the compiler as part of its run-time library). As

this is a DOS .EXE application, you do not need to supply start-up code that sets up the chip selects

or interrupts, etc... What if you wanted to build the application for an SH-3 target, one not running

DOS?

Before you can build that application to load onto the target, you need to build a C library for the

target that contains enough of the Standard C functions (like sprintf and strcpy) to let you build the

application. Epson Research and Development supplies the LIBSE for this purpose, but your

compiler may come with one included. You also need to build the 13705 HAL library for the target.

This library is the graphics chip dependent portion of the code. Finally, you need to build the ﬁnal

application, linked together with the libraries described earlier. The follo wing e xamples assume that

you have a copy of the complete source code for the S1D13705 utilities, including the nmake

makeﬁles, as well as a copy of the GNU Compiler v2.7-96q3a for Hitachi SH3. These are available

on the World W ide Web at http://www.eea.epson.com.

Building the LIBSE library for SH3 target example

In the LIBSE ﬁles, there are three main types of ﬁles:

• C ﬁles that contain the library functions.

• assembler ﬁles that contain the target speciﬁc code.

• makeﬁles that describe the build process to construct the library.

The C ﬁles are generic to all platforms, although there are some customizations for targets in the

form of #ifdef LCEVBSH3 code (the ifdef used for the example SH3 target Low Cost Eval Board

SH3). The majority of this code remains constant whichever target you build for.

The assembler ﬁles contain some platform setup code (stacks, chip selects) and jumps into the main

entry point of the C code that is contained in the C ﬁle entry.c. For our example, the assembler ﬁle is

STARTSH3.S and it performs only some stack setup and a jump into the code at _mainEntry

(entry.c).

In the embedded targets, printf (in ﬁle rprintf.c), putchar (putchar.c) and getch (kb .c) resolve to serial

character input/output. For SH3, much of the detail of handling serial IO is hidden in the monitor of

the e v aluation board, b ut in general the primiti v es are fairly straight forw ard, pro viding the ability to

get characters to/from the serial port.

For our tar get example, the nmake makeﬁle is mak esh3.mk. This makeﬁle calls the Gnu compiler at

a speciﬁc location (TOOLDIR), enumerates the list of ﬁles that go into the target and builds a .a

library ﬁle as the output of the build process.

With nmake.exe in your path run:

nmake -fmakesh3.mk

HelloApp Source code

13705 HAL Library

HelloApp C Library Functions (LIBSE for embedded platforms)

9: HARDWARE ABSTRACTION LAYER (HAL)

S1D13705F00A PROGRAMMING NOTES EPSON 2-45

AND EXAMPLES (X27A-G-002-01)

Building the HAL library for the target example

Building the HAL for the target example is less complex because the code is written in C and

requires little platform speciﬁc adjustment. The nmake makeﬁle for our example is

makesh3.mk.This makeﬁle contains the rules for b uilding sh3 objects, the ﬁles list for the library and

the library creation rules. The Gnu compiler tools are pointed to by TOOLDIR.

With nmake in your path run:

nmake -fmakesh3.mk

10: SAMPLE CODE

2-46 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

10SAMPLE CODE

Included in the sample code section are two examples of programing the S1D13705. The ﬁrst

sample uses the HAL to draw a red square, wait for user input then rotates to portrait mode and

draws a blue square. The second sample code performs the same procedures but directly accesses

the registers of the S1D13705. These code samples are for example purposes only.

10.1 Sample code using the S1D13705 HAL API

**===========================================================================

** SAMPLE1.C - Sample code demonstrating a program using the S1D13705 HAL.

**-------------------------------------------------------------------------

** Created 1998, Vancouver Design Centre

**-------------------------------------------------------------------------

** The HAL API code is configured for the following:

** 320x240 Single Color 4-bit STN

** 8 bpp - 70 Hz Frame Rate (6 MHz CLKi)

** High Performance enabled

**===========================================================================

#include <conio.h>

#include <stdio.h>

#include <stdlib.h>

#include <string.h>

#include "hal.h" /* Structures, constants and prototypes. */

#include "appcfg.h" /* HAL configuration information. */

/*--------------------------------------------------------------------------*/

void main(void)

{int ChipId;

** Initialize the HAL.

** The call to seRegisterDevice() actually prepares the HAL library

** for use. The S1D13705 is not accessed, except to read the revision

** code register.

if (ERR_OK != seRegisterDevice(&HalInfo))

{printf("\nERROR: Could not register S1D13705 device.");

exit(1);

}

** Get the product code to verify this is an S1D13705.

seGetId(&ChipId);

if (ID_S1D13705_Rev1 != ChipId)

{printf("\nERROR: Did not detect an S1D13705.");

exit(1);

}

** Initialize the S1D13705.

** This step programs the registers with values taken from

** the HalInfo struct in appcfg.h.

if (ERR_OK != seSetInit())

10: SAMPLE CODE

S1D13705F00A PROGRAMMING NOTES EPSON 2-47

AND EXAMPLES (X27A-G-002-01)

{printf("\nERROR: Could not initialize device.");

exit(1);

}

** The default initialization cleared the display.

** Draw a 100x100 red (color 1) rectangle in the upper

** left corner (0,0) of the display.

seDrawRect(0, 0, 100, 100, 1, TRUE);

** Pause here.

getch();

** Clear the display. Do this by writing 81920 bytes

seWriteDisplayBytes(0, 0, EIGHTY_K);

** Setup portrait mode.

seSetHWRotate(PORTRAIT);

** Draw a solid blue 100x100 rectangle in center of the display.

** This starting co-ordinates, assuming a 320x240 display is

** (320-100)/2 , (240-100)/2 = 110,70.

seDrawRect(110, 70, 210, 170, 2, TRUE);

** Done!

exit(0);

}

10: SAMPLE CODE

2-48 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

10.2 Sample code without using the S1D13705 HAL API

This second sample demonstrates exactly the same sequence as the ﬁrst howerver the HAL is not

used, all manipulation is done by directly accessing the registers.

**===========================================================================

** SAMPLE2.C - Sample code demonstating a direct access of the S1D13705.

**-------------------------------------------------------------------------

** Created 1998, Vancouver Design Centre

**-------------------------------------------------------------------------

** The sample code using direct S1D13705 access

** will configure for the following:

** 320x240 Single Color 4-bit STN

** 8 bpp color depth - 70 Hz Frame Rate (6 MHz CLKi)

** Notes:

** 1) This code is written to be compiled for use under 32-bit

** Windows. In order to function the vxd file S1D13XXX.VXD must

** be in the \WINDOWS\SYSTEM directory.

** 2) Register setup is done with discreet writes rather than being table

** driven. This allows for clear commenting. It is more efficient to

** loop through the array writing each element to a control register.

** 3) The array of register values as produced by 1375CFG.EXE is included

** here. I write the registers directly rather than refer to the register

** array in the sample code.

**===========================================================================

#include <conio.h>

#include <windows.h>

#include <winioctl.h>

#include "ioctl.h"

** Look-Up Table - 16 of 256 elements.

** For this sample only the first sixteen LUT elements are set.

unsigned char LUT[16*3] =

{ 0x00, 0x00, 0x00,/* BLACK */

0x00, 0x00, 0xA0,/* BLUE */

0x00, 0xA0, 0x00,/* GREEN */

0x00, 0xA0, 0xA0,/* CYAN */

0xA0, 0x00, 0x00,/* RED */

0xA0, 0x00, 0xA0,/* PURPLE */

0xA0, 0xA0, 0x00,/* YELLOW */

0xA0, 0xA0, 0xA0,/* WHITE */

0x00, 0x00, 0x00,/* BLACK */

0x00, 0x00, 0xF0,/* LT BLUE */

0x00, 0xF0, 0x00,/* LT GREEN */

0x00, 0xF0, 0xF0,/* LT CYAN */

0xF0, 0x00, 0x00,/* LT RED */

0xF0, 0x00, 0xF0,/* LT PURPLE */

0xF0, 0xF0, 0x00,/* LT YELLOW */

0xF0, 0xF0, 0xF0/* LT WHITE */

};

** Register data.

** These values were generated using 1375CFG.EXE.

** The sample code uses these values but does not refer to this array.

** In a typical application these values would be written to the registers

10: SAMPLE CODE

S1D13705F00A PROGRAMMING NOTES EPSON 2-49

AND EXAMPLES (X27A-G-002-01)

** using a loop.

unsigned char Reg[0x20] =

{0x00, 0x23, 0xC0, 0x03, 0x27, 0xEF, 0x00, 0x00,

0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0x00, 0x00, 0x00

};

#define MEM_SIZE 0x14000/* 80 kb display buffer. */

typedef unsigned short WORD; /* Some useful types */

typedef unsigned long DWORD;

typedef unsigned char BYTE;

typedef BYTE * PBYTE;

#define LOBYTE(w) ((BYTE)(w))

#define HIBYTE(w) ((BYTE)(((WORD)(w) >> 8) & 0xFF))

#define SET_REG(idx, val) (*(pRegs + idx)) = (val)

/*-----------------------------------------------------------------------*/

void main(void)

{PBYTE p13705;

PBYTE pRegs;

PBYTE pMem;

PBYTE pLUT;

int x, y, tmp;

int BitsPerPixel = 8;

int Width = 320;

int Height = 240;

int OffsetBytes;

int rc;

** Get a linear address we can use in our code to access the S1D13705.

** This is only needed to access the S1D13705 on the ISA eval board.

DWORD dwLinearAddress;

rc = IntelGetLinAddressW32(0xF00000, &dwLinearAddress);

if (rc != 0)

{printf("Error getting linear address");

return;

}

p13705 = (PBYTE)dwLinearAddress;

pRegs = p13705 + 0x1FFE0;

** Check the revision code. Exit if we don't find an S1D13705.

if (0x24 != *pRegs)

{printf("Didn't find an S1D13705");

return;

}

** Initialize the chip - after intialization the display will be

** setup for landscape use.

** Normally a loop would be used to write the register array near

** the top of this file to the registers.

** For purposes of documenting the sample code, each register write

** is performed individually.

** Register 01h: Mode Register 0 - Color, 8-bit format 2

SET_REG(0x01, 0x20);

10: SAMPLE CODE

2-50 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

** Register 02h: Mode Register 1 - 8BPP

SET_REG(0x02, 0xC0);

** Register 03h: Mode Register 2 - Normal power mode

SET_REG(0x03, 0x03);

** Register 04h: Horizontal Panel Size - 320 pixels - (320/8)-1 = 39 = 27h

SET_REG(0x04, 0x27);

** Register 05h: Vertical Panel Size LSB - 240 pixels

** Register 06h: Vertical Panel Size MSB - (240 - 1) = 239 = EFh

SET_REG(0x05, 0xEF);

SET_REG(0x06, 0x00);

** Register 07h - FPLINE Start Position - not used by STN

SET_REG(0x07, 0x00);

** Register 08h - Horizontal Non-Display Period = (Reg[08] + 4) * 8

** = (0+4) * 8 = 32 pels

** - HNDP and VNDP are calculated to achieve the

** desired frame rate according to:

** PCLK

** Frame Rate = ---------------------------

** (HDP + HNDP) * (VDP + VNDP)

SET_REG(0x08, 0x00);

** Register 09h - FPFRAME Start Position - not used by STN

SET_REG(0x09, 0x00);

** Register 0Ah - Vertical Non-Display Register = 3 lines

** -

Calculated in conjunction with register 08h (HNDP) to

** achieve the desired frame rate.

SET_REG(0x0A, 0x03);

** Register 0Bh - MOD Rate - not used by this panel

SET_REG(0x0B, 0x00);

** Register 0Ch - Screen 1 Start Word Address LSB

** Register 0Dh - Screen 1 Start Word Address MSB

** - Start address should be set to 0

SET_REG(0x0C, 0x00);

SET_REG(0x0D, 0x00);

** Register 0Eh - Screen 2 Start Word Address LSB

** Register 0Fh - Screen 2 Start Word Address MSB

** - Set this start address to 0 too

SET_REG(0x0E, 0x00);

SET_REG(0x0F, 0x00);

SET_REG(0x10, 0x00); /* Screen1/Screen2 Start Address High bits. */

** Register 11h - Memory Address Offset

** - Used for setting memory to a width greater than the

10: SAMPLE CODE

S1D13705F00A PROGRAMMING NOTES EPSON 2-51

AND EXAMPLES (X27A-G-002-01)

display size. Usually set to 0 during initialization

** and programmed to desired value later.

SET_REG(0x11, 0x00);

** Register 12h - Screen 1 Vertical Size LSB

** Register 13h - Screen 1 Vertical Size MSB

** - Set to maximum (i.e. 0x3FF). This register is used

** for split screen operation. Normally it is set to

** maximum value.

SET_REG(0x12, 0xFF);

SET_REG(0x13, 0x03);

** Look-Up Table registers

** The LUT is programmed at the end of the initialization sequence.

** Register 18h - GPIO Configuration - set to 0

** -

'0' configures the GPIO pins for input (power on default)

SET_REG(0x18, 0x00);

** Register 19h - GPIO Status - set to 0

** - This step has no real purpose. It sets the GPIO

** pins low should GPIO be set as outputs.

SET_REG(0x19, 0x00);

** Register 1Ah - Scratch Pad - set to 0

** - Use this register to store whatere state data your

** system may require.

SET_REG(0x1A, 0x00);

** Register 1Bh - Portrait Mode - set to 0 - disable portrait mode

SET_REG(0x1B, 0x00);

SET_REG(0x0C, 0x00);

** Look-Up Table

** In this example we only set the first sixteen LUT entries.

** In typical use all 256 entries would be setup.

** Register 15h - Look-Up Table Address

** -

Set to 0 to start RGB sequencing at the first LUT entry.

SET_REG(0x15, 0x00);

** Register 17h - Look-Up Table Data

** - Write 16 RGB triplets to the LUT.

pLUT = LUT;

for (tmp = 0; tmp < 16; tmp++)

{SET_REG(0x17, *pLUT);// Set Red

pLUT++;

SET_REG(0x17, *pLUT);// Set Green

pLUT++;

SET_REG(0x17, *pLUT);// Set Blue

10: SAMPLE CODE

2-52 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

pLUT++;

}

** Clear all of video memory by writing 81920 bytes of 0.

pMem = p13705;

for (tmp = 0; tmp < MEM_SIZE; tmp++)

{*pMem = 0;

pMem++;

};

** Draw a 100x100 red rectangle in the upper left corner (0,0)

** of the display.

for (y = 0; y < 100; y++)

{/*

** Set the memory pointer at the start of each line.

Pointer = MEM_OFFSET + (Y * Line_Width * BPP / 8) + (X * BPP / 8)

pMem = p13705 + (y * 320 * BitsPerPixel / 8) + 0;

for (x = 0; x < 100; x++)

{*pMem = 0x4;/* Draw a pixel with LUT color 4 */

pMem++;

}

** Wait for the user to press a key before continuing.

printf("Press any key to continue");

getch();

** Set and use PORTRAIT mode.

** Clear the display, and all of video memory, by writing 81920 bytes

of 0. This is done because an image in display memory is not rotated

** when the switch to portrait display mode occurs.

pMem = p13705;

for (tmp = 0; tmp < MEM_SIZE; tmp++)

{*pMem = 0;

pMem++;

};

** We will use the default portrait mode scheme so we have to adjust

** the ROTATED width to be a power of 2.

** (NOTE: current height will become the rotated width)

tmp = 1;

while (Height > (1 << tmp))

tmp++;

Height = (1 << tmp);

OffsetBytes = Height * BitsPerPixel / 8;

** Set:

1) Line Byte Count to size of the ROTATED width (i.e. current height)

2) Start Address to the offset of the width of the ROTATED display.

** (in portrait mode the start address registers point to bytes)

SET_REG(0x1C, (BYTE)OffsetBytes);

10: SAMPLE CODE

S1D13705F00A PROGRAMMING NOTES EPSON 2-53

AND EXAMPLES (X27A-G-002-01)

OffsetBytes--;

SET_REG(0x0C, LOBYTE(OffsetBytes));

SET_REG(0x0D, HIBYTE(OffsetBytes));

** Set Portrait mode.

Use the non-X2 (default) scheme so we don't have to re-calc the frame

** rate. MCLK will be <= 25 MHz so we can leave auto-switch enabled.

SET_REG(0x1B, 0x80);

** Draw a solid blue 100x100 rectangle centered on the display.

** Starting co-ordinates, assuming a 320x240 display are:

** (320-100)/2 , (240-100)/2 = 110,70.

for (y = 70; y < 180; y++)

{/*

** Set the memory pointer at the start of each line.

Pointer = MEM_OFFSET + (Y * Line_Width * BPP / 8) + (X * BPP / 8)

NOTICE: as this is default portrait mode, the width is a power

of two. In this case, we use a value of 256 pixels for

our calculations instead of the panel dimension of 240.

return -1;

Arr[0] = physaddr;

Arr[1] = 4 * 1024 * 1024;

rc = DeviceIoControl(hDriver, IOCTL_SED_MAP_PHYSICAL_MEMORY,

&Arr[0], 2 * sizeof(ULONG), &retVal, sizeof(ULONG),

&cbReturned, NULL);

if (rc)*linaddr = retVal;

** Close the handle.

** This will dynamically UNLOAD the Virtual Device for Win95.

CloseHandle(hDriver);

if (rc)return 0;

return -1;

}

10: SAMPLE CODE

2-54 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

10.3 Header Files

The header ﬁles included here are the required for the HAL sample to compile correctly.

**===========================================================================

** HAL.H - Header file for use with programs written to use the S1D13705 HAL.

**---------------------------------------------------------------------------

** Created 1998, Vancouver Design Centre

**===========================================================================

#ifndef _HAL_H_

#define _HAL_H_

#include "hal_regs.h"

/*-------------------------------------------------------------------------*/

typedef unsigned char BYTE;

typedef unsigned short WORD;

typedef unsigned long DWORD;

typedef unsigned int UINT;

typedef int BOOL;

#ifdef INTEL

typedef BYTE far *LPBYTE;

typedef WORD far *LPWORD;

typedef UINT far *LPUINT;

typedef DWORD far *LPDWORD;

#else

typedef BYTE *LPBYTE;

typedef WORD *LPWORD;

typedef UINT *LPUINT;

typedef DWORD *LPDWORD;

#endif

#ifndef LOBYTE

#define LOBYTE(w) ((BYTE)(w))

#endif

#ifndef HIBYTE

#define HIBYTE(w) ((BYTE)(((UINT)(w) >> 8) & 0xFF))

#endif

#ifndef LOWORD

#define LOWORD(l) ((WORD)(DWORD)(l))

#endif

#ifndef HIWORD

#define HIWORD(l) ((WORD)((((DWORD)(l)) >> 16) & 0xFFFF))

#endif

#ifndef MAKEWORD

#define MAKEWORD(lo, hi) ((WORD)(((WORD)(lo)) | (((WORD)(hi)) << 8)) )

#endif

#ifndef MAKELONG

#define MAKELONG(lo, hi) ((long)(((WORD)(lo)) | (((DWORD)((WORD)(hi))) << 16)))

#endif

#ifndef TRUE

#define TRUE 1

#endif

#ifndef FALSE

#define FALSE 0

#endif

#define OFF 0

#define ON 1

#define SCREEN1 1

#define SCREEN22

** Constants for HW rotate support

#define DEFAULT 0

10: SAMPLE CODE

S1D13705F00A PROGRAMMING NOTES EPSON 2-55

AND EXAMPLES (X27A-G-002-01)

#define LANDSCAPE 1

#define PORTRAIT2

#ifndef NULL

#ifdef __cplusplus

#define NULL 0

#else

#define NULL ((void *)0)

#endif

/*-------------------------------------------------------------------------*/

** SIZE_VERSION is the size of the version string (eg. "1.00")

** SIZE_STATUS is the size of the status string (eg. "b" for beta)

** SIZE_REVISION is the size of the status revision string (eg. "00")

#define SIZE_VERSION 5

#define SIZE_STATUS 2

#define SIZE_REVISION 3

#ifdef ENABLE_DPF /* Debug_printf() */

#define DPF(exp) printf(#exp "\n")

#define DPF1(exp) printf(#exp " = %d\n", exp)

#define DPF2(exp1, exp2) printf(#exp1 "=%d " #exp2 "=%d\n", exp1, exp2)

#define DPFL(exp) printf(#exp " = %x\n", exp)

#else

#define DPF(exp) ((void)0)

#define DPF1(exp) ((void)0)

#define DPFL(exp) ((void)0)

#endif

/*-------------------------------------------------------------------------*/

enum

{

ERR_OK = 0, /* No error, call was successful. */

ERR_FAILED, /* General purpose failure. */

ERR_UNKNOWN_DEVICE, /* */

ERR_INVALID_PARAMETER, /* Function was called with invalid parameter. */

ERR_HAL_BAD_ARG,

ERR_TOOMANY_DEVS

};

/*******************************************

* Definitions for seGetId()

*******************************************/

#define PRODUCT_ID 0x24

enum

{ID_UNKNOWN,

ID_S1D13705_Rev1

};

#define MAX_MEM_ADDR81920 - 1

#define EIGHTY_K81920

#define MAX_DEVICE 10

#define SE_RSVD0

/*******************************************

* Definitions for Internal calculations.

*******************************************/

#define MIN_NON_DISP_X 32

#define MAX_NON_DISP_X 256

#define MIN_NON_DISP_Y 2

#define MAX_NON_DISP_Y 64

enum

{RED,

GREEN,

BLUE

};

10: SAMPLE CODE

2-56 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

/*************************************************************************/

typedef struct tagHalStruct

{char szIdString[16];

WORD wDetectEndian;

WORD wSize;

BYTE Reg[MAX_REG + 1];

DWORD dwClkI;/* Input Clock Frequency (in kHz) */

DWORD dwDispMem;/* */

WORD wFrameRate;/* */

} HAL_STRUCT;

typedef HAL_STRUCT * PHAL_STRUCT;

#ifdef INTEL_16BIT

typedef HAL_STRUCT far * LPHAL_STRUCT;

#else

typedef HAL_STRUCT * LPHAL_STRUCT;

#endif

/*=========================================================================*/

/* FUNCTION PROTO-TYPES */

/*=========================================================================*/

/*---------------------------- Initialization -----------------------------*/

int seRegisterDevice( const LPHAL_STRUCT lpHalInfo );

int seSetInit( void );

int seInitHal( void );

/*----------------------------- Miscellaneous -----------------------------*/

int seGetId( int *pId );

void seGetHalVersion( const char **pVersion, const char **pStatus,

const char **pStatusRevision );

int seSetBitsPerPixel( int nBitsPerPixel );

int seGetBitsPerPixel( int *pBitsPerPixel );

int seGetBytesPerScanline( int *pBytes );

int seGetScreenSize( int *width, int *height );

void seDelay( int nMilliSeconds );

int seGetLastUsableByte( long *LastByte );

int seSetHighPerformance( BOOL OnOff );

/*------------------------------- Advanced --------------------------------*/

int seSetHWRotate( int nMode );

int seSplitInit( WORD Scrn1Addr, WORD Scrn2Addr );

int seSplitScreen( int WhichScreen, int VisibleScanlines );

int seVirtInit( int xVirt, long *yVirt );

int seVirtMove( int nWhichScreen, int x, int y );

/*------------------------ Register/Memory Access -------------------------*/

int seGetReg( int index, BYTE *pValue );

int seSetReg( int index, BYTE value );

int seReadDisplayByte( DWORD offset, BYTE *pByte );

int seReadDisplayWord( DWORD offset, WORD *pWord );

int seReadDisplayDword( DWORD offset, DWORD *pDword );

int seWriteDisplayBytes( DWORD addr, BYTE val, DWORD count );

int seWriteDisplayWords( DWORD addr, WORD val, DWORD count );

int seWriteDisplayDwords( DWORD addr, DWORD val, DWORD count );

/*---------------------------------- Power Save ---------------------------*/

int seHWSuspend( int nDevID, BOOL val );

int seSetPowerSaveMode( int nDevID, int PowerSaveMode );

/*----------------------------------- Drawing -----------------------------*/

int seDrawLine( int x1, int y1, int x2, int y2, DWORD color );

int seDrawRect( int x1, int y1, int x2, int y2, DWORD color, BOOL Solidfill );

/*------------------------------ Color ------------------------------------*/

int seSetLut( BYTE *pLut );

int seGetLut( BYTE *pLut );

int seSetLutEntry( int index, BYTE *pEntry );

int seGetLutEntry( int index, BYTE *pEntry );

#endif /* _HAL_H_ */

**===========================================================================

10: SAMPLE CODE

S1D13705F00A PROGRAMMING NOTES EPSON 2-57

AND EXAMPLES (X27A-G-002-01)

** APPCFG.H - Application configuration information.

**---------------------------------------------------------------------------

** Created 1998 - Vancouver Design Centre

**---------------------------------------------------------------------------

** The data in this file was generated using 1375CFG.EXE.

** The configureation parameters chosen were:

** 320x240 Single Color 4-bit STN

** 4 bpp - 100 Hz Frame Rate (12 MHz CLKi)

** High Performance enabled

**===========================================================================

/************************************************************/

/* 13705 HAL HDR (do not remove) */

/* HAL_STRUCT Information generated by 1375CFG.EXE */

/* */

/* Include this file ONCE in your primary source file */

/************************************************************/

HAL_STRUCT HalInfo =

{

"13705 HAL EXE", /* ID string */

0x1234, /* Detect Endian */

sizeof(HAL_STRUCT), /* Size */

0x00, 0x20, 0xC0, 0x03, 0x27, 0xEF, 0x00, 0x00,

0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

6000, /* ClkI (kHz) */

0xF00000, /* Display Address */

70, /* Panel Frame Rate (Hz) */

};

**===========================================================================

** HAL_REGS.H

**---------------------------------------------------------------------------

** Created 1998, Epson Research & Development

** Vancouver Design Center.

**===========================================================================

#ifndef __HAL_REGS_H__

#define __HAL_REGS_H__

** 13705 register names

#define REG_REVISION_CODE 0x00

#define REG_MODE_REGISTER_0 0x01

#define REG_MODE_REGISTER_1 0x02

#define REG_MODE_REGISTER_2 0x03

#define REG_HORZ_PANEL_SIZE 0x04

#define REG_VERT_PANEL_SIZE_LSB 0x05

#define REG_VERT_PANEL_SIZE_MSB 0x06

#define REG_FPLINE_START_POS 0x07

#define REG_HORZ_NONDISP_PERIOD 0x08

#define REG_FPFRAME_START_POS 0x09

#define REG_VERT_NONDISP_PERIOD 0x0A

#define REG_MOD_RATE 0x0B

#define REG_SCRN1_START_ADDR_LSB 0x0C

10: SAMPLE CODE

2-58 EPSON S1D13705F00A PROGRAMMING NOTES

AND EXAMPLES (X27A-G-002-01)

#define REG_SCRN1_START_ADDR_MSB 0x0D

#define REG_SCRN2_START_ADDR_LSB 0x0E

#define REG_SCRN2_START_ADDR_MSB 0x0F

#define REG_SCRN_START_ADDR_OVERFLOW 0x10

#define REG_MEMORY_ADDR_OFFSET 0x11

#define REG_SCRN1_VERT_SIZE_LSB 0x12

#define REG_SCRN1_VERT_SIZE_MSB 0x13

#define REG_LUT_ADDR 0x15

#define REG_LUT_BANK_SELECT 0x16

#define REG_LUT_DATA 0x17

#define REG_GPIO_CONFIG 0x18

#define REG_GPIO_STATUS 0x19

#define REG_SCRATCHPAD 0x1A

#define REG_PORTRAIT_MODE 0x1B

#define REG_LINE_BYTE_COUNT 0x1C

#define REG_NOT_PRESENT_1 0x1D

** WARNING!!! MAX_REG must be the last available register!!!

#define MAX_REG 0x1D

#endif /* __HAL_REGS_H__ */

/*----------------------------------------------------------------------------

** Module Name:

** ioctl.h

** Abstract:

** Include file for S1D13xxx PCI Board Driver.

** Define the IOCTL codes we will use. The IOCTL code contains a command

** identifier, plus other information about the device, the type of access

** with which the file must have been opened, and the type of buffering.

**----------------------------------------------------------------------------

#define SED_TYPE FILE_DEVICE_CONTROLLER

// The IOCTL function codes from 0x800 to 0xFFF are for customer use.

#define IOCTL_SED_QUERY_NUMBER_OF_PCI_BOARDS \

CTL_CODE( SED_TYPE, 0x900, METHOD_BUFFERED, FILE_ANY_ACCESS)

#define IOCTL_SED_MAP_PCI_BOARD \

CTL_CODE( SED_TYPE, 0x901, METHOD_BUFFERED, FILE_ANY_ACCESS)

#define IOCTL_SED_MAP_PHYSICAL_MEMORY \

CTL_CODE( SED_TYPE, 0x902, METHOD_BUFFERED, FILE_ANY_ACCESS)

#define IOCTL_SED_UNMAP_LINEAR_MEMORY \

CTL_CODE( SED_TYPE, 0x903, METHOD_BUFFERED, FILE_ANY_ACCESS)

S1D13705F00A

Embedded Memory LCD Controller

Utilities

 
CONTENTS
 
S1D13705F00A UTILITIES 
 
EPSON
 
3-i
CONTENTS
1 1375CFG C
 
ONFIGURATION
 
 P
 
ROGRAM
 
......................................................................................3-1
 
1.1 Introduction....................................................................................................................................3-1
1.2 Program Requirements .................................................................................................................3-1
Installation..................................................................................................................................3-1
Usage.........................................................................................................................................3-1
1.3 CFG Tab........................................................................................................................................3-2
Panel Information.......................................................................................................................3-3
Miscellaneous Options...............................................................................................................3-5
System.......................................................................................................................................3-6
LUT Control................................................................................................................................3-7
Message Bar..............................................................................................................................3-8
1.4 REGS Tab.....................................................................................................................................3-9
1.5 Buttons ........................................................................................................................................3-10
Open ........................................................................................................................................3-10
Save.........................................................................................................................................3-11
Help..........................................................................................................................................3-11
Exit...........................................................................................................................................3-11
1.6 Comments...................................................................................................................................3-12
 
2 1375SHOW D
 
EMONSTRATION
 
 P
 
ROGRAM
 
................................................................................3-13
 
2.1 1375SHOW .................................................................................................................................3-13
S1D13705 Supported Evaluation Platforms ............................................................................3-13
Installation................................................................................................................................3-13
Usage.......................................................................................................................................3-14
Comments................................................................................................................................3-14
Program Messages..................................................................................................................3-15
 
3 1375SPLT D
 
ISPLAY
 
 U
 
TILITY
 
..................................................................................................3-16
 
3.1 1375SPLT ...................................................................................................................................3-16
S1D13705 Supported Evaluation Platforms ............................................................................3-16
Installation................................................................................................................................3-16
Usage.......................................................................................................................................3-17
1375SPLT Example.................................................................................................................3-17
Program Messages..................................................................................................................3-18
 
4 1375VIRT D
 
ISPLAY
 
 U
 
TILITY
 
...................................................................................................3-19
 
4.1 1375VIRT ....................................................................................................................................3-19
S1D13705 Supported Evaluation Platforms ............................................................................3-19
Installation................................................................................................................................3-19
Usage.......................................................................................................................................3-20
1375VIRT Example..................................................................................................................3-20
 Program Messages.................................................................................................................3-21
 
5 1375PLAY D
 
IAGNOSTIC
 
 U
 
TILITY
 
............................................................................................3-22
 
5.1 1375PLAY ...................................................................................................................................3-22
S1D13705 Supported Evaluation Platforms ............................................................................3-22
Installation................................................................................................................................3-22
Usage.......................................................................................................................................3-23
1375PLAY Example.................................................................................................................3-24
Scripting...................................................................................................................................3-24
Comments................................................................................................................................3-24
Program Messages..................................................................................................................3-25
 
6 1375BMP D
 
EMONSTRAION
 
 P
 
ROGRAM
 
....................................................................................3-26
 
6.1 1375BMP.....................................................................................................................................3-26
Installation................................................................................................................................3-26

 
CONTENTS
 
3-ii
 
EPSON
 
S1D13705F00A UTILITIES 
 
Usage ......................................................................................................................................3-26
Comments ...............................................................................................................................3-26
Program Messages..................................................................................................................3-27
 
7 1375PWR P
 
OWER
 
 S
 
AVE
 
 U
 
TILITY
 
...........................................................................................3-28
 
7.1 1375PWR....................................................................................................................................3-28
S1D13705 Supported Evaluation Platforms............................................................................3-28
Installation................................................................................................................................3-28
Usage ......................................................................................................................................3-29
Program Messages..................................................................................................................3-29

 
CONTENTS
 
S1D13705F00A UTILITIES 
 
EPSON
 
3-iii
List of Figures
 
Figure 1-1 1375CFG Window................................................................................................................3-2
Figure 1-2 Panel Information.................................................................................................................3-3
Figure 1-3 Miscellaneous Options.........................................................................................................3-5
Figure 1-4 System Options....................................................................................................................3-6
Figure 1-5 ERROR: Frame Rate ...........................................................................................................3-6
Figure 1-6 ERROR: Zero Frame Rate...................................................................................................3-6
Figure 1-7 Look-Up Table Control.........................................................................................................3-7
Figure 1-8 REGS Window .....................................................................................................................3-9
Figure 1-9 1375CFG File Open Dialog................................................................................................3-10
Figure 1-10 ERROR: Unable to read HAL.............................................................................................3-10
Figure 1-11 1375CFG Save As Dialog..................................................................................................3-11
Figure 1-12 ERROR: Unable to read HAL.............................................................................................3-11
 
List of Table
 
Table 1-1 MCLK to PCLK Ratios..........................................................................................................3-5

1: 1375CFG CONFIGURATION PROGRAM

S1D13705F00A UTILITIES (X27A-B-001-01)

EPSON

3-1

1 1375CFG C

ONFIGURATION

ROGRAM

1.1 Introduction

1375CFG is 32-bit Windows program designed to calculate register values for the S1D13705. The

user enters data such as the input clock frequency, panel width and height, and other panel speciﬁc

information. After calculating the register values the information can be used to conﬁgure

ex ecutable ﬁles based on the S1D13705 Hardware Abstraction Layer (HAL) or written to ASCII text

ﬁles.

1375CFG can:

• Read programs, based on the S1D13705 HAL, modify the settings and write the changes back to

the ﬁle. The ability to read, modify and write executable ﬁles bypasses having to recompile after

conﬁguration changes.

• Write C header ﬁles containing register settings which then can be used to initialize the S1D13705

registers in programs which do not use the HAL.

• Write ASCII text ﬁles containing a list of the registers and the register values and the input clock

and frame rate the register calculations are based on.

1.2 Program Requirements

This program is designed to run under Windows 95/98 or Windows NT.

Installation

There is no installation program for 1375CFG. Installation to a local drive is done by copying

1375CFG.EXE and 1375CFG.HLP to your hard dri ve and optionally creating a link on the W indo ws

desktop for easy access to the program.

Usage

Open the drive and folder where you copied 1375CFG.EXE and double click the icon to start the

program. Optionally, if you created a link to the program on your desktop, double click the link icon.

After starting you will be presented with a tabbed dialog box containing four buttons and two tabs:

CFG and REGS. The follo wing sections will describe the using the tabs follo wed by a description of

the buttons.

X27A-B-001-01

1: 1375CFG CONFIGURATION PROGRAM

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1.3 CFG Tab

Upon opening 1375CFG the user is present with a window which appears as in Figure 1-1.

The CFG tab is the dominant portion of the window and consists of four main sections: Panel

information (includes Dimensions), Look-Up Table, Miscellaneous Options, and System settings.

Each of these sections will be discussed in detail.

Figure 1-1 1375CFG Window

1: 1375CFG CONFIGURATION PROGRAM

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Panel Information

Figure 1-2 Panel Information

The panel information portion of CFG tab describes the panel to be connected to the S1D13705.

This section of the 1375CFG dialog describes the panel connected to the S1D13705. Each of the

settings are described brieﬂy below.

•

Mono / Color

- selects whether the attached panel is monochrome or color.

Select mono for monochrome panels or color for color panels. This option is STN speciﬁc and is

disabled if TFT is selected.

•

Single / Dual

- selects whether the panel is a single STN or dual STN.

Select single for a single panel or dual for a dual panel. This option is STN speciﬁc and is

disabled if TFT is selected.

•

STN / TFT

- determines the technology used to construct the panel.

Select STN for passive panels or TFT for active panels. Selecting STN enables all the STN

options and disables (grays out) the TFT speciﬁc settings. Selecting TFT enables the TFT

settings and disables STN speciﬁc settings.

•

4 Bit / 8 Bit

- these setting select the data width the panel requires.

These radio buttons are STN/TFT speciﬁc. When STN is selected the options are “4 Bit” and “8

Bit”. Selecting a TFT type panel changes these options to “9 Bit” and “12 Bit”. Select the data

width as appropriate for your panel.

Note:

panel data width is not the same as color depth.

•

Dimensions

- the two boxes in the upper right corner of the CFG tab allow

selecting the panel dimensions.

In the left selection box enter the panel width in pixels and in the right selection box enter the

panel height in pixels.

Values in the selection boxes can be either chosen from the drop-down list or typed directly into

the edit portion of the selection box.

•

Mask FPSHIFT

- when selected causes the signal FPSHIFT to be masked.

This option is required by most ne wer monochrome panels. Whenever either color panel or TFT

is selected this option is disabled.

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S1D13705F00A UTILITIES (X27A-B-001-01)

•

Format 2

- determines the data clocking format for “8 Bit” single color panels.

8-bit single color panels typically use one of two data clocking formats arbitrarily named

“format 1” and “format 2”. Selecting “format 2” instructs the S1D13705 to use the second color

panel data format.

Most newer panels and, to date, all color panels smaller than 640x480 use “format 2”. Setting

this attribute incorrectly will result in a garbled display but will not damage the panel. The

display may appear “cut in half” or possibly horizontally skewed.

This option is STN speciﬁc and is disabled if TFT is selected. It is also disabled if the panel type

selected to be 4-bit data or monochrome.

•

Frame Repeat

- is a feature for EL panel support.

EL panels require a frame of repeated data as the cue to switch polarization. Without this change

in polarization panel quality deteriorates.

When Frame Repeat is selected an internal counter causes the periodic repeat of one frame of

modulated panel data. At a frame rate of 72 Hz the repeat period is roughly one hour. When not

selected the modulated image is never consecutively repeated.

This option is STN speciﬁc and is disabled if TFT is selected.

•

MOD Count

- speciﬁes the number of FPLINE pulses between toggles of the MOD

signal.

This setting is for passive panels only and is generally only required for older monochrome

panels. When set to “0” (default) the MOD output signal toggles every FPFRAME.

•

FPLINE Start

- speciﬁes the delay, in 8 pixel resolution, from the end of a line of display data

(FPDAT) to the leading edge of FPLINE.

This ﬁeld is a TFT speciﬁc setting and is disabled if an STN panel is chosen.

•

FPFRAME Start

- speciﬁes the number of lines between the last line of display data (FPDAT)

and the leading edge of FPFRAME.

This ﬁeld is a TFT speciﬁc setting and is disabled if an STN panel is chosen.

•

FPLINE / FPFRAME Polarity

- these settings control the sync pulse direction of the FPLINE

and FPFRAME pulses in TFT modes.

Select the appropriate pulse direction for the panel being connected. Selecting 'Lo' results in an

active low sync pulse while 'Hi' results in an active high pulse.

These settings are TFT speciﬁc and are disabled when STN panel is selected. When an STN

panel type is selected the pulse directions are preset to +ve, +ve.

1: 1375CFG CONFIGURATION PROGRAM

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Miscellaneous Options

Figure 1-3 Miscellaneous Options

Miscellaneous options cover several items which do not ﬁt into other categories.

•

HW Video Invert Enable

- when selected, enables the hardware video invert capability

of the S1D13705.

The S1D13705 supports in v erted color output. The color in v ersion can be toggled by software or

in response to a signal applied to pin FPDAT11. In order for the hardware color inversion to

succeed this option must be selected, or the software must enable this feature at run time.

There are two methods of performing color inversion. In the ﬁrst scheme the display memory

data is inverted and the resulting color is derived from the corresponding Look-Up Table

element. (i.e. the inverse of color 0 w ould be whate ver color was LUT[FF] was set to. If element

0 and FF were both set to set to White then we would observe the inverse of white as being

white). The second scheme is to invert the data as it comes out of the Look-Up Table resulting in

a true color inversion. The S1D13705 uses the second method.

TFT panels require all the FPDAT control lines, as a result hardware color inversion is not

possible when using TFT panels. Software invoked color inversion can be invoked when using

TFT panels.

•

HW Power Save Enable

- select this option to enable hardware invoked power save

modes.

The S1D13705 supports two means of invoking a power save mode. In response to a software

effected change or in response to input on the GPIO0 pin. In order for the hardware power save

mode to function this option must be selected.

•

High Performance

- improves chip throughput at the expense of power consumption.

When not selected the memory clock (MCLK) signal is a divided down version of the pixel

clock (PCLK) signal. Table 1 depicts the ratios when high performance is not selected.

With slo wer MCLK selections comes lower performance and also lower power use. This setting

allows the user to trade off power consumption for system performance.

Selecting this option result in MCLK equalling PCLK at all display resolution. Overall

performance is increased but so is power consumption.

•

SwivelView Mode

- selecting this option causes register settings and timings to be saved for

SwivelView mode operation.

Table 1-1 MCLK to PCLK Ratios

Color Depth (bpp) Ratio

1 MCLK = PCLK / 8

2 MCLK = PCLK / 4

4 MCLK = PCLK / 2

8 MCLK = PCLK

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•

Alternate SwivelView Mode

- selects the alternate mode.

The S1D13705 supports two SwivelView mode schemes. Default SwivelView mode offers

slightly slower performance with the gain of lower power consumption. Alternate SwivelView

mode is more ﬂexible and slightly faster at the expense of drawing more power.

This option is only enable if SwivelView Mode is selected.

Note:

The SwivelView mode settings are intended primarily for the case where a developer de-

sires a C header file set of register values for his own program.

The HAL is capable of performing rotations “on the ﬂy”. Most programs written for the HAL

will ignore this setting and set Swi velVie w or Landscape display modes as instructed by the user.

System

The options in the System section describe the items which are required for frame rate calculations

and the location in CPU address space where the S1D13705 will be located.

Figure 1-4 System Options

•

Memory Location

- this describes where in CPU address space the S1D13705 will be located.

This setting is required by the HAL to locate the S1D13705.

•

Frame Rate

- indicates the desired frame rate. 1375CFG will attempt to write register settings

which result in the requested frame rate. If the frame rate cannot be reached then the following

dialog inform the user of the problem.

Figure 1-5 ERROR: Frame Rate

A Frame rate must be entered in order for 1375CFG to complete the frame rate calculations. If

no frame rate is entered or the frame rate is set to 0 then the follo wing dialog box will inform the

user when they try to save the conﬁguration.

Figure 1-6 ERROR: Zero Frame Rate

•

Input Clock

- this ﬁeld speciﬁes the input clock being applied to the S1D13705 in kHz.

1: 1375CFG CONFIGURATION PROGRAM

S1D13705F00A UTILITIES (X27A-B-001-01)

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LUT Control

This section controls the color depth for the S1D13705 after initialization.

Figure 1-7 Look-Up Table Control

Select the desired color depth from the available options.

Color depth selections in this section are enabled or disabled dependent upon the selected panel

dimensions. i.e. there is only enough memory to operate a 640x480 panel at 2 bit per pixel so the

selections for 4 BPP and 8 BPP would be disabled when this panel size is selected.

Note:

The primary use for the Look-Up Table color depth settings are for a developer to derive a set

of register values for inclusion in a program. Most of the sample programs based on the HAL

override the color depth for testing purposes.

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Message Bar

The message bar is used to convey conﬁguration information to the person using 1375CFG. These

messages are intended to help the user in derive the best possible conﬁguration. Currently there are

three messages which may appear here:

• Warning: HNDP (???) is getting quite large.

This message is declaring the Horizontal Non-Display Period is getting quite large

1375CFG uses a loop to determine the best values for both horizontal and vertical non-display

periods. If the horizontal non-display period grows excessively large (greater than160 pixels) as

result of the calculations this message is issued.

Larger HNDP values usually result in fading of the display image.Try increasing the frame rate

or reducing the input clock to correct this problem.

This warning may be ignored with the understanding that there may be a display image

degradation.

• Warning: VNDP (???) is getting quite large.

This message is declaring the Vertical Non-Display Period is getting quite lar ge. The v alue (???)

is the VNDP that 13705 has calculated.

1375CFG uses a loop to determine the best values for both horizontal and vertical non-display

periods. If the vertical non-display period gro ws excessi vely lar ge (greater than 30 lines) as result

of the calculations this message is issued.

Larger VNDP values may result in image tearing, jitter or other display anomalies. Try

increasing the frame rate or reducing the input clock to correct this problem.

This warning may be ignored with the understanding that there may be a display image

degradation.

• Warning: unable to set the frame rate based on the current settings.

Based on the current setting for horizontal and vertical size, input clock and desired frame rate it

is not possible to calculate a combination of horsetail and vertical non-display times to satisfy

the requested frame rate.

Typical causes for this message are incorrect input clock or frame rate v alues. The v alues may be

excessively high or excessively low. Correct the suspect value before attempting to save the

conﬁguration.

If this warning is ignored it will lead to the message box shown in Figure 1-5 on page 3-6 or

Figure 1-6 on page 3-6 being displayed when the “Save” button is clicked.

1: 1375CFG CONFIGURATION PROGRAM

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1.4 REGS Tab

The REGS tab displays the register v alues deri v ed after converting the information on the CFG page

in to register values.

The automatic calculations may not result in precisely the register values required for a speciﬁc use.

For instance the HNDP or VNDP values may have to be tweaked for a particular panel. From this

page the user can set speciﬁc register to speciﬁc values.

Figure 1-8 REGS Window

Not all the S1D13705 registers are represented on this page. For example; it makes no sense to

represent REG[00], the Revision Code, which is read only. Nor are the Look-Up Table registers,

REG[15] and REG[17], as they must be specially handled by the application after the majority of the

S1D13705 registers have been initialized.

Typical use of 1375CFG involves using the CFG page to quickly set register values. After

performing the initial setup on the CFG page the user should switch to the REGS page and perform

any register adjusting that must be done.

IMPORTANT

: do

not

return to the CFG page after making register adjustments on this page. Doing

so will result in an automatic recalculation of some register values and the possible loss of adjusted

settings.

1: 1375CFG CONFIGURATION PROGRAM

3-10 EPSON S1D13705F00A UTILITIES (X27A-B-001-01)

1.5 Buttons

Outside of the page area of 1375CFG there are four buttons for reading and writing ﬁles, obtaining

help or for exiting the program. The following sections describe these buttons.

Open

Click the Open button to read the settings saved in an executable program based on the S1D13705

hardware abstraction layer.

Clicking the Open button brings up the standard Windows ﬁle open dialog.

Figure 1-9 1375CFG File Open Dialog

From here the user selects the ﬁle to be opened. 1375CFG is capable of opening executable ﬁles

based on the S1D13705 HAL. Typically the ﬁle extension for these ﬁle are .EXE for intel platform

executables and .S9 for 68k and SH3 platform executables.

Opening a ﬁle reads that ﬁles HAL conﬁguration information. Use the data read as a starting point in

conﬁguring this or other ﬁles or to check on the current conﬁguration.

If 1375CFG is unable locate the HAL information in the selected ﬁle the following dialog box is

displayed.

Figure 1-10 ERROR: Unable to read HAL

1: 1375CFG CONFIGURATION PROGRAM

S1D13705F00A UTILITIES (X27A-B-001-01) EPSON 3-11

Save

Click the Sav e b utton to sav e the current conﬁguration settings. When clicked the standard Windo ws

ﬁle “Save As” dialog box is displayed.

Figure 1-11 1375CFG Save As Dialog

From the save as dialog box ﬁrst select the type of ﬁle to save to in the “Save as type:” edit ﬁeld.

1375CFG currently saves in three ﬁle formats.

• .EXE ﬁles - are binary images containing a HAL structure for execution on Intel platforms

• .S9 ﬁles - are ASCII binary format ﬁles used by several embedded systems. The .S9 ﬁle is a varia-

tion of S19 ﬁles.

• .H ﬁles - are ASCII C header ﬁles which can be included in other programs.

If an ex ecutable ﬁle (.EXE or .S9) is selected as the type of ﬁle to sav e to the ﬁle being sa ved to must

already exist and be an S1D13705 HAL based program. 1375CFG is cannot save to a non-existent

program. If 1375CFG is unable to locate the HAL information in the ﬁle being saved to the

following dialog box is displayed.

Figure 1-12 ERROR: Unable to read HAL

Help

Clicking on the Help button will start the help ﬁle for 1375CFG.

Exit

Clicking on the Exit button exits 1375CFG immediately. The user is not prompted to save any

changes they may have made.

1: 1375CFG CONFIGURATION PROGRAM

3-12 EPSON S1D13705F00A UTILITIES (X27A-B-001-01)

1.6 Comments

It is assumed that the 1375CFG user is familiar with S1D13705 hardware and softw are. Refer to the

“S1D13705 Hardware Functional Speciﬁcation” drawing ofﬁce number X27A-A-001-02, and the

“S1D13705 Programming Notes and Examples” manual, drawing ofﬁce number X27A-G-002-01

for information.

2: 1375SHOW DEMONSTRATION PROGRAM

S1D13705F00A UTILITIES (X27A-B-002-01) EPSON 3-13

2 1375SHOW DEMONSTRATION PROGRAM

2.1 1375SHOW

1375SHOW is a program designed to demonstrate rudimentary display capabilities of the

S1D13705. The display abilities are shown by drawing a pattern image to the video display at all

supported color depths (1, 2, 4 and 8 bits-per-pixel)

The 1375SHOW display utility must be conﬁgured and/or compiled to work with your hardware

platform. The program 1375CFG.EXE can be used to conﬁgure 1375SHOW. Consult the

“1375CFG CONFIGURATION PROGRAM”, document number X27A-B-001-01, for more

information on conﬁguring S1D13705 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded en vironment, it is assumed that the system has a means of do wnloading software from

the PC to the target platform. Typically, this is done by serial communications. The PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13705 Supported Evaluation Platforms

1375SHOW has been tested with the following S1D13705 supported evaluation platforms:

• PC system with an x86 processor. Both 16-bit and 32-bit code is supported.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

If the platform you are using is different from the above, please see the “S1D13705 Programming

Notes and Examples” manual, document number X26A-G-002-01.

Installation

PC Intel Platform

For 16-Bit Program Version: copy the ﬁle 1375SHOW.EXE to a directory that is in the DOS path

on your hard drive.

For 32-Bit Program Version: install the 32-bit Windows device driver S1D13XXX.VXD as

described in the “S1D13XXX 32-Bit Windows Device Driver Installation Guide”, document number

X00A-E-003-xx. Copy the ﬁle 1375SHOW.EXE to a directory that is in the DOS path on your hard

drive.

Embedded Platform

Download the program 1375SHOW to the system.

X27A-B-002-01

2: 1375SHOW DEMONSTRATION PROGRAM

3-14 EPSON S1D13705F00A UTILITIES (X27A-B-002-01)

Usage

PC platform: at the prompt, type:

1375show [/a][b=n][/l][/p [/alt]][/vertical][/noinit][/?]

Embedded platform: execute 1375show and at the prompt, type the command line argument(s).

Where: /a automatically cycle through all video modes.

b=? starts 1375SHOW at a user specified

bit-per-pixel (bpp) level, where ? can be:

1, 2, 4, or 8.

/l set landscape mode.

/p set portrait mode.

/alt use alternate portrait mode

/vertical displays vertical line pattern.

/update continuously update display memory.

/noinit bypass register initialization and use

values which are currently in the registers.

/? displays the help screen.

Comments

• The /alt command line switch can only be used with the /p (portrait) mode switch. This switch will

have no effect in landscape display modes.

• The Intel 32-bit version of 1375SHOW is designed to work under either Windows 9x or Windo ws

NT. To install the 32-bit Windows device driver S1D13XXX.vxd see the “S1D13XXX 32-Bit

Windows Device Driver Installation Guide”, document number X00A-E-003-xx.

The 16-bit version of the program runs under DOS with no DOS extenders. The lack of a DOS

extender means that the 16-bit program can only be used on a hardware platform where the

S1D13705 is addressed below 1MB.

2: 1375SHOW DEMONSTRATION PROGRAM

S1D13705F00A UTILITIES (X27A-B-002-01) EPSON 3-15

Program Messages

ERROR: Did not find a 13705 device.

The HAL was unable to read the re vision code re gister on the S1D13705. Ensure that the S1D13705

hardware is installed and that the hardware platform has been conﬁgured correctly. Also check that

the display memory address has been conﬁgured correctly.

ERROR: Unable to locate/load S1D13XXX.VXD

1375PLAY was unable to load a required driver. The ﬁle S1D13XXX.VXD should be located in

x:\WINDO WS\SYSTEM or in x:\WINNT\SYSTEM. If the ﬁle is not there, install it as described in

the S1D13XXX 32-Bit Windows Device Driver Installation Guide, document number X00A-E-003-

xx.

ERROR: An IOCTL error occurred

This message indicates an error at the IO control layer occurred. The usual cause for this is an

incorrect hardware conﬁguration.

ERROR: The HAL returned an unknown error

This message should never be displayed, it indicates that 1375SHOW is unable to determine the

cause of an error returned from the HAL.

ERROR: Could not initialize device

The call to initialize the S1D13705 registers failed.

Not enough memory for www x hhh x bpp!!

This message is printed if there is insufﬁcient display memory to show a complete image with a

width of www pixels, a height of hhh pixels and a color depth of bpp bit-per-pixel. In this case the

mode is skipped and the next display mode is attempted.

3: 1375SPLT DISPLAY UTILITY

3-16 EPSON S1D13705F00A UTILITIES (X27A-B-003-01)

3 1375SPLT DISPLAY UTILITY

3.1 1375SPLT

1375SPLT demonstrates S1D13705 split screen capability by showing two dif ferent areas of display

memory on the screen simultaneously.

Screen 1 memory is located at the start of the display buf fer and is ﬁlled with horizontal bars. Screen

2 memory is located immediately after Screen 1 in the display buffer and is ﬁlled with vertical bars.

On either user input or elapsed time, the line compare register v alue is changed to adjust the amount

of display area taken up by each screen.

The 1375SPLT display utility must be conﬁgured and/or compiled to work with your hardware

platform. The program 1375CFG.EXE can be used to conﬁgure 1375SPLT. Consult the “1375CFG

CONFIGURATION PROGRAM”, document number X27A-B-001-01, for more information on

conﬁguring S1D13705 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded en vironment, it is assumed that the system has a means of do wnloading software from

the PC to the target platform. Typically, this is done by serial communications. The PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13705 Supported Evaluation Platforms

1375SPLT has been tested with the following S1D13705 supported evaluation platforms:

• PC system with an x86 processor. Both 16-bit and 32-bit code is supported.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

If the platform you are using is different from the above, please see the “S1D13705 Programming

Notes and Examples manual”, document number X26A-G-002-01.

Installation

PC Intel Platform

F or 16-Bit Program Version: cop y the ﬁle 1375SPLT.EXE to a directory that is in the DOS path on

your hard drive.

For 32-Bit Program Version: install the 32-bit Windows device driver S1D13XXX.VXD as

described in the S1D13XXX 32-Bit Windows Device Driver Installation Guide, document number

X00A-E-003-xx. Copy the ﬁle 1375SPLT.EXE to a directory that is in the DOS path on your hard

drive.

Embedded Platform

Download the program 1375SPLT to the system.

X27A-B-003-01

3: 1375SPLT DISPLAY UTILITY

S1D13705F00A UTILITIES (X27A-B-003-01) EPSON 3-17

Usage

PC platform: at the prompt, type 1375SPLT [/a] [/?]

Embedded platform: execute 1375splt and at the prompt, type the command line argument.

Where: no argument enables manual split screen operation

/a enables automatic split screen operation

(a timer is used to move screen 2)

/? display the help screen

After starting 1375SPLT the following keyboard commands are available.

Manual mode: ↑, u move Screen 2 up

↓, d move Screen 2 down

HOME covers Screen 1 with Screen 2

END displays only Screen 1

Automatic mode: any key change the direction of split screen movement

(for PC only)

Both modes: bchanges the color depth (bits-per-pixel)

ESC exits 1375SPLT

1375SPLT Example

1. Type “1375splt /a” to automatically move the split screen.

2. Press “b” to change the color depth from 1 bit-per-pixel to 2 bit-per-pixel.

3. Repeat step 2 for the remaining color depths (4 and 8 bit-per-pixel).

4. Press <ESC> to exit the program.

3: 1375SPLT DISPLAY UTILITY

3-18 EPSON S1D13705F00A UTILITIES (X27A-B-003-01)

Program Messages

ERROR: Did not find a 13705 device.

The HAL was unable to read the re vision code re gister on the S1D13705. Ensure that the S1D13705

hardware is installed and that the hardware platform has been conﬁgured correctly. Also check that

the display memory address has been conﬁgured correctly.

ERROR: Unable to locate/load S1D13XXX.VXD

1375PLAY was unable to load a required driver. The ﬁle S1D13XXX.VXD should be located in

x:\WINDO WS\SYSTEM or in x:\WINNT\SYSTEM. If the ﬁle is not there, install it as described in

the S1D13XXX 32-Bit Windows Device Driver Installation Guide, document number X00A-E-003-

xx.

ERROR: An IOCTL error occurred

This message indicates an error at the IO control layer occurred. The usual cause for this is an

incorrect hardware configuration.

ERROR: The HAL returned an unknown error

This message should never be displayed, it indicates that 13705SOLT is unable to determine the

cause of an error returned from the HAL.

Not enough memory for www x hhh x bpp!!

This message is displayed if there is insufﬁcient display memory to contain two complete images

with a width of www pixels, a height of hhh pixels, and a color depth of bpp bit-per-pixel. In this

case the mode is skipped and the next display mode is attempted.

4: 1375VIRT DISPLAY UTILITY

S1D13705F00A UTILITIES (X27A-B-004-01) EPSON 3-19

4 1375VIRT DISPLAY UTILITY

4.1 1375VIRT

1375VIRT demonstrates the virtual display capability of the S1D13705. A virtual display is where

the image to be displayed is larger than the physical display device. The display surface is used a

viewing window. The entire image can be seen only by panning and scrolling.

The 1375VIRT display utility must be conﬁgured and/or compiled to work with your hardware

platform. The program 1375CFG.EXE can be used to conﬁgure 1375VIRT. Consult the “1375CFG

CONFIGURATION PROGRAM”, document number X27A-B-001-01, for more information on

conﬁguring S1D13705 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded en vironment, it is assumed that the system has a means of do wnloading software from

the PC to the target platform. Typically, this is done by serial communications. The PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13705 Supported Evaluation Platforms

1375VIRT has been tested with the following S1D13705 supported evaluation platforms:

• PC system with an x86 processor.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

If the platform you are using is different from the above, please see the “S1D13705 Programming

Notes and Examples” manual, document number X26A-G-002-01.

Installation

PC Intel Platform

F or 16-Bit Program Version: cop y the ﬁle 1375VIR T.EXE to a directory that is in the DOS path on

your hard drive.

For 32-Bit Program Version: install the 32-bit Windows device driver S1D13XXX.VXD as

described in the “S1D13XXX 32-Bit Windows Device Driver Installation Guide”, document number

X00A-E-003-xx. Copy the ﬁle 1375VIRT.EXE to a directory that is in the DOS path on your hard

drive.

Embedded Platform

Download the program 1375VIRT to the system.

X27A-B-004-01

4: 1375VIRT DISPLAY UTILITY

3-20 EPSON S1D13705F00A UTILITIES (X27A-B-004-01)

Usage

PC platform: at the prompt, type 1375virt [/a] [/l] [/p] [/alt] [/w=???].

Embedded platform: execute 1375virt and at the prompt, type the command line argument.

Where: no argumentpanning and scrolling is performed manually

(defaults to virtual width = = physical width x 2

and maximum virtual height)

/a panning and scrolling is performed automatically

/l Force landscape display mode to be set

/p Force portrait display mode to be set

/alt Enable alternate portrait mode. Selecting this

option implies /p

/w=??? speciﬁes the virtual display width which includes

both on-screen and off-screen size

the maximum virtual width, not including display area, for each

display mode is:

1 bpp – 4096 pixels

2 bpp – 2048 pixels

4 bpp – 1024 pixels

8 bpp – 512 pixels

The following keyboard commands are for navigation within the program.

Manxual mode: ↑scrolls up

↓scrolls down

←pans to the left

→pans to the right

HOME moves the display screen so that the upper right of

the virtual screen shows in the upper right of the

display

END moves the display screen so that the lower left of

the virtual screen shows in the lower left of the

display

Automatic mode: any key changes the direction of screen

Both modes: bchanges the color depth (bits-per-pixel)

ESC exits 1375VIRT

1375VIRT Example

5. Type “1375virt /a” to automatically pan and scroll.

6. Press "b" to change the bits-per-pixel from 1 bit-per-pixel to 2 bits-per-pixel.

7. Repeat steps 1 and 2 for the remaining color depths (4 and 8 bit-per-pixel).

8. Press <ESC> to exit the program.

4: 1375VIRT DISPLAY UTILITY

S1D13705F00A UTILITIES (X27A-B-004-01) EPSON 3-21

Program Messages

ERROR: Did not find a 13705 device.

The HAL was unable to read the re vision code re gister on the S1D13705. Ensure that the S1D13705

hardware is installed and that the hardware platform has been conﬁgured correctly. Also check that

the display memory address has been conﬁgured correctly.

ERROR: Unable to locate/load S1D13XXX.VXD

1375PLAY was unable to load a required driver. The file S1D13XXX.VXD should be located in

x:\WINDOWS\SYSTEM or in x:\WINNT\SYSTEM. If the file is not there, install it as described in

the S1D13XXX 32-Bit Windows Device Driver Installation Guide, document number X00A-E-003-

xx.

ERROR: An IOCTL error occurred

This message indicates an error at the IO control layer occurred. The usual cause for this is an

incorrect hardware conﬁguration.

ERROR: The HAL returned an unknown error

This message should ne ver be displayed, it indicates that 1375VIRT is unable to determine the cause

of an error returned from the HAL.

Unable to use virtual mode at xx BPP

This message is displayed if there is insufﬁcient display memory to show a complete virtual image.

Speciﬁcally, the maximum number of lines for the image is calculated using the current virtual

width. If the number of possible lines is less than the physical display size this message is displayed.

Try restarting the program and manually specify a smaller virtual width.

5: 1375PLAY DIAGNOSTIC UTILITY

3-22 EPSON S1D13705F00A UTILITIES (X27A-B-005-01)

5 1375PLAY DIAGNOSTIC UTILITY

5.1 1375PLAY

1375PLAY is a utility which allows the user to easily read/write the S1D13705 registers, Look-Up

Table and display memory.

The user interface for 1375PLAY is similar to the DOS DEBUG program; commands are received

from the standard input de vice, and output is sent to the standard output device (console for Intel and

terminal for embedded platforms). This utility requires the target platform to support standard IO.

1375PLAY commands can be entered interactively using a keyboard/monitor or they can be

ex ecuted from a script ﬁle. Scripting is a po werful feature which allows command sequences played

back from a ﬁle thus avoiding having to retype lengthy sequences.

The 1375PLAY display utility must be conﬁgured and/or compiled to work with your hardware

platform. The program 1375CFG.EXE can be used to conﬁgure 1375PLAY. Consult the “1375CFG

CONFIGURATION PROGRAM”, document number X27A-B-001-01, for more information on

conﬁguring S1D13705 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded en vironment, it is assumed that the system has a means of do wnloading software from

the PC to the target platform. Typically, this is done by serial communications. The PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13705 Supported Evaluation Platforms

1375PLAY has been tested with the following S1D13705 supported evaluation platforms:

• PC system with an x86 processor. Both 16-bit and 32-bit code is supported.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

If the platform you are using is different from the above, please see the “S1D13705 Programming

Notes and Examples” manual, document number X26A-G-002-01.

Installation

PC Intel Platform

For 16-Bit Program Version: copy the ﬁle 1375PLAY.EXE to a directory that is in the DOS path

on your hard drive.

For 32-Bit Program Version: install the 32-bit Windows device driver S1D13XXX.VXD as

described in the “S1D13XXX 32-Bit Windows Device Driver Installation Guide”, document number

X00A-E-003-xx. Copy the ﬁle 1375PLAY.EXE to a directory that is in the DOS path on your hard

drive.

Embedded Platform

Download the program 1375PLAY to the system.

X27A-B-005-01

5: 1375PLAY DIAGNOSTIC UTILITY

S1D13705F00A UTILITIES (X27A-B-005-01) EPSON 3-23

Usage

PC platform: at the prompt, type 1375play [/?].

Embedded platform: execute 1375play and at the prompt, type the command line argument.

Where: /? displays program revision information.

The following commands are valid within the 1375PLAY program.

X index [data] Reads/writes the registers.

Writes data to the register specified by the index

when “data” is specified; otherwise the register is

read.

XA Reads all registers.

L index [data1 data2 data3] Reads/writes Look-Up Table (LUT) values.

Writes data to the LUT index when “data” is

specified; otherwise the LUT index is read.

Data must consist of 3 bytes: 1 red, 1 green, 1

blue. and range in value from 0x00 to 0x0F.

LA Reads all LUT values.

F[W] addr1 addr2 data . . . Fills bytes or words from address 1 to address 2

with data. Data can be multiple values

(e.g. F 0 20 1 2 3 4 fills address 0 to 0x20

with a repeating pattern of 1 2 3 4).

R[W] addr [count] Reads “count” of bytes or words from the address

specified by “addr”. If “count” is not specified,

then 16 bytes/words are read.

W[W] addr data . . . Writes bytes or words of data to address specified

by “addr”. Data can be multiple values

(e.g. W 0 1 2 3 4 writes the byte values

1 2 3 4 starting at address 0).

IInitializes the chip with user specified

configuration.

M [bpp] Returns information about the current mode.

If “bpp” is specified then set the requested

color depth.

P 0|1|2 Sets software power save mode 0-2.

Power save mode 0 is normal operation.

H [lines] Halts after specified lines of display.

This feature halts the display during long

read operations to prevent

data from scrolling off the display.

Set 0 to disable.

QQuits this utility.

?Displays Help information.

5: 1375PLAY DIAGNOSTIC UTILITY

3-24 EPSON S1D13705F00A UTILITIES (X27A-B-005-01)

1375PLAY Example

Type “1375PLAY” to start the program.

Type "?" for help.

Type "i" to initialize the registers.

Type "xa" to display the contents of the registers.

Type "x 5" to read register 5.

Type "x 3 10" to write 10 hex to register 3.

Type "f 0 ffff aa" to ﬁll the ﬁrst FFFF hex bytes of display memory with AA hex.

Type "f 0 1fffff aa" to ﬁll 2M bytes of display memory.

Type "r 0 ff" to read the ﬁrst 100 hex bytes of display memory.

Type "q" to exit the program.

Scripting

1375PLAY can be driven by a script ﬁle. This is useful when:

• there is no standard display output to monitor command entry and results.

• various registers must be quickly changed faster than can achieved by typing.

• The same series of keystrokes is being entered time and again.

A script ﬁle is an ASCII text ﬁle with one 1375PLAY command per line. All scripts must end with a

“q” (quit) command in order to return control to the operating system. The semi-colon is used as a

comment delimitor. Everything on a line after the semi-colon will be ignored.

On a PC platform, a typical script command line is: “1375PLAY < dumpregs.scr > results”.

This causes the script ﬁle “dumpregs.scr” to be interpreted and the results to be sent to the ﬁle

“results.”

Example 1 : The script ﬁle “dumpregs.scr” can be created with and text editor and

will look like the following:

; This ﬁle initializes the S1D13705 and reads the registers

i; Initialize the registers.

xa; Dump all the registers

la; And the LUT

q; Exit

Comments

• All numeric v alues are considered to be he xadecimal unless identiﬁed otherwise. F or e xample, 10

= 10h = 16 decimal; 10t = 10 decimal; 010b = 2 decimal.

• Redirecting commands from a script ﬁle (PC platform) allows those commands to be executed as

though they were typed.

5: 1375PLAY DIAGNOSTIC UTILITY

S1D13705F00A UTILITIES (X27A-B-005-01) EPSON 3-25

Program Messages

>>> WARNING: DID NOT DETECT S1D13705 <<<

The HAL was unable to read the re vision code re gister on the S1D13705. Ensure that the S1D13705

hardware is installed and that the hardware platform has been conﬁgured correctly. Also check that

the display memory address has been conﬁgured correctly.

ERROR: Unable to locate/load S1D13XXX.VXD

1375PLAY was unable to load a required driver. The ﬁle S1D13XXX.VXD should be located in

x:\WINDO WS\SYSTEM or in x:\WINNT\SYSTEM. If the ﬁle is not there, install it as described in

the “S1D13XXX 32-Bit Windows Device Driver Installation Guide”, document number X00A-E-

003-xx.

ERROR: An IOCTL error occurred

This message indicates an error at the IO control layer occurred. The usual cause for this is an

incorrect hardware conﬁguration.

ERROR: The HAL returned an unknown error

This message should never be displayed, it indicates that 1375PLAY is unable to determine the

cause of an error returned from the HAL.

6: 1375BMP DEMONSTRAION PROGRAM

3-26 EPSON S1D13705F00A UTILITIES (X27A-B-006-01)

6 1375BMP DEMONSTRAION PROGRAM

6.1 1375BMP

1375BMP is a demonstration program for the S1D13705 which can read and display .BMP format

(Windows bitmap) ﬁles.

The 1375BMP display utility is designed to operate on an x86 based personal computer. There are

both 16-bit and 32-bit versions of 1375BMP. The 16-bit version is for use under DOS when the

S1D13705 evaluation board has been conﬁgured for D0000. The 32-bit version is intended for use

under Win32. Before use 1375BMP must be conﬁgured for the display system. Consult

documentation for the program 1375CFG.EXE which can be used to conﬁgure 1375BMP.

1375BMP is not supported on non-PC platforms.

Installation

F or 16-Bit Program Version: copy the ﬁle 1375BMP.EXE to a directory that is in the DOS path on

your hard drive.

For 32-Bit Program Version: install the 32-bit Windows device driver S1D13XXX.VXD as

described in the “S1D13XXX 32-Bit Windows Device Driver Installation Guide”, document number

X00A-E-003-xx. Copy the ﬁle 1375BMP.EXE to a directory that is in the DOS path on your hard

drive.

Usage

At the prompt, type:

1375bmp bmp_file [/a[time]] [/l] [/p] [/noinit] [/?].

Where: bmp_file the name of the file to display

/a[time] automatic mode returns to the operating system after “time” seconds. If time is

not specified the default is 5 seconds. This option is intended for use with batch

files to automate displaying a series of images.

/l override default configuration settings and set landscape display mode.

/p override default configuration settings and set portrait display mode.

/noinit bypass the register initialization and use the current setup use this option to

override changes that take place to the timing registers

/? displays the Help screen

Comments

• 1375BMP currently views only Windows BMP format images.

X27A-B-006-01

6: 1375BMP DEMONSTRAION PROGRAM

S1D13705F00A UTILITIES (X27A-B-006-01) EPSON 3-27

Program Messages

ERROR: Did not find an S1D13705 device.

The HAL was unable to locate an S1D13705 at the conﬁgured address. Check that the correct

physical address was conﬁgured into 1375BMP.EXE

ERROR: Unable to locate/load S1D13XXX.VXD

The ﬁle S1D13XXX.VXD is required by the 32-bit version of the 1375BMP. Check that the .VXD

ﬁle is in c:\WINDOWS\SYSTEM. If the ﬁle is not there, install it as described in the “S1D13XXX

32-Bit Windows Device Driver Installation Guide”, document number X00A-E-003-xx.

ERROR: An IOCTL error occurred.

The device driver S1D13XXX.VXD was unable to assign memory. Check that the PC hardware is

conﬁgured correctly and that 1375BMP has been conﬁgured with the correct memory location.

ERROR: The HAL returned an unknown error.

This error message should never bee seen. Contact ERD.

ERROR: Could not initialize device.

The HAL failed to initialize the S1D13705.

Failed to open .BMP file '?.....?'

1375BMP was unable to open the .BMP ﬁle ?.....? speciﬁed on the command line.

?.....? is not a valid bitmap file.

While performing v alidity checks it was determined that the ﬁle ?.....? is either not a valid .BMP ﬁle

or is of an unsupported format.

ERROR: Unable to set a suitable display mode.

1375BMP was unable to set a display mode to view the image with.

ERROR: Currently unable to process images greater than 8 bpp.

1375BMP can decode images of 8BPP or less color depth. Try reducing the color depth of your

image.

ERROR: Image larger than display memory size.

The amount of memory required by this image is more than the amount of memory available to the

S1D13705. Try choosing a smaller image.

ERROR: Unable to allocate enough memory to decode the image.

In order to decode a .BMP image 1375BMP needs to allocate some additional system memory. This

message is seen if the call to allocate additional memory fails.

7: 1375PWR POWER SAVE UTILITY

3-28 EPSON S1D13705F00A UTILITIES (X27A-B-007-01)

7 1375PWR POWER SAVE UTILITY

7.1 1375PWR

The 1375PWR Power Save Utility is a tool to assist in the testing of the software and hardware

power save modes.

Refer to the section titled “Power Save Modes” in the “S1D13705 Programming Notes and

Examples” manual, document number X26A-G-002-01, and the “S1D13705 Functional Hardware

Speciﬁcation”, document number X26A-A-001-02 for further information.

The 1375PWR utility must be conﬁgured and/or compiled to work with your hardware platform.

Consult documentation for the program 1375CFG.EXE which can be used to conﬁgure 1375PWR.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded en vironment, it is assumed that the system has a means of do wnloading software from

the PC to the target platform. Typically this is done by serial communications, where the PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13705 Supported Evaluation Platforms

1375PWR has been designed to work with the following S1D13705 supported evaluation platforms:

• PC system with an x86 processor. Both 16-bit and 32-bit code is supported.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

If the platform you are using is different from the above, please see the S1D13705 “Programming

Notes and Examples” manual, document number X26A-G-002-01.

Installation

PC Platform

F or 16-Bit Program Version: cop y the ﬁle 1375PWR.EXE to a directory that is in the DOS path on

your hard drive.

For 32-Bit Program Version: install the 32-bit Windows device driver S1D13XXX.VXD as

described in the “S1D13XXX 32-Bit Windows Device Driver Installation Guide”, document number

X00A-E-003-xx. Copy the ﬁle 1375PWR.EXE to a directory that is in the DOS path on your hard

drive.

Embedded Platform

Download the program 1375PWR to the system.

X27A-B-007-01

7: 1375PWR POWER SAVE UTILITY

S1D13705F00A UTILITIES (X27A-B-007-01) EPSON 3-29

Usage

PC platform: at the prompt, type 1375pwr [s0] [s1] [h0] [h1].

Embedded platform: execute 1375pwr and at the prompt, type the command line argument.

Where:s0resets software power save mode

s1 sets software power save mode

h0 resets (disables) hardware power save mode (REG[03h] bit 2)

h1 sets (enables) hardware power save mode (REG[03h] bit 2)

/? displays this usage message

Program Messages

ERROR: Did not find a 13705 device.

The HAL was unable to read the re vision code re gister on the S1D13705. Ensure that the S1D13705

hardware is installed and that the hardware platform has been conﬁgured correctly. Also check that

the display memory address has been conﬁgured correctly.

ERROR: Unable to locate/load S1D13XXX.VXD

1375PLAY was unable to load a required driver. The ﬁle S1D13XXX.VXD should be located in

x:\WINDO WS\SYSTEM or in x:\WINNT\SYSTEM. If the ﬁle is not there, install it as described in

the S1D13XXX 32-Bit Windows Device Driver Installation Guide, document number X00A-E-003-

xx.

ERROR: An IOCTL error occurred

This message indicates an error at the IO control layer occurred. The usual cause for this is an

incorrect hardware conﬁguration.

ERROR: The HAL returned an unknown error

This message should never be displayed, it indicates that 1375SHOW is unable to determine the

cause of an error returned from the HAL.

Software Power Save Mode set.

This message is a conﬁrmation that the register setting to enable softw are power sa ve mode has been

set.

Software Power Save Mode reset.

This message is a conﬁrmation that the register setting to disable software power save mode has

been set.

Hardware Power Save Mode is now Enabled.

This message conﬁrms that hardware initiated power save mode has been enabled. The S1D13705

will enter a hardware power save mode upon application of the appropriate logic level to the

hardware power save mode input pin.

Hardware Power Save Mode is now Disabled.

This message conﬁrms that the register setting to disable hardware initiated power save mode has

been set. In this state the S1D13705 should ignore the state of the hardware power save mode input

pin.

7: 1375PWR POWER SAVE UTILITY

3-30 EPSON S1D13705F00A UTILITIES (X27A-B-007-01)

THIS PAGE IS BLANK.

S1D13705F00A

Embedded Memory LCD Controller

S5U13705B00C

.1.0

ISA Bus

Evaluation Board

User’s Manual

 
CONTENTS
 
S5U13705B00C REV. 1.0 ISA BUS EVALUATION 
 
EPSON
 
4-i
 
BOARD USER’S MANUAL
 
CONTENTS
1I
 
NTRODUCTION
 
.........................................................................................................................4-1
 
1.1 Features ........................................................................................................................................4-1
 
2I
 
NSTALLATION
 
AND
 
 C
 
ONFIGURATION
 
...........................................................................................4-2
3 LCD I
 
NTERFACE
 
 P
 
IN
 
 M
 
APPING
 
.................................................................................................4-3
4 CPU/B
 
US
 
 I
 
NTERFACE
 
 C
 
ONNECTOR
 
 P
 
INOUTS
 
..............................................................................4-4
5H
 
OST
 
 B
 
US
 
 I
 
NTERFACE
 
 P
 
IN
 
 M
 
APPING
 
.........................................................................................4-6
6T
 
ECHNICAL
 
 D
 
ESCRIPTION
 
..........................................................................................................4-7
 
6.1 Embedded Memory Support .........................................................................................................4-7
6.2 ISA Bus Support............................................................................................................................4-8
6.2 Display Adapter Card Support.........................................................................................4-8
6.2 Expanded Memory Manager Support..............................................................................4-8
6.3 Non-ISA Bus Support....................................................................................................................4-8
6.4 Decoding Logic..............................................................................................................................4-9
6.5 Clock Input Support.......................................................................................................................4-9
6.6 LCD Panel Voltage Setting............................................................................................................4-9
6.7 Monochrome LCD Panel Support .................................................................................................4-9
6.8 Color Passive LCD Panel Support ................................................................................................4-9
6.9 Color TFT/D-TFD LCD Panel Support.........................................................................................4-10
6.10 Power Save Modes .....................................................................................................................4-10
6.11 Adjustable LCD Panel Negative Power Supply...........................................................................4-10
6.12 Adjustable LCD Panel Positive Power Supply ............................................................................4-10
6.13 CPU/Bus Interface Header Strips................................................................................................4-10
 
7P
 
ARTS
 
 L
 
IST
 
...........................................................................................................................4-11
8S
 
CHEMATIC
 
 D
 
IAGRAMS
 
...........................................................................................................4-12

 
CONTENTS
 
4-ii
 
EPSON
 
S5U13705B00C  REV. 1.0 ISA BUS EVALUATION
BOARD USER’S MANUAL
 
List of Figures
 
Figure 8-1 S5U13705B00C Schematic Diagram (1 of 4) ....................................................................4-12
Figure 8-2 S5U13705B00C Schematic Diagram (2 of 4) ....................................................................4-13
Figure 8-3 S5U13705B00C Schematic Diagram (3 of 4) ....................................................................4-14
Figure 8-4 S5U13705B00C Schematic Diagram (4 of 4) ....................................................................4-15
 
List of Tables
 
Table 2-1 Configuration DIP Switch Settings.......................................................................................4-2
Table 2-2 Host Bus Selection...............................................................................................................4-2
Table 2-3 Jumper Settings...................................................................................................................4-2
Table 3-1 LCD Signal Connector (J5) Pinout.......................................................................................4-3
Table 4-1 CPU/BUS Connector (H1) Pinout ........................................................................................4-4
Table 4-2 CPU/BUS Connector (H2) Pinout ........................................................................................4-5
Table 5-1 Host Bus Interface Pin Mapping ..........................................................................................4-6

1: INTRODUCTION

S5U13705B00C

REV. 1.0 ISA BUS EVALUATION

EPSON

4-1

BOARD USER’S MANUAL (X27A-G-005-01)

NTRODUCTION

This manual describes the setup and operation of the S5U13705B00C Rev. 1.0 Evaluation Board.

Implemented using the S1D13705 Embedded Memory Color LCD Controller, the S5U13705B00C

board is designed for the 16-bit ISA bus environment. To accommodate other bus architectures, the

S5U13705B00C board also provides CPU/Bus interface connectors.

For more information regarding the S1D13705, refer to the

“S1D13705 Hardware Functional

Speciﬁcation”

, document number X27A-A-001-02.

1.1 Features

• 80-pin QFP14 package.

• SMT technology for all appropriate devices.

• 4/8-bit monochrome and color passive LCD panel support.

• 9/12-bit LCD TFT/D-TFD panel support.

• Selectable 3.3V or 5V LCD panel support.

• Oscillator support for CLKI (up to 50MHz with internal clock di vider or 25MHz with no internal

clock divider).

• Embedded 80K byte SRAM display buffer for 1/2/4 bit-per-pixel (bpp), 2/4/16-level gray shade

display and 1/2/4/8 bpp, 2/4/16/256 level color display.

• Support for software and hardware power save modes.

• On-board adjustable LCD bias positive power supply (+23V to +40V).

• On-board adjustable LCD bias negative power supply (-23V to -14V).

• 16-bit ISA bus support.

• CPU/Bus interface header strips for non-ISA bus support.

2: INSTALLATION AND CONFIGURATION

4-2

EPSON

S5U13705B00C

REV. 1.0 ISA BUS EVALUATION

BOARD USER’S MANUAL (X27A-G-005-01)

NSTALLATION

AND

ONFIGURATION

The S1D13705 has four conﬁguration inputs, CNF[3:0], which are read on the rising edge of

RESET# and are fully conﬁgurable on this evaluation board. One six-position DIP switch is

provided on the board to conﬁgure the four conﬁguration inputs, select the S5U13705B00C

memory/register start address, and enable/disable hardware power save mode.

The following settings are recommended when using the S5U13705B00C with the ISA bus.

Table 2-1 Conﬁguration DIP Switch Settings

Switch Signal Closed (0 or low) Open (1 or high)

S1-1 CNF0 See “Host Bus Selection” table below See “Host Bus Selection” table below

S1-2 CNF1

S1-3 CNF2

S1-4 CNF3 Little Endian Big Endian

S1-5 ADDR Memory/Register Start Address = C0000h Memory/Register Start Address = F00000h

S1-6 GPIO0 Hardware Suspend Disable Hardware Suspend Enable

= recommended settings (conﬁgured for ISA bus support)

Table 2-2 Host Bus Selection

S1-3 S1-2 S1-1 BS# Host Bus Interface

0 0 0 X SH-4 bus interface

0 0 1 X SH-3 bus interface

0 1 0 X reserved

0 1 1 X MC68K bus interface #1, 16-bit

1 0 0 X reserved

1 0 1 X MC68K bus interface #2, 16-bit

1100reserved

1101reserved

1110Generic #1, 16-bit

1 1 1 1 Generic #2, 16-bit

= recommended settings (conﬁgured for ISA bus support)

Table 2-3 Jumper Settings

Description 1-2 2-3

JP1 IOV

Selection 5.0V IOV

3.3V IOV

JP2 BS# Signal Selection Pulled up to IOV

No Connection

JP3 RD/WR# Signal Selection Pulled up to IOV

No Connection

JP4 LCD Panel Voltage Selection 5V LCD Panel 3.3V LCD Panel

JP5 LCDPWR polarity Active low (‘LCDPWR#’) Active high (‘LCDPWR’)

= recommended settings (JP1 through JP3 conﬁgured for ISA bus support)

3: LCD INTERFACE PIN MAPPING

S5U13705B00C

REV. 1.0 ISA BUS EVALUATION

EPSON

4-3

BOARD USER’S MANUAL (X27A-G-005-01)

3 LCD I

NTERFACE

APPING

Note:

1.Un-used GPIO pins must be connected to IO V

2.Inverse Video is enabled on FPDAT11 by REG[02h] bit 1.

Table 3-1 LCD Signal Connector (J5) Pinout

Connector Single Passive Panel Dual Passive Panel Color TFT/D-TFD

Pin Name Pin #

Color Mono Color Mono

4-bit 8-bit 8-bit

Alternate

Format 4-bit 8-bit 8-bit 8-bit 9-bit 12-bit

BFPDAT0 1 driven 0 D0 LD0 driven 0 D0 D0 LD0 R2 R3

BFPDAT1 3 driven 0 D1 LD1 driven 0 D1 D1 LD1 R1 R2

BFPDAT2 5 driven 0 D2 LD2 driven 0 D2 D2 LD2 R0 R1

BFPDAT3 7 driven 0 D3 LD3 driven 0 D3 D3 LD3 G2 G3

BFPDAT4 9 D0 D4 UD0 D0 D4 D4 UD0 G1 G2

BFPDAT5 11 D1 D5 UD1 D1 D5 D5 UD1 G0 G1

BFPDAT6 13 D2 D6 UD2 D2 D6 D6 UD2 B2 B3

BFPDAT7 15 D3 D7 UD3 D3 D7 D7 UD3 B1 B2

BFPDAT8 17 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 B0 B1

BFPDAT9 19 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 R0

BFPDAT10 21 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 G0

BFPDAT11 23 GPIO4/

Inverse

Video

GPIO4/

Inverse

Video

GPIO4/

Inverse

Video

GPIO4/

Inverse

Video

GPIO4/

Inverse

Video

GPIO4/

Inverse

Video

GPIO4/

Inverse

Video

GPIO4 B0

BFPSHIFT 33 FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT

BFPSHIFT2 35 FPSHIFT2

BFPLINE 37 FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE

BFP-

FRAME 39 FPFRAM

EFPFRAM

GND 2-26

(Even

Pins)

GND GND GND GND GND GND GND GND GND

N / C 28

VLCD 30 LCD panel negative bias voltage (-24V to -14V)

LCDV

32 +3.3V or +5V (selectable with JP4)

+12V 34 +12V +12V +12V +12V +12V +12V +12V +12V +12V

VDDH 36 LCD panel positive bias voltage (+23V to +40V)

BDRDY 38 MOD MOD MOD MOD MOD MOD DRDY DRDY

BLCDPWR 40 LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR

4: CPU/BUS INTERFACE CONNECTOR PINOUTS

4-4

EPSON

S5U13705B00C

REV. 1.0 ISA BUS EVALUATION

BOARD USER’S MANUAL (X27A-G-005-01)

4 CPU/B

NTERFACE

ONNECTOR

INOUTS

Table 4-1 CPU/BUS Connector (H1) Pinout

Connector Pin

No. CPU/BUS Pin

Name Comments

1 SD0 Connected to DB0 of the S1D13705

2 SD1 Connected to DB1 of the S1D13705

3 SD2 Connected to DB2 of the S1D13705

4 SD3 Connected to DB3 of the S1D13705

5 GND Ground

6 GND Ground

7 SD4 Connected to DB4 of the S1D13705

8 SD5 Connected to DB5 of the S1D13705

9 SD6 Connected to DB6 of the S1D13705

10 SD7 Connected to DB7 of the S1D13705

11 GND Ground

12 GND Ground

13 SD8 Connected to DB8 of the S1D13705

14 SD9 Connected to DB9 of the S1D13705

15 SD10 Connected to DB10 of the S1D13705

16 SD11 Connected to DB11 of the S1D13705

17 GND Ground

18 GND Ground

19 SD12 Connected to DB12 of the S1D13705

20 SD13 Connected to DB13 of the S1D13705

21 SD14 Connected to DB14 of the S1D13705

22 SD15 Connected to DB15 of the S1D13705

23 RESET# Connected to the RESET# signal of the S1D13705

24 GND Ground

25 GND Ground

26 GND Ground

27 +12V 12 volt supply

28 +12V 12 volt supply

29 WE0# Connected to the WE0# signal of the S1D13705

30 WAIT# Connected to the WAIT# signal of the S1D13705

31 CS# Connected to the CS# signal of the S1D13705

32 NC Not connected

33 WE1# Connected to the WE1# signal of the S1D13705

34 IOV

Connected to the IOV

supply of the S1D13705

4: CPU/BUS INTERFACE CONNECTOR PINOUTS

S5U13705B00C

REV. 1.0 ISA BUS EVALUATION

EPSON

4-5

BOARD USER’S MANUAL (X27A-G-005-01)

Table 4-2 CPU/BUS Connector (H2) Pinout

Connector Pin No. CPU/BUS Pin

Name Comments

1 SA0 Connected to AB0 of the S1D13705

2 SA1 Connected to AB1 of the S1D13705

3 SA2 Connected to AB2 of the S1D13705

4 SA3 Connected to AB3 of the S1D13705

5 SA4 Connected to AB4 of the S1D13705

6 SA5 Connected to AB5 of the S1D13705

7 SA6 Connected to AB6 of the S1D13705

8 SA7 Connected to AB7 of the S1D13705

9 GND Ground

10 GND Ground

11 SA8 Connected to AB8 of the S1D13705

12 SA9 Connected to AB9 of the S1D13705

13 SA10 Connected to AB10 of the S1D13705

14 SA11 Connected to AB11 of the S1D13705

15 SA12 Connected to AB12 of the S1D13705

16 SA13 Connected to AB13 of the S1D13705

17 GND Ground

18 GND Ground

19 SA14 Connected to AB14 of the S1D13705

20 SA15 Connected to AB15 of the S1D13705

21 SA16 Connected to AB16 of the S1D13705

22 SA17 Connected to SA17 of the ISA bus connector

23 SA18 Connected to SA18 of the ISA bus connector

24 SA19 Connected to SA19 of the ISA bus connector

25 GND Ground

26 GND Ground

27 V

5 volt supply

28 V

5 volt supply

29 RD/WR# Connected to the R/W# signal of the S1D13705

30 BS# Connected to the BS# signal of the S1D13705

31 BUSCLK Connected to the BCLK signal of the S1D13705

32 RD# Connected to the RD# signal of the S1D13705

33 NC Not connected

34 CLKI Connected to the CLKI signal of the S1D13705

5: HOST BUS INTERFACE PIN MAPPING

4-6

EPSON

S5U13705B00C

REV. 1.0 ISA BUS EVALUATION

BOARD USER’S MANUAL (X27A-G-005-01)

OST

US INTERFACE PIN MAPPING

Table 5-1 Host Bus Interface Pin Mapping

S1D13705

Pin Names SH-3 SH-4 MC68K #1 MC68K #2 Generic Bus #1 Generic Bus #2

AB[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1]

AB0 A0 A0 LDS# A0 A0 A0

DB[15:0] D[15:0] D[15:0] D[15:0] D[15:0] D[15:0] D[15:0]

WE1# WE1# WE1# UDS# DS# WE1# BHE#

CS# CSn# CSn# External Decode External Decode External Decode External Decode

BCLK CKIO CKIO BCLK BCLK BCLK BCLK

BS# BS# BS# AS# AS# Connect to VSS

Connect to IO V

RD/WR# RD/WR# RD/WR# R/W# R/W# RD1#

Connect to IO V

RD# RD# RD#

Connect to IO V

SIZ1 RD0# RD#

WE0# WE0# WE0#

Connect to IO V

SIZ0 WE0# WE#

WAIT# WAIT# RDY# DTACK# DSACK1# WAIT# WAIT#

RESET# RESET# RESET# RESET# RESET# RESET# RESET#

6: TECHNICAL DESCRIPTION

S5U13705B00C REV. 1.0 ISA BUS EVALUATION EPSON 4-7

BOARD USER’S MANUAL (X27A-G-005-01)

6TECHNICAL DESCRIPTION

6.1 Embedded Memory Support

The S1D13705 contains 80K bytes of embedded, 16-bit, SRAM used for the display buffer and a 32

byte internal register set.

Since the S1D13705 does not distinguish between memory and register accesses, both the 80K byte

display buffer and the 32 byte register set must be memory mapped into the host’s memory space.

When using the S5U13705B00C board on an ISA bus system, the board can be conﬁgured to map

the S1D13705 to one of two memory blocks.

The SRAM start address is determined by a DIP switch setting. See “Table 2-1 Conﬁguration DIP

Switch Settings,” on page 4-2.

1. When switch S1-5 is in the closed position, the S1D13705 is mapped into segments 0C0000h

and 0D0000h.

This memory space is in the ﬁrst 1M byte of ISA bus memory and should be used if these

segments are not taken up by other devices such as network adapters, SCSI cards, or other

peripherals.

Note: Since VGA and VGA compatible video adapters use address 0C8000, these cards cannot be

used while using the S5U13705B00C board at this memory address. A monochrome display

adapter, a terminal, or a non-VGA compatible display adapter must be used.

2. When switch S1-5 is in the open position, the S1D13705 is mapped into the upper megabyte of

ISA bus memory, starting address of F00000h. To use this memory on an ISA bus system, the

system BIOS has to be conﬁgured to set a memory ‘hole’ starting at this address. Some systems

allow the user to conﬁgure the size of this hole and the starting address of where it begins while

others just allow a 1M byte hole at the top of the 16M byte memory space. This memory hole is

conﬁgured by entering the system CMOS Setup Utility. This memory space should be used if

segments 0Dh and 0Eh are being used by other devices or if a VGA display adapter is needed.

Starting at the SRAM start address, the board design decodes a 128K byte segment accommodating

both the 80K byte display buf fer and the S1D13705 internal re gister set. The S1D13705 re gisters are

mapped into the upper 32 bytes of the 128K byte segment (1FFE0h to 1FFFFh).

When using the S5U13705B00C board on a non-ISA bus system, system or external decode logic

must map the S1D13705 into an appropriate memory space.

6: TECHNICAL DESCRIPTION
4-8 EPSON S5U13705B00C REV. 1.0 ISA BUS EVALUATION 
BOARD USER’S MANUAL (X27A-G-005-01)
6.2 ISA Bus Support
The S5U13705B00C board has been designed to directly support the 16-bit ISA bus environment 
and can be used in conjunction with either a VGA or a monochrome display adapter card.
There are 4 conﬁguration inputs associated with the Host Interface (CNF[2:0] and BS#). Refer to 
“Table 2-3 Jumper Settings,” on page 4-2 and “Table 5-1 Host Bus Interface Pin Mapping,” on 
page 4-6 for complete details.
Display Adapter Card Support
When using the S5U13705B00C in conjunction with another primary Display Adapter (VGA or 
Monochrome) the following applies:
VGA Display Adapter
All VGA display adapters can be used with the S5U13705B00C board if the S1D13705 is mapped 
to the upper 1M Byte of ISA bus memory, address F00000-F1FFFF. If the S1D13705 is mapped to 
the address range 0C0000-0D0000, then no VGA or VGA compatible display adapters can be used 
with the S5U13705B00C board. See “6.1 Embedded Memory Support” on page 4-7.
Monochrome Display Adapter
The S5U13705B00C board can be used with monochrome display adapters at both memory 
addresses.
Expanded Memory Manager Support
If a memory manager is being used for system memory, the address range selected for the SRAM 
start address must be excluded from use or memory conﬂicts will arise.
6.3 Non-ISA Bus Support
The S5U13705B00C board is speciﬁcally designed to support the standard 16-bit ISA bus. Ho we ver , 
the S1D13705 directly supports many other host bus interfaces. Header strips H1 and H2 are 
provided and contain all the necessary IO pins to interface to these host buses. See “4 CPU/Bus 
Interface Connector Pinouts” on page 4-4; “Table 2-1 Conﬁguration DIP Switch Settings,” on 
page 4-2; and “Table 2-3 Jumper Settings,” on page 4-2 for details.
When using the header strips to provide the bus interface observe the following:
• All signals on the ISA bus card edge must be isolated from the ISA bus (do not plug the card into 
a computer). Power must be provided through the headers.
• U7, a PLD of type 22V10-15, is used to provide the S1D13705 CS# (pin 74) and other decoding 
logic signals for ISA bus mode. For non-ISA applications, this functionality must be provided 
externally. Remove the PAL from its socket to eliminate conﬂicts driving S1D13705 control sig-
nals. Refer to Table 5-1  for connection details. 
Note: When using a 3.3V host bus interface, IO VDD must be set to 3.3V by setting jumper (JP1) to 
the 2-3 position. Refer to “Table 2-3 Jumper Settings,” on page 4-2.

6: TECHNICAL DESCRIPTION

S5U13705B00C REV. 1.0 ISA BUS EVALUATION EPSON 4-9

BOARD USER’S MANUAL (X27A-G-005-01)

6.4 Decoding Logic

All the required decode logic is provided through a PLD of type 22V10-15 (U7, sock eted). This PAL

contains the following equations.

!CS = (Address >= ^hC0000) & (Address <= ^hDFFFF) & !ADDR & REFRESH & ENAB

# (Address1 >= ^hF00000) & (Address1 <= ^hF1FFFF) & ADDR & REFRESH & ENAB;

!MEMCS16 = (Address1 >= ^h0C0000) & (Address1 <= ^h0DFFFF) & !ADDR & !CS

# (Address1 >= ^hF00000) & (Address1 <= ^hF1FFFF) & ADDR & !CS;

!WE0 = (!CS & !ADDR & !SMEMW) # (!CS & ADDR & !MEMW);

!RD = (!CS & !ADDR & !SMEMR) # (!CS & ADDR & !MEMR);

Note:ADDR = Switch S1-5 (see Table 2-1, “Configuration DIP Switch Settings,” on page 1-2).

6.5 Clock Input Support

The input clock (CLKI) frequency can be up to 50MHz for the S1D13705 if the internal clock

divide-by-2 mode is set. If the clock divider is not used, the maximum CLKI frequency is 25MHz.

There is no minimum input clock frequency.

A 25.0MHz oscillator (U2, socketed) is pro vided as the input clock source. Ho wever, depending on

the LCD resolution , desired frame rate, and po wer consumtion budget, a lo wer frequency clock may

be required.

6.6 LCD Panel Voltage Setting

The S5U13705B00C board supports both 3.3V and 5V LCD panels through the LCD connector J5.

The voltage level is selected by setting jumper J4 to the appropriate position. Refer to “Table 2-3

Jumper Settings,” on page 4-2 for setting this jumper.

Although not necessary for signal buffering, buffers have been implemented in the board design to

provide ﬂexibility in handling 3 and 5 volt panels.

6.7 Monochrome LCD Panel Support

The S1D13705 directly supports 4 and 8-bit, dual and single, monochrome passi v e LCD panels. All

necessary signals are provided on the 40-pin ribbon cable header J5. The interface signals on the

cable are alternated with grounds to reduce crosstalk and noise.

Refer to “Table 3-1 LCD Signal Connector (J5) Pinout,” on page 4-3 for speciﬁc connection

information.

6.8 Color Passive LCD Panel Support

The S1D13705 directly supports 4 and 8-bit, dual and single, color passive LCD panels. All the

necessary signals are provided on the 40-pin ribbon cable header J5. The interface signals on the

cable are alternated with grounds to reduce crosstalk and noise.

Refer to “Table 3-1 LCD Signal Connector (J5) Pinout,” on page 4-3 for speciﬁc connection

information.

6: TECHNICAL DESCRIPTION

4-10 EPSON S5U13705B00C REV. 1.0 ISA BUS EVALUATION

BOARD USER’S MANUAL (X27A-G-005-01)

6.9 Color TFT/D-TFD LCD Panel Support

The S1D13705 directly supports 9 and 12-bit active matrix color TFT/D-TFD panels. All the

necessary signals can also be found on the 40-pin LCD connector J5. The interface signals on the

cable are alternated with grounds to reduce crosstalk and noise.

Refer to “Table 3-1 LCD Signal Connector (J5) Pinout,” on page 4-3 for connection information.

6.10 Power Save Modes

The S1D13705 supports hardware and software power save modes. These modes are controlled by

the utility 1375PWR. The hardware power save mode needs to be enabled by 1375PWR and then

activated by DIP switch S1-6. See “Table 2-1 Conﬁguration DIP Switch Settings,” on page 4-2 for

details on setting this switch.

6.11 Adjustable LCD Panel Negative Power Supply

For those LCD panels requiring a negative power supply to provide between -23V and -14V

(Iout=25mA) a power supply has been provided as an integral part of this design. The VLCD power

supply can be adjusted by R21 to give an output voltage from -23V to -14V, and is enabled and

disabled by the active high S1D13705 control signal LCDPWR, inverted externally.

Determine the panel’s speciﬁc power requirements and set the potentiometer accordingly before

connecting the panel.

6.12 Adjustable LCD Panel Positive Power Supply

For those LCD panels requiring a positive power supply to provide between +23V and +40V

(Iout=45mA) a power supply has been provided as an integral part of this design. The VDDH power

supply can be adjusted by R15 to provide an output voltage from +23V to +40V and is enabled and

disabled by the active high S1D13705 control signal LCDPWR, inverted externally.

Determine the panel’s speciﬁc power requirements and set the potentiometer accordingly before

connecting the panel.

6.13 CPU/Bus Interface Header Strips

All of the CPU/Bus interface pins of the S1D13705 are connected to the header strips H1 and H2 for

easy interface to a CPU/Bus other than ISA.

Refer to “Table 4-1 CPU/BUS Connector (H1) Pinout,” on page 4-4 and “Table 4-2 CPU/BUS

Connector (H2) Pinout,” on page 4-5 for speciﬁc settings.

Note: These headers only provide the CPU/bus interface signals from the S1D13705. When another

host bus interface is selected by CNF[3:0] and BS#, appropriate external decoding logic MUST

be used to access the S1D13705. Refer to “Table 5-1 Host Bus Interface Pin Mapping,” on

page 4-6 for connection details.

7: PARTS LIST

S5U13705B00C REV. 1.0 ISA BUS EVALUATION EPSON 4-11

BOARD USER’S MANUAL (X27A-G-005-01)

7PARTS LIST

Item # Qty/board Designation Part Value Description

1 15 C1-C11, C15-17,C24 0.1uF, 20%, 50V 0805 ceramic capacitor

2 3 C12-14 10uF, 10%, 25V Tantalum capacitor size D

3 2 C18, C22 47uF, 10%, 16V Tantalum capacitor size D

4 3 C19-C21 4.7uF, 10%, 50V Tantalum capacitor size D

5 1 C23 56uF, 20%, 63V Electrolytic, radial, low ESR

6 2 H1,H2 CON34A Header 0.1” 17x2 header, PTH

7 5 JP1-JP4, JP6 HEADER 3 0.1” 1x3 header, PTH

8 1 J1 AT CON-A ISA Bus gold ﬁngers

9 1 J2 AT CON-B ISA Bus gold ﬁngers

10 1 J3 AT CON-C ISA Bus gold ﬁngers

11 1 J4 AT CON-D ISA Bus gold ﬁngers

12 1 J5 CON40A Shrouded header 2x20, PTH, center key

13 1 L1 1µH MCI-1812 inductor

14 2 L3, L4 Ferrite bead Philips BDS3/3/8.9-4S2

15 1 Q1 2N3906 PNP signal transistor, SOT23

16 1 Q2 2N3904 NPN signal transistor, SOT23

17 6 R1-R6 15K, 5% 0805 resistor

18 9 R7-R13, R17, R18 10K, 5% 0805 resistor

19 1 R14 475K, 1% 0805 resistor

20 1 R15 200K Pot. 200K Trim POT Spectrol 63S204T607 (or equivalent)

21 1 R16 14K, 1% 0805 resistor

22 3 R19, R20, R22 100K, 5% 0805 resistor

23 1 R21 100K Pot. 100K Trim POT Spectrol 63S104T607 (or equivalent)

24 1 S1 SW DIP-6 6 position DIP switch

25 1 U1 S1D13705F00A QFP14-80, 80 pin, SMT

26 1 U2 25.0 MHz oscillator FOX 25MHz oscillator or equiv., 14 pin DIP socketed

27 3 U3-U5 74AHC244 SO-22, TI74AHC244

28 1 U6 LT1117CM-3.3 Linear Technology 5V to 3.3V regulator, 800mA

29 1 U7 PLD22V10-15 PLD type 22V10-15, 20 Pin DIP, socketed

30 1 U8 74ALS125 SO-14, 74ALS125

31 1 U9 74HCT04 SO-14, 74HCT04

32 1 U10 RD-0412 Xentek RD-0412, positive PS

33 1 U11 EPN001 Xentek EPN001 negative PS

8: SCHEMATIC DIAGRAMS

4-12 EPSON S5U13705B00C REV. 1.0 ISA BUS EVALUATION

BOARD USER’S MANUAL (X27A-G-005-01)

8SCHEMATIC DIAGRAMS

Figure 8-1 S5U13705B00C Schematic Diagram (1 of 4)

By-pass Capacitors (1 per power pin)

1 2 5.0V IOVDD

2 3 3.3V IOVDD 1.0

Epson Research & Development, Inc.

S5U13705B00C ISA-Bus Rev. 1.

0 Evaluation Board : 13705F00A Chip

14Monday, January 04, 1999

Size Document Number Rev

Date: Sheet of

FPDAT2

SD2

FPDAT4SD11

SD4

SA3

SD13

SD5 FPDAT[0..7]

SD6

SA15

SD8

SA7

FPDAT0

SD10

SD7

SD1

SA[0..19]

SD[0..15]

SD12

SD3

SA2

SA5

SD14

SA13

SA1

FPDAT3

SA4

SA0

SD15

SA10

SA9

SA8

FPDAT1

SD9

SD0

SA14

SA12

SA11

SA6

FPDAT5

FPDAT6

FPDAT7

CNF2

CNF1

CNF2

CNF0

CNF3

CNF[0..3]

CNF1

CNF0

SA16

3.3V

IOVDD

3.3V

IOVDD

IOVDD IOVDD

IOVDD

VCC

0.1uF

0.1uF C7

0.1uF

JP2

HEADER 3

JP3

HEADER 3

15K

15K R5

15K

0.1uF C4

0.1uF

JP1

HEADER 3

15K

SW DIP-6

S1D13705F00A

AB0

70 AB1

69 AB2

68 AB3

67 AB4

66 AB5

65 AB6

64 AB7

63 AB8

62 AB9

59 AB10

58 AB11

57 AB12

56 AB13

55 AB14

54 AB15

FPDAT0 37

FPDAT1 36

FPDAT2 35

FPDAT3 34

FPDAT5 32

FPDAT6 31

FPDAT7 30

CS#

LCDPWR 43

COREVDD

VSS

72 VSS

60 VSS

50 VSS

VSS

DB0

19 DB1

18 DB2

17 DB3

16 DB4

15 DB5

14 DB6

13 DB7

12 DB8

11 DB9

9DB10

8DB11

7DB12

6DB13

5DB14

4DB15

FPDAT4 33

CNF0 49

CNF1 48

CNF2 47

CNF3 46

AB16

RD/WR#

79 WE1#

78 WE0#

77 RD#

76 BS#

RESET#

CLKI

51 BCLK

WAIT#

TESTEN

COREVDD

1COREVDD

IOVDD

COREVDD

IOVDD

52 IOVDD

FPDAT8/GPIO1 26

FPDAT9GPIO2 25

FPDAT10/GPIO3 24

FPDAT11/GPIO4 23

FPFRAME 39

FPLINE 38

FPSHIFT 28

DRDY 42

GPIO0 22

SD[0..15] LCDPWR

DRDY

FPFRAME

FPLINE

FPSHIFT

FPDAT[0..7]

RD/WR#

WE1#

WE0#

CS#

BUSCLK

CLKI

RESET#

RD#

WAIT#

BS#

SA[0..19]

FPDAT8

FPDAT9

FPDAT10

FPDAT11

CNF[0..3]

SUSPEND

BS#

RD/WR#

CNF[0..3]

SUSPEND

ADDR

8: SCHEMATIC DIAGRAMS

S5U13705B00C REV. 1.0 ISA BUS EVALUATION EPSON 4-13

BOARD USER’S MANUAL (X27A-G-005-01)

Figure 8-2 S5U13705B00C Schematic Diagram (2 of 4)

C C

D D

MEMCS16

1.0

Epson Research & Development, Inc.

S5U13705B00C ISA-Bus Rev. 1.0 Evaluation Board : ISA-Bus and PAL Decode

24Monday, January 04, 1999

Size Document Number Rev

Date: Sheet of

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

SD[0..15]

SA[0..19]

SA9

SA10

LA21

SA14

SA17

SA8

SA15

SA0

SA4

SA13

LA23

LA[17..23]

SA19

LA19

LA18

SA7

SA3

LA20

SA16

SA6

SA2

SA11

SA12

LA22

LA17

SA1

SA18

SA5

LA[17..23]

SA[0..19]

LA23

LA22

LA21

LA20

LA19

LA18

LA17

SA19

SA18

SA17

SA16

IOVDD

VCC

IOVDD

VCC

+12V

IOVDDIOVDD VCC

VCC

IOVDD

VCC

AT CON-A

/IOCHCK

1SD7

2SD6

3SD5

4SD4

5SD3

6SD2

7SD1

8SD0

9IOCHRDY

10 AEN

11 SA19

12 SA18

13 SA17

14 SA16

15 SA15

16 SA14

17 SA13

18 SA12

19 SA11

20 SA10

21 SA9

22 SA8

23 SA7

24 SA6

25 SA5

26 SA4

27 SA3

28 SA2

29 SA1

30 SA0

AT CON-B

GND 1

RESET 2

+5V 3

IRQ9 4

-5V 5

DRQ2 6

-12V 7

OWS 8

+12V 9

GND 10

/SMEMW 11

/SMEMR 12

/IOW 13

/IOR 14

/DACK3 15

DRQ3 16

/DACK1 17

DRQ1 18

/REFRESH 19

CLK 20

IRQ7 21

IRQ6 22

IRQ5 23

IRQ4 24

IRQ3 25

/DACK2 26

T/C 27

BALE 28

+5V 29

OSC 30

GND 31

AT CON-D

/MEMCS16 1

/IOCS16 2

IRQ10 3

IRQ11 4

IRQ12 5

IRQ15 6

IRQ14 7

/DACK0 8

DRQ0 9

/DACK5 10

DRQ5 11

/DACK6 12

DRQ6 13

/DACK7 14

DRQ7 15

+5V 16

MASTER 17

GND 18

+C14

10uF/25V

10K

+C13

10uF/25V

AT CON-C

/SBHE

1LA23

2LA22

3LA21

4LA20

5LA19

6LA18

7LA17

8/MEMR

9/MEMW

10 SD8

11 SD9

12 SD10

13 SD11

14 SD12

15 SD13

16 SD14

17 SD15

10K R10

10K R12

10K

U8A

74LS125

2 3

C16

0.1uF

10K

TIBPAL22V10

CLK/IN

1IN

2IN

3IN

4IN

5IN

6IN

7IN

8IN

9IN

10 IN

GND

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 18

I/O 17

I/O 16

I/O 15

I/O 14

IN 13

VCC 24

C15

0.1uF

R11

10K

R13

10K

C17

0.1uF

U9A

74HCT04

1 2

R22

100K

REFRESH#

RESET

MEMCS16#

WE1#

SD[0..15]

SA[0..19]

LA[17..23]

WAIT#

BUSCLK

SMEMW#

SMEMR#

CS#

RESET#

RESET

REFRESH# MEMCS16#

MEMW#

MEMR#

LA[17..23]

SA[0..19]

ADDR

MEMR#

MEMW#

SMEMR#

SMEMW#

RD#

WE0#

8: SCHEMATIC DIAGRAMS

4-14 EPSON S5U13705B00C REV. 1.0 ISA BUS EVALUATION

BOARD USER’S MANUAL (X27A-G-005-01)

Figure 8-3 S5U13705B00C Schematic Diagram (3 of 4)

SELECTABLE 3.3V / 5.0V COLOR/MONO LCD CONNECTOR

1 2 5.0V LCD Panels

2 3 3.3V LCD Panels

1.0

Epson Research & Development, Inc.

S5U13705B00C ISA-Bus Rev. 1.0 Evaluation Card : LCD Connector & Headers

34Monday, January 04, 1999

Size Document Number Rev

Date: Sheet of

FPDAT[0..7]

BFPDAT0

BFPDAT1

BFPDAT2

BFPDAT3

BFPDAT4

BFPDAT5

BFPDAT6

BFPDAT7

BFPDAT8

BFPDAT9

BFPDAT10

BFPDAT11

FPDAT0

FPDAT1

FPDAT2

FPDAT3

FPDAT4

FPDAT5

FPDAT6

FPDAT7

FPDAT8

FPDAT9

FPDAT10

FPDAT11

SA[0..19]

SA1

SA3

SA9

SA11

SA13

SA15

SA17

SA19

SA0

SA2

SA4

SA6

SA8

SA10

SA12

SA14

SA16

SA18

SA5

SA7

SD14

SD9

SD13SD12

SD7

SD11SD10

SD8

SD5

SD3

SD6

SD4

SD1

SD[0..15]

SD2

SD0

SD15

FPSHIFT

LCDVCC

FPFRAME

BLCDPWR

DRDY

BDRDY

FPLINE

BFPFRAME

BFPSHIFT

BFPLINE

LCDP

+12V

VDDH

VLCD

VCC

VCCVCC+12V+12V

3.3V

VCC

IOVDD

CON40A

74AHC244

1A1

21Y1 18

1A2

41Y2 16

1A3

61Y3 14

1A4

81Y4 12

2A1

11 2Y1 9

2A2

13 2Y2 7

2A3

15 2Y3 5

2A4

17 2Y4 3

12G

19 VCC 20

GND 10

74AHC244

1A1

21Y1 18

1A2

41Y2 16

1A3

61Y3 14

1A4

81Y4 12

2A1

11 2Y1 9

2A2

13 2Y2 7

2A3

15 2Y3 5

2A4

17 2Y4 3

12G

19 VCC 20

GND 10

0.1uF

JP4

HEADER 3

+C12

10uF/25V

LT1117CM-3.3

VIN

ADJ

VOUT 2

C11

0.1uF

HEADER 17X2

1 2

3 4

5 6

7 8

910

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

HEADER 17X2

1 2

3 4

5 6

7 8

910

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

C10

0.1uF

74AHC244

1A1

21Y1 18

1A2

41Y2 16

1A3

61Y3 14

1A4

81Y4 12

2A1

11 2Y1 9

2A2

13 2Y2 7

2A3

15 2Y3 5

2A4

17 2Y4 3

12G

19 VCC 20

GND 10

25.0Mhz

OUT

8GND 7

VCC 14

C24

0.1uF

JP6

HEADER 3

FPSHIFT

DRDY

FPLINE

FPFRAME

FPDAT[0..7]

FPDAT8

FPDAT9

FPDAT10

FPDAT11

BS#

RD#

WAIT#WE0#

CS#

RESET#

WE1#

SA[0..19]

SD[0..15]

RD/WR#

BUSCLK

CLKI

LCDPWR LCDPWR#

8: SCHEMATIC DIAGRAMS

S5U13705B00C REV. 1.0 ISA BUS EVALUATION EPSON 4-15

BOARD USER’S MANUAL (X27A-G-005-01)

Figure 8-4 S5U13705B00C Schematic Diagram (4 of 4)

B B

D D

1.0

Epson Research & Development, Inc.

S5U13705B00C ISA-Bus Rev. 1.0 Evaluation Board : LCD Power Supply

44Monday, January 04, 1999

Size Document Number Rev

Date: Sheet of

LCDPWR#

PSVCC

VCC

PSVCC

IOVDD

VLCD

VDDH

VCC

VCC VCC VCC VCC

+C21

4.7uF/50V

R18

10K R19

100K

R20

100K

R14

475K

R15

200K Pot.

R16

14K

+C19

4.7uF/50V +C20

4.7uF/50V

+C22

47uF/16V

C23

56uF/35V Low ESR

C18

47uF/16V

R17

10K

R21

100K Pot.

U10

RD-0412

VOUT_ADJ

DC_IN

REMOTE

GND

4GND

5GND

6GND

7GND

GND

10 GND

DC_OUT

U11

EPN001

DC_OUT

1DC_OUT

2NC

GND

4GND

5VOUT_ADJ

7NC

8NC

DC_IN

11 DC_IN

1uH

2 5

1 2

U9B

74HCT04

3 4

MMBT3904

2 3

MMBT3906

U9C

74HCT04

U9D

74HCT04

U9E

74HCT04

11 10

U9F

74HCT04

13 12

PSGND

LCDPWR

LCDPWR#

8: SCHEMATIC DIAGRAMS

4-16 EPSON S5U13705B00C REV. 1.0 ISA BUS EVALUATION

BOARD USER’S MANUAL (X27A-G-005-01)

THIS PAGE IS BLANK.

S1D13705F00A

Embedded Memory LCD Controller

Application Notes

 
CONTENTS
 
S1D13705F00A APPLICATION NOTES
 
EPSON
 
5-i
Contents
1I
 
NTERFACING
 
 
 
TO
 
 
 
THE
 
 M
 
OTOROLA
 
 MC68328 “D
 
RAGONBALL
 
” M
 
ICROPROCESSOR
 
..........................5-1
 
1.1 Introduction....................................................................................................................................5-1
1.2 Interfacing to the MC68328...........................................................................................................5-1
The MC68328 System Bus........................................................................................................5-1
Chip-Select Module....................................................................................................................5-2
1.3 S1D13705 Host Bus Interface.......................................................................................................5-2
Host Bus Pin Connection...........................................................................................................5-2
Generic #1 Interface Mode ........................................................................................................5-3
MC68K #1 Interface Mode.........................................................................................................5-4
1.4 MC68328 To S1D13705 Interface.................................................................................................5-5
Hardware Description ................................................................................................................5-5
S1D13705 Hardware Configuration...........................................................................................5-7
MC68328 Chip Select Configuration..........................................................................................5-7
1.5 Software ........................................................................................................................................5-7
 
2I
 
NTERFACING
 
 
 
TO
 
 
 
THE
 
 M
 
OTOROLA
 
 MPC821 M
 
ICROPROCESSOR
 
....................................................5-8
 
2.1 Introduction....................................................................................................................................5-8
2.2 Interfacing to the MPC821.............................................................................................................5-8
The MPC8xx System Bus..........................................................................................................5-8
MPC821 Bus Overview..............................................................................................................5-8
Memory Controller Module.......................................................................................................5-11
2.3 S1D13705 Host Bus Interface.....................................................................................................5-11
Host Bus Interface Modes........................................................................................................5-12
Generic #1 Host Bus Interface Mode.......................................................................................5-12
2.4 MPC821 to S1D13705 Interface .................................................................................................5-13
Hardware Description ..............................................................................................................5-13
MPC821ADS Evaluation Board Hardware Connections..........................................................5-14
S1D13705 Hardware Configuration.........................................................................................5-15
MPC821 Chip Select Configuration .........................................................................................5-16
Test Software...........................................................................................................................5-17
2.5 Software ......................................................................................................................................5-17
 
3I
 
NTERFACING
 
 
 
TO
 
 
 
THE
 
 M
 
OTOROLA
 
 MCF5307 “C
 
OLD
 
F
 
IRE
 
” M
 
ICROPROCESSOR
 
............................5-18
 
3.1 Introduction..................................................................................................................................5-18
3.2 Interfacing to the MCF5307.........................................................................................................5-18
The MCF5307 System Bus......................................................................................................5-18
Chip-Select Module..................................................................................................................5-20
3.3 S1D13705 Bus Interface .............................................................................................................5-20
Host Bus Pin Connection.........................................................................................................5-20
Generic #1 Interface Mode ......................................................................................................5-21
3.4 MCF5307 To S1D13705 Interface ..............................................................................................5-21
Hardware Description ..............................................................................................................5-21
S1D13705 Hardware Configuration.........................................................................................5-22
MCF5307 Chip Select Configuration .......................................................................................5-23
3.5 Software ......................................................................................................................................5-23
 
4I
 
NTERFACING
 
 
 
TO
 
 
 
THE
 
 PC C
 
ARD
 
 B
 
US
 
.......................................................................................5-24
 
4.1 Introduction..................................................................................................................................5-24
4.2 Interfacing to the PC Card Bus....................................................................................................5-24
The PC Card System Bus........................................................................................................5-24
4.3 S1D13705 Bus Interface .............................................................................................................5-26
Host Bus Pin Connection.........................................................................................................5-26
Generic #2 Interface Mode ......................................................................................................5-26
4.4 PC Card to S1D13705 Interface..................................................................................................5-27
Hardware Connections ............................................................................................................5-27
S1D13705 Hardware Configuration.........................................................................................5-28
Register/Memory Mapping.......................................................................................................5-28

 
CONTENTS
 
5-ii
 
EPSON
 
S1D13705F00A APPLICATION NOTES
 
4.5 Software......................................................................................................................................5-28
 
5I
 
NTERFACING
 
 
 
TO
 
 
 
THE
 
 T
 
OSHIBA
 
 MIPS TMPR3912 M
 
ICROPROCESSOR
 
........................................5-29
 
5.1 Introduction .................................................................................................................................5-29
5.2 Interfacing to the TMPR3912......................................................................................................5-29
5.3 S1D13705 Host Bus Interface.....................................................................................................5-29
Host Bus Pin Connection.........................................................................................................5-29
Generic #1 Interface Mode......................................................................................................5-30
Generic #2 Interface Mode......................................................................................................5-31
5.4 Direct Connection to the Toshiba TMPR3912.............................................................................5-31
General Description.................................................................................................................5-31
Memory Mapping and Aliasing ................................................................................................5-32
S1D13705 Configuration .........................................................................................................5-33
5.5 Using the ITE IT8368E PC Card Buffer ......................................................................................5-33
Hardware Description..............................................................................................................5-33
IT8368E Configuration.............................................................................................................5-34
Memory Mapping and Aliasing ................................................................................................5-35
S1D13705 Configuration .........................................................................................................5-35
5.6 Software......................................................................................................................................5-35
 
6I
 
NTERFACING
 
 
 
TO
 
 
 
THE
 
 P
 
HILIPS
 
 MIPS PR31500/PR31700 P
 
ROCESSOR
 
......................................5-36
 
6.1 Introduction .................................................................................................................................5-36
6.2 Interfacing to the PR31500/PR31700 .........................................................................................5-36
6.3 S1D13705 Host Bus Interface.....................................................................................................5-36
Host Bus Pin Connection.........................................................................................................5-37
Generic #1 Interface Mode......................................................................................................5-37
Generic #2 Interface Mode......................................................................................................5-38
6.4 Direct Connection to the Philips PR31500/PR31700..................................................................5-39
General Description.................................................................................................................5-39
Memory Mapping and Aliasing ................................................................................................5-40
S1D13705 Configuration and Pin Mapping .............................................................................5-40
6.5 Using the ITE IT8368E PC Card Buffer ......................................................................................5-40
Hardware Description..............................................................................................................5-40
IT8368E Configuration.............................................................................................................5-42
Memory Mapping and Aliasing ................................................................................................5-42
S1D13705 Configuration .........................................................................................................5-42
6.6 Software......................................................................................................................................5-43
 
7I
 
NTERFACING
 
 
 
TO
 
 
 
THE
 
 NEC VR4102/VR4111 M
 
ICROPROCESSOR
 
..............................................5-44
 
7.1 Introduction .................................................................................................................................5-44
7.2 Interfacing to the NEC VR4102/VR4111.....................................................................................5-44
The NEC VR4102/VR4111 System Bus..................................................................................5-44
7.3 S1D13705 Host Bus Interface.....................................................................................................5-46
Host Bus Pin Connection.........................................................................................................5-46
Generic #2 Interface Mode......................................................................................................5-46
7.4 VR4102/VR4111 to S1D13705 Interface....................................................................................5-47
Hardware Description..............................................................................................................5-47
S1D13705 Hardware Configuration.........................................................................................5-48
NEC VR4102/VR4111 Configuration.......................................................................................5-48
7.5 Software......................................................................................................................................5-48
 
8I
 
NTERFACING
 
 
 
TO
 
 
 
THE
 
 NEC VR4181ATM M
 
ICROPROCESSOR
 
....................................................5-49
 
8.1 Introduction .................................................................................................................................5-49
8.2 Interfacing to the NEC VR4181A ................................................................................................5-49
The NEC VR4181A System Bus .............................................................................................5-49
8.3 S1D13705 Host Bus Interface.....................................................................................................5-50
Host Bus Pin Connection.........................................................................................................5-50
Generic #2 Interface Mode......................................................................................................5-50
8.4 VR4181A to S1D13705 Interface................................................................................................5-51

 
CONTENTS
 
S1D13705F00A APPLICATION NOTES
 
EPSON
 
5-iii
 
Hardware Description ..............................................................................................................5-51
S1D13705 Hardware Configuration.........................................................................................5-52
NEC VR4181A Configuration...................................................................................................5-52
8.5 Software ......................................................................................................................................5-53
 
9 S1D13705 P
 
OWER
 
 C
 
ONSUMPTION
 
.........................................................................................5-54
 
9.1 S1D13705 Power Consumption..................................................................................................5-54
Conditions................................................................................................................................5-55
9.2 Summary.....................................................................................................................................5-55

 
CONTENTS
 
5-iv
 
EPSON
 
S1D13705F00A APPLICATION NOTES
 
List of Figures
 
Figure 1-1 Typical Implementation of MC68328 to S1D13705 Interface - MC68K #1 ..........................5-5
Figure 1-2 Typical Implementation of MC68328 to S1D13705 Interface - Generic #1..........................5-6
Figure 2-1 Power PC Memory Read Cycle ...........................................................................................5-9
Figure 2-2 Power PC Memory Write Cycle..........................................................................................5-10
Figure 2-3 Typical Implementation of MPC821 to S1D13705 Interface..............................................5-13
Figure 3-1 MCF5307 Memory Read Cycle..........................................................................................5-19
Figure 3-2 MCF5307 Memory Write Cycle..........................................................................................5-19
Figure 3-3 Typical Implementation of MCF5307 to S1D13705 Interface ............................................5-22
Figure 4-1 PC Card Read Cycle..........................................................................................................5-25
Figure 4-2 PC Card Write Cycle..........................................................................................................5-25
Figure 4-3 Typical Implementation of PC Card to S1D13705 Interface ..............................................5-27
Figure 5-1 S1D13705 to TMPR3912 Direct Connection .....................................................................5-32
Figure 5-2 S1D13705 to TMPR3912 Connection Using an IT8368E..................................................5-34
Figure 6-1 S1D13705 to PR31500/PR31700 Direct Connection ........................................................5-39
Figure 6-2 S1D13705 to PR31500/PR31700 Connection Using an IT8368E.....................................5-41
Figure 7-1 NEC VR4102/VR4111 Read/Write Cycles.........................................................................5-45
Figure 7-2 Typical Implementation of VR4102/VR4111 to S1D13705 Interface.................................5-47
Figure 8-1 Typical Implementation of VR4181A to S1D13705 Interface.............................................5-51
 
List of Tables
 
Table 1-1 Host Bus Interface Pin Mapping ..........................................................................................5-2
Table 1-2 Summary of Power-On/Reset Options.................................................................................5-7
Table 1-3 Host Bus Interface Selection................................................................................................5-7
Table 2-1 Host Bus Interface Pin Mapping ........................................................................................5-12
Table 2-2  List of Connections from MPC821ADS to S1D13705.......................................................5-14
Table 2-3 Configuration Settings........................................................................................................5-15
Table 2-4 Host Bus Interface Selection..............................................................................................5-15
Table 3-1 Host Bus Interface Pin Mapping ........................................................................................5-20
Table 3-2 Summary of Power-On/Reset Options...............................................................................5-22
Table 3-3 Host Bus Interface Selection..............................................................................................5-22
Table 4-1 Host Bus Interface Pin Mapping ........................................................................................5-26
Table 4-2 Summary of Power-On/Reset Options...............................................................................5-28
Table 4-3 Host Bus Interface Selection..............................................................................................5-28
Table 5-1 Host Bus Interface Pin Mapping ........................................................................................5-29
Table 5-2 S1D13705 Configuration for Direct Connection.................................................................5-33
Table 5-3 TMPR3912 to PC Card Slots Address Mapping With and Without the IT8368E...............5-35
Table 5-4 S1D13705 Configuration Using the IT8368E.....................................................................5-35
Table 6-1 Host Bus Interface Pin Mapping ........................................................................................5-37
Table 6-2 S1D13705 Configuration for Direct Connection.................................................................5-40
Table 6-3 PR31500/PR31700 to PC Card Slots Address Mapping With and Without the IT8368E ..5-42
Table 6-4 S1D13705 Configuration Using the IT8368E.....................................................................5-42
Table 7-1 Host Bus Interface Pin Mapping ........................................................................................5-46
Table 7-2 Summary of Power-On/Reset Options...............................................................................5-48
Table 7-3 Host Bus Interface Selection..............................................................................................5-48
Table 8-1 Host Bus Interface Pin Mapping ........................................................................................5-50
Table 8-2 Summary of Power-On/Reset Options...............................................................................5-52
Table 8-3 Host Bus Interface Selection..............................................................................................5-52
Table 9-1 S1D13705 Total Power Consumption................................................................................5-55

1: INTERFACING TO THE MOTOROLA MC68328 “DRAGONBALL” MICROPROCESSOR

S1D13705F00A APPLICATION NOTES

EPSON

5-1

(X27A-G-007-01)

NTERFACING

THE

OTOROLA

MC68328

“D

RAGONBALL

” M

ICROPROCESSOR

1.1 Introduction

This application note describes the hardware required to interface the S1D13705 Embedded

Memory LCD Controller and the Motorola MC68328 “Dragonball” Microprocessor. By

implementing an embedded display refresh buffer, the S1D13705 can reduce system power

consumption, improve image quality, and increase system performance as compared to the

Dragonball’s on-chip LCD controller.

1.2 Interfacing to the MC68328

The MC68328 System Bus

The MC68328 is an integrated controller for handheld products, based upon the MC68EC000

microprocessor core. It implements a 16-bit data bus and a 32-bit address bus. The bus interface

consists of all the standard MC68000 bus interface signals, plus some new signals intended to

simplify the task of interfacing to typical memory and peripheral devices.

The MC68000 bus control signals are well documented in Motorola’s user manuals, and will not be

described here. A brief summary of the new signals appears below:

• Output Enable (OE#) is asserted when a read cycle is in process; it is intended to connect to the

output enable control of a typical static RAM, EPROM, or Flash EPROM device.

• Upper Write Enable and Lower Write Enable (UWE#/LWE#) are asserted during memory write

cycles for the upper and lower bytes of the 16-bit data bus; they may be directly connected to the

write enable inputs of a typical memory device.

The S1D13705 implements the MC68000 bus interface using its MC68K #1 mode, so this mode

may be used to connect the MC68328 directly to the S1D13705 with no glue logic. Ho wev er , sev eral

of the MC68000 bus control signals are multiplexed with IO and interrupt signals on the MC68328,

and in many applications it may be desirable to make these pins available for these alternate

functions. This requirement may be accommodated through the use of the Generic #1 interface

mode on the S1D13705.

X27A-G-007-01

1: INTERFACING TO THE MOTOROLA MC68328 “DRAGONBALL” MICROPROCESSOR

5-2

EPSON

S1D13705F00A APPLICATION NOTES

(X27A-G-007-01)

Chip-Select Module

The MC68328 can generate up to 16 chip select outputs, organized into four groups “A” through

“D”.

Each chip select group has a common base address register and address mask re gister , to set the base

address and block size of the entire group. In addition, each chip select within a group has its own

address compare and address mask register, to activate the chip select for a subset of the group’s

address block. Finally, each chip select may be individually programmed to control an 8 or 16-bit

device, and each may be individually programmed to generate from 0 through 6 wait states

internally, or allow the memory or peripheral device to terminate the cycle e xternally through use of

the standard MC68000 DTACK# signal.

Groups A and B can have a minimum block size of 64K bytes, so these are typically used to control

memory devices. Chip select A0 is active immediately after reset, so it is typically used to control a

boot EPROM device. Groups C and D have a minimum block size of 4K bytes, so they are well-

suited to controlling peripheral devices. Chip select D3 is associated with the MC68328 on-chip

PCMCIA control logic.

1.3 S1D13705 Host Bus Interface

This section is a summary of the host bus interface modes available on the S1D13705 that may be

used to interface to the MC68328.

The S1D13705 implements a 16-bit interface to the host microprocessor which may operate in one

of several modes compatible with most of the popular embedded microprocessor families. The two

interface modes that may be used for the MC68328 are:

• Motorola MC68K #1 (using Upper Data Strobe/Lower Data Strobe).

• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).

Host Bus Pin Connection

The following table shows the functions of each host bus interface signal.

For details on conﬁguration, refer to the

“S1D13705 Hardware Functional Speciﬁcation”

document number X27A-A-001-01.

Table 1-1 Host Bus Interface Pin Mapping

S1D13705

Pin Names MC68K #1 Generic #1

AB[15:1] A[15:1] A[15:1]

AB0 LDS# A0

DB[15:0] D[15:0] D[15:0]

WE1# UDS# WE1#

CS# External Decode External Decode

BCLK CLK BCLK

BS# AS# connect to V

RD/WR# R/W# RD1#

RD# connect to IO V

RD0#

WE0# connect to IO V

WE0#

WAIT# DTACK# WAIT#

RESET# RESET# RESET#

1: INTERFACING TO THE MOTOROLA MC68328 “DRAGONBALL” MICROPROCESSOR

S1D13705F00A APPLICATION NOTES

EPSON

5-3

(X27A-G-007-01)

Generic #1 Interface Mode

Generic #1 interface mode is the most general and least processor-speciﬁc interface mode on the

S1D13705. The Generic # 1 interf ace mode was chosen for this interface due to the simplicity of its

timing.

The interface requires the following signals:

• BUSCLK is a clock input which is required by the S1D13705 host interface. It is separate from

the input clock (CLKI) and is typically driven by the host CPU system clock.

• The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect directly to

the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power

PC, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big

endian hosts, they would connect to the low-order data lines. The hardware engineer must ensure

that CNF3 selects the proper endian mode upon reset.

• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper register

and memory address space.

• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be

driven low when the host CPU is writing data to the S1D13705. These signals must be generated

by external hardware based on the control outputs from the host CPU.

• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively, to be

driven low when the host CPU is reading data from the S1D13705. These signals must be gener-

ated by external hardware based on the control outputs from the host CPU.

• WAIT# is a signal output from the S1D13705 that indicates the host CPU must wait until data is

ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the

S1D13705 may occur asynchronously to the display update, it is possible that contention may

occur in accessing the S1D13705 internal registers and/or refresh memory. The WAIT# line

resolves these contentions by forcing the host to wait until the resource arbitration is complete.

This signal is active low and may need to be inverted if the host CPU wait state signal is active

high.

• The Bus Status (BS#) signal is not used in the bus interf ace for Generic #1 mode. Howe v er , BS# is

used to conﬁgure the S1D13705 for Generic #1 mode and should be tied lo w (connected to GND).

1: INTERFACING TO THE MOTOROLA MC68328 “DRAGONBALL” MICROPROCESSOR

5-4

EPSON

S1D13705F00A APPLICATION NOTES

(X27A-G-007-01)

MC68K #1 Interface Mode

The MC68K #1 Interface Mode can be used to interface to the MC68328 microprocessor if the

previously mentioned, multiplexed, bus signals will not be used for other purposes.

The interface requires the following signals:

• BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705.

It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.

• The address inputs AB1 through AB16, and the data bus DB0 through DB15, connect directly to

the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power

PC, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big

endian hosts, they would connect to the low-order data lines. The hardware engineer must ensure

that CNF3 selects the proper endian mode upon reset.

• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper register

and memory address space.

• A0 and WE1# are the enables for the low-order and high-order bytes, respectively, to be driven

low when the host CPU is reading or writing data to the S1D13705.

• RD/WR# is the read/write signal that is driven low when the CPU writes to the S1D13705 and is

driven high when the CPU is doing a read from the S1D13705.

• WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates when data is

ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the

S1D13705 may occur asynchronously to the display update, it is possible that contention may

occur in accessing the S1D13705 internal registers and/or refresh memory. The WAIT# line

resolves these contentions by forcing the host to wait until the resource arbitration is complete.

• The Bus Status (BS#) signal indicates that the address on the address bus is valid.

• The WE0# and RD# signals is not used in the bus interface for MC68K #1 and must be tied high

(tied to IO V

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S1D13705F00A APPLICATION NOTES EPSON 5-5

(X27A-G-007-01)

1.4 MC68328 To S1D13705 Interface

Hardware Description

The interface between the MC68328 and the S1D13705 can be implemented using either the

MC68K #1 or Generic #1 host bus interface of the S1D13705.

Using The MC68K #1 Host Bus Interface

The MC68328 multiplex es dual functions on some of its bus control pins (speciﬁcally UDS#, LDS#,

and DTACK#). In implementations where all of these pins are available for use as bus control pins,

then the S1D13705 interface is a straightforward implementation of the “MC68K #1” host bus

interface. For further information on this host bus interface, refer to the “S1D13705 Hardware

Functional Speciﬁcation”, document number X27A-A-001-02.

The following diagram shows a typical implementation of the MC68328 to S1D13705 using the

MC68K #1 host bus interface.

Figure 1-1 Typical Implementation of MC68328 to S1D13705 Interface - MC68K #1

MC68328 S1D13705

A[16:0]

D[15:0]

DTACK#

UDS#

LDS#

R/W#

CLK0

AB[16:1]

DB[15:0]

CS#

WAIT#

WE1#

AB0

RD/WR#

RD#

BUSCLK

RESET#

Vcc

470

CSB3

AS# BS#

Vcc

System RESET

WE0##

Vcc

Note:

When connecting the S1D13705 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

1: INTERFACING TO THE MOTOROLA MC68328 “DRAGONBALL” MICROPROCESSOR

5-6 EPSON S1D13705F00A APPLICATION NOTES

(X27A-G-007-01)

Using The Generic #1 Host Bus Interface

If UDS# and/or LDS# are required for their alternate IO functions, then the MC68328 to S1D13705

interface may be implemented using the S1D13705 Generic #1 host b us interface. Note that in either

case, the DTACK# signal must be made available for the S1D13705, since it inserts a variable

number of wait states depending upon CPU/LCD synchronization and the LCD panel display mode.

WAIT# must be inv erted (using an in verter enabled by CS#) to mak e it an acti ve high signal and thus

compatible with the MC68328 architecture. A single resistor is used to speed up the rise time of the

WAIT# (DTACK#) signal when terminating the bus cycle.

The following diagram shows a typical implementation of the MC68328 to S1D13705 using the

Generic #1 host bus interface.

Figure 1-2 Typical Implementation of MC68328 to S1D13705 Interface - Generic #1

MC68328 S1D13705

A[16:0]

D[15:0]

DTACK#

UWE#

LWE#

OE#

CLK0

AB[16:0]

DB[15:0]

CS#

WAIT#

WE1#

WE0#

RD/WR#

RD#

BUSCLK

RESET#

Vcc

470

CSB3

BS#

Note:

When connecting the S1D13705 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

System RESET

1: INTERFACING TO THE MOTOROLA MC68328 “DRAGONBALL” MICROPROCESSOR

S1D13705F00A APPLICATION NOTES EPSON 5-7

(X27A-G-007-01)

S1D13705 Hardware Conﬁguration

The S1D13705 uses CNF3 through CNF0 and BS# to allow selection of the bus mode and other

conﬁguration data on the rising edge of RESET#. Refer to the “S1D13705 Hardware Functional

Speciﬁcation”, document number X27A-A-001-02 for details.

The tables belo w sho w those conﬁguration settings important to the MC68K #1 and Generic #1 host

bus interfaces.

MC68328 Chip Select Conﬁguration

The S1D13705 requires a 128K byte address space for the display buffer and its internal registers.

To accommodate this block size, it is preferable (b ut not required) to use one of the chip selects from

groups A or B. Virtually any chip select other than CSA0 or CSD3 would be suitable for the

S1D13705 interface.

In the example interface, chip select CSB3 is used to control the S1D1375. A 128K byte address

space is used with the S1D13705 control registers mapped into the top 32 bytes of the 128K byte

block and the 80K bytes of display buffer mapped to the starting address of the block. The chip

select should have its RO (Read Only) bit set to 0, and the WAIT ﬁeld (Wait states) should be set to

111b to allow the S1D13705 to terminate bus cycles externally.

1.5 Software

Test utilities and Windows® CE v2.0 display drivers are available for the S1D13705. Full source

code is available for both the test utilities and the drivers.

The test utilities are conﬁgurable for different panel types using a program called 1375CFG, or by

directly modifying the source. The Windows® CE v2.0 display drivers can be customized by the

OEM for different panel types, resolutions and color depths only by modifying the source.

Table 1-2 Summary of Power-On/Reset Options

S1D13705

Pin Name value on this pin at the rising edge of RESET# is used to conﬁgure: (1/0)

CNF0 See “Table 1-3: Host Bus Interface Selection”CNF1

CNF2

CNF3 Little Endian Big Endian

= conﬁguration for MC68328 support

Table 1-3 Host Bus Interface Selection

CNF2 CNF1 CNF0 BS# Host Bus Interface

0 0 0 X SH-4 interface

0 0 1 X SH-3 interface

0 1 0 X reserved

0 1 1 X MC68K #1, 16-bit

1 0 0 X reserved

1 0 1 X MC68K #2, 16-bit

1100reserved

1101reserved

1 1 1 0 Generic #1, 16-bit

1 1 1 1 Generic #2, 16-bit

= conﬁguration for MC68328 using Generic #1 host bus interface

= conﬁguration for MC68328 using MC68K #1 host bus interface

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR

5-8 EPSON S1D13705F00A APPLICATION NOTES

(X27A-G-010-01)

2INTERFACING TO THE MOTOROLA

MPC821 MICROPROCESSOR

2.1 Introduction

This application note describes the hardware and software environment required to interface the

S1D13705 Embedded Memory LCD Controller and the Motorola MPC821 Processor.

2.2 Interfacing to the MPC821

The MPC8xx System Bus

The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern

RISC microprocessors. This section provides an overview of the operation of the CPU bus in order

to establish interface requirements.

MPC821 Bus Overview

The MPC8xx microprocessor family uses a synchronous address and data bus. All IO is

synchronous to a square-wave reference clock called MCLK (Master Clock). This clock runs at the

machine cycle speed of the CPU core (typically 25 to 50 MHz). Most outputs from the processor

change state on the rising edge of this clock. Similarly, most inputs to the processor are sampled on

the rising edge.

Note: The external bus can run at one-half the CPU core speed using the clock control register. This

is typically used when the CPU core is operated above 50 MHz.

The MPC821 can generate up to eight independent chip select outputs, each of which may be

controlled by one of two types of timing generators: the General Purpose Chip Select Module

(GPCM) or the User-Programmable Machine (UPM). Examples are given using the GPCM.

It should be noted that all Po wer PC microprocessors, including the MPC8xx family, use bit notation

opposite from the convention used by most other microprocessor systems. Bit numbering for the

MPC8xx always starts with zero as the most signiﬁcant bit, and increments in value to the least-

signiﬁcant bit. For e xample, the most signiﬁcant bits of the address bus and data bus are A0 and D0,

while the least signiﬁcant bits are A31 and D31.

The MPC8xx uses both a 32-bit address and data bus. A parity bit is supported for each of the four

byte lanes on the data bus. Parity checking is done when data is read from external memory or

peripherals, and generated by the MPC8xx bus controller on write cycles. All IO accesses are

memory-mapped meaning there is no separate IO space in the Power PC architecture.

Support is provided for both on-chip (DMA controllers) and off-chip (other processors and

peripheral controllers) bus masters.

The bus can support both normal and burst cycles. Burst memory cycles are used to ﬁll

on-chip cache memory, and for certain on-chip DMA operations. Normal cycles are used for all

other data transfers.

X27A-G-010-01

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR

S1D13705F00A APPLICATION NOTES EPSON 5-9

(X27A-G-010-01)

Normal (Non-Burst) Bus Transactions

A data transfer is initiated by the bus master by placing the memory address on address lines A0

through A31 and driving TS (T ransfer Start) lo w for one clock c ycle. Se veral control signals are also

provided with the memory address:

• TSIZ[0:1] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32-bit.

• RD/WR -- set high for read cycles and low for write cycles.

• AT[0:3] (Address Type Signals) -- provides more detail on the type of transfer being attempted.

When the peripheral device being accessed has completed the bus transfer, it asserts TA (Transfer

Acknowledge) for one clock cycle to complete the bus transaction. Once TA has been asserted, the

MPC821 will not start another bus cycle until TA has been de-asserted. The minimum length of a

bus transaction is two bus clocks.

Figure 2-1 “Power PC Memory Read Cycle” illustrates a typical memory read cycle on the Power

PC system bus.

Figure 2-1 Power PC Memory Read Cycle

A[0:31]

D[0:31]

TSIZ[0:1], AT[0:3]

SYSCLK

Wait StatesTransfer Start Transfer Next Transfer

Sampled when TA low

RD/WR

Complete Starts

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR

5-10 EPSON S1D13705F00A APPLICATION NOTES

(X27A-G-010-01)

Figure 2-2 “Po wer PC Memory Write Cycle” illustrates a typical memory write cycle on the Power

PC system bus.

Figure 2-2 Power PC Memory Write Cycle

If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is aborted. For

example, a peripheral device may assert TEA if a parity error is detected, or the MPC821 bus

controller may assert TEA if no peripheral de vice responds at the addressed memory location within

a bus time-out period.

For 32-bit transfers, all data lines (D[0:31]) are used and the two low-order address lines A30 and

A31 are ignored. For 16-bit transfers, data lines D0 through D15 are used and address line A30 is

ignored. For 8-bit transfers, data lines D0 through D7 are used and all address lines (A[0:31]) are

used.

Note: This assumes that the Power PC core is operating in big endian mode (typically the case for

embedded systems).

Burst Cycles

Burst memory cycles are used to ﬁll on-chip cache memory and to carry out certain on-chip DMA

operations. They are very similar to normal bus cycles with the following exceptions:

• Always 32-bit.

• Always attempt to transfer four 32-bit words sequentially.

• Always address longword-aligned memory (i.e. A30 and A31 are always 0:0).

• Do not increment address bits A28 and A29 between successive transfers; the addressed device

must increment these address bits internally.

If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI)

simultaneously with TA, and the processor will revert to normal bus cycles for the remaining data

transfers.

Burst cycles are mainly intended to f acilitate cache line ﬁlls from program or data memory. They are

normally not used for transfers to/from IO peripheral devices such as the S1D13705, therefore the

interfaces described in this document do not attempt to support burst cycles. However, the example

interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is

accidently enabled for the S1D13705 address space.

A[0:31]

D[0:31]

TSIZ[0:1], AT[0:3]

SYSCLK

Wait StatesTransfer Start

RD/WR

Valid

Transfer Ne xt Transf er

Complete Starts

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR

S1D13705F00A APPLICATION NOTES EPSON 5-11

(X27A-G-010-01)

Memory Controller Module

General-Purpose Chip Select Module (GPCM)

The General-Purpose Chip Select Module (GPCM) is used to control memory and peripheral

devices which do not require special timing or address multiplexing. In addition to the chip select

output, it can generate active-low Output Enable (OE) and Write Enable (WE) signals compatible

with most memory and x86-style peripherals. The MPC821 bus controller also provides a Read/

Write (RD/WR) signal which is compatible with most 68K peripherals.

The GPCM is controlled by the v alues programmed into the Base Register (BR) and Option Register

(OR) of the respective chip select. The Option Register sets the base address, the block size of the

chip select, and controls the following timing parameters:

• The ACS bit ﬁeld allows the chip select assertion to be delayed with respect to the address bus

valid, by 0, 1/4, or 1/2 clock cycle.

• The CSNT bit causes chip select and WE to be negated 1/2 clock cycle earlier than normal.

• The TRLX (relaxed timing) bit will insert an additional one clock delay between assertion of the

address bus and chip select. This accommodates memory and peripherals with long setup times.

• The EHTR (Extended hold time) bit will insert an additional 1-clock delay on the ﬁrst access to a

chip select.

• Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself by assert-

ing TA (Transfer Acknowledge).

• Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its memory

space is addressed by the processor core.

User-Programmable Machine (UPM)

The UPM is typically used to control memory types, such as Dynamic RAMs, which have complex

control or address multiplexing requirements. The UPM is a general purpose RAM-based pattern

generator which can control address multiplexing, wait state generation, and ﬁve general-purpose

output lines on the MPC821. Up to 64 pattern locations are available, each 32 bits wide. Separate

patterns may be programmed for normal accesses, burst accesses, refresh (timer) events, and

exception conditions. This ﬂexibility allows almost any type of memory or peripheral device to be

accommodated by the MPC821.

In this application note, the GPCM is used instead of the UPM, since the GPCM has enough

ﬂexibility to accommodate the S1D13705 and it is desirable to leave the UPM free to handle other

interfacing duties, such as EDO DRAM.

2.3 S1D13705 Host Bus Interface

This section is a summary of the host bus interface mode used on the S1D13705 to interface to the

MPC821.

The S1D13705 implements a 16-bit interface to the host microprocessor which may operate in one

of several modes compatible with most of the popular embedded microprocessor families. The

interface mode used for the MPC821 is:

• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR

5-12 EPSON S1D13705F00A APPLICATION NOTES

(X27A-G-010-01)

Host Bus Interface Modes

For details on conﬁguration, refer to the “S1D13705 Hardware Functional Speciﬁcation”,

document number X27A-A-001-01.

Generic #1 Host Bus Interface Mode

Generic #1 host bus interface mode is the most general and least processor-speciﬁc host bus

interface mode on the S1D13705. The Generic # 1 host bus interface mode was chosen for this

interface due to the simplicity of its timing.

The host bus interface requires the following signals:

• BUSCLK is a clock input which is required by the S1D13705 host interface. It is separate from

the input clock (CLKI) and is typically driven by the host CPU system clock.

• The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect directly to

the CPU address and data bus, respectively. On 32-bit big endian architectures such as the Power

PC, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big

endian hosts, they would connect to the low-order data lines. The hardware engineer must ensure

that CNF3 selects the proper endian mode upon reset.

• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper IO or

memory address space.

• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be

driven low when the host CPU is writing data to the S1D13705.

• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively, to be

driven low when the host CPU is reading data from the S1D13705.

• WAIT# is a signal output from the S1D13705 that indicates the host CPU must wait until data is

ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the

S1D13705 may occur asynchronously to the display update, it is possible that contention may

occur in accessing the S1D13705 internal registers and/or refresh memory. The WAIT# line

resolves these contentions by forcing the host to wait until the resource arbitration is complete.

This signal is active low and may need to be inverted if the host CPU wait state signal is active

high.

• The Bus Status (BS#) signal is not used in the bus interf ace for Generic #1 mode. Howe v er , BS# is

used to conﬁgure the S1D13705 for Generic #1 mode and should be tied lo w (connected to GND).

Table 2-1 Host Bus Interface Pin Mapping

S1D13705

Pin Names Generic #1

AB[15:1] A[15:1]

AB0 A0

DB[15:0] D[15:0]

WE1# WE1#

CS# External Decode

BCLK BCLK

BS# connect to VSS

RD/WR# RD1#

RD# RD0#

WE0# WE0#

WAIT# WAIT#

RESET# RESET#

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR

S1D13705F00A APPLICATION NOTES EPSON 5-13

(X27A-G-010-01)

2.4 MPC821 to S1D13705 Interface

Hardware Description

The interface between the S1D13705 and the MPC821 requires minimal glue logic. One inverter is

required to change the polarity of the WAIT# signal (an activ e low signal) to insert wait states in the

bus cycle. The MPC821 Transfer Acknowledge signal (TA) is an active low signal which ends the

current bus cycle. The inverter is enabled using CS# so that TA is not driven by the S1D13705

during non-S1D13705 bus cycles. A single resistor is used to speed up the rise time of the WAIT#

(TA) signal when terminating the bus cycle.

BS# (bus start) is not used in this implementation and should be tied low (connected to GND).

The following diagram shows a typical implementation of the MPC821 to S1D13705 interface.

Figure 2-3 Typical Implementation of MPC821 to S1D13705 Interface

MPC821 S1D13705

A[15:31]

D[0:15]

CS4

WE0

WE1

SYSCLK

AB[16:0]

DB[15:0]

CS#

WAIT#

WE1#

WE0#

RD/WR#

RD#

BUSCLK

RESET#

Vcc

470

BS#

System RESET

Note:

When connecting the S1D13705 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR

5-14 EPSON S1D13705F00A APPLICATION NOTES

(X27A-G-010-01)

MPC821ADS Evaluation Board Hardware Connections

The following table details the connections between the pins and signals of the MPC821 and the

S1D13705.

Note: The bit numbering of the Power PC bus signals is reversed from the normal convention, e.g.:

the most significant address bit is A0, the next is A1, A2, etc.

Table 2-2 List of Connections from MPC821ADS to S1D13705

MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13705 Signal Name

Vcc P6-A1, P6-B1 Vcc

A15 P6-D20 A16

A16 P6-B24 A15

A17 P6-C24 A14

A18 P6-D23 A13

A19 P6-D22 A12

A20 P6-D19 A11

A21 P6-A19 A10

A22 P6-D28 A9

A23 P6-A28 A8

A24 P6-C27 A7

A25 P6-A26 A6

A26 P6-C26 A5

A27 P6-A25 A4

A28 P6-D26 A3

A29 P6-B25 A2

A30 P6-B19 A1

A31 P6-D17 A0

D0 P12-A9 D15

D1 P12-C9 D14

D2 P12-D9 D13

D3 P12-A8 D12

D4 P12-B8 D11

D5 P12-D8 D10

D6 P12-B7 D9

D7 P12-C7 D8

D8 P12-A15 D7

D9 P12-C15 D6

D10 P12-D15 D5

D11 P12-A14 D4

D12 P12-B14 D3

D13 P12-D14 D2

D14 P12-B13 D1

D15 P12-C13 D0

SRESET P9-D15 RESET#

SYSCLK P9-C2 BUSCLK

CS4 P6-D13 CS#

TA P6-B6 to inverter enabled by CS# WAIT#

WE0 P6-B15 WE1#

WE1 P6-A14 WE0#

OE P6-B16 RD/WR#, RD#

GND

P12-A1, P12-B1, P12-A2, P12-B2,

P12-A3, P12-B3, P12-A4, P12-B4,

P12-A5, P12-B5, P12-A6, P12-B6,

P12-A7

Vss

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S1D13705F00A APPLICATION NOTES EPSON 5-15

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S1D13705 Hardware Conﬁguration

The S1D13705 uses CNF3 through CNF0 and BS# to allow selection of the bus mode and other

conﬁguration data on the rising edge of RESET#. Refer to the “S1D13705 Hardware Functional

Speciﬁcation”, document number X27A-A-001-02 for details.

The tables below show only those conﬁguration settings important to the MPC821 interface. The

settings are very similar to the ISA bus with the following exceptions:

• the WAIT# signal is active high rather than active low.

• the Power PC is big endian rather than little endian.

Table 2-3 Conﬁguration Settings

Signal Low High

CNF0 See “Host Bus Interface Selection” table4-3

below. See “Host Bus Interface Selection” table4-3 below.CNF1

CNF2

CNF3 Little Endian Big Endian

= conﬁguration for MPC821 host bus interface

Table 2-4 Host Bus Interface Selection

CNF2 CNF1 CNF0 BS# Host Bus Interface

1 1 1 0 Generic #1, 16-bit

= conﬁguration for MPC821 host bus interface

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5-16 EPSON S1D13705F00A APPLICATION NOTES

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MPC821 Chip Select Conﬁguration

The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the

S1D13705 is addressed starting at 40 0000h. The S1D13705 uses a 128K byte segment of memory

starting at this address, with the ﬁrst 80K bytes used for the display buffer and the upper 32 bytes of

this memory block used for the S1D13705 internal registers.

Chip select 4 is used to control the S1D13705. The follo wing options are selected in the base address

• BA (0:16) = 0000 0000 0100 0000 0 - set starting address of S1D13705 to 40 0000h

• AT (0:2) = 0 - ignore address type bits

• PS (0:1) = 1:0 - memory port size is 16 bits

• PARE = 0 - disable parity checking

• WP = 0 - disable write protect

• MS (0:1) = 0:0 - select General Purpose Chip Select module to control this

chip select

• V = 1 - set valid bit to enable chip select

The following options were selected in the option register (OR4):

• AM (0:16) = 1111 1111 1100 0000 0 - mask all but upper 10 address bits; S1D13705 consumes

4M byte of address space

• ATM (0:2) = 0 - ignore address type bits

• CSNT = 0 - normal CS/WE negation

• ACS (0:1) = 1:1 - delay CS assertion by 1/2 clock cycle from address lines

• BI = 1 - assert Burst Inhibit

• SCY (0:3) = 0 - wait state selection; this ﬁeld is ignored since external

transfer acknowledge is used; see SETA below

• SETA = 1 - the S1D13705 generates an external transfer ackno wledge

using the WAIT# line

• TRLX = 0 - normal timing

• EHTR = 0 - normal timing

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S1D13705F00A APPLICATION NOTES EPSON 5-17

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Test Software

The test software to e xercise this interf ace is v ery simple. It conﬁgures chip select 4 on the MPC821

to map the S1D13705 to an unused 128k byte block of address space and loads the appropriate

values into the option register for CS4. At that point the software runs in a tight loop reading the

S1D13705 Re vision Code Register REG[00h], which allo ws monitoring of the b us timing on a logic

analyzer.

The source code for this test routine is as follows:

BR4 equ $120 ; CS4 base register

OR4 equ $124 ; CS4 option register

MemStart equ $40 ; upper word of S1D13705 start address

RevCodeReg equ 1FFE0 ; address of Revision Code Register

Start mfspr r1,IMMR ; get base address of internal registers

andis. r1,r1,$ffff ; clear lower 16 bits to 0

andis. r2,r0,0 ; clear r2

oris r2,r2,MemStart ; write base address

ori r2,r2,$0801 ; port size 16 bits; select GPCM; enable

stw r2,BR4(r1) ; write value to base register

andis. r2,r0,0 ; clear r2

oris r2,r2,$ffc0 ; address mask – use upper 10 bits

ori r2,r2,$0708 ; normal CS negation; delay CS

1/2

clock;

; inhibit burst

stw r2,OR4(r1) ; write to option register

andis. r1,r0,0 ; clear r1

oris r1,r1,MemStart ; point r1 to start of S1D13705 mem space

Loop lbz r0,RevCodeReg(r1) ; read revision code into r1

b Loop ; branch forever

end

This code was entered into the memory of the MPC821ADS using the line-by-line assembler in

MPC8BUG, the debugger provided with the ADS board. It was executed on the ADS and a logic

analyzer was used to verify operation of the interface hardware.

Note: MPC8BUG does not support comments or symbolic equates; these have been added for

clarity.

It is important to note that when the MPC821 comes out of reset, its on-chip caches and MMU are

disabled. If the data cache is enabled, then the MMU must be set up so that the S1D13705 memory

block is tagged as non-cacheable, to ensure that accesses to the S1D13705 will occur in proper

order , and also to ensure that the MPC821 does not attempt to cache an y data read from or written to

the S1D13705 or its display buffer.

2.5 Software

Test utilities and Windows® CE v2.0 display drivers are available for the S1D13705. Full source

code is available for both the test utilities and the drivers.

The test utilities are conﬁgurable for different panel types using a program called 1375CFG, or by

directly modifying the source. The Windows® CE v2.0 display drivers can be customized by the

OEM for different panel types, resolutions and color depths only by modifying the source.

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3INTERFACING TO THE MOTOROLA

MCF5307 “COLDFIRE” MICROPROCESSOR

3.1 Introduction

This application note describes the hardware required to interface the S1D13705 Embedded

Memory LCD Controller and the Motorola MCF5307 Processor. The pairing of these two devices

results in an embedded system offering impressive display capability with very low power

consumption.

3.2 Interfacing to the MCF5307

The MCF5307 System Bus

The MCF5200/5300 family of processors feature a high-speed synchronous system bus typical of

modern microprocessors. This section is an overview of the operation of the CPU bus to establish

interface requirements.

Overview

The MCF5307 microprocessor family uses a synchronous address and data bus, very similar in

architecture to the MC68040 and MPC8xx. All outputs and inputs are timed with respect to a

square-wa ve reference clock called BCLK0 (Master Clock). This clock runs at a software-selectable

di visor rate from the machine cycle speed of the CPU core, typically 20 to 33 MHz. Both the address

and the data bus are 32 bits in width. All IO accesses are memory-mapped; there is no separate IO

space in the Coldﬁre architecture.

The bus can support two types of cycles, normal and burst. Burst memory cycles are used to ﬁll on-

chip cache memories, and for certain on-chip DMA operations. Normal cycles are used for all other

data transfers.

Normal (Non-Burst) Bus Transactions

A data transfer is initiated by the bus master by placing the memory address on address lines A31

through A0 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also

provided with the memory address:

• SIZ[1:0] (Transfer Size), which indicate whether the bus cycle is 8, 16, or 32 bits in width.

• R/W, which is high for read cycles and low for write cycles.

• A set of transfer type signals (TT[1:0]) which provide more detail on the type of transfer being

attempted.

• TIP (Transfer In Progress), which is asserted whenever a bus cycle is active.

When the peripheral device being accessed has completed the bus transfer, it asserts TA (Transfer

Acknowledge) for one clock cycle, completing the bus transaction. Once TA has been asserted, the

MCF5307 will not start another bus cycle until TA has been de-asserted. The minimum length of a

bus transaction is two bus clocks.

X27A-G-011-01

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Figure 3-1 illustrates a typical memory read cycle on the MCF5307 system bus, and Figure 3-2

illustrates a memory write cycle.

Figure 3-1 MCF5307 Memory Read Cycle

Figure 3-2 MCF5307 Memory Write Cycle

A[31:0]

D[31:0]

SIZ[1:0], TT[1:0]

BCLK0

Wait StatesTransfer Start Transfer Next Transfer

Sampled when TA low

R/W

Complete Starts

TIP

A[31:0]

D[31:0]

SIZ[1:0], TT[1:0]

BCLK0

Wait StatesTransfer Start

R/W

Valid

Transfer Next Transfer

Complete Starts

TIP

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5-20 EPSON S1D13705F00A APPLICATION NOTES

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Burst Cycles

Burst cycles are very similar to normal cycles, except that they occur as a series of four back-to-

back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output asserted

continuously through the burst. Burst memory cycles are mainly intended to facilitate cache line ﬁll

from program or data memory; they are typically not used for transfers to or from IO peripheral

devices such as the S1D13705. The MCF5307 chip selects provide a mechanism to disable burst

accesses for peripheral devices which are not able to support them.

Chip-Select Module

In addition to generating eight independent chip-select outputs, the MCF5307 Chip Select Module

can generate acti ve-lo w Output Enable (OE ) and Write Enable (BWE) signals compatible with most

memory and x86-style peripherals. The MCF5307 bus controller also provides a Read/Write (R/W)

signal which is compatible with most 68K peripherals.

Chip selects 0 and 1 can be programmed independently to respond to any base address and block

size. Chip select 0 can be active immediately after reset, and is typically used to control a boot

ROM. Chip select 1 is likewise typically used to control a large static or dynamic RAM block.

Chip selects 2 through 7 have ﬁxed block sizes of 2M bytes each. Each has a unique, ﬁxed offset

from a common, programmable starting address. These chip selects are well-suited to typical IO

addressing requirements.

Each chip select may be individually programmed for port size (8/16/32 bits), 0 to 15 wait states or

external acknowledge, address space type, burst or non-burst cycle support, and write protect.

3.3 S1D13705 Bus Interface

This section is a summary of the host bus interface mode used on the S1D13705 to interface to the

MCF5307.

The S1D13705 implements a 16-bit interface to the host microprocessor which may operate in one

of several modes compatible with most of the popular embedded microprocessor families. The

interface mode used for the MCF5307 is:

• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).

Host Bus Pin Connection

For details on conﬁguration, refer to the “S1D13705 Hardware Functional Speciﬁcation”,

document number X27A-A-001-02.

Table 3-1 Host Bus Interface Pin Mapping

S1D13705

Pin Names Generic #1

AB[15:1] A[15:1]

AB0 A0

DB[15:0] D[15:0]

WE1# WE1#

CS# External Decode

BCLK BCLK

BS# connect to VSS

RD/WR# RD1#

RD# RD0#

WE0# WE0#

WAIT# WAIT#

RESET# RESET#

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S1D13705F00A APPLICATION NOTES EPSON 5-21