© 2008 Microchip Technology Inc. DS22056B-page 1
MCP1825/MCP1825S
Features
• 500 mA Output Current Capability
• Input Operating Voltage Range: 2.1V to 6.0V
• Adjustable Output Voltage Range: 0.8V to 5.0V
(MCP1825 only)
• Standard Fixed Output Voltages:
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V
• Other Fixed Output Voltage Options Available
Upon Request
• Low Dropout Voltage: 210 mV Typical at 500 mA
• Typical Output Voltage Tolerance: 0.5%
• Stable with 1.0 µF Ceramic Output Capacitor
• Fast response to Load Transients
• Low Supply Curre nt : 12 0 µA (typical)
• Low Shutdown Supply Current: 0.1 µA (typical)
(MCP1825 only)
• Fixed Delay on Power Good Output
(MCP1825 only)
• Short Circuit Current Limiting and
Overtemperature Protection
• TO-263-5 (DDPAK-5), TO-220-5, SOT-223-5
Package Options (MCP1825).
• TO-263-3 (DDPAK-3), TO-220-3, SOT-223-3
Package Options (MCP1825S).
Applications
• High-Speed Driver Chipset Power
• Networking Backplane Cards
• Notebook Computers
• Network Interface Cards
• Palmtop Computers
• 2.5V to 1.XV Regulators
Description
The MCP1825/MCP1825S is a 500 mA Low Dropout
(LDO) linear regulator that provides high current and
low output voltages. The MCP1825 comes in a fixed or
adjustable output voltage version, with an output
voltage range of 0.8V to 5.0V. The 500 mA output
current capability , combined with the low output voltage
capability, make the MCP1825 a good choice for new
sub-1.8V output voltage LDO applications that have
high current demands. The MCP1825S is a 3-pin fixed
voltage version.
The MCP1825/MCP1825S is stable using ceramic
output capacitors that inherently provide lower output
noise and reduce the size and cost of the entire
regulator solution. Only 1 µF of output capacitance is
needed to stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1825/MCP1825S is typically
less than 120 µA over the entire input voltage range,
making it attractive for portable computing applications
that demand high output current. The MCP1825
versions have a Shutdown (SHDN) pin. When shut
down, the quiescent current is reduced to less than
0.1 µA.
On the MCP1825 fixed output versions, the scaled-
down output voltage is internally monitored and a
power good (PWRGD) output is provided when the
output is within 92% of regulation (typical). The
PWRGD delay is internally fixed at 110 µs (typical).
The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
fault conditions.
500 mA, Low Voltage, Low Quiescent Current LDO Regulator
MCP1825/MCP1825S
DS22056B-page 2 © 2008 Microchip Technology Inc.
Package Types
MCP1825
12345
6
SOT-223-5
Pin Fixed Adjustable
1 SHDN SHDN
2V
IN VIN
3 GND (TAB) GND (TAB)
4V
OUT VOUT
5 PWRGD ADJ
6 GND (TAB) GND (TAB)
123
SOT-223-3
4
MCP1825S
Pin
1V
IN
2 GND (TAB)
3V
OUT
4 GND (TAB)
Fixed/Adjustable
DDPAK-3DDPAK-5 TO-220-3TO-220-5
12345 12345
123
123
© 2008 Microchip Technology Inc. DS22056B-page 3
MCP1825/MCP1825S
Typical Applications
MCP1825 Adjustable Output Voltage
MCP1825 Fixed Output Voltage
VOUT = 1.8V @ 500 mA
VIN = 2.3V to 2.8V
On
Off
1µF
100 kΩ
4.7 µF
C1C2
R1
SHDN
VIN
GND
VOUT
PWRGD
20 kΩ
R2
VOUT = 1.2V @ 500 mA
VIN = 2.1V to 2.8V
On
Off
1µF
40 kΩ
4.7 µF
C1C2
R1
SHDN
VIN
GND
VOUT
VADJ
1
1
MCP1825/MCP1825S
DS22056B-page 4 © 2008 Microchip Technology Inc.
Functional Block Diagram - Adjustable Output
EA +
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
ADJ/SENSE
Undervoltage
Lock Out
VIN Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
© 2008 Microchip Technology Inc. DS22056B-page 5
MCP1825/MCP1825S
Functional Block Diagram - Fixed Output (3-Pin)
EA +
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
Sense
Undervoltage
Lock Out
VIN Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
MCP1825/MCP1825S
DS22056B-page 6 © 2008 Microchip Technology Inc.
Functional Block Diagram - Fixed Output (5-Pin)
EA +
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
Sense
Undervoltage
Lock Out
VIN Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
PWRGD
© 2008 Microchip Technology Inc. DS22056B-page 7
MCP1825/MCP1825S
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VIN....................................................................................6.5V
Maximum Voltage on Any Pin..(GND – 0.3V) to (VDD + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration................................Continuous
Storage temperature.....................................-65°C to +150°C
Maximum Junction Temperature, TJ...........................+150°C
ESD protection on all pins (HBM/MM) ........... ≥ 4kV; ≥ 300V
† Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Input Operating Voltage VIN 2.1 6.0 VNote 1
Input Quiescent Current Iq— 120 220 µA IL = 0 mA, VOUT = 0.8V to
5.0V
Input Quiescent Current for
SHDN Mode ISHDN —0.13µA SHDN = GND
Maximum Output Current IOUT 500 ——mAV
IN = 2.1V to 6.0V
VR = 0.8V to 5.0V, Note 1
Line Regulation ΔVOUT/
(VOUT x ΔVIN)— ±0.05 ±0.16 %/V (Note 1) ≤ VIN ≤ 6V
Load Regulation ΔVOUT/VOUT -1.0 ±0.5 1.0 %I
OUT = 1 mA to 500 mA,
(Note 4)
Output Short Circuit Current IOUT_SC —1.2—AR
LOAD <0.1Ω, Peak Current
Adjust Pin Characteristics (Adjustable Output Only)
Adjust Pin Reference Voltage VADJ 0.402 0.410 0.418 VV
IN = 2.1V to VIN =6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current IADJ -10 ±0.01 +10 nA VIN = 6.0V, VADJ =0Vto6V
Adjust Temperature Coefficient TCVOUT — 40 — ppm/°C Note 3
Fixed-Output Characteristics (Fixed Output Only)
Voltage Regulation VOUT VR - 2.5% VR ±0.5% VR + 2.5% VNote 2
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., T A, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150 °C can impact device reliability.
7: The junction temperature is approximated by soaking the device u nder test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
MCP1825/MCP1825S
DS22056B-page 8 © 2008 Microchip Technology Inc.
Dropout Characteristics
Dropout Voltage VDROPOUT — 210 350 mV Note 5, IOUT = 500 mA,
VIN(MIN) =2.1V
Power Good Characteristics
PWRGD Input Voltage Operat-
ing Range VPWRGD_VIN 1.0 — 6.0 V TA = +25°C
1.2 —6.0 TA = -40°C to +125°C
For VIN < 2.1V, ISINK = 100 µA
PWRGD Threshold Voltage
(Referenced to VOUT)VPWRGD_TH %VOUT Falling Edge
89 92 95 VOUT < 2.5V Fixed,
VOUT = Adj.
90 92 94 VOUT >= 2.5V Fixed
PWRGD Threshold Hysteresis VPWRGD_HYS 1.0 2.0 3.0 %VOUT
PWRGD Output Voltage Low VPWRGD_L —0.20.4 VI
PWRGD SINK = 1.2 mA,
ADJ = 0V
PWRGD Leakage PWRGD_LK —1—nAV
PWRGD = VIN = 6.0V
PWRGD Time Delay TPG — 110 — µs Rising Edge
RPULLUP = 10 kΩ
Detect Threshold to PWRGD
Active Time Delay TVDET-PWRGD — 200 — µs VOUT = VPWRGD_TH + 20 mV
to VPWRGD_TH - 20 mV
Shutdown Input
Logic High Input VSHDN-HIGH 45 ——%V
IN VIN = 2.1V to 6.0V
Logic Low Input VSHDN-LOW ——15 %VIN VIN = 2.1V to 6.0V
SHDN Input Leakage Current SHDNILK -0.1 ±0.001 +0.1 µA VIN =6V, SHDN =VIN,
SHDN = GND
AC Performance
Output Delay From SHDN TOR — 100 — µs SHDN = GND to VIN,
VOUT = GND to 95% VR
Output Noise eN—2.0—µV/√Hz IOUT = 200 mA, f = 1 kHz,
COUT = 10 µF (X7R Ceramic),
VOUT = 2.5V
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Note 1: The minimum VIN must meet two condit ions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., T A, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2008 Microchip Technology Inc. DS22056B-page 9
MCP1825/MCP1825S
Power Supply Ripple Rejection
Ratio PSRR — 60 — dB f = 100 Hz, COUT = 4.7 µF,
IOUT = 100 µA,
VINAC = 100 mV pk-pk,
CIN = 0 µF
Thermal Shutdown Temperature TSD — 150 — °C IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Thermal Shutdown Hysteresis ΔTSD —10—°CI
OUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., T A, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150 °C can impact device reliability.
7: The junction temperature is approximated by soaking the device u nder test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
MCP1825/MCP1825S
DS22056B-page 10 © 2008 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Junction Temperature Range TJ-40 — +125 °C Steady State
Maximum Junction Temperature TJ— — +150 °C Transient
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 3LD DDPAK θJA — 31.4 — °C/W 4-Layer JC51 Standard
Board
θJC —3.0—
Thermal Resistance, 3LD TO-220 θJA — 29.4 — °C/W 4-Layer JC51 Standard
Board
θJC —2.0—
Thermal Resistance, 3LD SOT-223 θJA — 62 — °C/W EIA/JEDEC JESD51-751-7
4 Layer Board
θJC — 15.0 —
Thermal Resistance, 5LD DDPAK θJA — 31.2 — °C/W 4-Layer JC51 Standard
Board
θJC —3.0—
Thermal Resistance, 5LD TO-220 θJA — 29.3 — °C/W 4-Layer JC51 Standard
Board
θJC —2.0—
Thermal Resistance, 5LD SOT-223 θJA — 62 — °C/W EIA/JEDEC JESD51-751-7
4 Layer Board
θJC — 15.0 —
© 2008 Microchip Technology Inc. DS22056B-page 11
MCP1825/MCP1825S
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
FIGURE 2-1: Quiescent Current vs. Input
Voltage (Adjustable Version).
FIGURE 2-2: Ground Curr en t vs . Lo ad
Current (Ad j us table Version).
FIGURE 2-3: Quiescent Current vs.
Junction Temperature (Adjustable Version).
FIGURE 2-4: Line Regulation vs.
Temperature (Adjustable Version).
FIGURE 2-5: Load Regulation vs.
Temperature (Adjustable Version).
FIGURE 2-6: Adjust Pin Voltage vs.
Tem pe r atu r e ( A d justable Version).
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provide d for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified pow er supply range) and therefore outside the warranted range.
90
100
110
120
130
140
23456
Input Voltage (V)
Quiescent Current (μA)
130°C
-45°C
25°C
90°C
VOUT = 1.2V Adj
IOUT = 0 mA
0°C
100
110
120
130
140
150
160
170
180
190
200
0 100 200 300 400 500 600
Load Current (mA)
Ground Current (μA)
VIN=3.3V
VOUT = 1.2V Adj
VIN=5.0V
VIN=2.5V
90
100
110
120
130
140
150
160
170
-45 -20 5 30 55 80 105 130
Temperature (°C)
Quiescent Current (μA)
VIN=6.0V
VIN=3.0V
VIN=4.0V
VOUT = 1.2V Adj
IOUT = 0 mA
VIN=5.0V
VIN=2.1V
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
-45 -20 5 30 55 80 105 130
Temperature (°C)
Line Regulation (%/V)
VOUT = 1.2V adj
VIN
= 2.1V to 6.0
V
IOUT = 1 mA
IOUT=500 mA
IOUT = 50 mA
IOUT=100 mA
IOUT=250 mA
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
IOUT = 1.0 mA to 500 mA
VOUT = 5.0V
VOUT = 3.3V
VOUT = 0.8V
VOUT = 1.8V
0.4070
0.4075
0.4080
0.4085
0.4090
0.4095
0.4100
0.4105
0.4110
-45 -20 5 30 55 80 105 130
Temperature (°C)
Adjust Pin Voltage (V)
VOUT = 1.8V
IOUT = 1.0 mA
VIN = 2.3V
VIN = 6.0V
VIN = 4.0V
MCP1825/MCP1825S
DS22056B-page 12 © 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
FIGURE 2-7: Dropout Voltage vs. Load
Current (Adjustable Ve rsion).
FIGURE 2-8: Dropout Voltage vs.
Temperature (Adjustable Version).
FIGURE 2-9: Power Good (PWRGD)
Time Delay vs. Temperature.
FIGURE 2-10: Quiescent Current vs. Input
Voltage.
FIGURE 2-11: Quiescent Current vs. Input
Voltage.
FIGURE 2-12: Ground Current vs. Load
Current.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0 50 100 150 200 250 300 350 400 450 500
Load Current (mA)
Dropout Voltage (V)
VOUT = 2.5V Adj
VOUT = 5.0V Adj
0.20
0.22
0.24
0.26
0.28
0.30
-45 -20 5 30 55 80 105 130
Temperature (°C)
Dropout Voltage (V)
VOUT = 3.3V Adj
VOUT = 5.0V Adj
VOUT = 2.5V Adj
IOUT = 500 mA
100
110
120
130
140
150
160
170
-45-205 305580105130
Temperature (°C)
Power Good Time Delay (µS)
VOUT
= 2.5V Fixed
VIN = 3.0V
VIN = 5.0V
VIN = 4.0V
VIN = 6.0V
90
100
110
120
130
140
150
160
23456
Input Voltage (V)
Quiescent Current (μA)
-45°C
+130°C
+90°C
+25°C
VOUT = 0.8V
IOUT = 0 mA
0°C
90
100
110
120
130
140
150
33.544.555.56
Input Voltage (V)
Quiescent Current (μA)
VOUT = 2.5V
IOUT = 0 mA
+130°C
-45°C
+25°C
+90°C
+0°C
0
50
100
150
200
250
0 100 200 300 400 500 600
Load Current (mA)
Ground Current (μA)
VIN = 2.3V for VR
=0.8
V
VIN = 3.0V for VR
=2.5
V
VOUT=0.8V
VOUT=2.5V
© 2008 Microchip Technology Inc. DS22056B-page 13
MCP1825/MCP1825S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
FIGURE 2-13: Quiescent Current vs.
Temperature.
FIGURE 2-14: ISHDN vs. Temperature.
FIGURE 2-15: Line Regulation vs.
Temperature.
FIGURE 2-16: Line Regulation vs.
Temperature.
FIGURE 2-17: Load Regulation vs.
Temperature (VOUT < 2.5V Fixed).
FIGURE 2-18: Load Regulation vs.
Temperature (VOUT
≥
2.5V Fixed).
95
100
105
110
115
120
125
130
135
140
-45 -20 5 30 55 80 105 130
Temperature (°C)
Quiescent Current (μA)
VOUT = 0.8V
VOUT = 2.5V
IOUT = 0 mA
VOUT = 5V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-45-205 305580105130
Temperature (°C)
Ishdn (μA)
VIN = 2.3V
VIN = 4.0V
VIN = 5.0V
VR = 0.8V
VIN = 6.0V
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
-45-205 305580105130
Temperature (°C)
Line Regulation (%/V)
VOUT = 0.8V
VIN = 2.1V to 6.0V
IOUT = 100 mA
IOUT = 500 mA
IOUT = 50 mA
IOUT = 250 mA
IOUT = 1 mA
0.015
0.020
0.025
0.030
0.035
0.040
0.045
-45 -20 5 30 55 80 105 130
Temperature (°C)
Line Regulation (%/V)
IOUT = 100 mA
IOUT = 1 mA
IOUT = 50 mA
IOUT = 250 mA IOUT = 500 mA
VR = 2.5V
VIN = 3.1V to 6.0V
-0.25
-0.15
-0.05
0.05
0.15
0.25
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
VOUT = 0.8V
IOUT = 1 mA to 500 mA
VIN
= 2.1
V
VIN
= 4.0
V
V
IN
= 5.0V
VIN
= 6.0
V
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
VOUT = 2.5V
VOUT = 5.0V
IOUT = 1 mA to 500 mA
MCP1825/MCP1825S
DS22056B-page 14 © 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
FIGURE 2-19: Dropout Voltage vs. Load
Current.
FIGURE 2-20: Dropout Voltage vs.
Temperature.
FIGURE 2-21: Short Circuit Current vs.
Input Voltage.
FIGURE 2-22: Output Noise Voltage
Density vs. Frequency.
FIGURE 2-23: Power Supply Ripple
Rejection (PSRR) vs. Frequency (Adj.).
FIGURE 2-24: Power Supply Ripple
Rejection (PSRR) vs. Frequency.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0 100 200 300 400 500
Load Current (mA)
Dropout Voltage (V)
VOUT = 5.0V
VOUT = 2.5V
0.18
0.20
0.22
0.24
0.26
0.28
0.30
-45 -20 5 30 55 80 105 130
Temperature (°C)
Dropout Voltage (V)
IOUT = 500 mA
VOUT = 2.5V
VOUT = 5.0V
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.00 1.00 2.00 3.00 4.00 5.00 6.00
Input Voltage (V)
Short Circuit Current (A)
VOUT
= 2.5V
0.01
0.1
1
10
0.01 0.1 1 10 100 1000
Frequency (kHz)
Noise (mV/ √Hz)
VR=0.8V, VIN=2.3V
VR=2.5V, VIN=3.3V COUT
=1 μF ce
r
CIN
=10 μF ce
r
IOUT=200 mA
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=1.2V Adj
COUT=10 μF ceramic X7R
VIN=2.5V
CIN=0 μF
IOUT=10 mA
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=2.5V (Fixed)
COUT=22 μF ceramic X7R
VIN=3.3V
CIN=0 μF
IOUT=10 mA
© 2008 Microchip Technology Inc. DS22056B-page 15
MCP1825/MCP1825S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output.
FIGURE 2-25: 2.5V (Adj.) Startup from VIN.
FIGURE 2-26: 2.5V (Adj.) Startup from
Shutdown.
FIGURE 2-27: Power Good (PWRGD)
Timing.
FIGURE 2-28: Dynamic Line Response.
FIGURE 2-29: Dynamic Load Response
(1 mA to 500 mA).
FIGURE 2-30: Dynamic Load Response
(10 mA to 500 mA).
MCP1825/MCP1825S
DS22056B-page 16 © 2008 Microchip Technology Inc.
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3 -1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typi ca l quiescent current is 0.1 µA.
3.2 Input Voltage Supply (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
3.3 Ground (GND)
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 µA), so a heavy trace is not required.
For applications that have switching or noisy inputs, tie
the GND pin to the return of the output capacitor.
Ground planes help lower inductance and voltage
spikes caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4 Regulated Output Voltage (VOUT)
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1825/MCP1825S
is stable with ceramic, tantalum and aluminum-electro-
lytic capacitors. See Section 4.3 “Output Capacitor”
for output capacitor selection guidance.
3.5 Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is delayed by 110 µs (typi cal) from the
time the LDO output is within 92% + 3% (maximum
hysteresis) of the regulated output value on power-up.
This delay time is internally fixed.
3.6 Output Voltage Adjust Input (ADJ)
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the user the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.7 Exposed Pad (EP)
The DDPAK and TO-220 package have an exposed
tab on the package. A heat sink may may be mount to
the tab to aid in the removal of heat from the package
during operation. The exposed tab is at the ground
potent ia l of th e LD O.
3-Pin Fixed
Output
5-Pin Fixed
Output
Adjustable
Output Name Description
—11SHDNShutdown Control Input (active-low)
122V
IN Input Voltage Supply
2 3 3 GND Ground
344V
OUT Regulated Output Voltage
—5—PWRGD Power Good Output
——5 ADJ Voltage Adjust/Sense Input
Exposed Pad Exposed Pad Exposed Pad EP Exposed Pad of the Package (ground potential)
© 2008 Microchip Technology Inc. DS22056B-page 17
MCP1825/MCP1825S
4.0 DEVICE OVERVIEW
The MCP1825/MCP1825S is a high output current,
Low Dropout (LDO) voltage regulator . The low dropout
voltage of 210 mV typical at 500 mA of current makes
it ideal for battery-powered applications. Unlike other
high output current LDOs, the MCP1825/MCP1825S
only draws a maximum of 220 µA of quiescent current.
The MCP1825 has a shutdown control input and a
power good output.
4.1 LDO Output Voltage
The 5-pin MCP1825 LDO is available with either a fixed
output voltage or an adjustable output voltage. The
output voltage range is 0.8V to 5.0V for both versions.
The 3-pin MCP1825S LDO is available as a fixed
voltage device.
4.1.1 ADJUST INPUT
The adjustable version of the MCP182 5 uses the ADJ
pin (pin 5) to get the output voltage feedback for output
voltage regulation. This allows the user to set the
output voltage of the device with two external resistors.
The nominal voltage for ADJ is 0.41V.
Figure 4-1 shows the adjustable version of the
MCP1825. Resistors R1 and R2 form the resistor
divider network necessary to set the output voltage.
With this configuration, the equation for setting VOUT is:
EQUATION 4-1:
FIGURE 4-1: Typical adjustable output
voltage application circuit.
The allowable resistance value ra nge for resistor R2 is
from 10 kΩ to 200 kΩ. Solving the equation for R1
yields the following equation:
EQUATION 4-2:
4.2 Output Current and Current
Limiting
The MCP1825/MCP1825S LDO is tested and ensured
to supply a minimum of 500 mA of output current. The
MCP1825/MCP1825S has no minimum output load, so
the output load current can go to 0 mA and the LDO will
continue to regulate the output voltage to within
tolerance.
The MCP1825/MCP1825S also incorporates an output
current limit. If the outpu t voltage falls below 0.7V due
to an overload condition (usually re presents a shorted
load condition), the output current is limited to 1.2A
(typical). If the overload condition is a soft overload, the
MCP1825/MCP1825S wil l supply higher load currents
of up to 1.5A. The MCP1825/MCP1825S should not be
operated in this condition continu ously as it may result
in failure of the device. However, this does allow for
device usage in applications that have higher pulsed
load currents having an average output current value of
500 mA or less.
Output overload conditions may also resul t in an over-
temperature shutdown of the device. If the junction
temperature rises above 150°C, the LDO will shut
down the output voltage. See Section 4.8 “Overtem-
perature Protection” for more information on
overtemperature shutdown.
4.3 Output Capacitor
The MCP1825/MCP1825S requires a minimum output
capacitance of 1 µF for output voltage stability.
Ceramic capacitors are recommended because of their
size, cost and environmental robustness qualities.
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capacitor has an ESR of 50 milli-ohms.
Larger LDO output capacitors can be used with the
MCP1825/MCP1825S to improve dynamic
performance and power supply ripple rejection
performance. A maximum of 22 µF is recommended.
Aluminum-electrolytic capacitors are not recom-
mended for low temperature applications of < -25°C.
MCP1825/MCP1825S
DS22056B-page 18 © 2008 Microchip Technology Inc.
4.4 Input Capacitor
Low input source impedan ce is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For applications that have output step load
requirements, the input capacitance of the LDO is ve ry
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5 Power Good Output (PWRGD)
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
Section 1.0 “Electrical Characteristics” for Minimum
and Maximum specifications) o f its nominal regulation
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time de lay is started (shown as TPG in the
Electrical Characteristics table). The power good time
delay is fixed at 110 µs (typical). After the time delay
period, the PWRGD output will g o high, indicating that
the output voltage is stable and within regulation limits.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low . The power good circuitry has a 170 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering o f the power good output durin g
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA (VPWRGD < 0.4V maximum).
FIGURE 4-2: Power Good Timing.
FIGURE 4-3: Power Good Timing from
Shutdown.
4.6 Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of VIN, with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 n s in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the sh utdown inpu t si gn a l.
© 2008 Microchip Technology Inc. DS22056B-page 19
MCP1825/MCP1825S
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation valu e. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the d elay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regul ation is
typically 100 µs. See Figure 4-4 for a timing diagr am of
the SHDN input.
FIGURE 4-4: Shutdown Input Timing
Diagram.
4.7 Dropout Voltage and
Undervoltage Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR + 0.5V differential applied. The MCP1825/
MCP1825S LDO has a very low dropout voltage
specification of 210 mV (typical) at 500 mA of output
current. See Section 1.0 “Electrical Characteristics”
for maximum dropout voltage specifications.
The MCP1825/MCP1825S LDO operates across an
input voltage range of 2.1V to 6.0V and incorporates
input Undervoltage Lockout (UVLO) circuitry that
keeps the LDO output voltage off until the input voltage
reaches a minimum of 2.00V (typical) on the rising
edge of the input voltage. As the input voltage falls, the
LDO output will remain on until the input voltage level
reaches 1.82V ( typi c al ).
Since the MCP1825/MCP1825S LDO undervoltage
lockout activates at 1.82V as the input voltage is falling,
the dropout voltage specification does not apply for
output voltages that are less than 1.8V.
For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with inp ut voltages near 2.1V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervoltage lockout.
4.8 Overtemperature Protection
The MCP1825/MCP1825S LDO has temperature-
sensing circuitry to prevent the junction temperature
from exceeding approximately 150°C. If the LDO
junction temperature does reach 150°C, the LDO
output will be turned off until the junction temperature
cools to approximately 140°C, at which point the LDO
output will automatically resume normal operation. If
the internal power dissipation continues to be
excessive, the device will again shut off. The junction
temperature of the die is a function of power
dissipation, ambient temperature and package thermal
resistance. See Section 5.0 “Application Circuits/
Issues” for more information on LDO power
dissipation and junction temperature.
MCP1825/MCP1825S
DS22056B-page 20 © 2008 Microchip Technology Inc.
5.0 APPLICATION CIRCUITS/
ISSUES
5.1 Typical Application
The MCP1825/MCP1825S is used for applications that
require high LDO output current and a power good
output.
FIGURE 5-1: Typical Application Circuit.
5.1.1 APPLICATION CONDITIONS
5.2 Power Calculations
5.2.1 POWER DISSIPATION
The internal power dissipation within the MCP1825/
MCP1825S is a function of input voltage, output
voltage, output current and quiescent current.
Equation 5-1 can be used to calculate the internal
power dissipation for the LDO.
EQUATION 5-1:
In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1825/
MCP1825S as a result of quiescent or grou nd current.
The power dissipation as a result of the ground current
can be calculated using the follo wing equation:
EQUATION 5-2:
The total power dissipated within the MCP1825/
MCP1825S is the sum of the power dissipated in the
LDO pass device and the P(IGND) term. Because of the
CMOS construction, the typical IGND for the MCP1825/
MCP1825S is 120 µA. Operating at a maximum VIN of
3.465V results in a power dissipation of 0.12 milli-W atts
for a 2.5V output. For most applications, this is small
compared to the LDO pass device power dissipation
and can be neglected.
The maximum continuous operating junction
temperature specified for the MCP1825/MCP1825 S is
+125°C. To estimate the internal junction temperature
of the MCP1825/MCP1825S, the total internal power
dissipation is multiplied by the thermal resistance from
junction to ambient (RθJA) of the device. The thermal
resistance from junction to ambient for the TO-220-5
package is estimated at 29.3°C/W.
EQUATION 5-3:
Package Typ e = TO-220-5
Input Voltage Range = 3.3V ± 5%
VIN maximum = 3.465V
VIN minimum = 3.135V
VDROPOUT (max) = 0.350V
VOUT (typical) = 2.5V
IOUT = 500 mA maximum
PDISS (typical) = 0.483W
Temperature Rise = 14.2°C
10 µF
VOUT = 2.5V @ 500 mA
R1C2
10 kΩ
PWRGD
SHDN
GND
2
4.7 µF
On
Off
C1
MCP1825-2.5
1345
3.3V VIN
© 2008 Microchip Technology Inc. DS22056B-page 21
MCP1825/MCP1825S
The maximum power dissipation capability for a
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient
temperature for the application. Equation 5-4 can be
used to determine the package maximum internal
power dissipation.
EQUATION 5-4:
EQUATION 5-5:
EQUATION 5-6:
5.3 Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
is calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
5.3.1 POWER DISSIPATION EXAMPLE
5.3.1.1 Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (RθJA) is
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
JESD51. The standard describes the test me thod and
board specifications for measuring the thermal
resistance from junction to ambient. The actual thermal
resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
Package
Package Type = TO-220-5
Input Voltage
VIN =3.3V ± 5%
LDO Output Voltage and Current
VOUT =2.5V
IOUT =500mA
Maximum Ambient Temperature
TA(MAX) =60°C
Internal Power Dissipation
PLDO(MAX) =(V
IN(MAX) – VOUT(MIN)) x IOUT(MAX)
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
x 500 mA
PLDO = 0.514 Watts
TJ(RISE) =P
TOTAL x RθJA
TJRISE = 0.514 W x 29.3° C/W
TJRISE = 15.06°C
MCP1825/MCP1825S
DS22056B-page 22 © 2008 Microchip Technology Inc.
5.3.1.2 Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is add ed to the ambient or
offset temperature. For this example, the worst-case
junction temp erature is estimated below:
5.3.1.3 Maximum Package Power
Dissipation at 60°C Ambient
Temperature
From this table, you can see the difference in maximum
allowable power dissipation between the TO-220-5
package and the DDPAK-5 package.
TJ =T
JRISE + TA(MAX)
TJ = 15.06°C + 60.0°C
TJ = 75.06°C
TO-220-5 (29.3°C/W RθJA):
PD(MAX) = (125°C – 60°C) / 29.3°C/W
PD(MAX) = 2.218W
DDPAK-5 (31.2°C/Watt RθJA):
PD(MAX) = (125°C – 60°C)/ 31.2°C/W
PD(MAX) = 2.083W
© 2008 Microchip Technology Inc. DS22056B-page 23
MCP1825/MCP1825S
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 dig its of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
Example:3-Lead DDPAK (MCP1825S)
3-Lead TO-220 (MCP1825S)
123
123
XXXXXXXXX
XXXXXXXXX
YYWWNNN
XXXXXXXXX
XXXXXXXXX
YYWWNNN
123
MCP1825S
08EEB
0710256
123
MCP1825S
12EAB
0710256
Example:
3
e
3
e
3-Lead SOT-223 (MCP1825S)
XXXXXXX
XXXYYWW
NNN
Example:
1825S08
EDB0710
256
MCP1825/MCP1825S
DS22056B-page 24 © 2008 Microchip Technology Inc.
Package Marking Information (Continued)
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 dig its of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
5-Lead DDPAK (MCP1825)
5-Lead TO-220 (MCP1825)
12345
12345
XXXXXXXXX
XXXXXXXXX
YYWWNNN
XXXXXXXXX
XXXXXXXXX
YYWWNNN
12345
MCP1825
12EET
0710256
12345
MCP1825
08EAT^^
0710256
Example:
Example:
3
e
3
e
5-Lead SOT-223 (MCP1825)
XXXXXXX
XXXYYWW
NNN
Example:
1825-08
EDC0710
256
© 2008 Microchip Technology Inc. DS22056B-page 25
MCP1825/MCP1825S
3-Lead Plastic (EB) [DDPAK]
Notes:
1. § Significant Characteristic.
2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 3
Pitch e .100 BSC
Overall Height A .160 – .190
Standoff § A1 .000 – .010
Overall Width E .380 – .420
Exposed Pad Width E1 .245 – –
Molded Package Length D .330 – .380
Overall Length H .549 – .625
Exposed Pad Length D1 .270 – –
Lead Thickness c .014 – .029
Pad Thickness C2 .045 – .065
Lower Lead Width b .020 – .039
Upper Lead Width b1 .045 – .070
Foot Length L .068 – .110
Pad Length L1 – – .067
Foot Angle φ0° – 8°
EE1
H
L1
D
D1
N
1
e
b
b1
c
C2
L
A
A1
BOTTOM VIEW
TOP VIEW
CHAMFER
OPTIONAL
φ
Microchip Technology Drawing C04-011B
MCP1825/MCP1825S
DS22056B-page 26 © 2008 Microchip Technology Inc.
3-Lead Plastic Small Outline Transistor (DB) [SOT-223]
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits M IN NOM MAX
Number of Leads N 3
Lead Pitch e 2.30 BSC
Outside Lead Pitch e1 4.60 BSC
Overall Height A – – 1.80
Standoff A1 0.02 – 0.10
Molded Package Height A2 1.50 1.60 1.70
Overall Width E 6.70 7.00 7.30
Molded Package Width E1 3.30 3.50 3.70
Overall Length D 6.30 6.50 6.70
Lead Thickness c 0.23 0.30 0.35
Lead Width b 0.60 0.76 0.84
Tab Lead Width b2 2. 90 3.00 3.10
Foot Length L 0.75 – –
Lead Angle φ0° – 10°
D
b2
EE1
123
e
e1
AA2
A1
b
c
L
φ
Microchip Technology Drawing C04-032B
© 2008 Microchip Technology Inc. DS22056B-page 27
MCP1825/MCP1825S
/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU'%>627@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
MCP1825/MCP1825S
DS22056B-page 28 © 2008 Microchip Technology Inc.
3-Lead Plastic Transistor Outline (AB) [TO-220]
Notes:
1. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM M AX
Number of Pins N 3
Pitch e .100 BSC
Overall Pin Pitch e1 .200 BSC
Overall Height A .140 – .190
Tab Thickness A1 .020 – .055
Base to Lead A2 .080 – .115
Overall Width E .357 – .420
Mounting Hole Center Q .100 – .120
Overall Length D .560 – .650
Molded Package Length D1 .330 – . 355
Tab Length H1 .230 – .270
Mounting Hole Diameter φP .139 – .156
Lead Length L .500 – .580
Lead Shoulder L1 – – .250
Lead Thickness c .012 – .024
Lead Width b .015 .027 .040
Shoulder Width b2 .045 .057 .070
E
Q
D
D1
L1
L
12
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b
b2
N
A2
c
H1
A1
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P
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Microchip Technology Drawing C04-034B
© 2008 Microchip Technology Inc. DS22056B-page 29
MCP1825/MCP1825S
5-Lead Plastic (ET) [DDPAK]
Notes:
1. § Significant Characteristic.
2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e .067 BSC
Overall Height A .160 – . 190
Standoff § A1 .000 – . 010
Overall Width E .380 – .420
Exposed Pad Width E1 .245 – –
Molded Package Length D .330 – .380
Overall Length H .549 – .625
Exposed Pad Length D1 .270 – –
Lead Thickness c .014 – .029
Pad Thickness C2 .045 – .065
Lead Width b .020 – .039
Foot Length L .068 – .110
Pad Length L1 – – .067
Foot Angle φ0° – 8°
E
L1
D
D1
H
N
1
be
TOP VIEW
BOTTOM VIEW
A
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C2
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Microchip Technology Drawing C04-012B
MCP1825/MCP1825S
DS22056B-page 30 © 2008 Microchip Technology Inc.
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© 2008 Microchip Technology Inc. DS22056B-page 31
MCP1825/MCP1825S
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DS22056B-page 32 © 2008 Microchip Technology Inc.
5-Lead Plastic Transistor Outli ne (AT) [TO-220]
Notes:
1. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits M IN NOM MAX
Number of Pins N 5
Pitch e .067 BSC
Overall Pin Pitch e1 .268 BSC
Overall Height A .140 – .190
Overall Width E .380 – .420
Overall Length D .560 – .650
Molded Package Length D1 .330 – .355
Tab Length H1 . 204 – . 293
Tab Thickness A1 .020 – .055
Mounting Hole Center Q .100 – .120
Mounting Hole Diameter φP .139 – .156
Lead Length L .482 – .590
Base to Bottom of Lead A2 .080 – .115
Lead Thickness c .012 – .025
Lead Width b .015 .027 .040
E
Q
D
D1
H1
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A1
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Microchip Technology Drawing C04-036B
© 2008 Microchip Technology Inc. DS22056B-page 33
MCP1825/MCP1825S
APPENDIX A: REVISION HISTORY
Revision B (February 2008)
The following is the list of modifications
1. Updated Figure 2-4, Figure 2-5, Figure 2-16,
Figure 2-29, and Figure 2-30.
2. Update d package outline drawings and landing
pattern drawings to Section 6.0 “Packaging
Information”.
3. Updated Appendix A: “Revision History”.
Revision A (August 2007)
• Original Release of this Document.
MCP1825/MCP1825S
DS22056B-page 34 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS22056B-page 35
MCP1825/MCP1825S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP1825: 500 mA Low Dropout Regulator
MCP1825T: 500 mA Low Dropout Regulator
Tape and Reel
MCP1825S: 500 mA Low Dropout Regulator
MCP1825ST: 500 mA Low Dropout Regulator
Tape and Reel
Output Voltage *: 08 = 0.8V “Standard”
12 = 1.2V “Standard”
18 = 1.8V “Standard”
25 = 2.5V “Standard”
30 = 3.0V “Standard”
33 = 3.3V “Standard”
50 = 5.0V “Standard”
ADJ = Adjustable Output Voltage ** (MCP1825 Only)
*Contact factory for other output voltage options
** When ADJ is used, the “extra feature code” and
“tolerance” columns do not apply. Refer to examples.
Extra Feature Code: 0 = Fixed
Tolerance: 2 = 2.5% (Standard)
Temperature: E = -40°C to +125°C
Package Type: AB = Plastic Transistor Outline, TO-220, 3-lead
AT = Plastic Transistor Outline, TO-220, 5-lead
EB = Plastic, DDPAK, 3-lead
ET = Plastic, DDPAK, 5-lead
DB = Plastic Small Transistor Outline, SOT-223, 3-lead
DC = Plastic Small Transistor Outline, SOT-223, 5-lead
Note: ADJ (Adjustable) only available in 5-lead version.
PART NO. XXX
Output Feature
Code
Device
Voltage
X
Tolerance
X/
Temp.
XX
Package
Examples:
a) MCP1825-0802E/XX: 0.8V LDO Regulator
b) MCP1825-1202E/XX: 1.2V LDO Regulator
c) MCP1825-1802E/XX: 1.8V LDO Regulator
d) MCP1825-2502E/XX: 2.5V LDO Regulator
e) MCP1825-3002E/XX: 3.0V LDO Regulator
f) MCP1825-3302E/XX: 3.3V LDO Regulator
g) MCP1825-5002E/XX: 5.0V LDO Regulator
h) MCP1825-ADJE/XX: ADJ LDO Regulator
a) MCP1825S-0802E/YY:0.8V LDO Regulator
b) MCP18 25S-120 2E/YY:1.2V LDO Regu lator
c) MCP 1825S-1 802E/Y Y:1.8V LDO Regulato r
d) MCP18 25S-250 2E/YY:2.5V LDO Regu lator
e) MCP18 25S-250 2E/YY:3.0V LDO Regu lator
f) MCP1825S-3302E/YY:3.3V LDO Regu lator
g) MCP18 25S-500 2E/YY:5.0V LDO Regu lator
XX = AT for 5LD TO-220 package
= DC for 5LD SOT-223 package
= ET for 5LD DDPAK package
YY = AB for 3LD TO-220 package
= DB for 3LD SOT-223 package
= EB for 3LD DDPAK package
MCP1825/MCP1825S
DS22056B-page 36 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS22056B-page 37
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defen d, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICST ART, PRO MA TE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design cent ers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22056B-page 38 © 2008 Microchip Technology Inc.
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