1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND/HEATSINK
NC
IN
IN
EN
RESET
FB/SENSE
OUTPUT
OUTPUT
GND/HEATSINK
GND/HEATSINK
NC
NC
GND
NC
NC
NC
NC
NC
GND/HEATSINK
TPS75201M-EP
www.ti.com
SGLS325A –JANUARY 2006–REVISED JULY 2013
Fast-Transient-Response 2-A Low-Dropout Voltage Regulator with Reset
Check for Samples: TPS75201M-EP
1FEATURES • Fast Transient Response
• 2% Tolerance Over Specified Conditions for
2• Controlled Baseline Fixed-Output Versions
– One Assembly/Test Site, One Fabrication • 20-Pin TSSOP (PWP) PowerPAD™ Package
Site • Thermal Shutdown Protection
• Enhanced Diminishing Manufacturing Sources
(DMS) Support PWP PACKAGE
• Enhanced Product-Change Notification (TOP VIEW)
• Qualification Pedigree (1)
• 2-A Low-Dropout (LDO) Voltage Regulator
• Open-Drain Power-On Reset With 100-ms
Delay
• Ultralow 75-μA Typ Quiescent Current
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over the
specified temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified NC - No internal connection
performance and environmental limits.
DESCRIPTION
The TPS75201M-EP is a low dropout regulator with an integrated power-on reset (RESET) function. This device
is capable of supplying 2 A of output current with a dropout of 210 mV. Quiescent current is 75 μA at full load
and drops down to 1 μA when the device is disabled. The TPS75201M-EP is designed to have fast transient
response for larger load current changes.
Because the PMOS device operates like a low-value resistor, the dropout voltage is very low (typically 210 mV at
an output current of 2 A) and is directly proportional to the output current. Additionally, since the PMOS pass
element is a voltage-driven device, the quiescent current is very low and independent of output loading (75 μA
typ over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant
improvement in operating life for battery-powered systems.
The device is enabled when the enable (EN) input is connected to a low-level input voltage. This low-dropout
(LDO) device also features a sleep mode; applying a TTL high signal to EN shuts down the regulator, reducing
the quiescent current to 1 μA at TJ= 25°C.
The RESET (SVS, POR, or power-on reset) output of the TPS75201M-EP initiates a reset in microcomputer and
microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS75201M-EP
monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms
delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., overload
condition) of its regulated voltage.
The TPS75201M-EP is adjustable (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is
specified as a maximum of 2% over line, load, and temperature ranges.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
RESET
OUT
OUT
4
3
5
IN
IN
EN
GND
17
6
8
9
VI
0.22 µF
RESET Output
VO
47 µF
+
CO†
SENSE 7
T −
JJunction Temperature − C°
−40 10 11060
− Dropout Voltage − mV
VDO
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
300
160
250
200
150
100
50
0
IO= 0.5 A
IO= 1.5 A
IO= 2 A
t − Time − ms
LOAD TRANSIENT RESPONSE
I − Output Current − A
O
VO− Change in
∆
Output Voltage − mV
−150
321 4 5 76 8 9 100
0
0
50
−50
IL= 2 A
CL= 100 µF (Tantalum)
VO= 3.3 V
−100
2
1
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
OUTPUT VOLTAGE
TJPACKAGE(2) ORDERABLE PART NUMBER
(TYP)
–55°C to 125°C Adjustable 1.5 V to 5 V TSSOP – PWP Tape and reel TPS75201MPWPREP
(1) The TPS75201M-EP is programmable using an external resistor divider (see Application Information).
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
†See application information section for capacitor selection details.
Figure 1. Typical Application Configuration (for Fixed-Output Options)
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100-ms Delay
(for RESET)
_
+
Vref = 1.1834 V
OUT
FB
EN
GND
RESET
_
+
IN
R1
R2
External to the Device
TPS75201M-EP
www.ti.com
SGLS325A –JANUARY 2006–REVISED JULY 2013
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
EN 5 I Enable
FB/SENSE 7 I Feedback input voltage for adjustable device (sense input for fixed-voltage option)
GND 17 Regulator ground
GND/HEATSINK 1, 10, 11, 20 Ground/heat sink
IN 3, 4 I Input voltage
2, 12, 13, 14, 15,
NC No connection
16, 18, 19
OUTPUT 8, 9 O Regulated output voltage
RESET 6 O Reset
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V
V
I
res
(see Note A)
Vres
t
t
t
V
Threshold
O
Voltage
RESET
Output 100-ms
Delay
100-ms
Delay
Output
Undefined
Output
Undefined
VIT + (see Note B)
VIT − (see Note B)
VIT − (see Note B)
VIT + (see Note B)
Less Than 5% of the
Output Voltage
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
RESET TIMING DIAGRAM
A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
B. VIT −Trip voltage typically is 5% lower than the output voltage (95% VO) VIT−to VIT+ is the hysteresis voltage.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIInput voltage range(2) –0.3 6 V
Voltage range at EN –0.3 16.5 V
Maximum RESET voltage 16.5 V
Peak output current Internally limited V
VOOutput voltage (OUTPUT, FB) 5.5 V
Continuous total power dissipation See Dissipation Rating Table
TJOperating virtual junction temperature range –55 125 °C
Tstg Storage temperature range –65 150 °C
ESD rating, Human-Body Model 2 kV
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE −FREE-AIR TEMPERATURES
AIR FLOW TA< 25°C DERATING FACTOR TA= 70°C TA= 85°C
PACKAGE (CFM) POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
0 2.9 W 23.5 mW/°C 1.9 W 1.5 W
PWP(1) 300 4.3 W 34.6 mW/°C 2.8 W 2.2 W
(1) This parameter is measured with the recommended copper heat- sink pattern on a one-layer PCB, 5-in × 5-in PCB, 1-oz copper, 2-in ×
2-in coverage (4 in2).
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SGLS325A –JANUARY 2006–REVISED JULY 2013
DISSIPATION RATING TABLE −FREE-AIR TEMPERATURES (continued)
AIR FLOW TA< 25°C DERATING FACTOR TA= 70°C TA= 85°C
PACKAGE (CFM) POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
3 3 w 23.6 mW/°C 1.9 W 1.5 W
PWP(2) 300 7.2 W 57.9 mW/°C 4.6 W 3.8 W
(2) This parameter is measured with the recommended copper heat-sink pattern on an eight-layer PCB, 1.5-in × 2-in PCB, 1-oz copper with
layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2), and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI
technical brief SLMA002.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIInput voltage(1) 2.7 5.5 V
VOOutput voltage range 1.5 5 V
IOOutput current 0 2.0 A
TJOperating virtual junction temperature –55 125 °C
(1) To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
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( )
V V V 1 V
O imax O
Line regulation (mV) (% / V) 1000
100
- +
= ´ ´
é ù
ë û
( )
imax
V V 2.7 V
O
Line regulation (mV) (% / V) 1000
100
-
= ´ ´
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range (TJ=−55°C to 125°C), VI= VO(typ) + 1 V, IO= 1 mA, EN = 0 V, mm
Co= 47 μF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ= 25°C VO
Output voltage(1)(2) Adjustable voltage 1.5 V ≤VO ≤5 V V
0.98VO1.02VO
75
Quiescent current (GND current)(1) TJ= 25°C(2) μA
125
TJ= 25°C 0.01
Output voltage line regulation (ΔVO/VO)(1)(3) VO+ 1 V < VI≤5 V %/V
0.1
Load regulation(2) 1 mV
BW = 300 Hz to 50 kHz,
Output noise voltage TJ= 25°C 60 μVrms
VO= 1.5 V, CO= 100 μF
Output current limit VO= 0 V 3.3 4.5 A
Thermal shutdown junction temperature 150 °C
TJ= 25°C 1
Standby current EN = VIμA
10
FB input current FB = 1.5 V –1 1 μA
High-level enable input voltage 2 V
Low-level enable input voltage 0.7 V
f = 100 Hz, CO= 100 μF,
Power-supply ripple rejection(3) 60 dB
TJ= 25°C, IO= 2 A, (1)
Minimum input voltage for valid RESET IO(RESET) = 300 μA, V(RESET) ≤0.8 V 1 1.3 V
Trip threshold voltage VOdecreasing 92 98
Hysteresis voltage Measured at VO0.5 %VO
Reset Output low voltage VI= 2.7 V, IO(RESET) = 1 mA 0.15 0.4 V
Leakage current V(RESET) = 5 V 1 μA
RESET time-out delay 100 ms
(1) Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage is 5 V.
(2) IO= 1 mA to 2 A
(3) If VO≤1.8 V, Vimin = 2.7 V, Vimax = 5 V:
If VO≥2.5 V, Vimin = VO+ 1 V, Vimax = 5 V:
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range (TJ=−40°C to 125°C), VI= VO(typ) + 1 V, IO= 1 mA, EN = 0 V, mm
Co= 47 μF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN = VI−1 1 μA
Input current (EN) EN = 0 V −1 0 1 μA
High-level EN input voltage 2 V
Low-level EN input voltage 0.7 V
IO= 2 A, VI= 3.2 V, TJ= 25°C 210
Dropout voltage (3.3-V output) mV
IO= 2 A, VI= 3.2 V 400
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I −
OOutput Current − mA
1.502
1.499
1.501
1.5
1.498
1.503
0
− Output Voltage − V
VO
1.497 500 15001000 2000
VO
VI= 2.7 V
TJ= 25°C
TPS75201M-EP
www.ti.com
SGLS325A –JANUARY 2006–REVISED JULY 2013
TYPICAL CHARACTERISTICS
spacer
Table of Graphs FIGURE
vs Output current Figure 2 and Figure 3
VOOutput voltage vs Junction temperature Figure 4 and Figure 5
Ground current vs Junction temperature Figure 6
Power-supply ripple rejection vs Frequency Figure 7
Output spectral noise density vs Frequency Figure 8
ZoOutput impedance vs Frequency Figure 9
vs Input voltage Figure 10
VDO Dropout voltage vs Junction temperature Figure 11
Input voltage (min) vs Output voltage Figure 12
Line transient response Figure 13 and Figure 16
Load transient response Figure 14 and Figure 16
VOOutput voltage vs Time (startup) Figure 17
Equivalent series resistance (ESR) vs Output current Figure 19 and Figure 20
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 2. Figure 3.
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T −
JJunction Temperature − C°
Ground Current − Aµ
10 11060−40 160
90
70
60
80
85
75
65
55
50
VI= 5 V
IO= 2 A
100k10k
PSRR Power Supply Ripple Rejection − dB
f − Frequency − Hz
60
50
40
30
20
10
0
90
80
1k10010 1M
VI= 4.3 V
CO= 100 µF
IO= 1 mA
TJ= 25°C
VI= 4.3 V
CO= 100 µF
IO= 2 A
TJ= 25°C
100
10M
T −
JJunction Temperature − C°
− Output Voltage − V
VO
3.31
−50 0
3.33
150
3.35
3.29
50 100
3.25
3.27
1 mA
3.23
3.37
2 A
T −
JJunction Temperature − C°
− Output Voltage − V
VO
1.48
−40 10
1.50
11060 160
1.52
1.51
1.49
1.47
1.53
1 mA
2 A
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 4. Figure 5.
GROUND CURRENT POWER-SUPPLY RIPPLE REJECTION
vs vs
JUNCTION TEMPERATURE FREQUENCY
Figure 6. Figure 7.
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V −
IInput Voltage − V
150
0
3 4
100
50
3.52.5
− Dropout Voltage − mV
4.5 5
VDO
250
200
300
350
TJ= 125°C
TJ= 25°C
TJ= −40°C
IO= 2 A
T −
JJunction Temperature − C°
−40 10 11060
− Dropout Voltage − mV
VDO
300
160
250
200
150
100
50
0
IO= 0.5 A
IO= 1.5 A
IO= 2 A
f − Frequency − Hz
− Output Impedance −
ZoΩ
10 100 100k 1M
10−1
1k 10M
1
101
CO= 100 µF
IO= 1 mA
CO= 100 µF
IO= 2 A
10-2
10k
f − Frequency − Hz
1010 100 1k 10k 50k
1.8
1.4
1.2
0.8
0.4
0
1.6
1
0.6
0.2
2
VI= 4.3 V
VO= 3.3 V
CO= 100 µF
TJ= 25°C
IO= 1 mA
IO= 2 A
nV/ Hz
− Voltage Noise −
Vn
TPS75201M-EP
www.ti.com
SGLS325A –JANUARY 2006–REVISED JULY 2013
OUTPUT SPECTRAL NOISE DENSITY OUTPUT IMPEDANCE
vs vs
FREQUENCY FREQUENCY
Figure 8. Figure 9.
DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
Figure 10. Figure 11.
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Product Folder Links :TPS75201M-EP
t − Time − ms
I − Output Current − A
O
VO− Change in
∆
Output Voltage − mV
−100
0
0 321 4 5 76 8 9 10
0
50
−50
IL= 2 A
CL= 100 µF (Tantalum)
VO= 1.5 V
−150
2
1
t − Time − ms
VO− Change in
VI− Input Voltage − V ∆
Output Voltage − mV
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 10
−100
5.3
0
4.3
IO= 2 A
CO= 100 µF
VO= 3.3 V
100
dv
dt
1 V
s
3
2.7
2
1.5 1.75 2 2.25 2.5 2.75
− Input Voltage (Min) −V
4
3 3.25 3.5
VI
V −
OOutput Voltage − V
IO= 2 A
TA= 25°C
TA= 125°C
TA= −40°C
VO− Change in
4
100
0
VI
t − Time − ms
0 0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 1
− Input Voltage − V ∆
Output Voltage − mV
IO=2 A
CO= 100 µF
VO= 1.5 V
3
−100
dv
dt
1 V
s
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
INPUT VOLTAGE (MIN)
vs
OUTPUT VOLTAGE LINE TRANSIENT RESPONSE
Figure 12. Figure 13.
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 14. Figure 15.
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0.010 0.5 1 1.5 2
10
I −
OOutput Current − A
ESR
−
Equivalent Series Resistance
−
Ω
1
Region of Instability
0.1
Region of Stability
VO= 3.3 V
CO= 100 µF
VI= 4.3 V
TJ= 25°C
0.05
0.010 0.5 1 1.5 2
10
I −
OOutput Current − A
1
Region of Instability
0.1
Region of Stability
VO= 3.3 V
CO= 47 µF
VI= 4.3 V
TJ= 25°C
ESR
−
Equivalent Series Resistance
−
Ω
t − Time − ms
I − Output Current − A
O
VO− Change in
∆
Output Voltage − mV
−150
321 4 5 76 8 9 100
0
0
50
−50
IO= 2 A
CO= 100 µF (Tantalum)
VO= 3.3 V
−100
2
1
t − Time − ms
VI= 4.3 V
TJ= 25°C
0
3.3
0
0
4.3
0.2 10.4 0.6 0.8
− Output Voltage − V
VO
Enable Voltage − V
TPS75201M-EP
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SGLS325A –JANUARY 2006–REVISED JULY 2013
LOAD TRANSIENT RESPONSE OUTPUT VOLTAGE vs TIME (STARTUP)
Figure 16. Figure 17.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1) EQUIVALENT SERIES RESISTANCE(1)
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 19. Figure 20.
(1) Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series
resistance added externally, and PWB trace resistance to CO.
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APPLICATION INFORMATION
The TPS75201M-EP is an adjustable regulator (from 1.5 V to 5 V).
MINIMUM LOAD REQUIREMENTS
The TPS75201M-EP is stable, even at no load; no minimum load is required for operation.
PIN FUNCTIONS
Enable (EN)
The EN input enables or shuts down the device. If EN is a logic high, the device is in shutdown mode. When EN
goes to logic low, the device is enabled.
Reset (RESET)
The RESET terminal is an open-drain, active-low output that indicates the status of VO. When VOreaches 95% of
the regulated voltage, RESET goes to a low-impedance state after a 100-ms delay. RESET goes to a high-
impedance state when VOis below 95% of the regulated voltage. The open-drain output of RESET requires a
pullup resistor.
Sense (SENSE)
The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier
through a resistor-divider network, and noise pickup feeds through to the regulator output. It is essential to route
the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between SENSE and
VOto filter noise is not recommended because it may cause the regulator to oscillate.
Feedback (FB)
FB is an input used for the adjustable-output options and must be connected to an external feedback resistor
divider. The FB connection should be as short as possible. It is essential to route it in such a way to
minimize/avoid noise pickup. Adding RC networks between FB and VOto filter noise is not recommended
because it may cause the regulator to oscillate.
Ground/Heat Sink (GND/HEATSINK)
All GND/HEATSINK terminals are connected directly to the mount pad for thermal-enhanced operation. These
terminals could be connected to GND or left floating.
Input Capacitor
For a typical application, an input bypass capacitor (0.22 μF−1μF) is recommended for device stability. This
capacitor should be as close to the input pins as possible. For fast transient condition, where droop at the input
of the LDO may occur due to high in-rush current, it is recommended to place a larger capacitor at the input as
well. The size of this capacitor is dependant on the output current and response time of the main power supply,
as well as the distance to the load (LDO).
Output Capacitor
As with most LDO regulators, the TPS75201M-EP requires an output capacitor connected between OUT and
GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 μF, and the ESR
must be between 100 mΩand 10 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic
capacitors are all suitable, provided they meet the requirements described in this section. Larger capacitors
provide a wider range of stability and better load transient response.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the
user’s application. When necessary to achieve low height requirements along with high output current and/or
high load capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines.
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LDO
V
V
I
ESR
I
R
O
ESR
C
R
O
LOAD
VO
+
−
RESR LESL C
TPS75201M-EP
www.ti.com
SGLS325A –JANUARY 2006–REVISED JULY 2013
ESR and Transient Response
LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors
are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is
used to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are
resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the
inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any
capacitor therefore can be drawn as shown in Figure 21.
Figure 21. ESR and ESL
In most cases, the effect of inductive impedance ESL can be neglected. Therefore, the following application
focuses mainly on the parasitic resistance ESR.
Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow), and the voltage across
the capacitor is the same as the output voltage [V(CO) = VO]. This means no current is flowing into the CObranch.
If IO suddenly increases (transient condition), the following occurs:
• The LDO is not able to supply the sudden current need due to its response time (t1in Figure 24). Therefore,
capacitor COprovides the current for the new load condition (dashed arrow). COnow acts like a battery with
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at
RESR. This voltage is shown as VESR in Figure 23.
• When COis conducting current to the load, initial voltage at the load is VO= V(CO) – VESR. Due to the
discharge of CO, the output voltage VOdrops continuously until the response time, t1, of the LDO is reached
and the LDO resumes supplying the load. From this point, the output voltage starts rising again until it
reaches the regulated voltage. This period is shown as t2in Figure 24.
Figure 23 also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs, where number 1 displays the lowest and number 3 displays the highest ESR.
From the previous paragraphs, the following conclusions can be drawn:
• The higher the ESR, the larger the droop at the beginning of load transient.
• The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
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O
ref
V
R1 1 R2
V
æ ö
= - ´
ç ÷
è ø
O ref
R1
V V 1
R2
æ ö
= ´ +
ç ÷
è ø
ESR 1
ESR 2
ESR 3
3
1
2
tt
I
V
12
O
O
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
Conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
Figure 23. Correlation of Different ESRs and Their Influence to Regulation of VOat
Load Step From Low-to-High Output Current
Programming the Adjustable LDO Regulator
The output voltage of the TPS75201M-EP adjustable regulator is programmed using an external resistor divider
(see Figure 24). The output voltage is calculated using:
(1)
Where:
Vref = 1.1834 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 40-μA divider current. Lower-value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ
to set the divider current at 40 μA and then calculate R1 using:
(2)
14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links :TPS75201M-EP
( )
D I O O
P V V I= - ´
J A
D(max)
JA
T max T
PRq
-
=
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
UNIT
33.2
53.6
61.9
30.1
30.1
30.1
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
V
VRESET
O
I
OUT
FB/SENSE
R1
R2
GND
EN
IN
≤0.7 V
≥2 V
RESET Output
0.22 µF
250 kΩ
NOTE: To reduce noise and prevent
oscillation, R1 and R2 must be as close as
possible to the FB/SENSE terminal.
CO
TPS75201M-EP
www.ti.com
SGLS325A –JANUARY 2006–REVISED JULY 2013
Figure 24. Adjustable LDO Regulator Programming
REGULATOR PROTECTION
The TPS75201M-EP PMOS-pass transistor has a built-in back diode that conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to
the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS75201M-EP also features internal current limiting and thermal protection. During normal operation, the
TPS75201M-EP limits output current to approximately 3.3 A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package. If the
temperature of the device exceeds 150°C (typ), thermal-protection circuitry shuts it down. Once the device has
cooled below 130°C (typ), regulator operation resumes.
POWER DISSIPATION AND JUNCTION TEMPERATURE
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max).
The maximum power dissipation limit is determined by using Equation 3:
(3)
Where:
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 34.6°C/W for the 20-terminal PWP
with no airflow (see Dissipation Rating Table).
TAis the ambient temperature.
The regulator dissipation is calculated using:
(4)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links :TPS75201M-EP
DIE
(a) Side View
(b) End View
(c) Bottom View
DIE
Thermal
Pad
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
THERMAL INFORMATION
THERMALLY-ENHANCED TSSOP-20 (PWP −PowerPAD™)
The thermally-enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see
Figure 25(c)] to provide an effective thermal contact between the IC and the PWB.
Traditionally, surface mount and power have been mutually-exclusive terms. A variety of scaled-down TO220-
type packages have leads formed as gull wings to make them applicable for surface-mount applications. These
packages, however, suffer from several shortcomings – they do not address the very low-profile requirements
(<2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to accommodate
increasing integration. Conversely, traditional low-power surface-mount packages require power dissipation
derating that severely limits the usable range of many high-performance analog circuits.
The PWP package (thermally-enhanced TSSOP) combines fine-pitch surface-mount technology, with thermal
performance comparable to much larger power packages.
The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and
limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths
that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending)
and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad
is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultra-thin, fine-pitch,
surface-mount package can be reliably achieved.
Figure 25. Views of Thermally-Enhanced PWP Package
Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal
considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface),
which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air [reference
Figure 27(a), 8 cm2 of copper heat sink and natural convection]. Increasing the heat-sink size increases the
power-dissipation range for the component. The power-dissipation limit can be further improved by adding airflow
to a PWB/IC assembly (see Figure 26 and Figure 27). The line drawn at 0.3 cm2 in Figure 26 and Figure 27
indicates performance at the minimum recommended heat-sink size (see Figure 29).
The thermal pad is connected directly to the substrate of the IC, which for the TPS75201MPWPREP is a
secondary electrical connection to device ground. The heat-sink surface that is added to the PWP can be a
ground plane or left electrically isolated. In TO220-type surface-mount packages, the thermal connection also is
the primary electrical connection for a given terminal, which is not always ground. The PWP package provides up
to 16 independent leads that can be used as inputs and outputs (Note: leads 1, 10, 11, and 20 are connected
internally to the thermal pad and the IC substrate).
16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links :TPS75201M-EP
100
75
50
25
0 2 3 5
− Thermal Resistance −
125
THERMAL RESISTANCE
vs
COPPER HEAT-SINK AREA
150
7 8
1 4 60.3
Natural Convection
50 ft/min
250 ft/min
300 ft/min
C/W
°
Copper Heat-Sink Area − cm2
100 ft/min
150 ft/min
200 ft/min
RJA
θ
TPS75201M-EP
www.ti.com
SGLS325A –JANUARY 2006–REVISED JULY 2013
Figure 26.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links :TPS75201M-EP
1
0.5
3
00 2 4 6
2
1.5
2.5
3.5
8
0.3
300 ft/min
150 ft/min
Natural Convection
Copper Heat-Sink Size − cm2
TA= 55°C
(b)
1
0.5
3
00 2 4 6
2
1.5
2.5
3.5
8
0.3
300 ft/min
150 ft/min
Natural Convection
Copper Heat-Sink Size − cm2
TA= 105°C
(c)
1
0.5
3
00 2 4 6
− Power Dissipation Limit − W
2
1.5
2.5
3.5
8
0.3
300 ft/min
150 ft/min
Natural Convection
PD
Copper Heat-Sink Size − cm2
TA= 25°C
(a)
− Power Dissipation Limit − W
PD
− Power Dissipation Limit − W
PD
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
Figure 27. Power Ratings of PWP Package at TA= 25°C, 55°C, and 105°C
Figure 28 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This board
configuration was used in the thermal experiments that generated the power ratings shown in Figure 26 and
Figure 27. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RθJA
for this assembly is shown in Figure 26 as a function of heat-sink area. A family of curves is included to show the
effect of airflow introduced into the system.
18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links :TPS75201M-EP
( ) ( )
I O OD(total) V V I 5 3.3 0.8 1.36 WP - ´ = - ´ ==
J A
D(max)
JA(system)
T max T 125 C 55 C
P 1.4W
R 50 C / W
q
-° - °
= = =
°
( )
D(total) I O O
P V V I= - ´
( )
D(total) I O O I Q
P V V I V I- += ´ ´
J A
D(max)
JA(system)
T max T
PRq
-
=
Board thickness 62 mil
Board size 3.2 in × 3.2 in
Board material FR4
Copper trace/heat sink 1 oz
Exposed pad mounting 63/67 tin/lead solder
Heat-Sink Area
1-oz Copper
TPS75201M-EP
www.ti.com
SGLS325A –JANUARY 2006–REVISED JULY 2013
Figure 28. PWB Layout (Including Copper Heat-Sink Area) for Thermally-Enhanced PWP Package
From Figure 26, RθJA for a PWB assembly can be determined and used to calculate the maximum power-
dissipation limit for the component/PWB assembly, with the equation:
(5)
Where:
TJmax is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended
operating limit) and TAis the ambient temperature.
PD(max) should then be applied to the internal power dissipated by the TPS75201M-EP regulator. The equation for
calculating total internal power dissipation of the TPS75201M-EP is:
(6)
Since the quiescent current of the TPS75201M-EP is very low, the second term is negligible, further simplifying
the equation to:
(7)
For the case where TA= 55°C, airflow = 200 ft /min, copper heat-sink area = 4 cm2, the maximum power-
dissipation limit can be calculated. First, from Figure 26, the system RθJA is 50°C/W, therefore, the maximum
power-dissipation limit is:
(8)
If the system implements a TPS75201M-EP regulator, where VI=5VandIO= 800 mA, the internal power
dissipation is:
(9)
Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated
limit. When it does, one of two corrective actions should be made – raising the power-dissipation limit by
increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing
the input voltage or the load current. In either case, the previous calculations should be repeated with the new
system parameters.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links :TPS75201M-EP
Location of Exposed
Thermal Pad on
PWP Package
Minimum Recommended
Heat-Sink Area
TPS75201M-EP
SGLS325A –JANUARY 2006–REVISED JULY 2013
www.ti.com
MOUNTING INFORMATION
The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The
thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted.
Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data
included in Figure 26 and Figure 27 is for soldered connections with voiding between 20% and 50%. The thermal
analysis shows no significant difference resulting from the variation in voiding percentage.
Figure 29 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink area
also is shown. This is simply a copper plane under the body extent of the package, including metal routed under
terminals 1, 10, 11, and 20.
Figure 29. PWP Package Land Pattern
20 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links :TPS75201M-EP
PACKAGE OPTION ADDENDUM
www.ti.com 31-May-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS75201MPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 75201EP
V62/03635-11XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 75201EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 31-May-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS75201MPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS75201MPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-May-2013
Pack Materials-Page 2
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