General Description
The MAX5500/MAX5501 integrate four low-power, 12-bit
digital-to analog converters (DACs) and four precision
output amplifiers in a small, 20-pin package. Each nega-
tive input of the four precision amplifiers is externally
accessible providing flexibility in gain configurations,
remote sensing, and high output drive capacity, making
the MAX5500/MAX5501 ideal for industrial-process-con-
trol applications. Other features include software shut-
down, hardware shutdown lockout, an active-low reset
which clears all registers and DACs to zero, a user-pro-
grammable logic output, and a serial-data output.
Each DAC provides a double-buffered input organized
as an input register followed by a DAC register. A 16-bit
serial word loads data into each input register. The seri-
al interface is compatible with SPI™/QSPI™/
MICROWIRE™. The serial interface allows the input and
DAC registers to be updated independently or simulta-
neously with a single software command. The 3-wire
interface simultaneously updates the DAC registers. All
logic inputs are TTL/CMOS-logic compatible. The
MAX5500 operates from a single +5V power supply,
and the MAX5501 operates from a single +3V power
supply. The MAX5500/MAX5501 are specified over the
extended -40°C to +105°C temperature range.
Applications
Industrial Process Controls
Automatic Test Equipment
Microprocessor (μP)-Controlled Systems
Motion Control
Digital Offset and Gain Adjustment
Remote Industrial Controls
Features
oFour 12-Bit DACs with Configurable Output
Amplifiers
o+5V or +3V Single-Supply Operation
oLow Supply Current:
0.85mA Normal Operation
10µA Shutdown Mode (MAX5500)
oForce-Sense Outputs
oPower-On Reset Clears All Registers and DACs
to Zero
oCapable of Recalling Last State Prior to Shutdown
oSPI/QSPI/MICROWIRE Compatible
oSimultaneous or Independent Control of DACs
through 3-Wire Serial Interface
oUser-Programmable Digital Output
oGuaranteed Over Extended Temperature Range
(-40°C to +105°C)
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
________________________________________________________________
Maxim Integrated Products
1
MAX5500
MAX5501 OUTA
FBA
FBB
FBC
FBD
DAC A
DAC B
DAC C
DAC D
REFAB
DAC
REGISTER A
DECODE
CONTROL
INPUT
REGISTER A
DAC
REGISTER B
INPUT
REGISTER B
DAC
REGISTER C
INPUT
REGISTER C
DAC
REGISTER D
INPUT
REGISTER D
16-BIT
SHIFT
REGISTER
SR
CONTROL LOGIC
OUTPUT
CS DIN SCLK
OUTB
OUTC
OUTD
DOUT PDL
CL VDD
AGND
DGND
UPO REFCD
Functional Diagram
19-4368; Rev 1; 4/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp.
Ordering Information
PART PIN-
PACKAGE
INL (LSB)
SUPPLY (V)
MAX5500AGAP+ 20 SSOP ±0.75 +5
MAX5500BGAP+ 20 SSOP ±2 +5
MAX5501AGAP+ 20 SSOP ±0.75 +3
MAX5501BGAP+ 20 SSOP ± 2 +3
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Note: All devices are specified over the -40°C to +105°C operating
temperature range.
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V to +3.6V, VREFAB = VREFCD = 1.25V), VAGND = VDGND
= 0, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in
unity-gain configuration (Figure 9).)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND............................................................-0.3V to +6V
VDD to DGND ...........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
REFAB, REFCD to AGND...........................-0.3V to (VDD + 0.3V)
OUT_, FB_ to AGND...................................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND.............................................-0.3V to +6V
DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V)
Continuous Current into Any Pin.......................................±20mA
Continuous Power Dissipation (TA= +70°C)
20-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE (Analog Section)
Resolution N 12 Bits
MAX5500A/MAX5501A ±0.25 ±0.75
Integral Nonlinearity
(Note 1) INL MAX5500B/MAX5501B ±2.0 LSB
Differential Nonlinearity DNL Guaranteed monotonic ±1.0 LSB
Offset Error VOS ±3.5 mV
Offset-Error Tempco 6 ppm/ oC
MAX5500 -0.3 ±2.0
Gain Error (Note 1) GE MAX5501 -0.7 ±4.0 LSB
Gain-Error Tempco 1 ppm/ oC
MAX5500 100 600
Power-Supply Rejection Ratio PSRR MAX5501 100 300 µV/V
MATCHING PERFORMANCE (TA = +25oC)
MAX5500 -0.3 ±2.0
Gain Error GE MAX5501 -0.85 ±4.0 LSB
Offset Error VOS ±1.0 ±3.5 mV
Integral Nonlinearity INL (Note 1) ±0.35 ±1.0 LSB
REFERENCE INPUT
Reference Input Range VREF 0V
DD - 1.4 V
Reference Input Resistance RREF Code-dependent, minimum at code
555H 8kΩ
Refer ence C ur r ent i n S hutd ow n 0.01 ±1.0 µA
DIGITAL INPUTS
MAX5500A/MAX5500B 2.4
Input High Voltage VIH MAX5501A/MAX5501B 2.0 V
Input Low Voltage VIL 0.8 V
Input Leakage Current IIN VIN = 0 or VDD ±0.1 ±1.0 µA
Input Capacitance CIN 8pF
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V to +3.6V, VREFAB = VREFCD = 1.25V), VAGND = VDGND
= 0, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in
unity-gain configuration (Figure 9).)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUTS
Output High Voltage VOH ISOURCE = 2mA VDD - 0.5 V
Output Low Voltage VOL ISINK = 2mA 0.13 0.4 V
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR 0.6 V/µs
To ±0.5 LSB, VSTEP = 2.5V
MAX5500A/MAX5500B 12
Output Settling Time
To ±0.5 LSB, VSTEP = 1.25V
MAX5501A/MAX5501B 16
µs
Output Voltage Swing Rail-to-rail (Note 2) 0 to VDD V
Current into FB_ 0 0.1 µA
OUT_ Leakage Current in
Shutdown RL = ∞±0.01 ±1.0 µA
MAX5500A/MAX5500B 15
Startup Time Exiting
Shutdown Mode MAX5501A/MAX5501B 20 µs
Digital Feedthrough CS
=VDD, fIN = 100kHz 5 nV•s
Digital Crosstalk 5nV•s
POWER SUPPLIES
MAX5500A/MAX5500B 4.5 5.5
Supply Voltage VDD MAX5501A/MAX5501B 3.0 3.6 V
Supply Current IDD (Note 3) 0.85 1.1 mA
Supply Current in Shutdown (Note 3) 10 20 µA
TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period tCP 100 ns
SCLK Pulse-Width High tCH 40 ns
SCLK Pulse-Width Low tCL 40 ns
CS Fall to SCLK Rise Setup
Time tCSS 40 ns
SCLK Rise to CS Rise Hold
Time tCSH 0ns
DIN Setup Time tDS 40 ns
DIN Hold Time tDH 0ns
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V to +3.6V, VREFAB = VREFCD = 1.25V), VAGND = VDGND
= 0, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in
unity-gain configuration (Figure 9).)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5500 80
SCLK Rise to DOUT Valid
Propagation Delay tD01 CLOAD = 200pF MAX5501 120 ns
MAX5500 80
SCLK Fall to DOUT Valid
Propagation Delay tD02 CLOAD = 200pF MAX5501 120 ns
SCLK Rise to CS Fall Delay tCS0 40 ns
CS Rise to SCLK Rise Hold
Time tCS1 40 ns
CS Pulse-Width High tCSW 100 ns
Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration.
Note 2: Accuracy is better than 1.0 LSB for VOUT = 6mV to (VDD - 60mV), guaranteed by PSR test on endpoints.
Note 3: RL = ∞, digital inputs at DGND or VDD.
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
MAX5500 toc01
REFERENCE VOLTAGE (V)
INL (LSB)
3.62.82.01.2
-0.8
-0.6
-0.4
-0.2
0
0.2
-1.0
0.4 4.4
MAX5500
VDD = 5V
RL = 5kΩ
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
MAX5500 toc02
REFERENCE VOLTAGE (V)
INL (LSB)
1.91.40.9
-0.8
-0.6
-0.4
-0.2
0
-1.0
0.4 2.4
MAX5501
VDD = 3V
RL = 5kΩ
SUPPLY CURRENT
vs. TEMPERATURE
MAX5500 toc03
TEMPERATURE (°C)
IDD (µA)
1109580655035205-10-25-40
860
870
880
890
900
910
850
-55 125
MAX5500
VDD = 5V
CODE = FFF hex
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 5
SUPPLY CURRENT
vs. TEMPERATURE
MAX5500 toc04
TEMPERATURE (°C)
IDD (µA)
1109580655035205-10-25-40
740
760
780
800
820
750
770
790
810
830
730
-55 125
MAX5501
VDD = 3V
CODE = FFF hex
FULL-SCALE ERROR
vs. LOAD
MAX5500 toc05
LOAD (kΩ)
INL (LSB)
1010.1
-4
-3
-2
-1
0
-5
0.01 100
MAX5500
VDD = 5V
FULL-SCALE ERROR
vs. LOAD
MAX5500 toc06
LOAD (kΩ)
INL (LSB)
1010.1
-4
-3
-2
-1
0
-5
0.01 100
MAX5501
VDD = 3V
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5500 toc07
VDD (V)
IDD (µA)
5.255.004.75
780
800
820
840
860
880
900
920
940
760
4.50 5.50
MAX5500
VDD = 5V
CODE = FFF hex
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5500 toc08
VDD (V)
IDD (µA)
3.53.43.1 3.2 3.3
784
786
788
790
792
794
796
798
782
3.0 3.6
MAX5501
VDD = 3V
CODE = FFF hex
ANALOG CROSSTALK 5V
MAX5500 toc09
10µs/div
OUTA
1V/div
OUTB
AC-COUPLED
10mV/div
VREF = 2.5V, RL = 5kΩ, CL = 100pF
DACA CODE SWITCHING FROM 00C hex TO FCC hex
DACB CODE SET TO 800 hex
ANALOG CROSSTALK 3V
MAX5500 toc10
10µs/div
OUTA
0.5V/div
OUTB
AC-COUPLED
50mV/div
VREF = 1.5V, RL = 5kΩ, CL = 100pF
DACA CODE SWITCHING FROM 00C hex TO FFF hex
DACB CODE SET TO 800 hex
DYNAMIC RESPONSE 5V
MAX5500 toc11
10µs/div
OUTA
1V/div
VREF = 2.5V, RL = 5kΩ, CL = 100pF
SWITCHING FROM CODE 000 hex TO FB4 hex
OUTPUT AMPLIFIER GAIN = +2
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
6 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 AGND Analog Ground
2 FBA DAC A Output Amplifier Feedback
3 OUTA DAC A Output Voltage
4 OUTB DAC B Output Voltage
5 FBB DAC B Output Amplifier Feedback
6 REFAB DAC A/DAC B Reference Voltage Input
7CL Active-Low Clear Input. CL clears all DACs and registers. CL resets all outputs (OUT_, UPO, and DOUT)
to 0.
8CS Active-Low Chip-Select Input
9 DIN Serial Data Input
10 SCLK Serial Clock Input
11 DGND Digital Ground
12 DOUT Serial Data Output
13 UPO User-Programmable Logic Output
14 PDL Active-Low Power-Down Lockout. Drive PDL low to lock out software shutdown.
15 REFCD DAC C/DAC D Reference Voltage Input
16 FBC DAC C Output Amplifier Feedback
17 OUTC DAC C Output Voltage
18 OUTD DAC D Output Voltage
19 FBD DAC D Output Amplifier Feedback
20 VDD Positive Power Supply
DYNAMIC RESPONSE 3V
MAX5500 toc12
10µs/div
OUTA
0.5V/div
VREF = 1.5V, RL = 5kΩ, CL = 100pF
SWITCHING FROM CODE 000 hex TO FB4 hex
OUTPUT AMPLIFIER GAIN = +1
DIGITAL FEEDTHROUGH 3V
(SCLK = 100kHz)
MAX5500 toc13
4µs/div
SCLK
1V/div
OUTA
AC-COUPLED
10mV/div
VREF = 1.5V, RL = 5kΩ, CL = 100pF
VCS = VPDL = VCL = 3.3V, VDIN = 0V
DACA CODE SET TO 800 hex
DIGITAL FEEDTHROUGH 5V
(SCLK = 100kHz)
MAX5500 toc14
2µs/div
SCLK
2V/div
OUTA
AC-COUPLED
10mV/div
VREF = 2.5V, RL = 5kΩ, CL = 100pF
VCS = VPDL = VCL = 5V, VDIN = 0V
DACA CODE SET TO 800 hex
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 7
Detailed Description
The MAX5500/MAX5501 integrate four 12-bit, voltage-
output digital-to-analog converters (DACs) that are
addressed through a simple 3-wire serial interface. The
devices include a 16-bit data-in/data-out shift register.
Each internal DAC provides a doubled-buffered input
composed of an input register and a DAC register (see
the
Functional Diagram
). The negative input of each
amplifier is externally accessible.
The DACs are inverted rail-to-rail ladder networks that
convert 12-bit digital inputs into equivalent analog out-
put voltages in proportion to the applied reference volt-
age inputs. DACs A and B share the REFAB input,
while DACs C and D share the REFCD input. The two
reference inputs allow different full-scale output voltage
ranges for each pair of DACs. Figure 1 shows a simpli-
fied circuit diagram of one of the four DACs.
Reference Inputs
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets the
full-scale output voltage for the two corresponding
DACs. The reference input voltage range is 0V to (VDD
- 1.4V). The output voltages (VOUT_) are represented by
a digitally programmable voltage source as:
VOUT_ = (VREF x NB/4096) x Gain
where NB is the numeric value of the binary input code
(0 to 4095) of the DAC. VREF is the reference voltage.
Gain is the externally set voltage gain.
The impedance at each reference input is code-depen-
dent, ranging from a low value of 10kΩwhen both
DACs connected to the reference accept an input code
of 555 hex, to a high value exceeding giga-ohms with
an input code of 000 hex. The load regulation of the ref-
erence source affects the performance of the devices
as the input impedance at the reference inputs is code
dependent. The REFAB and REFCD reference inputs
provide a 10kΩguaranteed minimum input impedance.
When the same voltage source drives the two reference
inputs, the effective minimum impedance is 5kΩ. A volt-
age reference with an excellent load regulation of
0.0002mV/mA, such as the MAX6033, is capable of dri-
ving both reference inputs simultaneously at 2.5V.
Driving REFAB and REFCD separately improves refer-
ence accuracy.
The REFAB and REFCD inputs enter a high-impedance
state, with a typical input leakage current of 0.02µA,
when the MAX5500/MAX5501 are in shutdown. The ref-
erence input capacitance is also code dependent and
typically ranges from 20pF with an input code of all 0s
to 100pF with an input code of all 1s.
Output Amplifiers
All DAC outputs are internally buffered by precision
amplifiers with a typical slew rate of 0.6V/µs. Access to
the inverting input of each output amplifier provides the
greater flexibility in output gain setting/signal condition-
ing (see the
Applications Information
section).
With a full-scale transition at the output, the typical set-
tling time to within ±0.5 LSB is 12µs when the output is
loaded with 5kΩin parallel with 100pF. A load of less
than 2kΩat the output degrades performance. See the
Typical Operating Characteristics
for the output dynamic
responses and settling performances of the amplifiers.
Power-Down Mode
The MAX5500/MAX5501 feature a software-program-
mable shutdown that reduces supply current to a typi-
cal value of 10µA. Drive PDL high to enable the
shutdown mode. Write 1100XXXXXXXXXXXX as the
input-control word to put the device in power-down
mode (Table 1).
In power-down mode, the output amplifiers and the ref-
erence inputs enter a high-impedance state.
The serial interface remains active. Data in the input
registers is retained in power-down, allowing the
devices to recall the output states prior to entering shut-
down. Start up from power-down either by recalling the
previous configuration or by updating the DACs with
new data. Allow 15µs for the outputs to stabilize when
powering up the devices or bringing the devices out of
shutdown.
OUT_
FB_
SHOWN FOR ALL 1s ON DAC
D0 D9 D10 D11
2R 2R 2R 2R 2R
RRR
REF_
AGND
Figure 1. Simplified DAC Circuit Diagram
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
8 _______________________________________________________________________________________
SCLK
DIN
DOUT*
CS
SK
SO
SI*
I/O
MAX5500
MAX5501
MICROWIRE
PORT
*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX5500/MAX5501, BUT CAN BE USED FOR READBACK PURPOSES.
Figure 2. Connections for MICROWIRE
Serial-Interface Configurations
The MAX5500/MAX5501s’ 3-wire serial interface is
compatible with both MICROWIRE (Figure 2) and
SPI/QSPI (Figure 3). The serial input word consists of
two address bits and two control bits followed by 12
data bits (MSB first), as shown in Figure 4. The 4-bit
address/control code determines the MAX5500/
MAX5501s’ response outlined in Table 1. The connec-
tion between DOUT and the serial-interface port is not
necessary, but may be used for data echo. Data held in
the shift register can be shifted out of DOUT and
returned to the µP for data verification.
The digital inputs of the MAX5500/MAX5501 are double
buffered. Depending on the command issued through the
serial interface, the input register(s) can be loaded without
affecting the DAC register(s), the DAC register(s) can be
loaded directly, or all four DAC registers can be updated
simultaneously from the input registers (Table 1).
Serial-Interface Description
The MAX5500/MAX5501 require 16 bits of serial data.
Table 1 lists the serial-interface programming com-
mands. For certain commands, the 12 data bits are
don’t-care bits. Data is sent MSB first and can be sent
in two 8-bit packets or one 16-bit word (CS must remain
low until 16 bits are transferred). The serial data is com-
posed of two DAC address bits (A1, A0) and two control
bits (C1, C0), followed by the 12 data bits D11–D0
(Figure 4). The 4-bit address/control code determines:
•The register(s) to be updated
•The clock edge on which data is to be clocked out
through the serial-data output (DOUT)
•The state of the user-programmable logic output
(UPO)
•If the device is to enter shutdown mode (assuming
PDL is high)
•How the device is configured when exiting out of
shutdown mode
DOUT*
DIN
SCLK
CS
MISO*
MOSI
SCK
I/O
SPI/QSPI
PORT
SS
+5V
CPOL = 0, CPHA = 0
*THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX5500/MAX5501, BUT CAN BE USED FOR READBACK PURPOSES.
MAX5500
MAX5501
Figure 3. Connections for SPI/QSPI
MSB.................................................................................................................................LSB
MSB...........................................................................................LSB
16 BITS OF SERIAL DATA
ADDRESS
BITS
CONTROL
BITS
DATA BITS
4 ADDRESS/
CONTROL BITS
D11..............................................................................................D0
A1 A0 C1 C0
12 DATA BITS
Figure 4. Serial-Data Format
MAX5500/MAX5501
16-BIT SERIAL WORD
A1 A0 C1 C0 D11................D0
MSB LSB
FUNCTION
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
Load input register A; DAC registers unchanged.
Load input register B; DAC registers unchanged.
Load input register C; DAC registers unchanged.
Load input register D; DAC registers unchanged.
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
Load input register A; all DAC registers updated.
Load input register B; all DAC registers updated.
Load input register C; all DAC registers updated.
Load input register D; all DAC registers updated.
0 1 0 0 XXXXXXXXXXXX Update all DAC registers from their respective input registers (startup).
1 0 0 0 12-bit DAC data Load all DAC registers from shift register (startup).
1 1 0 0 XXXXXXXXXXXX Shutdown (provided PDL = 1)
0 0 1 0 XXXXXXXXXXXX UPO goes low (default)
0 1 1 0 XXXXXXXXXXXX UPO goes high
0 0 0 0 XXXXXXXXXXXX No operation (NOP) to DAC registers
1 1 1 0 XXXXXXXXXXXX Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers updated.
1 0 1 0 XXXXXXXXXXXX Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers updated
(default).
Table 1. Serial-Interface Programming Commands
Figure 5 shows the serial-interface timing requirements.
The CS input must be low to enable the DAC’s serial
interface. When CS is high, the interface control circuitry
is disabled. CS must go low for at least tCSS before the
rising serial clock (SCLK) edge to properly clock in the
first bit. When CS is low, data is clocked into the internal
shift register through the serial data input (DIN) on the
rising edge of SCLK. The maximum guaranteed clock
frequency is 10MHz. Data is latched into the appropriate
input/DAC registers on the rising edge of CS.
The programming command “load-all-dacs-from-shift-
register” allows all input and DAC registers to be simul-
taneously loaded with the same digital code from the
input shift register. The no operation (NOP) command
leaves the register contents unaffected. This feature is
used in a daisy-chain configuration (see the
Daisy
Chaining Devices
section).
The command to change the clock edge on which seri-
al data is shifted out of DOUT also loads data from all
input registers to their respective DAC registers.
Serial-Data Output (DOUT)
The serial-data output, DOUT, is the internal shift regis-
ter’s output. The MAX5500/MAX5501 can be pro-
grammed so that data is clocked out of DOUT on the
rising edge of SCLK (mode 1) or the falling edge (mode
0). In mode 0, output data at DOUT lags input data at
DIN by 16.5 clock cycles, maintaining compatibility with
MICROWIRE, SPI/QSPI, and other serial interfaces. In
mode 1, output data lags input data by 16 clock cycles.
On power-up, DOUT defaults to mode 0 timing.
User-Programmable Logic Output (UPO)
The user-programmable logic output, UPO, allows an
external device to be controlled through the
MAX5500/MAX5501 serial interface (Table 1).
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 9
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
10 ______________________________________________________________________________________
CS
SCLK
DIN
DOUT
(MODE 1)
MSB FROM
PREVIOUS WRITE
MSB FROM
PREVIOUS WRITE
COMMAND
EXECUTED
9
816
1
A0
A1 D0
C1 C0 D11 D10 D9 D6 D5 D4 D3 D2 D1
D8 D7
DOUT
(MODE 0) A0
A1 D0 A1
C1 C0 D11 D10 D9 D6 D5 D4 D3 D2 D1
D8 D7
A0
A1 D0 A1
C1 C0 D11 D10 D9 D6 D5 D4 D3 D2 D1
D8 D7
DATA PACKET (N)
DATA PACKET (N-1) DATA PACKET (N)
DATA PACKET (N-1) DATA PACKET (N)
Figure 5. Serial-Interface Timing Diagram
SCLK
DIN
DOUT
tCSO
tCSS tCL
tCH tCP
tDO1
tCSW
tCS1
tDO2
tCSH
tDS tDH
CS
Figure 6. Detailed Serial-Interface Timing Diagram
Power
-
Down Lockout
(PDL)
Drive power-down lockout, PDL, low to disable software
shutdown. When in shutdown, transitioning PDL from
high to low wakes up the device with the output set to
the state prior to shutdown. Use PDL to asynchronously
wake up the device.
Daisy Chaining Devices
The MAX5500/MAX5501 can be daisy chained by con-
necting DOUT of one device to DIN of another device
(Figure 7).
Each DOUT output of the MAX5500/MAX5501 includes
an internal active pullup. The sink/source capability of
DOUT determines the time required to discharge/charge
a capacitive load. See the serial-data-out VOH and VOL
specifications in the
Electrical Characteristics.
Figure 8 shows an alternate method of connecting sev-
eral MAX5500/MAX5501 devices. In this configuration,
the data bus is common to all devices. Data is not shift-
ed through a daisy chain. More I/O lines are required in
this configuration because a dedicated chip-select
input (CS) is required for each IC.
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________________________________ 11
DIN
CS
TO OTHER
SERIAL DEVICES
MAX5500
MAX5501
SCLK
DIN
CS
DOUT
MAX5500
MAX5501
SCLK
DIN
CS
DOUT
MAX5500
MAX5501
SCLK
DIN
CS
DOUT
SCLK
Figure 7. Daisy Chaining MAX5500/MAX5501
TO OTHER
SERIAL DEVICES
MAX5500
MAX5501
DIN
SCLK
CS
MAX5500
MAX5501
DIN
SCLK
CS
MAX5500
MAX5501
DIN
SCLK
CS
DIN
SCLK
CS1
CS2
CS3
Figure 8. Multiple MAX5500/MAX5501 Devices Sharing a Common DIN Line
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
12 ______________________________________________________________________________________
DAC CONTENTS ANALOG OUTPUT
MSB LSB
4095
1111 1111 1111 +VREF (——— )
4096
2049
1000 0000 0001 +VREF (——— )
4096
2048 +VREF
1000 0000 0000 +VREF (——— )= ————
4096 2
2047
0111 1111 1111 +VREF (——— )
4096
1
0000 0000 0001 +VREF (——— )
4096
0000 0000 0000 0V
Table 2. Unipolar Code Table
DAC CONTENTS ANALOG OUTPUT
MSB LSB
2047
1111 1111 1111 +VREF (——— )
2048
1
1000 0000 0001 +VREF (——— )
2048
1000 0000 0000 0V
1
0111 1111 1111 -VREF (——— )
2048
2047
0000 0000 0001 -VREF (——— )
2048
2048
0000 0000 0000 -VREF (——— )= -VREF
2048
Table 3. Bipolar Code Table
Note: 1 LSB = (VREF) (4096 )
1
MAX5500
MAX5501
DAC A
DAC B
DAC C
DAC D
OUTA
FBA
FBB
FBC
FBD
OUTB
OUTC
OUTD
DGNDAGND
REFAB REFCD
REFERENCE INPUTS +5V
VDD
Figure 9. Unipolar Output Circuit
MAX5500
MAX5501
DAC A
DAC B
DAC C
DAC D
VREFAB = VREFCD = 2.5V
OUTA
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
OUTB
OUTC
OUTD
DGNDAGND
REFAB REFCD
REFERENCE INPUTS +5V
VDD FBA
FBB
FBC
FBD
Figure 10. Unipolar Rail-to-Rail Output Circuit
Applications Information
Unipolar Output
For a unipolar output, the output voltages and the refer-
ence inputs are of the same polarity. Figure 9 shows
the MAX5500/MAX5501 unipolar output circuit, which is
also the typical operating circuit. Table 2 lists the unipo-
lar output codes.
See Figure 10 for rail-to-rail outputs. Figure 10 shows
the MAX5500/MAX5501 with the output amplifiers con-
figured with a closed-loop gain of +2 to provide 0 to 5V
full-scale range with a 2.5V external reference voltage.
Bipolar Output
Figure 11 shows the MAX5500/MAX5501 configured for
bipolar operation.
VOUT = VREF [(2NB/4096) - 1]
where NB is the numeric value of the DAC’s binary
input code. Table 3 shows digital codes (offset binary)
and corresponding output voltages for the circuit of
Figure 11.
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________________________________ 13
Digitally Programmable Current Source
The circuit of Figure 12 places an npn transistor
(2N3904 or similar) within the op-amp feedback loop to
implement a digitally programmable, unidirectional cur-
rent source. This circuit drives 4mA to 20mA current
loops, which are commonly used in industrial-control
applications. The output current is calculated with the
following equation:
IOUT = (VREF/R) x (NB/4096)
where NB is the numeric value of the DAC’s binary input
code and R is the sense resistor shown in Figure 12.
Power-Supply Considerations
On power-up, all input and DAC registers are cleared
(set to zero code) and DOUT is in mode 0 (serial data is
shifted out of DOUT on the clock’s falling edge).
For rated MAX5500/MAX5501 performance, limit VREFAB/
VREFCD to 1.4V below VDD. Bypass VDD with a 4.7µF
capacitor in parallel with a 0.1µF capacitor to AGND.
Use short lead lengths and place the bypass capaci-
tors as close as possible to the supply inputs.
Grounding and Layout Considerations
Digital or AC transient signals between AGND and
DGND create noise at the analog outputs. Connect
AGND and DGND together at the DAC, and then con-
nect this point to the highest-quality ground available.
Good PCB ground layout minimizes crosstalk between
DAC outputs, reference inputs, and digital inputs.
Reduce crosstalk by keeping analog lines away from
digital lines. Do not use wire-wrapped boards.
Chip Information
PROCESS: BiCMOS
DAC
VOUT
+5V
-5V
R1 = R2 = 10kΩ ± 0.1%
MAX5500
MAX5501
REF_
R1 R2
FB_
OUT_
Figure 11. Bipolar Output Circuit
DAC_
MAX5500
MAX5501
REF_
OUT_
R
IOUT
2N3904
VL
FB_
Figure 12. Digitally Progammable Current Source
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
14 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 SSOP A20-2 21-0056
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
VDD
FBD
OUTD
OUTCOUTB
OUTA
FBA
AGND
TOP VIEW
FBC
REFCD
PDL
UPOCS
CL
REFAB
FBB
12
11
9
10
DOUT
DGNDSCLK
DIN
SSOP
MAX5500
MAX5501
+
Pin Configuration
MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 11/08 Initial release —
1 4/09 Removed future product asterisk from MAX5501 in Ordering Information table
and updated Electrical Characteristics table 1–4
