Product Technical Brief Date: 05/2001 picoPACKTM General Purpose I/O Introduction Architecture The General Purpose I/O module is a synthesizable Config Registers environment. Several modes are supported for dealing APB Control with asynchronous signals. The module is part of the picoPACK IP series from picoTurbo, Inc. Features GPIO Logic Events on input lines may generate interrupts Event detection modes Applications - signal level changes - asynchronous signal edges * * * * * GPIO[n] Programmable direction of the pins GPIO[2] 16 multiple function I/O pins GPIO[1] 32 bit APB bus GPIO[0] * * * * * Interrupt Controller GPIO Interrupt components such as microprocessors to the system's Address Select Data and output port capabilities for connecting intelligent Control APB Bus intellectual property block that provides digital input Programmable polarity of the pins Status registers provide information on the pins Configuration options Targeted at gate array and standard cell technologies Equivalent NAND2 gate count 4.4K * Mobile applications * High performance multi-CPU controllers * Low cost single chip controllers Interface Ports * 32 bit APB bus interface * 16 general purpose pins picoPACKTM General Purpose I/O Bus Support Operating Conditions * AMBATM 2.0 For the minimum clock speed there is no limitation due Functional Description to fully static design. The maximum clock speed The General Purpose I/O module provides a set of I/O signals being programmed by any intelligent component such as a microprocessor. In the output direction, logical depends on target technology and constraining. Therefore any clock frequency from 0 MHz to the actual maximum frequency may be chosen for safe operation. values are programmed for each signal. In the input direction, the raw signal value may be read or level triggered respectively edge triggered interrupts are generated. The General Purpose I/O module is a little endian device. Please refer to the AMBA 2.0 specification for further details. Deliverables * * * * * Fully synthesizable VHDL-RTL source code Fully synthesizable VERILOG-RTL source code Synopsys synthesis scripts Testbench with functional test vectors User documentation For more information, please contact: picoTurbo, Inc. 860 Hillview Court, Suite 160 Milpitas, CA. 95035 Ph: (408) 586-8801 Fax: (408) 586-8802 www.picoturbo.com info@picoturbo.com About picoTurbo, Inc. picoTurbo, Inc. is a premier provider of 16/32-bit RISC microprocessor cores, designed for use with applications that require ARM(R) (version 4T) instructions. pT-100, pT-100Ax, pT-110, pT-110Ax, pT-120, and picoPACK are trademarks of picoTurbo, Inc. ARM is a registered trademark of ARM Limited. AMBA is a trademark of ARM Limited. picoPACKTM General Purpose I/O