Rev. 4118J–AERO–08/04
Features
•Int eger Unit Based on SPARC V7 High-perf ormance RISC Architecture
•Optimized Integr ated 32/64-bi t Floating- point Unit
•On-chip Peripherals
– EDAC and Parit y Generat or and Checker
– Memory Interface
Chip Select Generator
Waitstate Generation
Memory Protection
–DMA Arbiter
–Timers
General Purp ose Timer (GPT)
Real-t ime Clock Tim er (RTCT)
W atchdog T imer ( WDT)
– Interrupt Cont rol ler with 5 Extern al In puts
– General Purpose Interface ( GPI)
– Dual UART
•S peed Optimi zed Code RAM Interface
8- or 40-bit boot-P ROM (Flash) Interface
•IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
•Fully Static Design
•Performance: 20 MIPs/5 MFlops (Double Precision) at SYSCLK = 25 MHz
•Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs
•Operating Range: 4.5V to 5.5V(1) -55°C to +125°C
•Tes ted up to Total Dose of 300 KRADs (Si) according to MIL STD 883 Method 1019
•SEU Event Rate Bet ter than 3 E-8 Error/Component/Day (Worst Case)
•No Single Event Lat ch-up below an LET Threshold of 80 MeV/mg/cm2
•Quality Grades: ESCC wit h 9512/003 and QML-Q or V with 5962-00540
•Package: 256 MQFPF ; Bare Di e
Note: 1. For 3.3V capability see the TSC695FL datas heet on the Atmel si te.
Description
The TSC695F (ERC32 Single-Chip) is a highly integrated, high-perf ormance 32-bit
RISC embed ded processor imple menting the SPARC architec ture V7 specification. It
has been developed with the support of the ESA (European Space Agency), and
off ers a full development environment for embedded space applications.
The p rocessor i s manufactured us ing the Atmel 0.5 µm radiation tolerant ( ≥ 300
KRADs (Si)) CMOS enhanced process (RTP). It has been spe cially designed for
space, a s it has on-chip concurrent transient and permanent erro r detection.
The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a
Memory Controller a nd a DMA arbiter. For real-time applications, the TSC695 F offers
a high secu rity wat chdog, two tim ers, an interrup t contro ller, paralle l and se rial int er-
faces. Fault tolerance is supported using parity on internal/external buses and an
EDAC on the external data bus. The design is highly testable with the support of an
On-Chip Debugger (OCD), and a boundary scan through JTAG interface.
Rad-Hard 32-bit
SPARC
Embedded
Processor
TSC695F
2TSC695F 4118J–AERO–08/04
Block Diagram
Figu re 1. TSC695F Block Diagram
Pin D escriptions For pin assignment , refer t o package section.
General Purpose
Interface UART A
TAP
Clock
Managt
Error
Managt General Purpose
Timer Real Time Clock
Timer
32-bit
Integer
Unit
DMA
Arbiter
Access
Controller
Address
Interface
Wait State
Controller
InterruptsRxD, TxDGPI bits
DMA Ctrl
Mem Ctrl
Ready/Busy
Add.+Size+ASI
Data+Check bits
Parities
EDAC
Watch
Dog
Parity
Parity
Gen./Check.
Reset
&
UART B Interrupt
Controller
32/64-bit
Floating-Point
Unit
Parity
Gen./Chk.
Gen./Chk.
Table 1. Pin Descriptions
Signal Type Active Description
RA[31:0] I/O, 32-bit registered address bus Output bu ffer: 400 pF
RAPAR I/O High Registered address bus parity -
RASI[3:0] I/O 4-bit registered address space identifier -
RSIZE[1:0] I/O 2-bit registered bus transaction size -
RASPAR I/O High Registered ASI and SIZE parity -
CPAR I/O High Control bus parity -
D[31:0] I/O 32-bit data bus -
CB[6:0] I/O 7-bi t check-bit bus -
DPAR I/O High Data bus parity -
RLDSTO I/O High Registered atomic load-store -
ALE O Low Address latch enable -
DXFER I/O High Data transfer -
LOCK I/O High Bus lock -
RD I /O H ig h Rea d ac c es s -
WE I/O Low Write enable -
WRT I/O High Advanced write -
MHOLD O Low Memory bu s hold MHOLD+FHOLD
+BHOLD+FCCV
MDS O Low Memory data strobe -
MEXC O Low Memory exceptio n -
PROM8 I Low Se lec t 8- b it w id e PR O M -
BA[1:0] O Latched address used for 8-bit wide boot PROM -
ROMCS O Low PROM chip sele ct -
ROMWRT I Low ROM write enable -
MEMCS[9:0] O Low Memory chi p s elect Output buffer: 400 pF
MEMWR O Low Memory write strobe Output buffer: 400 pF
3
TSC695F
4118J–AERO–08/04
Note: If not specified, the output buffer typ e is 150 pF, the input buffer type i s TTL.
OE O Low Memory output enable Output bu ffer: 400 pF
BUFFEN O Low Data buffer enable -
DDIR O High Data buffer direction -
DDIR O Low Data buffer direction -
IOSEL[3:0] O L ow I/O chip sele c t -
IOWR O Low I/O and exchange memory write strobe -
EXMCS O Low Exchange memory chip select -
BUSRDY ILowBus ready -
BUSERR I Low Bus error -
DMAREQ I Low DMA request -
DMAGNT O Low DMA grant -
DMA AS I High DMA ad dre s s strobe -
DRDY O Low Data ready during DMA access -
IUERR O Low IU error -
CPUHALT O Lo w Processor (IU & FP U) halt and freeze -
SYSERR O Low System error -
SYSHALT I Low System halt -
SYSAV O High Sys tem availability -
NOPAR I L ow N o parity -
INULL O High Integer unit nullify cycle -
IN ST O Hig h In st ruc tio n fe tch Used to check the exec ut e
s tage o f IU
instruction pipeline
FLUSH O High FPU instruction flush
DIA O High Delay in struction annull ed
RTC O High Real Time Clock Counter output -
RxA/RxB I Recei v e data UAR T ’A’ and ’B’ Input trigger
TxA/TxB O Tran smit da ta UART ’A’ and ’B’ -
GPI[7:0] I/O GPI input/output Input trigger
GPIINT O High GP I interrupt -
EXTINT[4:0] I External interrupt Input trigger
EXTINTACK O High External interr upt acknowledge -
IWD E I High Internal watch dog en able -
EWDINT I High External watch dog input interrupt Input trigger
WDCLK I Watch dog cl ock -
CL K2 I D ou ble freq u ency clo ck -
SYSC LK O System cl ock -
RESET OLowOutput reset -
SYSRESET I Low System input reset Input trigger
TMO DE[1:0] I Factory test mo de Functional mode=00
DEBU G I High Software debug mode -
TCK I Test (JTAG) clock -
TRST I Low Test (JTAG) reset pull-up ≈ 37 kΩ
TMS I Test (JTAG) mode sel ect pull-up ≈ 37 kΩ
TDI I Test (JTAG) data input pull-up ≈ 37 kΩ
TDO O Test (JTAG) data output -
VCCI/VSSI Main internal power -
VCCO/VSSO Output driver power -
Table 1. Pin Descriptions (Continued)
Signal Type Active Description
4TSC695F 4118J–AERO–08/04
Syst em Architecture The TSC695F is to be used as an embedded processor requiring only memory and
appl ication s pecific perip herals to be add ed to form a compl ete on-board c omp uter. All
other system support functions are provided by the core.
Figu re 2. System Arch itecture Base d on TSC695F
IU
FPU Memory
ALE
SYSCLK
A[31:0]
RA[31:0]
Master
Ax[31:0]
TSC695F
DMA Unit
Local
Memory
DMAGNT
DMAREQ
DMAAS
RAMCtrl
(ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY,...)
D[31:0]
(0 WS )
RAM
CB[6:0] DPAR
Boot PROM
Xtd PROM
Xchg Mem
Xtd RAM
Xtd I/O
Xtd general
I/O 0
to
I/O 3
Memory
Glue
Logic
DMA
DMA
(MEMCS[9 :0] , MEM W R , OE)
(BUFFEN, DDIR)
Interface
User
Peripherals
Application
MEMCtrl
5
TSC695F
4118J–AERO–08/04
Product Description
Integer Unit The Integer Unit (IU) is designed for hi ghly dependable sp ace and military a pplications,
and inclu des support for error det ect ion. Th e RI SC arch itecture mak es the c reat ion of a
processor that can execute instructions at a rate approaching one instruction per pro-
cessor clock possible.
To a chiev e that rate of exe cution, the I U emp loys a four-s tage in struct ion p ipeline that
permits parallel execution of mul tiple instructions.
• Fetc h - The processor outputs the instruction address to fetch the instruction.
• Dec ode - The instruction is placed in the in struction register and is decoded. The
processor reads the operands from the register file and computes the next
instruction address.
• Execute - The processor executes t he instruction and saves the results in t emporary
registers. Pending traps are prioritized and internal t raps are t a ken during this stage.
• Write - If no trap is taken, the processo r writes the result to the destination register.
All four stages operate in parallel, working on up to four different instructions at a time. A
basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles.
By the time it reaches the write stage, three more instructions have entered and are
moving through the pipeline behind it. So, after the first four cycles, a single-cycle
instruction exits the pipeline and a single-cycle instruction enters the pipeline on every
cycle. Of course, a ’single-cy cle’ instruction actually takes four cycles to comp lete, but
they are called single cycle because with this type of instruction the processor can com-
plete one instruction per cycle after the initial four-cycle delay.
Floating-point Unit Th e FL oa ting Poin t Un it ( FPU) is desi gned to prov ide exec uti on of sin gle and do uble -
precision floating-point instructions concurrently with execution of integer instructions by
the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard.
The FPU is designed for highly dependable space and military applications, and
includes su pport for concurrent error detection and testability.
The FPU us es a f our stage ins truction pipe line consi sting of fetch, decode, exec ute and
write stages (F, D, E and W). The fetch unit captures instructions and their addresses
from t he data and address buses. The decode unit contains logic to decode the floating-
point instruction opcodes. The execution unit handle s all instruction execution. The exe-
cution unit includes a floating-point queue (FP queue), which contains stored floating-
point operate (FPop) instructions under execution and their addresses. The execution
unit con trols the loa d unit, the st ore unit, and t he dat apath unit . The F PU depends up on
the IU to acces s all addresses and control signals for memory acces s. Floating-point
loads and stores are executed in conjunction wit h the IU, which provides addresses and
control signals while the FPU supplies or stores the data. Instruction fetch for integer
and floating-point instructions is provided by the IU.
The FPU provides t hree ty pes of r egisters: f r egisters, FSR, and the FP queue. The FSR
is a 32-bit status and control register. It keeps track of rounding modes, floating-point
trap ty pes, queue s ta tus, condi tion c odes, and various IEE E exce ption in formation. T he
floating-point queue contains the floating-point instruction currently under execution,
along with its corresponding add ress.
6TSC695F 4118J–AERO–08/04
Instruction Set TSC695F instructions fall into six functional categ ories: load/store, arithmetic/logi-
cal/shift, control transfer, read/wr ite con trol register, floating-point, and miscellaneo us.
Please refer to SPARC V7 Instruction-set Manual.
Note: The executi on of IFLUSH wi ll cause an illegal inst ruction trap.
On-chip Peripherals
Me mory I nte rface The TSC695F is designed to allow easy interfacing to internal/external memory
resources.
System Registers T he system registers are only writable by IU in the supervisor mode or by DMA du ring
halt mode.
Table 2. Memo ry Mapping
Memory Conte nts Start Address Size (byt es) Data Size and Parity Opti ons
Boot PROM 0 x
0000
0000 128K → 16M 8-bit mode No parity/-No EDAC/-Only byte write
40-bit mode Parity + EDAC mandatory/-Only word write
Extended PROM 0x
0100
000 0 Ma x : 1 5M 8-b it mo d e N o parity/-No ED A C /- O n ly by te write
40-bit mode Parity + EDAC mandatory/-Only word write
Exchange Memory 0x
01F0
0000 4k → 512k Pari ty + EDAC option/-Only word write
System Registers 0x
01F8
0000 512K (124 used) Parity/- On ly word read/write access
RAM (8 blocks) 0x
0200
0000 8*32K → 8*4M Parity + EDAC option/ -Al l data sizes allowed
Extended RAM 0x
0400
0000 Max: 192M
I/O A re a 0 0x
1000
0000 0 → 16M Parity option/-All data sizes allowed
I/O A re a 1 0x
1100
0000 0 → 16M
I/O A re a 2 0x
1200
0000 0 → 16M
I/O A re a 3 0x
1300
0000 0 → 16M
Extended I/O Area 0x
1400
0000 Max: 1728M
Extended General 0x
8000
0000 Max: 2G No parity/-All data sizes allowed
Table 3. System Registers Address Map
System Register Name Address
System Control Regi ster SYSCTR 0x 01F8 0000
Software Re set SWRST 0x 01F8 0004
Power Down PDOWN 0x 01F8 0008
System Fault Status Regi ster SYSFSR 0x 01F8 00A0
Fail ing Addre ss Register FAILAR 0x 01F8 00A4
Error & Reset Stat us Regi ster ERRRSR 0x 01F8 00B0
Test Contr ol Regi ster TESCTR 0x 01F8 00D0
7
TSC695F
4118J–AERO–08/04
Wait-state and Time-out
Generator It is possible to cont rol the wait -state generation by progra mming a Wait-sta te Configu-
ration Register. The maximum programmable number of wait-states is applied by
defaul t a t re s e t.
It is possible to program the number of wait-states for the following combinations:
– RAM read and write
– PROM read and write (i.e. EEPROM or Flash write)
– Exchange Memory read/ wri te
– Four individual I/O peripherals read/write
A bus time-out function of 256 system cloc k cycles is provided for the bus ready con-
trolled memory areas, i.e., the Extended PROM, Exchange Memory, Extended RAM,
Memor y Confi guration Register MCNFR 0x 01F8 0010
I/O Conf iguration Register IOCNFR 0x 01F8 0014
Waitstate Configur ati on Register WSCNFR 0x 01F8 0018
Access Protecti on Segment 1 Base Regi ster APS1BR 0x 01F8 0020
Access Protecti on Segment 1 End Register APS1ER 0x 01F8 0024
Access Protecti on Segment 2 Base Regi ster APS2BR 0x 01F8 0028
Access Protecti on Segment 2 End Register APS2ER 0x 01F8 002C
Interrupt Shape Register INTSHR 0x 01F8 0044
Interrupt Pending Register INTPDR 0x 01F8 0048
Interrupt Mask Regi ster INTMKR 0x 01F8 004C
Interrupt Clear Register INTCLR 0x 01F8 0050
Interrupt Force Register INTFCR 0x 01F8 0054
Watchdog Timer Regi ster WDOGTR 0x 01F8 0060
Watchdog T imer T rap Door Set WDOGST 0x 01F8 0064
Real Tim e Cloc k Timer <Counter > Register R TCCR 0x 01F8 0080
Real Tim e Clock T imer <Scaler> Register R TCSR 0x 01F8 0084
Gene ral Purpose Timer <Counter> Register GP TCR 0x 01F8 0088
Gene ral Purpose Timer <Scaler> Register GP TSR 0x 01F8 008C
Timers Control Register TIMC TR 0x 01F8 0098
Gene ral Purpose Inter face Configurati on Regis ter GPICNFR 0x 01F8 00A8
Gene ral Purpose Interface Dat a Register GPID ATR 0x 01F8 00AC
UAR T ’A’ Rx & Tx Regi ster UAR TAR 0x 01F8 00E0
UAR T ’B’ Rx & Tx Register UAR TBR 0x 01F8 00E4
UAR T Status Register UAR TSR 0x 01F8 00E8
Table 3. System Registers Address Map (Continued)
System Register Name Address
8TSC695F 4118J–AERO–08/04
Exte nded I/O and the Extended General areas.
EDAC The TSC695F includes a 32-bit EDAC (Error Detection And Correction). Seven bits
(CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signa l (DP AR)
is use d to ch eck and gene rate the odd pari ty over the 32-bit data bus. This mean s that
altoget her 40 bits are used when the EDAC is enabled.
The TSC695F EDAC uses a 7-bit Hamm ing code which detects a ny dou ble bit error on
the 40-bit bus as a non-c orrectable error. In addition, the EDAC detects all bits stuck -at-
one and stuck-at-zero f ailure f or any nibble in the data word a s a non-correctable e rror.
Stuck-at-one and stuck-at-z ero for all 32 bits of the dat a word is also detected as a non-
correctable error.
Me m ory an d I/O P ari ty The TSC6 95F handles pari ty to wards memory and I/O in a specia l way. The proc essor
can be program m ed t o use no parity, only pa rity or p arity and E DA C prot ection t owards
mem ory and to use parity or no towards I/O. The signal used for the parity bit is DPAR.
Memory Redundancy Programming the Memory Configuration Register, the TSC695F provides chip selects
for two redundant mem ory banks for replacement of faulty banks.
Memory Access Pro tecti on • Unimplemented Areas - Acces s to all uni mplemented memory areas are handled by
the TSC695F and detecte d as illegal.
• RAM Write Access Protection - The TSC695F can be programme d to detect and
mask write acc esses in any part of the RAM. The protection scheme is enabled only
for data area, not for the instruction area. The program mab le write access
protection is based on two segments.
• Boot PROM Write Protection - The TS C695F support s a quali fied PROM write for
an 8-bit wide PROM and/or for a 40-bit wide PROM.
DMA
DMA Interface The TSC695 F supp orts Direct Memory Access (DMA). T he DMA unit requests access
to the p rocesso r bus by a sserting the DM A requ est sign al (DMAREQ ). When the DM A
unit receives t he DMAGNT s ignal in response, the processor bus is granted. In case the
processor is in the po wer-down mod e the processor is pe rmanent tri-stated, and a
DMAREQ will direc t ly g iv e a DM AGNT. The TSC695F includes a DMA session time-out
funct ion.
Bus Arbiter The TSC695F always has the lowest priority on the system bus.
Traps A trap is a vectored t ransfer of control to the supervisor through a special trap table that
contain s the first four instructi ons of e ach trap h andler. The base addres s of the table is
es tabli shed by supe rviso r and t he di splace men t, w ithin th e tab le, is de term ine d by th e
trap type. Two categories of traps can appear.
9
TSC695F
4118J–AERO–08/04
Synchronous Traps
Tab le 4. Sy nchronous Traps
T rap Priority T rap Type (tt) Comments
Reset 1 –
Sources: SYSRESET* pin
software reset
watchdog reset
IU or System err or reset
Hardwar e Error
Non-restartable, imprecise
error
2
2.1 64h Severe error requiring a re-boot
TSC695F enters (if not masked) in halt or res et mode
Non-restartable,
precise error 2.2 62h Error not removable, PC & nPC OK
TSC695F enters (if not masked) in halt or res et mode
Register fil e error 2.3 65h Special case of non-r estart able, pre cise error.
TSC695F enters (if not masked) in halt or res et mode
Restartable, late error 2.4 63h Retryi ng instruction but PC & nPC have to be re-adju sted
TSC695F enters (if not masked) in halt or res et mode
Restartable,
precise error 2.5 61h Retrying instruction
TSC695F enters (if not masked) in halt or res et mode
Instruction access
(Err o r on in s tru c ti on fe tc h )3 01h
Pa ri ty erro r o n co n t ro l bu s
Pa ri ty erro r o n d ata bu s
Parity error on address bus
Access to protected or uni m plement ed area
Uncorrectable error in memory
Bus time out
Bus error
Illegal Instruction 4 02h
–
Privileged instruction 5 03h
–
FPU disabled 6 04h
–
Window
Overflow
7
05h During SAVE instr uction or trap tak en
Underflow 06h During RESTORE instruction or RETT instruction
Memory address not aligned 8 07h
–
FP U exception
Non - r e star t a ble e rror
9
9.1
08h
Severe error, cannot restart the instr uction
Data bus err or 9.2 Parity error on FPU data bus
Restartable error 9.3 Can be remo ved restarting the instru ction
Sequence er ror 9.4
–
Unimplemented FPop 9.5
–
IEEE exceptions: 9.6
Invalid oper ation
Division by zero
Overflow
Underflow
Inexact
10 TSC695F 4118J–AERO–08/04
It is possib le to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register
are cleared automatically when the interrupt is acknowledged.
By programming the Interrupt Shape Register, it is possible to define the external interrupts to either be active low or active
high and to def ine the external interrupts to either be edge or level sensitive.
Data access exception
(Er r or on da t a l o ad) 10 09h I dem “instruction access”
System register access vi olation
Tag overflow 11 0Ah TADDccTV and TSUBccTV instructions
Trap instruct ions 12 80h to FFh Trap on integer con dit ion codes (Ticc)
Tab le 4. Sy nchronous Traps (Continued)
T rap Priority T rap Type (tt) Comments
Tab le 5. Interrupts or Asynchronous Traps
Trap Priority Trap Type (tt) Comments
Watchdog time-out 13 1Fh Int ernal or externa l (EWDINT pin)
Externa l INT 4 14 1Eh EXTINTAK on only one of EXTINT[ 4:0]
Real time clock timer 15 1Dh
–
General purpose timer 16 1Ch
–
Externa l INT 3 17 1Bh EXTINTAK on only one of EXTINT[ 4:0]
Externa l INT 2 18 1Ah EXTINTAK on only one of EXTINT[ 4:0]
DMA time-out 1 9 19h
–
DMA access erro r 20 18h
–
UART Error 21 17h
–
Correctable error in memory 22 16h Data r ead OK but source not updated
UART B Data ready
Transmitter ready 23 15h
–
UART A Data ready
Transmitter ready 24 14h
–
External INT 1 25 13h EXTINTAK on only one of EXTINT[ 4:0]
External INT 0 26 12h EXTINTAK on only one of EXTINT[ 4:0]
Ma s k e d h ar d w a re er ro rs 27 11h
Logical OR of:
IU hardware error masked
IU error mode masked
System hardware error masked
11
TSC695F
4118J–AERO–08/04
Timers In software d ebug mo de the timers are con trolled by a system register bit and the exter-
nal pin DEBUG.
General Purpose Timer The General Purpos e Timer (GPT ) prov ides, in add ition to a ge neralize d count er func-
tion, a mechanis m for setting the step size in which actual time counts are performed.
GP T is clocked by th e internal system clock. Th ey are possible to progra m to be e ither
of si ngle-sho t type or periodic al type and i n both ca ses gen erate an int errupt when the
delay time ha s elapsed. The current value of the scaler and coun ter of the GPT can be
read.
Real Time Clock Timer The only functional differences between the two timers are that the Real Time Clock
Timer (RTCT) has an 8-bit scaler (16-bit scale r f or GPT) and that the RTCT interrupt has
higher priority than t he GPT interrupt.
RTCT information is available on RTC output pin.
Watchdog Timer Setting the external pin IWDE to VCC enables the internal watc hdog timer. Otherwise the
watchdog function must be externally provided.
The watchdog is supplied from a separate external input (WDCLK). After reset, the timer
is enabled and starts running with the maximum range. If the timer is not refreshed
(reprogrammed) bef ore the counter reaches zero value, an interrupt is sent. Simulta-
neously, the timer starts counting a reset time-out period. If the timer is not
acknowledged before the reset time-out peri od elapses, a reset is applied t o TSC695F.
UARTs Two full duplex asynchronous rec eiver transmitters (UART) are included. In software
debug mo de the UART’s are controlled by system register bits.
The data format of the UART’s is eight bits. It i s possible to choose between even or odd
parity, or no parity, and between one and t wo stop bits. The UART’s provide double buf f-
ering, i.e. each UART co nsists of a transmitter holding reg ister, a receiver holding
register, a trans mitter shift register, and a rece i ver shift register. Each o f these regi sters
are 8-bit wide. For each UART a RX and TX Register is provided. The UART’s generate
an in terrupt each time a byte ha s been received or a byte has been sent. There is
another interrupt to indicate errors.
The baud rate of both the UART’s is programmable. The clock is derived either from the
system clock or can use the watchdog clock.
General Purpose Interface The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be config-
ured as an input or an output.
A fa lling or rising edg e detect ion is made on each selecte d GP I inpu ts. Every input tran-
sition on GPI generat es an external positive pulse on GPIINT pin of two SYSCLK width.
Execution Modes
Reset Mode Rese t mode is entered when:
– The SYSRES input is assert ed
– Software reset which is caused by the so ftware writing to a Softw are Reset
Register
– Watchdog reset which is caused by a Watchdog c ounter time-out
– Error reset which is caused by a hardware parity error
12 TSC695F 4118J–AERO–08/04
This RESET output h as a minimum of 1024 SYSCLK width to allow the usage of Flash
memories.
The error and Reset Status Register contain the source of the last processor reset.
Run Mo de In this mode the IU/FPU is executing, while all peripherals are running (if software
enabled).
System Halt Mode System Halt mode is entered when the SYSHALT inpu t is asserted . In this mode, the IU
and FPU are frozen, while the timers (includeing the inter nal watchdog timer) an d
UART’ s are stopped.
Power Down Mode This mode is en tered by writing to the P ower-down Reg is ter. In this mod e, the IU and
FP U are froz en. T he TSC6 95 F leav es the pow er-d own m ode if an exter nal in terrup t is
asserted.
Error Halt Mode Error Halt mode is ent ered under the following ci rcumstances:
– A internal hardware parity error .
– The IU enters err or mode.
The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET.
Error Ha ndler The TSC695F has one error output s ignal (SYSERR) which indicates that an unmasked
error has occurred. Any error signalled on the error inputs from the IU and the FPU is
latch ed and reflected in the E rror a nd Reset Status Re gister. By defaul t, an error le ads
to a processor halt.
Parity Checking The TSC695F includes:
– Parity checking and generation (if required) on the external d ata bus
– Parity checking on the external address bus
– Parity checking on ASI and SIZE
– Parity checking and generat ion on all system registers
– Parity generation and checking on the internal control bus to the IU
All external parity checking can be disabled using the NOPA R signal.
Syst em Clock The TSC695F uses CLK2 clock input directly and creates a system clock signal by
dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the appli-
cation. It is highly recommended that only SYSCLK rising edge is used as reference as
far as possible.
Syst em A v ailab ility The SYSAV bit in the Error and Reset Status R egist er can b e u se d by sof tw are to in di-
cate system avail ability.
Test Mode The TSC695F includes a number of software test facilitie s such as ED AC test, Parity
test, In terrupt test, Er ror test and a sim ple Test A ccess Port. Th ese test fu nctions ar e
controlled using the Test Control Register.
13
TSC695F
4118J–AERO–08/04
Te st an d D iag no st ic
Hardware Functi ons A v ari ety o f TS C695F tes t and diagnostic hard ware f unc tions, including boundary scan,
internal scan, clock control and On -chip Debugger, are controlled through an IEEE
1149. 1 (JTAG) standard Test Access Port (TAP).
Test Access Port The TAP interfaces to the JTAG bus v ia 5 dedicated pins on the TS C695F chip . Th ese
pins are:
• TCK (input): Test Clock
• TMS (input): Test Mode Select
• TDI (input ): Test Dat a Input
• TDO (output): Test Data Output
•TRST
(input): Test Reset
Instruction Register Five standard instructions are supported by the TSC695F TAP.
Debugging The design is highly testa ble with the support of an On-Chip Debugger (O CD), an inter-
nal and boundary scan through JTAG interface.
Binary Value Name of Instruction Data Register Scan Chain Accessed
00. 0000 EXTEST Boun dary Scan
Register Boundary scan chain
00. 0001 SAMPLE/PRELO AD Boundary Scan
Register Boundary scan chain
00. 0011 INTEST Boundary Scan
Register Boundary scan chain
11. 1111 BYPASS Bypass Register Bypass register
10. 0000 IDCODE Device ID Register ID register scan chain
14 TSC695F 4118J–AERO–08/04
Electrical Characteristics
Ab solu te Maximum Rati ngs
DC Characteristics
Military Range............................... ................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Su pply Voltag e..... .......... .. .......... .. .......... ... .. ..... ..-0. 5V to +7.0 V
Input Voltage....... ..... .. ..... .. .......... .. ........ .. ..... ......- 0.5V to +7.0V
Note: Stresses at or above those listed under “Absolute
Maxim um Ra ti ngs” may cause pe rmanent damage to the
device. This is a stress rati ng only and functional operation
of the device at th ese or any other condi tions above those
indicated in the operational sections of this specification is
not impl ied. Exposure to absolute maxim um rat ing
conditions may affect device reliability.
Tab le 6. DC Characteristics at VDD 5V ± 10%
Symbol Parameter Min Typ Max Unit Test Conditions
VIL trigger Input Low Voltage
for trigger input –– 0.8 V V
CC = 4. 5 to 5.5V
VIH trigger Input High Voltage
for trigger input 3.0 – – V VCC = 4.5 to 5.5V
∆VT Input Hy s teresis
for trigger input –0.9 – V V
CC = 4. 5 to 5.5V
VIL TTL Input Low Vo ltage
for TTL input –– 0.8 V V
CC = 4. 5 to 5.5V
VIH TTL Input High Voltage
for TTL input 2.2 – – V VCC = 4.5 to 5.5V
VOL400 pF Output Low Volt age
for 400 pF buffer –0.3 0.4 V VCC = 4.5 to 5. 5V
IOL = 12 mA
VOH400 pF Outp ut Hi gh Voltage
for 400 pF buffer 2.4 0.3 – V VCC = 4.5 to 5.5V
IOH = -16 m A
VOL150 pF Output Low Volt age
for 150 pF buffer –0.3 0.4 V VCC = 4.5 to 5. 5V
IOL = 4 mA
VOH150 pF Outp ut Hi gh Voltage
for 150 pF buffer 2.4 4.3 – V VCC = 4.5 to 5.5V
IOH = -6 mA
IccOP Operati ng Supply Current
for core processor
––230
mA
VCC = 5. 5V, f = 2 5 MH z
––210 V
CC = 5. 5V, f = 2 0 MH z
––170 V
CC = 5. 5V, f = 1 0 MH z
IccPD Power Down Supply Curren t
for core processor
–– 41
mA
VCC = 5.5V, f = 25MHz
–– 38 V
CC = 5. 5V, f = 2 0 MH z
–– 30 V
CC = 5. 5V, f = 1 0 MH z
15
TSC695F
4118J–AERO–08/04
Cap a cit a n ce Ratings
AC Characteristics
Parameter Description Max
CIN Input Capacitance 7 pF
COUT Output Capacitance 8 pF
CIO Input/Output Capaci tance 8 pF
Tab le 7. AC Charact e r i stics (SYSCL K Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V
Parameter Min
(ns) Max
(ns) Comment Reference Edge
t1 20 – CLK2 period –
t2 40 – SYSCLK period –
t3 9.75 – CLK2 high and low pulse width –
t4 – 6.5 RA(31:0) RAPAR RSIZE RLDSTO output delay SYSCLK+
t5 – 12. 5 MEMCS*(9: 0) ROMCS* EXMCS* output delay SYSCLK+
t6 – 15 DDIR DDI R* out put delay SYSCLK+
t7 – 23.5 MEMW R* IOW R *output delay
formula: 13.5 ns + 1/4 t2 SYSCLK- or SYSCLK+
t8 – 20.5 OE* HL output del ay
formula: 10.5 ns + 1/4 t2 SYSCLK+
t9 t9_1 11.5 – Data setup time during load SYSCLK+
t9_2 9 – Data setup time during load NOPAR = 0 rpa = rec
= eith er 1 or 0 SYSCLK+
t10 5 – Data hold time during loa d SYSCLK+
t11 – 28 Data output delay SYSCLK-
t12 8 – Data output valid to HZ – guaranteed by design SYSCLK+
t13 – 19 CB output delay SYSCLK+
t14 – 13 ALE* output del ay SYSCLK-
t15 – 21 BUFFEN* HL out put delay
formula: 11 ns + 1/4 t2 SYSCLK+
t16 – 15 MHOLD* out put delay – guarante ed by design SYSCLK+
t17 – 15 MDS* DRDY* output delay SYSCLK+
t20 – 15 MEXC* output del ay SYSCLK-
t21 10 – RASI(3:0) RSIZE(1:0) RASPAR setup time SYSCLK+
t22 3 – RASI(3:0) RSIZE(1:0 ) RASPAR hol d time SYSCLK+
t23 – 13 BOOT PROM address output delay SYSCLK+
16 TSC695F 4118J–AERO–08/04
t24 12 – BUSRDY* setup time SYSCLK+
t25 0 – BUSRDY* hold time SYSCLK+
t27 – 15 I O SEL output delay SYSCLK+ HL
SYSCLK- LH
t28 12 20 DMAAS setup ti me
for mu la of max: 1/2 t2 SYSCLK+
t29 0 20 DMAAS hold ti me
for mu la of max: 1/2 t2 SYSCLK-
t30 12 – DMAREQ* set up ti me SYSCLK+
t31 – 15 DMAGNT* out put delay SYSCLK+
t32 10 – RA(31:0) RAPAR CPAR setup time SYSCLK+
t33 3 – RA(31:0) RAPAR CPAR hold time SYSCLK+
t36 100 – TCK period -
t37 10 – TMS setup time TCK+
t38 4 – TMS hold time TCK+
t39 10 – TDI setup time TCK+
t40 10 – TDI hold time TCK+
t41 – 20 TDO output delay TCK-
t46 – 22 INULL output delay SYSCLK+
t48 – 22 RESET* CPUHALT* output delay SYSCLK+
t49 – 20 SYSERR* SYSAV output delay SYSCLK+
t50 – 20 IUERR* output delay SYSCLK+
t52 12 – EXTINT(4:0 ) setup time SYSCLK-
t53 0 – EXTINT(4:0 ) hol d ti me SYSCLK+
t54 – 15 EXTINTACK o utput delay SYSCLK+
t56 – 8.5 OE* LH output delay (no DMA mode) SYSCLK+
t57 – 9 BUFFEN* LH output del ay SYSCLK+
t60 – 22 INST output del ay SYSCLK+
t61 20 – Data output delay to low-Z – guaranteed by design
formula: 10 ns + 1/4 t2 SYSCLK+
t80 12 BUSERR* setup time SYSCLK+
t81 0 64 BUSERR* hold time
formula: 24 ns + t2 SYSCLK+
Tab le 7. AC Charact e r i stics (SYSCL K Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V (Continued)
Parameter Min
(ns) Max
(ns) Comment Reference Edge
17 TSC695F 4118J–AERO–08/04
Figu re 3. 150 pF Buff er Respons e (Data from simulat i on)
18 TSC695F 4118J–AERO–08/04
Figu re 4. 400 pF Buff er Respons e (Data from simulat i on)
19
TSC695F
4118J–AERO–08/04
Figu re 5. OE*/400 pF Buffer Response (Data from simulation)
20 TSC695F 4118J–AERO–08/04
Timing Diagrams
Figu re 6. RAM Fetch, RAM Load and RAM St ore Seq uence - n Waitstates for Read, m Waitstates for Write
1 (RAM fetch) 2 (RAM load) 3 (RAM fetch) 4 (RAM store) 5 (RAM fetch)
t17t17t17t17t17t17t17
t16t16
t60t60t60t60
t12t13t61
t12
t11
t61
t12
t11
t61
t8t56t56t8
t7t7
t6t6
t5t5
t5t5
t14t14
t4_1t4_1t4_1t4_1
n wsn wsm wsm wsn wsn wsn wsn wsn wsn ws
t10
t9
t10
t9
t10
t9
t2t2
t3t3t3t3t1t1
FA1 FA2LA1 SA1 FA3
FD1 LD1 FD2 SD1 FD3
FP1 LP1 FP2 SP1 FP3
FC1 LC1 FC2 SC1 FC3
previous stored checkbyte
previ ous stored dat a
previous stored parity
CLK2
SYSCLK
RA [31:0]
ALE
MEMC S * [0]
MEMCS* [1]
ROMCS*
DDIR
MEMWR*
BUFFEN*
OE *
D [31:0]
DPAR
CB [6:0]
INST
MHOLD*
MDS*
21
TSC695F
4118J–AERO–08/04
Figu re 7. RAM “Atomic-load-store” byte Sequence - 0 Waitstate
1 (RAM fetch) 2 (RAM atomic load store) 3 (RAM fetch)
t4_2t4_2
t4_1t4_1
t46t46
t16t16
t60t60
t12t13
t61
t12t11
t61
t12t11
t61
t8t56t8t56t8
t7t7
t6t6t6t6
t5t5
t5t5
t4_1t4_1
t10
t9
t10
t9
t10
t9
t10
t9
t10
t9
t10
t9
t2t2
FA1 ALSA
FD1 byte from RAM word from RAM word to RAM
FA5
FP1 FP5
FD5
FC1 FC5
held to update the full word
parity from RAM
checkbyte from RAM
parity to RAM
checkbyte to RAM
parity from RAM
checkbyte from RAM
SYSCLK
RA [31:0]
ALE*
MEMCS* [0]
MEMCS* [1]
DDIR
MEMWR*
BUFFEN*
OE*
D [31:0]
DPAR
CB [6:0]
INST
MHOLD *
MDS*
INULL
RLDSTO
LOCK
22 TSC695F 4118J–AERO–08/04
Figu re 8. RAM Load-double and RAM Store-double Sequence - 0 Waitstate
1 (RAM fetch) 2 (RAM double loa d) 3 (RAM fetch) 4 (RAM double store) 5 (RAM fetch)
t4_2t4_2
t46t46
t16t16
t60t60
t12t13t13t61
t12t11t11t61
t12t11t11t61
t8t56t8t56t8
t7t7t7t7
t6t6
t5t5t5t5
t5t5t5t5
t4_1t4_1t4_1t4_1t4_1t4_1
t10t9
t10t9
t10t9
t2t2
FA1 LA1 LA2 FA2 SA1 SA2 FA3
FD1 LD1 LD2 FD2 SD1 SD2 FD3
FP1 LP1 LP2 FP2 SP1 SP2 FP3
FC1 LC1 LC2 FC2 SC1 SC2 FC3
SYSCLK
RA [31:0]
ALE*
MEMCS* [0]
MEMCS* [1]
DDIR
MEMW R*
BUFFEN*
OE*
D [31:0]
DPAR
CB [6:0]
INST
MHOLD*
MDS*
INULL
LOCK
23
TSC695F
4118J–AERO–08/04
Figu re 9. RAM Load with Correctable Error - 0 Waitstate
1 (RA M fetc h) 2 (RAM load correctable data) 3 (RAM fetch) 4 (RAM fetch)
t60t60
t17t17
t16
t16
t8t56t56t8
t5t5
t5t5
t4_1t4_1t4_1
t14t14
internal error correcti oninte rnal erro r correctionloadload
t10t9t10t9
t2t2
FD1 LD1 FD2 FD2 FD3
FA1 LA1 FA2 FA3
FC1 LC1 FC2 FC2 FC3
FP1 LP1 FP2 FP2 FP3
1-bit error on 40-bit data
SYSCLK
ALE*
RA[31-0]
MEMCS*[0]
MEMCS*[1]
DDIR
MEM WR *
IOWR*
OE*
BUFFEN*
D[31-0]
CB[6-0]
DPAR
MHOLD*
MEXC*
MDS*
INST
INULL
data correction
made inside
24 TSC695F 4118J–AERO–08/04
Figu re 10. RAM Load with Uncorrectable Error - 0 Waitstate
1 (RAM fetch) 2 (RAM load) 3 (RAM fetch) 4 (null cycle) 5 (RAM fetch) 6 (RAM fetch)
t46t46
t60t60t60t60
t17t17
t20t20
t16
t16
t56t8t56t8
t5t5
t5t5
t4_1t4_1t4_1t4_1
t14t14
traptrapexceptionint ernal err or detect i o nint ernal err or detect i o nloadload
t10
t9
t10
t9
t2t2
FA1 LD1 FA2 FA3 TA1 TA2
FD1 LD1 FD2 FD2 FD2 FD3 TD1 TD2
2-bit error on 40-bit data
FC1 LC1 FC2 FC2 FC2 FC3 TC1 TC2
FP1 LP1 FP2 FP2 FP2 FP3 TP1 TP2
SYSCLK
ALE*
RA[ 31-0]
MEMCS*[0]
MEMCS*[1]
DDI R
MEMWR*
IOWR*
OE*
BUFFEN*
D[31-0]
CB[6 -0]
DPA R
MHOLD*
MEXC*
MDS*
IN ST
IN U LL
25
TSC695F
4118J–AERO–08/04
Figu re 11. RAM Load with Unimplement ed Area Access - 0 Waitstate
1 (RAM fet ch) 2 (RAM load) 3 (RAM fetch) 4 (null cycle) 5 (RAM fetch) 6 (RAM fetch)
t46t46
t60t60t60t60
t17t17
t20t20
t16t16
t56t8t8t56
t5t5
t4_1t4_1
traptrapfetchfetchinternal errorinternal error
t10t9t10t9
t2t2
unimplemented address
FA1 LA1 FA2 FA3 TA1 TA2
no dataFD1 FD2 FD3 TD1 TD2
SYSCLK
ALE*
RA[31-0]
MEMCS*[0]
MEMCS*[1]
DDIR
MEMW R *
IOWR*
BUFF EN*
OE*
D[31-0]
MHOLD*
MEXC*
MDS*
INST
INULL
26 TSC695F 4118J–AERO–08/04
Figu re 12. I/O Store Sequence with BUSRDY* and n Waitstates (Timing for 0 Waitstate = Timing for 1 Waitstates)
1 (RAM fetch) 2 (i/o store) 3 (RAM fetch)
t16t16
t60t60
t12t11
t61
t8t56
t57t15
t7t7
t6t6
t27t27
t5t5
t4_1t4_1t4_1
end of cyclerdy waiting(n-1) ws
start of cycle
t10
t9
t25
t24t24
t2t2
FA1 SA1 FA2
FD1 FD2SD1
previous stored data
SYSCLK
ALE*
RA[31-0]
MEMCS*[0]
IOS EL *[0]
BUSRDY*
DDIR
MEMWR*
IOWR*
BUFFEN*
OE*
D[31-0]
INST
MHOLD*
MDS*
27
TSC695F
4118J–AERO–08/04
Figu re 13. I/O Load Sequence with BUSRDY* and n Waitstates (T iming for 0 ws = T i m ing for 1 ws)
1 (RAM fetch) 2 (i/o load ) 3 (RAM fetch)
t17t17
t16t16
t60t60
t8t56t8t56
t57t15
t27t27
t5t5
t4_1t4_1
t14t14
end of cyc leend of cyc lerdy waitingrdy waiting(n-1) w s
start of cycle
t10t9
t10
t9
t25
t24t24
t2t2
FA1 LA1 FA2
FD1 FD2LD1
data driv en by ext ern al buffers (c.f BUFFEN *)
SYSCLK
ALE*
RA[31-0]
M E MC S* [0]
IOSEL*[0]
BUSRDY*
DDIR
MEMWR*
IOWR *
BUFFEN*
OE*
D[31-0]
INST
MHOLD*
MDS*
28 TSC695F 4118J–AERO–08/04
Figu re 14. EXCHANGE RAM Store with BUSDRY* and n W a i tstates
1 (RAM fetch) 2 (xchgRA M sto re) 3 (RAM fetch)
t16t16
t60t60
t12t11t61
t8t56
t57t15
t7t7
t7t7
t6t6
t5t5
t5t5
t4_1t4_1
end of cycleend of cycl en wsn wsin betweenin betweenrdy wait ingrdy wait ingstar t of cyclestar t of cycle
t25
t24t24
t2t2
prev io us sto red data
FA1 SA1 FA2
FD1 SD1 FD2
SYSCLK
ALE*
RA[31-0]
MEMCS*[0]
EXMCS*
DDIR
MEMWR*
IOWR*
BUFFEN*
OE*
BUSRDY*
D[31-0 ]
INST
MHOLD*
MDS*
t24 t25
29
TSC695F
4118J–AERO–08/04
Figu re 15. EXCHANGE RAM Load with BUSDRY* and n Wai tstates
1 (RAM fetch) 2 (xchgRAM load) 3 (RAM fetch)
t17t17
t16t16
t60t60
t8t56
t57t15
t5t5
t5t5
t4_1t4_1
t14t14
end of cycleend of cyclen wsn wsrdy waitingrdy waitingstart of cyclestart of cycle
t10t9
t25t24t24
t2t2
FA1 LA1 FA2
FD1 LD1 FD
2
data driven by external buffers (c.f BUFFEN*)
SYSCLK
ALE*
RA[31-0]
MEMCS*[0]
EXMCS*
DDIR
MEMWR*
IOWR*
BUFFEN*
OE*
BUSRDY*
D[31-0]
INST
MHOLD*
MDS*
t25
t24
30 TSC695F 4118J–AERO–08/04
Figu re 16. 8-bit BOOT PROM Fetch (or Load Word) - n Waitstates
1 (ROM fetch) 2 (8-bit ROM fetch or load word) 3 (ROM fetc
h)
t17t17t17
t16t16t16
t60t60
t8t56t8
t15t57t15
t5t5t5
t23t23t23t23
t4_1t4_1
t4_1t4_1
t4t14
(n-1) ws end of
by te 3
(n-1) ws(n-1) ws by te 3byte 2
(n-1) ws(n-1) ws by te 2byte 1
(n-1) ws(n-1) ws byte 1byte 0
(n-1) ws
byte 0
start of
t10t10 t9
t10 t9
t10 t9t9
t2t2
01230
10
(address mod. 4)
FD2-0 FD2-1 FD2-2 FD2-3
data driven by external buffers (c.f BUFFEN*)
FA2
(1 = fetch, 0 = load word)
FA1 FA2
SYSCLK
ALE*
RSIZE[0,1]
RA[31-0]
BA[0,1]
ROMCS *
MEMCS*[0]
DDI R
MEM WR *
BUFFEN*
OE*
D[31-8]
D[7-0]
INST
MHOLD*
MDS*
cycle cycle
31
TSC695F
4118J–AERO–08/04
Figu re 17. 8-bit BOOT PROM 2x Store byte - n Wai tsta te
1 (RAM fetch) 2 (8-bit ROM write) 3 (RAM fetch) 4 (8-bit ROM write) 5 (RAM fetch)
t16t16t16t16
t60t60t60
t12t11
t61
t12t11
t61
t56t8t56
t57t15t57t15
t7t7t7t7
t6t6t6t6
t5t5t5t5
t5t5t5t5
t4_1t4_1t4_1t4_1
t23t23
t4_1t4_1t4_1t4_1
(n-1) ws(n-1) ws
start of
(n-1) ws(n-1) ws
start of
t9t9
t2t2
addr.=mo d. 4 addr.= m od. 4 +1
byte D[7:0]
00 01
10 00 0010 10
byte D[7:0]
00
FA1 SA1 FA2 SA2 FA3
FD1SD1FD2SD2
SYSCLK
ALE*
RA[31-0]
BA[0,1]
RSIZE[0,1]
MEMCS*[0]
ROMCS*
DDIR
MEMWR*
IOWR*
BUFFEN*
OE*
D[31-0]
INST
MHOLD*
MDS*
cyclecycle
32 TSC695F 4118J–AERO–08/04
Figu re 18. DMA RAM load wit h or without Correct abl e Error and DMA RAM Store - 0 Wait st ates
1 (R AM fetch)2 (RA M fe tch) 3 (DMA session) 4 (RAM fetch)5 (RAM fetch
)
t16t16
t13t13
t13t13t12t11
t12t11
t6t6
t7t7
t56t8t56t8
t17t17t17t17
t5t5t5t5t5
t31t31
t31t31
t31t31
t4_1t4_1t4_1
t4_1t4_1t4_1
t4_1
t4_1t4_1
t14t14t14t14
cont'lead-outnth DMA store (0 ws)(0 cycle min) nth DMA store (0 ws)1st DMA load (0 ws)(0 cycle min) 1st DMA load (0 ws)lead-inlead-in(nu ll cy c le )
t10
t9
t10
t9
t10
t9
t10
t9
t10
t9
t10
t9
t10
t9t10t9
t10
t9
t10
t9
t33
t32
t33
t32
t33
t32
t33
t32
t29t28t29t28
t30t30
t22
t21
t22
t21
t22
t21
t22
t21
t33
t32
t33
t32
t2t2
FA1 (held to the end of RAM access)
FD1 D LD1
FA2 D SAn FA2
FD2
FA3
(from RAM) D LD1
(from TSC695F)
D LA1
FC1 D LC1 FC2
(from RAM)
FP1 D LP1 FP2
(from RAM) D LP1
(from TSC695F)
FS1 FS2 D SSn FS2 FS3D LS1
FZ1 FZ2 1 0 FZ2 FZ31 0
(on ly word access) early time for DMAREQ* desass ertion
(held to th e end of RAM access)
Parity generated by T SC695F if dpe =1,
else, same timing as D[31-0]
D SDn
DSPn
D SCn
(pull-up on WE*)
SYSCLK
ALE*
RA[31-0]
RASI[3-0]
RSIZE[1-0]
DMAREQ*
DMAGNT*
DMAAS
RD
WRT
MEMCS*[ 9-0]
DRDY*
OE*
MEMWR*
DDIR
D[31-0]
DPAR
CB[7-0]
MHOLD*
(held to th e end of RAM access)
(only word access)
cor rect ed dat a if ne ed ed
corrected parity if needed
33
TSC695F
4118J–AERO–08/04
Figu re 19. Edge Triggered I nterrupt Timing
FA(-1) FA0 FA1 FA2 FA3 FA4 TTA0 TTA1 TSA0 TSA1 TSA2
FD(-1) FD0 FD1 FD2 FD3 FD4 TD0 TD1 TSD0 TSD1
t54t54
TakenTaken
PrioritizedPrioritized
LatchedLatched
SampledSampled
t53t52
SYSCLK
RA[31:0]
ALE*
D[31:0]
INULL
EXTINT[i]
EXTINTACK
34 TSC695F 4118J–AERO–08/04
Figu re 20. Halt T i ming
FAn-1 FAn FAn+1 FAn+1 FAn+2
09H 09H 09H 09H 09H
10 10 10 10 10
FDn-1 FDn FDn+1 FDn+2
t48t48
t49t49
t16t16
t14t14
SYSCLK
RA[31:0]
RASI[3:0]
RSIZE[1:0]
ALE*
SYSHALT*
MHOLD*
SYSAV
CPUHALT*
D[31:0]
35
TSC695F
4118J–AERO–08/04
Figu re 21. External Error with Halt Timing
FAn-1 FAn
FAn+1
09H 09H 09H
10 10 10
FDn-1
FDn
t48
t49
t16
t49
t50t50
t14
SYSCLK
RA[31:0]
RASI[3:0]
RSIZE[1:0]
ALE*
IUERR*
SYSERR*
MHOLD*
SYSAV
CPUHALT*
D[31:0]
36 TSC695F 4118J–AERO–08/04
Figu re 22. Reset Timing
FA n FA n+1 0H 4H 8H
t48t48
t47t46
t14t14
SYSCLK
SYSRESET*
RA[31:0]
RASI[3:0]
RSIZE[1:0]
ALE*
INULL
RESET*
37
TSC695F
4118J–AERO–08/04
Figu re 23. External Error sign aling with BUSERR* and BUSRDY *
t20
t80t81t80
t24
SYSCLK
B
USRDY*
B
USERR*
MEXC*
38 TSC695F 4118J–AERO–08/04
Pac kag e Dra win g s
256-lead MQFP-F Package
39
TSC695F
4118J–AERO–08/04
256-lead MQF P-F Pin
Assignments Table 8. Pin Assignments
Pin Signal Pin Signal Pin Signal Pin Signal
1 GPIINT 65 D[0] 129 RA[0] 193 DXFER
2 GPI[7] 66 RSIZE[1] 130 VCCO 194 MEXC
3 VCCO 67 RSIZE[0] 131 VSSO 195 VCCO
4 VSSO 68 RASI[3] 132 RAPAR 196 VSSO
5 GPI[6] 69 VCCO 133 RASPAR 197 RESET
6 GPI[5] 70 VSSO 134 DPAR 198 SYSRESET
7 GPI[4] 71 RASI[2] 135 VCCO 199 BA[1]
8 GPI[3] 72 RASI[1] 136 VSSO 200 BA[0]
9 VCCO 73 RASI[0] 137 SYSCLK 201 CB[6]
10 VSSO 74 RA[31] 138 TDO 202 CB[5]
11 GPI[2] 75 RA[30] 139 TRST 203 VCCO
12 GPI[1] 76 VCCO 140 TMS 204 VSSO
13 GPI[0] 77 VSSO 141 TDI 205 CB[4]
14 D[31] 78 RA[29] 142 TCK 206 CB[3]
15 D[30] 79 RA[28] 143 CLK2 207 CB[2]
16 VCCO 80 RA[27] 144 DRDY 208 CB[1]
17 VSSO 81 VCCO 145 DMAAS 209 VCCO
18 D[29] 82 VSSO 146 VCCO 210 VSSO
19 D[28] 83 RA[26] 147 VSSO 211 CB[0]
20 VCCI 84 RA[25] 148 DMAGNT 212 ALE
21 VSSI 85 RA[24] 149 EXMCS 213 VCCI
22 D[27] 86 VCCI 150 VCCI 214 VSSI
23 D[26] 87 VSSI 151 VSSI 215 PROM8
24 VCCO 88 VCCO 152 DMAREQ 216 ROMCS
25 VSSO 89 VSSO 153 BUSERR 217 MEMCS[9]
26 D[25] 90 RA[23] 154 BUSRDY 218 VCCO
27 D[24] 91 RA[22] 155 ROMWRT 219 VSSO
28 D[23] 92 RA[21] 156 NOPAR 220 MEMCS[8]
29 D[22] 93 VCCO 157 SYSHALT 221 MEMCS[7]
30 VCCO 94 VSSO 158 CPUHALT 222 MEMCS[6]
31 VSSO 95 RA[20] 159 VCCO 223 MEMCS[5]
32 D[21] 96 RA[19] 160 VSSO 224 MEMCS[4]
33 D[20] 97 RA[18] 161 SYSERR 225 MEMCS[3]
34 D[19] 98 VCCO 162 SYSAV 226 VCCO
35 D[18] 99 VSSO 163 EXTINT[4] 227 VSSO
40 TSC695F 4118J–AERO–08/04
36 VCCO 100 RA[17] 164 EXTINT[3] 228 MEMCS[2]
37 VSSO 101 RA[16] 165 EXTINT[2] 229 MEMCS[1]
38 D[17] 102 RA[15] 166 EXTINT[1] 230 MEMCS[0]
39 D[16] 103 VCCO 167 EXTINT[0] 231 VCCI
40 VCCI 104 VSSO 168 VCCI 232 VSSI
41 VSSI 105 RA[14] 169 VSSI 233 OE
42 D[15] 106 VCCI 170 EXTINTACK 234 VCCO
43 D[14] 107 VSSI 171 IUERR 235 VSSO
44 VCCO 108 RA[13] 172 VCCO 236 MEMWR
45 VSSO 109 RA[12] 173 VSSO 237 BUFFEN
46 D[13] 110 VCCO 174 CPAR 238 DDIR
47 D[12] 111 VSSO 175 TXA 239 VCCO
48 D[11] 112 RA[11] 176 RXA 240 VSSO
49 D[10] 113 RA[10] 177 RXB 241 DDIR
50 VCCO 114 RA[9] 178 TXB 242 MHOLD
51 VSSO 115 VCCO 179 IOWR 243 MDS
52 D[9] 116 VSSO 180 IOSEL[3] 244 WDCLK
53 D[8] 117 RA[8] 181 VCCO 245 IWDE
54 D[7] 118 RA[7] 182 VSSO 246 EWDINT
55 D[6] 119 RA[6] 183 IOSEL[2] 247 TMODE[1]
56 VCCO 120 VCCO 184 IOSEL[1] 248 TMODE[0]
57 VSSO 121 VSSO 185 IOSEL[0] 249 DEBUG
58 D[5] 122 RA[5] 186 WRT 250 INULL
59 D[4] 123 RA[4] 187 WE 251 DIA
60 D[3] 124 RA[3] 188 VCCO 252 VCCO
61 D[2] 125 VCCO 189 VSSO 253 VSSO
62 VCCO 126 VSSO 190 RD 254 FLUSH
63 VSSO 127 RA[2] 191 RLDSTO 255 INST
64 D[1] 128 RA[1] 192 LOCK 256 RTC
Table 8. Pin Assi gnments (Continued)
Pin Signal Pin Signal Pin Signal Pin Signal
41
TSC695F
4118J–AERO–08/04
Ordering Information
Tab le 9. Pos sible Order Entries
Part-Number Supply Voltage Temperature
Range Maximum Speed
(MHz) Packa gin g Quality Flow
TSC695F-25MA-E 5V 25°C 25 MQF P-F256 Engineering Samples
TSC695F-25 MA 5V -55° t o +125°C 25 MQFP -F256 Standard Mil.
5962-0054001QXC 5V -55° to +125°C 25 MQFP-F256 QML-Q
5962-0054001VXC 5V -55° to +125°C 25 MQFP-F256 QML-V
5962R0054001VXC 5V -55° to +125°C 25 MQF P-F256 QMLV-RHA
951200301 5V -55° to +125°C 25 MQFP-F256 ESCC B
TSC695F -25 MB-E 5V 25°C 25 D ie Eng ineering Samples
5962-0054001Q9A 5V -55° to +125°C 25 Die QML-Q
5962-0054001V9A 5V -55° to +125°C 25 Die QML-V
Pr inted o n rec ycled paper.
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4118J–AERO–08/04 /xM
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