January 1983 EUROTECHNIQUE | ET9420/9421/9422 and ET9320/9321/9322 Single-Chip N-Channel Microcontrollers General Description Features The ET9420/9421/9422, ET9320/9321 and 9322 Single- Chip N-Channel Microcontrollers are fully compatible with the COPSfamily, fabricated using N-channel, silicon gate XMOS technology. They are complete microcomputers 1k x 8 ROM, 64x 4 RAM containing all system timing, internal logic, ROM, RAM 23 I/O lines (ET9420, ET9320) Low cost = 5 5 and I/O necessary to implement dedicated control func- > True vectored interrupt, plus restart a . 2 2 2 Powerful instruction set tions in a variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and 1/O scheme designed to facilitate keyboard input, display output and BCD data manipulation. The ET9421 is identi- cal to the ET9420, except with 19 1/0 lines instead of 23 : the ET9422 has 15 I/O lines. They are an appropriate Internal oinary counter register with MICROWIRE choice for use in numerous human interface control envi- compatible serial !/O capability ronments. Standard test procedures and reliable high- General purpose and TRI-STATE outputs density fabrication techniques provide the medium to . . large volume customers with a customized Controller @ TTLIGMOS compatible in and out Oriented Processor at a low end-product cost. @ LED direct drive outputs a a Three-level subroutine stack 4.0us instruction time Single supply operation Internal time-base counter for real-time processing The ET9320 is the extended temperature range version MICROBUS compatible of the ET9420 (likewise the ET9321 and ET9322 are the Software/hardware compatible with other members extended temperature range versions of the ET9421/ of ET9400 ET9422). The ET9326/9321/9322 are exact functional : / E d ET /9321 equivalents of the ET9420/9421/9422. BTM dO! Coe a gee ee cote ET9820/9821! COPS and MICROWIRE are trademarks of National Semiconductor Corp. TRI- STATE is a registered trademark of National Semiconductor Corp. Vec GND cK) cko | i { 1 TIME.BASE CLOCK COUNTER DIVIDER GENERATOR INSTRUCTION CLOCK (SYNCI ; RESET PROGRAM MEMORY liex 8 ROM ADDRESS IT ADDRESS DATAMEMORY -REG 64x 4 RAM ADDR iN O REGISTER o2 SUFFER oy" 4 Dg INSTRUCTION OECODECONTROL _-s To SKIP LOGIC so! MICROWIRE 1/0 S103 S102 S101 SI0g SERIAL | 0 REGISTER $1 4 8 4 Qa T9420/T9320 ONLY 2 : REGISTER 83 8 Ge G REGISTER & IL 4 BUFFER REG 2 L ORIVERS Gor 5 20 110 19 . INg* IN?" IN{* IND* Lp lp ty t4 Lz lz ty to * Not available on ET9322, ET9422. Figure 1. ET9420/9421/9422, ET9320/9321/9322 Block Diagram t Printed in FranceET9420/9421/9422 and ET9320/9321/9322 Absolute Maximum Ratings Voltage at Any Pin Operating Temperature Range ET9420/9421/9422 ET9320/9321 /9322 Storage Temperature Range Total Sink Current Total Source Current -0.3Vto+7V Package Power Dissipation 24 and 28 pin 0C to 70C , -40C to+85C = Package Power Dissipation -65C to +150C 20 pin 75mA 95mMA Lead Temperature (soldering, 10 sec.) 750 mW at 25C 400 mW at 70C 250mW at 85C 650 mW at 25C 300 mW at 70C 200 mW at 85C 300C Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical speciti- cations are not ensured when operating the device at absolute maximum ratings. ET9420/9421/9422 DC Electrical Characteristics oc < %] < 70C, 4.5V < Voc < 6.3V unless otherwise noted. Parameter Conditions Min. Max. Units Operation Voltage 4.5 6.3 Vv Power Supply Ripple Peak to Peak (Note 3) 0.4 Vv Supply Current Outputs Open 38 mA Supply Current Outputs Open, Voc = 5V, Ta = 25C 30 mA Input Voltage Levels CKI Input Levels Crystal Input Logic High Vec = Max. 3.0 Logic High Veco =5V+5% 2.0 V Logic Low -0.3 0.4 V TTL Input Voc = 5V+5% Logic High 2.0 Vv Logic Low -0.3 0.8 Vv Schmitt Trigger Inputs RESET, CKI (+4) Logic High 0.7 Voc Vv Logic Low -0.3 0.6 Vv SO Input Level (Test Mode) 2.0 3.0 Vv Ail Other Inputs Logic High Voc = Max. 3.0 Vv Logic High Veco = 8V+5% 2.0 Vv Logic Low -0.3 0.8 Vv Input Levels High Trip Option Logic High 3.6 Vv Logic Low -0.3 1.2 Vv Input Load Source Current Voc = 5V, Vin = OV CKO -4 -800 pA All Others -100 -800 uA Input Capacitance 7 pF Hi-Z Input Leakage Veco = 5V -1 +4 uA Output Voltage levels Standard Outputs TTL Operation Voc = 5V+5% Logic High lou =-100pA 2.4 V Logic Low lol = 1.6mA -0.3 0.4 Vv CMOS Operation Logic High lou =-10yA Vec -1 VET9420/9421/9422 DC Electrical Characteristics (Cont'd) 0C < Ta < 70C, 4.5V < Voc < 6.3V unless otherwise noted. Parameter Conditions Min. Max. Units Output Current Levels LED Direct Drive Output Voc = 6V Logic High Von = 2.0V 2.5 14 mA CKI Sink Current (R/C Option) Vin =3.5V 2 mA CKO (RAM Supply Current) VR =3.3V 3 mA TRI-STATE or Open Drain Leakage Current Veco = 5V -2.5 +2.5 pA Output Current Levels Output Sink Current (lo,) Voc =6.3V, Vo. = 0.4V 2.0 mA Veco = 4.5V, VoL =0.4V -1.0 mA Output Source Current (lox) Standard Configuration All Outputs Voc =6.3V, Voy = 3.0V -200 -900 pA Voc = 4.5V, Vou = 2.0V 100 ~500 pA Push-Pull Configuration SO, SK Outputs Voc =6.3V, Von = 3.0V -1.0 mA Veco = 4.5V, Vou =2.0V 0.4 mA TRI-STATE Configuration Ly-L7 Outputs Voc = 6.3V, Voy = 3.0V -2.0 mA Vec = 4.5V, Vou =2.0V -0.8 mA LED Configuration Lo-L7 Outputs Voc = 6.3V, Voy = 3.0V ~1.0 mA Voc = 4.5V, Vou =2.0V 0.5 mA Allowable Sink Current Per Pin (L, D, G) 10 mA Per Pin (Ali Others) 2 mA Per Port (L) 16 mA Per Port (D, G) 10 mA Allowable Source Current Per Pin (L) -15 mA Per Pin (All Others) -1.5 mAET9320/9321/9322 DC Electrical Characteristics -40c < 1, < +85C, 4.5V < Voc < 5.5V unless otherwise noted. Parameter Conditions Min. Max. Units Operation Voltage 45 5.5 Vv Power Supply Ripple Peak to Peak (Note 3) 0.4 Vv Supply Current Ta = 40C, Outputs Open 40 mA Input Voitage Levels CKI Input Levels Crystal Input Logic High 2.2 V Logic Low -0.3 0.3 V TTL Input Veco =5V 45% Logic High 2.2 V Logic Low -0.3 0.6 V Schmitt Trigger Inputs RESET, CKI (+4) Logic High 0.7 Vec V Logic Low -0.3 0.4 Vv SO Input Level (Test Mode) 2.0 3.0 V All Other Inputs Logic High Voc = Max. 3.0 Vv Logic High Veco = 5V +5% 2.2 Vv Logic Low -0.3 0.6 Vv Input Levels High Trip Option Logic High 3.6 Vv Logic Low -0.3 1.2 Vv Input Load Source Current Voc = 5V, Vin = OV CKO -4 -800 uA All Others -100 -800 uA input Capacitance 7 pF Hi-Z Input Leakage Veco = 5V -2 +2 uA Output Voltage levels Standard Outputs TTL Operation Veco = 5V 45% Logic High lon = 75 yA 2.4 Vv Logic Low lop =1.6mMA -0.3 0.4 Vv CMOS Operation Logic High lou =10pA Veco -1 Vv Logic Low lop = 10uA -0.3 0.2 Vv Output Current Levels LED Direct Drive Output Vec = 5V (Note 4) Logic High Vou = 2.0V 1.0 12 mA CKI Sink Current (R/C Option) Vin =3.5V 2 mA CKO (RAM Supply Current) VR =3.3V 4 mA TRI-STATE or Open Drain Leakage Current Veco = 5V -5 +5 uA Allowable Sink Current Per Pin (L, D, G) 10 mA Per Pin (Ail Others) 2 mA Per Port (L) 16 mA Per Port (D, G) 10 mA Allowable Source Current Per Pin (L) -15 mA Per Pin (All Others) ~1.5 mAAC Electrical Characteristics ET9420/9421 /9422 0C <Ta < 70C, 4.5V <Voc <.6.3V unless otherwise noted. ET9320/9321/9322 -40C < Ty < +85C, 4.5V < Vec < 5.5V unless otherwise noted. Parameter Conditions Min. Max. Units Instruction Cycle Time 4 10 us Operating CKI Frequency +16 mode 1.6 4.0 MHz +8 mode 0.8 2.0 MHz CKI Duty Cycle (Note 1) 40 60 % Rise Time Freq. = 4MHz 60 ns Fall Time Freq. = 4MHz 40 ns CKI Using RC (Figure 8c) +4 mode Frequency R=15k2+5%, C=100pF + 10% 0.5 1.0 MHz Instruction Cycle Time 4 8 us CKO as SYNC input (Figure 8d) tsync Figure 3a 50 ns Inputs: Sl tsetup 0.3 us tHotp 250 ns All Other Inputs tseTuP 1.7 us tHoLb 300 ns Output Propagation Delay Test Conditions: 300 ns RL =5kQ, GC, = 50 pF, Vout = 1.5V SO and SK teat 1.0 us todo 1.0 ys CKO / toas 0.25 us tpao 0.25 us All Other Outputs todt 1.4 us tpao 1.4 us MICROBUS Timing C_ = 100 pF, Vog = 5V 45% Read Operation (Figure 4) Chip Select Stable before RDtcsa 65 ns Chip Select Hoid Time for RDtracs 20 ns RD Pulse Widthter 400 ns Data Delay from RDtap 375 ns RD to Data Floatingtpr 250 ns Write Operation (Figure 5) Chip Select Stable before WRtcsw 65 ns Chip Select Hold Time for WRtwes 20 ns WR Pulse Widthtyy 400 ns Data Set-Up Time for WRtpw 320 ns Data Hold Time for WRtwop 100 ns INTR Transition Time from WRty, 700, ns Note 1: Duty cycle = tywy/(tws + two). Note 2: See Figure 9 for additional I/O characteristics. Note 3: Voltage change must be less than 0.5 volts in a 1ms period. Note 4: Exercise great care not to exceed maximum device power dissipation limits when direct driving LEDs (or sourcing similar loads) at high temperature.GNDq cKO CKI RESET ~4 l6 is 4u IN 1 IN2 Vcc L3 tt- aw Nn awn = 9 10 11 12 13 14 28 f- 00 27p-0t 26 P 02 25 p 03 24G3 23 p G2 22 (Gt 21 Ge 20 ING 19 p=ING 18 PSK 17 -so 16 FSI 1 LO Order Number ET 9420/N ET 9320/N Package N28A cno cko4 cKi~q RESET uo i is 4 vec iu .2 1 24 2 23 3 22 4 24 5 20 6 19 7 18 8 7 9 16 10 18 i) 14 12 13 bo poe [) 1 poe (92 pm 113 po 63 pee G2 pa ol po G0 pom SK p SO poe S| CKOS 3 20 b GND CKi 2 19 } 02 RESET +4 3 18 p= U3 ua 17 } G3 l645 16 - G2 is46 15 bp SK io4a7 14- So Vec 1 8 13} Si L319 12}- Lo L2 10 1p L1 Order Number ET 9421/N, ET 9321/N Package N24A Order Number ET 9422/N ET 9322/N Package N20A Figure 2. Connection Diagrams Pin Description Pin Description L7-Lo 8 bidirectional I/O ports with TRI-STATE* SK Logic-controlled clock (or general G3-Go 4 bidirectional VO ports purpose output) D3-Do 4 general purpose outputs CKI System oscillator input . CKO System oscillator output (or general IN3-!No oy purpose inputs (COP420/320 purpose input or RAM power supply) S| Serial input (or counter input) RESET System reset input so Serial output (or general purpose output) Voc Power supply GND Ground CK CLOCK IN3-INg, G3-Go, L7-Lg. ck0& Si INPUTS G3-Go, 03-Do, }-- INSTRUCTION CYCLE TIME (tc) *| tpot | SK (ASA vOn x tPDt > te < tPpo VoL | | f+ tseTuP-e{ |< HOLD X PULL KX L7~Lo, SO, SK OUTPUTS I tppo v Figure 3. Input/Output Timing Diagrams (crystal divide by 16 mode) WO CKt | km J tsynco cko \ \ (INPUT) L v Figure 3A. Synchronization Timing PLL so FP +] fe Figure 3B. CKO Output Timing(INQ) (IN 4) (L7-Lgi 07-09 ______________- Figure 4. MICROBUS' Read Operation Timing |e-tcSW | (N2) cs \ WW veoele eso! uN) WA \ tL} D7-Dy 2 Wl (Gg! INTR Figure 5. MICROBUS! Write Operation Timing Functional Description ET9420/9421/9422, ET9320/9321/9322 For ease of reading this description, only ET9420 and or ET9421 are referenced ; however, all such references apply equally to the ET9422, 9322, 9320 and/or ET9321, respectively. A block diagram of the ET9420 is given in figure 1. Data paths are illustrated in simplifieq form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used. When a bit is set, it is a logic 1" (greater than 2 volts). When a bit is reset, it is a logic "0" (less than 0.8 volts). Program Memory Programm Memory consists of a 1,024 byte ROM. As can be seen by an examination of the ET9420.'9421 instruction set. these words may be program instructions. program data or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID and LQID instructions. ROM must often be thought of as being organized into 16 pages of 64 words each. ROM addressing is accomplished by a 10-bit PC register. Its binary value selects one of the 1,024 8-bit words contained in ROM. A new adcress is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control instruction, the PC register is loaded with the next sequential 10-bit binary count value. Three levels of subroutine nesting are implemented by the 10-bit subroutine save registers, SA, SB and SC, providing a last-in, first-out (LIFO) hardware subroutine stack. ROM instruction words are fetched, decoded and exe- cuted by the Instruction Decode, Control and Skip Logic circuitry. Data Memory Data memory consists of a 256-bit RAM, organized as 4 data registers of 16 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1 of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected daia register. While the 4-bit contents of the selected RAM digit (M) is usually loaded into or from, or exchanged with, the A register (accumulator), it may also be loaded into or from the Q latches or loaded from the L ports. RAM addressing may aiso be performed directly by the LDD and XAD instructions based upon the 6-bit contents of the operand field of these instructions. The Bd register also serves aS a source register for 4-bit data sent directly to the D outputs. internal Logic The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory access operations. It can also be used to load the Br and Bd portions of the B register. to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L I/O port data and to perform data exchanges with the SIO register. A 4-bit adder performs the arithmetic and logic func- tions of the ET9420;9421, storing its results in A. It also outputs a carry bit to the 1-bit C register. most often em- ployed to indicate arithmetic overflow. The C register. in conjunction with the XAS instruction and the EN register, also serves to control the SK output. C can be outputted directly to SK or can enable SK to be a sync clock each instruction cycle time. (See XAS instruction and EN reg- ister description, below.) Four general-purpose inputs, IN3-INo. are provided; IN,, IN> and IN3 may be selected, by a mask-programmable option, as Read Strobe, Chip Select and Write Strobe inputs, respectively, for use in MICROBUS appili- cations. The D register provides 4 general-purpose outputs and is used as the destination register for the 4-bit contents of Bd. The G register contents are outputs to 4 general-purpose bidirectional !/O ports. Gg may be mask-programmed as an output for MICROBUS applications.The Q register is an internal, latched, 8-bit register, used to hold data loaded to or from M and A, as well as 8-bit data from ROM. Its contents are output to the L I/O ports when the L drivers are enabled under program control. (See LEI instruction). With the MICROBUS option selected, Q can also be loaded with the 8-bit contents of the L I/O ports upon the occurence of a write strobe from the host CPU. The 8 L drivers,when enabled, output the contents of - latched Q datato the L1I/O ports. Also, the contents of L may be read directly into A and M. As explained above, the MICROBUS option allows L I/O port data to be latched into the Q register. L I/O ports can be directly connected to the segments of a multiplexed LED display (using the LED Direct Drive output configuration option) with Q data being outputted to the Sa-Sg and decimal point segments of the display. The SIO register functions as a 4-bit serial-in/serial-out shift register or as a binary counter depending on the contents of the EN register. (See EN register description, below.) Its contents can be exchanged with A, allowing it to input-or output a continuous serial data stream. ~ SIO may also be used to provide additional parallel |/O by connecting SO to external serial-in/parallel-out shift registers. The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output of SKL; in the shift register mode, SK outputs SKL ANDed with the clock. The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register (EN3-ENo). 1. The least significant bit of the enable register, ENo, selects the SIO register as either a 4-bit shift register or a 4bit binary counter. With ENog set, SIO is an asynchronous binary counter, decrementing its value by one upon each low-going pulse (1 to 0) ocurring on the SI input. Each pulse must be at least two instruction cycles wide. SK outputs the value of SKL. The SO output is equal to the value of EN3. With ENo reset, SIO is a serial shift register shifting left each instruction cycle time. The data present at Sl goes into the least significant bit of SIO. SO can be enabled to output the most significant bit of SIO each cycle time. (See 4 below.) The SK output becomes a logic-controlled clock. 2. With EN, set the IN, input is enabled as an interrupt input. Immediately following an interrupt, EN, is reset to disable further interrupts. 3. With ENo set, the L drivers are enabled to output the data in Q to the L I/O ports. Resetting EN2 disables the L drivers, placing the L I/O ports in a high- impedance input state. 4. ENg, in conjunction with ENo, affects the SO output. With ENog set (binary counter option selected) SO will output the value loaded into EN 3. With ENo reset (serial shift register option selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting EN3 with the serial shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains reset to 0. The table below provides a summary of the modes associated with EN3 and ENo. Enable Register Modes Bits EN3 and ENg EN; ENo SIO so SK 0 0 Shift Register Input to Shift Register 0 If SKL= 1, SK = CLOCK lf SKL = 0,SK = 0 1 0 Shift Register Input to Shift Register Serial Out If SKL = 1,SK = CLOCK If SKL = 0, SK = 0 0 1 Binary Counter Input to Binary Counter 0 If SKL = 1,SK = 1 if SKL = 0, SK = 0 1 1 Binary Counter Input to Binary Counter 1 If SKL = 1,SK = 1 If SKL = 0, SK = 0Interrupt The following features are associated with the !N, interrupt procedure and protoco! and must be consi- dered by the programmer when utilizing interrupts. a. The interrupt, once acknowledged as explained below, pushes the next sequential program counter address (PC + 1) onto the stack, pushing in turn the contents of the other subroutine-save registers to the next lower level (PC +1 ~ SA > SB > SC). Any previous contents of SC are lost. The program counter is set to hex address OFF (the last word of page 3) and EN, is reset. b. An interrupt will be acknowledged only after the following conditions are met: 1. EN, has been set. 2. Alow-going pulse (1 to 0) at least two instruc- tion cycles wide occurs on the IN, input. 3. A currently executing instruction has been com- pleted. 4. All successive transfer of control instructions and successive LBis have been completed (e.g., if the main program is executing a JP instruction which transfers program control to another JP instruction, the interrupt will not be acknowledged until the second JP instruction has been executed. c. Upon acknowledgement of an interrupt, the skip logic status is saved and later restored upon popping of the stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction which results in carry, the skip logic status is saved and program control is trans- ferred to the interrupt servicing routine at hex address OFF. At the end of the interrupt routine, a RET instruction is executed to pop the stack and return program control to the instruction following the original ASC. At this time, the skip logic is enabled and skips this instruction because of the previous ASC carry. Subroutines and LQID instruc- tions should not be nested within the interrupt ser- vice routine, since their popping the stack will enable any previously saved main program skips, interfering with the orderly execution of the interrupt routine. d. The first instruction of the interrupt routine at hex address OFF must be a NOP. e. A LEI instruction can be put immediately before the RET to re-enable interrupts. Microbus Interface The ET9420 has an option which allows it to be used as a peripheral microprocessor device. inputting and out- putting data from and to a host microprocessor (uP). IN;, INz and IN3 general purpose inputs become MICROBUS compatible read-strobe, chip-select, and write-strobe lines, respectively. IN; becomes RD a logic 0 on this input will cause Q latch data to be enabled to the L ports for input to the uP. IN2 becomes CS a logic 0 on this line selects the ET9420 as the uP peripheral device by enabling the operation of the RD and WR lines and allows for the selection of one of several peripheral components. IN3 becomes WRa logic 0 on this line will write bus data from the L ports to the Q latches for input to the ET9420. Gy becomes INTR a ready output, reset by a write pulse from the uP on the WR line, providing the handshaking capability necessary for asynchronous data transfer between the host CPU and the ET9420. This option has been designed for compatibility with National's MICROBUS a standard interconnect system for 8-bit parallel data transfer between MOSILSI CPUs and interfacing devices. (See MICROBUS National Publication.) The functioning and timing rela- tionships between the ET9420 signal lines affected by this option are as specified for the MICROBUS inter- face, and are given in the AC electrical characteristics and shown in the timing diagrams (figures 4 and 5). Connection of the ET9420 to the MICROBUS'M js shown in Figure 6. POWER SUPPLY CLOCK cc CKI CKO G G1- 0 a3 Lo-t7 00-03 MICROPROCESSOR ET9420 INy (N2 iN3 Figure 6. MICROBUS Option Interconnect Initialization The Reset Logic, internal to the ET9420/9421, will initia- lize (clear) the device upon power-up if the power supply rise time is less than 1ms and greater than tuys. If the power supply rise time is greater than 1ms, the user must provide an external RC network and diode to the RESET pin as shown below. The RESET pin is configured as a Schmitt trigger input. If not used it should be con- nected to Vcc. Initialization will occur whenever a logic Q is applied to the RESET input, provided it stays low for at least three instruction cycle times. Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared. The SK output is enabled as a SYNC output, providing a pulse each instruction cycle time. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA. p+ q Vee R ____ 19420/ s RESET ~ 949} P t ; GND oe RC > 5x POWER SUPPLY RISE TIME Figure 7. Power-Up Clear CircuitOscillator There are four basic clock oscillator configurations available as shown by figure 8. a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time equals the crystal frequency divided by 16 (optional by 8). b. External Oscillator. CKI is an external clock input signal. The external frequency is divided by 16 (optional by 8) to give the instruction cycle time. CKO is now available to be used as the RAM power supply (Va) or as a general purpose input. c. RC Controlled Oscillator. CKi is configured as a single pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4. CKO is available for non-timing func- tions. d. Externally Synchronized Oscillator. Intended for use in multi-COP systems, CKO is programmed to function as an input connected to the SK output of another ET9420/9421 with CKI connected as shown. in this configuration, the SK output connected to CKO must provide a SYNC (instruction cycle) signal to CKO, thereby allowing synchronous data transfer between the COPs using only the SI and SO serial I/O pins in conjunction with the XAS instruction. Note that on power-up SK is automatically enabled as a SYNC out- put (See Functional Description, Initialization, above). 8 |. ; Su EXTERNAL PURPOSE INFUT cLocK PIN T tH ! Crystal Oscillator External Oscitlator Crystal Oscillator c ; ; iq OR GENERAL je iV OR GENERAL PURPOSE INPUT St so RC Controlled Oscillator Crystal Component Values Value Rt (c2) R2 (2) C (pF) 4MHz 1k 1M 27 3.58 MHz 1k 1M 27 2.09 MHz 1k 1M 56 CKO Pin Options In acrystal controiled oscillator system, CKO is used as an output to the crystal network. As an option CKO can be a SYNC input as described above. As another option CKO can be a general purpose input, read into bit 20f A (accumulator) upon execution of an INIL instruction. As another option, CKO can be a RAM power supply pin (Va), allowing its connection to a standby/backup power supply to maintain the integrity of RAM data with mini- mum power drain when the main supply is inoperative or shut down to conserve power. Using either option is appropriate in applications where the ET9420/9421 system timing configuration does not require use of the CKO pin. RAM Keep-Alive Option (Not available on ET9422} Selecting CKO as the RAM power supply (Vp) allows the user to shut off the chip power supply (Vcc) and maintain data in the RAM. To insure that RAM data integrity is maintained, the following conditions must be met: 1. RESET must go low before Voc goes betow spec during power off; Voc must be within spec before RESET goes high on power up. 2. Va must be within the operating range of the chip, and equal to Voc + 1V during normal operation. 3. Va must be 23.3V with Voc off. SYNC: ET9420/9421 ET9420/9421 $0 st Externally Synchronized Oscillator RC Controlled Oscillator Instruction Cycle Time R (k&) C (pF) (us) 12 100 5+20% 6.8 220 5.3 + 23% 8.2 300 8+ 29% 22 100 8.6 + 16% Note: 50k2 > R 2 5kQ 360 pF 2 C 2 50pF Figure 8. ET9420/9421/ET9320/9321 OscillatorVO Options ET9420/9421 outputs have the following optional confi- gurations, illustrated in Figure Qa : a. Standard an enhancement mode device to ground in conjunction with a depletion-mode device to Vcc, compatible with TTL and CMOS input requirements. Available on SO, SK, and all D and G outputs. b. Open-Drain an enhancement-mode device to ground only, allowing external pull-up as required by the users application. Available on SO, SK, and all D and G outputs. c. Push-Pull An enhancement-mode device to ground in conjunction with a depletion-mode device paralleled by an enhancement-mode device to Vcc. This configu- ration has been provided to allow for fast rise and fall times when driving capacitive loads. Available on SO and SK outputs only. d. Standard L same as a., but may be disabled. Available on L outputs only. e. Open Drain L same as b., but may be disabled. Available on L outputs only. f. LED Direct Drive .an enhancement-mode device to ground and to Voc, meeting the .typical current sourcing requirements of the segments of an LED display. The sourcing device is clamped to limit current flow. These devices may be turned off under program control (See Functional Description, EN Register), placing the outputs in a high-impedance State to provide required LED segment blanking for a multiplexed display. g-. TRI-STATE Push-Pull an enhancement-mode de- vice to ground and Vcc. These outputs are TRI-STATE outputs, allowing for connection of these outputs to a data bus shared by other bus drivers. Voc os al a. Standard Output DISABLE Vee al d. Standard L Output a. DISABLE Vcc 5 vO g. TRI-STATE* Push-Puil (L Output) h. peg bh. Open-Drain Output DISABLE ) >| 21 Open-Drain L Output f. vec #6 a (NPUT Input with Load i. ET9420/9421 inputs have the following optional confi- gurations : h. An on-chip depletion load device to Voc. i. A Hi-Z input which must be driven to a 1 or 0 by external components. The above input and output configurations share com- mon enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices (numbered 1-6, respectively). Minimum and maximum current (lout and Vout) curves are given in Figure 9b for each of these devices to allow the designer to effectively use these I/O configurations in designing a ET9420/9421 system. The SO, SK outputs can be configured as shown in a., b., or c. The D and G outputs can be configured as shown in a. or b. Note that when inputting data to the G ports, the G outputs should be set to 1. The L outputs can be configured as in d., e., f. or g. An important point to remember if using configuration d. or f. with the L drivers is that even when the L drivers are disabled, the depletion load device will source a small amount of current (see Figure 9b, device 2); however, when the L lines are used as inputs, the disabled depletion device can not be relied on to source sufficient current to pull an input to logic 1". ET9421 lf the ET9420 is bonded as a 24-pin device, it becomes the ET9421, illustrated in Figure 2, ET9420/9421 Connection Diagrams. Note that the ET9421 does not contain the four general purpose IN inputs (IN, - INo). Use of this option precludes, of course, use of the IN options, interrupt fea- ture, and the MICROBUS option which uses IN, - IN3. All other options are available for the ET9421. c. Push-Puill Output DISABLE vee (a@lS DEPLETION DEVICE! LED (L Output) input SX}- C Hi-Z Input Figure 9a. Input/Output Configurations 14Output Sink Current 15 Vec=6.3V \ Vcc =4.5 (MAX) 10 z Voc =6.3V (MIN) = ~ > o < =4.5V (MIN) 5 0 o #1 2 3004 5 66 7 Vout (VOLTS) DEVICE 1 Standard Output Source Current -20 ~1.75 Vcc = 6.3V (MAX) 15 > 71.25 t & Vec= 4.5V (MAX} 10 3 Vcc = 4.5V (MIN) ~-0.75 Vcc = 6.3V (MIN) -05 0.25 0 1 2 3 4 5 6 7 Vout (VOLTS) DEVICE 2 LED Output Source Current -20 7%8 Vec = 6.3 (MAX) 16 4 Veg = 4.5V (MAX) <-12 10 3, Vcc > 4.5 (MIN) -6 Vec = 6.3V (MIN) -4 -2 0 1 2 3 4 6 7 Vout (VOLTS) DEVICE 4 AND 2 TRI-STATE Output Source Current v V (MAX) tout (mA) 6.3V (MIN) o 1 2 3 4 S$ 6 F Vout (VOLTS) DEVICE 5 Figure 9b. ET9420/9421 L Output Depletion Load OFF Source Current -04 0.3 igut (mA) -0.1 1 2 3 4 6 7 Vout (VOLTS) DEVICE 2 Push-Pull Source Current Vee = 6.3V (MAX Vec=6.3V (MIN) tour (mA) 1 2 3 4 5 6 ? Vout (VOLTS) DEVICE 3 AND 2 LED Output Direct LED Drive -18 16 -14 Vout =2.0V = QUT <4: = 10 5 3 8 6 -4 -2 0 4 45 5 5.5 6 65 Vec (VOLTS) DEVICE 4 AND 2 tnput Load Source Current ~0.7 0.75 toe Voc 7 4.5 (MAX) Vee = 6.3V (MIN) < = 4.5V (MIN Z -05 Vog * 4.8 (MIN) - ' : \ 5 i 2 -0.25 o 1 2 3 4@ 5S 6 7 Vout (VOLTS) DEVICES Input/Output Characteristics 12OUTPUT SINK CURRENT 15 r . Vcc = 5.5 (MAX) j | ES Vee = 4.50 (MAX) LC 10 Vcc =5.5 (MIN) | Z L) = = 3 by Vec = 4.5 (MIN) 5 o 1 2 3 4 5 6 Vout (VOLTS) DEVICE 1 STANDARD OUTPUT SOURCE CURRENT ~1.75 Vcc = 5.5V (MAX ash cc (MAX) 71.25 \ Vane (MAX) = \ =< -10 eur 5 ee 3B-0.75 \ Vee = 5.5 \ Voc = 4.50 (MIN) -0.5 +(MIN} K -0.25 __ o 1 2 3 4 5 6 Vout (VOLTS) DEVICE 2 LED OUTPUT SOURCE CURRENT 24 Vec = 5.5 (MAX 20 }ec ) \ Vec = 4.5 (MAX) = \ Nec =5.5 (MIN) ~ 12 = 2 Vcc = 4.5 (MIN) -8 Y LA 0 1 2 3 4 858 6 Vout (VOLTS) DEVICE 4 AND 2 TRISTATE OUTPUT SOURCE CURRENT \ Voc = 5.5 (MAX) | -15 + T \ Vee = 4.5V (MAX) | | _ \ A Voc =5.5V Z -10 . A (MIN) = | | 2 Vcc = 4.5V = At ~5 AMA | C/N 0 1 2 3 4 5 6&6 Vout (VOLTS) DEVICE 5 lout (mA) tout (mA) IouT (mA) 2 a -3.0 , ica ss5v -25 \ (MAX) Vee = 4.5 ~2.0 \ \ nas) -15 A \ / Voc = 5.5 (MIN) -1.0+-Y Vcc = 4.5V \ /\ 0.5 (MIN) \ L OUTPUT DEPLETION LOAD OFF SOURCE CURRENT I = ! z x 4 o o 1 2 3 4 +5 6 Vout (VOLTS) = DEVICE 2 PUSH PULL SOURCE CURRENT 0 1 2 3 4 5 6 VOUT (VOLTS) DEVICE 2 AND 3 LED OUTPUT DEVICE LED DRIVE 7 4 14 7 -12 / MAX -10 / qi IZ ~ 7 3 / -6 + / VouT = 2.0V -4 7 , -2 aoo4 pet 40 45 50 55 60 Vcc (VOLTS) DEVICE 4 AND 2 INPUT LOAD SOURCE CURRENT NS Vec = 5.5 (MAX) -0.6 NNO is = be Twi cat NN vee =4.5VN Veo =5.8V MIN (MIN) | -0.2 { ) Nx beenseeseeny i o 1 2 3 4 5 6 Vout (VOLTS) DEVICE 6 Figure 9c. ET9320/9321 Input/Output CharacteristicsET9420/9421/9422 .ET9320/9321/9322 Instruction Set lable 1 is asymbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table. Table 2 provides the mnemonic, operand, machine code, data flow, skip conditions, and description asso- ciated with each instruction in the ET9420/9421/9422 instruction set. Table 2. ET9420/9421/9422,ET9320/9321/9322 Instruction Set Table Symbols Symbol Definition Symbol Definition INTERNAL ARCHITECTURE SYMBOLS INSTRUCTION OPERAND SYMBOLS A 4-bit Accumulator d 4-bit Operand Field, 0-15 binary (RAM Digit B 6-bit RAM Address Register Select) Br Upper 2 bits of B (register address) r 2-bit Operand Fie!d, 0-3 binary (RAM Register Bd Lower 4 bits of B (digit address) Select) Cc 1-bit Carry Register a 10-bit Operand Field. 0- 1023 binary (ROM D 4-bit Data Output Port Address) EN 4-bit Enable Register y 4-bit Operand Field, 0-15 binary (Immediate G 4-bit Register to latch data for G V/O Port Data) IL Two 1-bit latches associated with the IN3 or RAM(s) Contents of RAM location addressed by s INo inputs ROM(t) Contents of ROM location addressed by t IN 4-bit Input Port L 8-bit TRI-STATE 1/O Port OPERATIONAL SYMBOLS M 4-bit contents of RAM Memory pointed to by B Register + Plus PC 10-bit ROM Address Register (program - Minus counter) > Replaces Q 8-bit Register to latch data for L I/O Port a Is exchanged with SA 10-bit Subroutine Save Register A _ Is equal to SB 10-bit Subroutine Save Register B _ SC 10 Subroutine Save Register A A The ones complement of A SIO 4-bit Shift Register and Counter a Exclusive-OR SK Logic-Controlled Clock Output Range of values Table 2. ET9420/9421/9422.ET9320/9321/9322 instruction Set Machine Hex Language Code Mnemonic Operand Code (Binary) Data Flow Skip Conditions Description ARITHMETIC INSTRUCTIONS ASC 30 ADD 31 ADT 4A AISC y 5- CASC 10 CLRA 00 COMP 40 NOP 44 RC 32 sc 22 XOR 02 0011/0000 0011/0001 0100)1010 0101| y 0001/0000 0000/0000 0100/0000 [0100/0100 0011/0010 0010/0010 0000/0010 A+C+RAM(B) A Carry > C A+RAM(3) > A A+1019 >A Aty7A A+RAM(B)+C = A Carry > C O-A A-A None Ov +C A @ RAM(B) > A Carry None None Carry Carry None None None None None None Add with Carry. Skip on Carry Add RAM to A Add Tento A Add Immediate. Skip on Carry (y # Q) Complement and Add with Carry. Skip on Carry Clear A One's complement of Ato A No Operation Reset C Set Exclusive-OR RAM with A t 14Table 2. ET9420/9421 /9422.ET9320/9321/9322 Instruction Set (continued) Hex Mnemonic Operand Code Machine Language Code (Binary) TRANSFER OF CONTROL INSTRUCTIONS Data Flow Skip Conditions Description JID JMP JP JSRP JSR RET RETSK FF 6- 48 49 1114/1111 0110/0 Olag.g 47:0 1} ag-0 (pages 2,3 only) or 1 a5-0 (all other pages) 10] aso 01 10|10jag| a7:0 0100/1000 0100/1001 MEMORY REFERENCE INSTRUCTIONS CAMQ CQMA LD LDD LQID RMB SMB rd on + O on - O 33 3 33 2c -5 23 BF 4c 45 42 43 4D 47 46 4B 0011/0011 0011/1100 0011/0011 0010/1100 00 r {0101 0010/0011 or d [1011|1111 0100/1100 0100/0101 0100/0010 0100/0011 0100/1101 0100/1101 [0100/0110 [0100/1011 ROM (PCg-g, A.M) > PC7-9 None a>PC a PC-0 a > PC5-9 PC+1-> SA SB > SC 0010 + PC9-6 a7 PC5-0 PC+1> SA ~ SB ~ SC aPC SC > SB SA > PC SC > SB ~ SA ~ PC A> Q7:4 RAM(B) > Q3:9 Q7.4 > RAM(B) Q3:0 > A RAM(B) > A Brer> Br RAM(r,d) + A ROM(PCg-g,A,M) + Q SB SC 0 + RAM(B)o 0 + RAM(B)4 0 + RAM(B)2 0 > RAM(B)3 1+ RAM(B)o 1+ RAM(B)4 1+ RAM(B)2 1 > RAM(B)3 None None None None None Always Skip on Return None None None None None None None Jump Indirect (Note 3) Jump Jump within Page (Note 4) Jump to Subroutine Page (Note 5) Jump to Subroutine Return from Subroutine Return from Subroutine then Skip Copy A, RAM to Q Copy Q to RAM, A Load RAM into A, Exclusive-OR Br with r Load A with RAM pointed to directly by rd Load Q Indirect (Note 3) Reset RAM Bit Set RAM Bit 15Table 2. ET9420/9421/9422,ET9320/9321/9322 instruction Set (continued) Hex Machine Language Code Mnemonic Operand Code (Binary) Data Flow Skip Conditions Description MEMORY REFERENCE INSTRUCTIONS (continued) STi! y 7- O111) y y > RAM(B) None Store Memory Immediate Bd+1-8d and Increment Bd Xx r -6 00} r |O110 RAM(B) + A None Exchange RAM with A, Brer Br Exclusive-OR Br with r XAD rd 23 0010/0011 RAM(r,d) > A None Exchange A with RAM pointed to directly by rd -- 10] r d XDS r -7 Oo} r 10111 RAM(B) + A Bd decrements past 0 Exchange RAM with A Bd -1 Bd and Decrement Bd, Brer- Br Exclusive-OR Br with r XIS r -4 00} r /0100 RAM(B) > A Bd increments past 15 Exchange RAM with A Bd+1- Bd and Increment Bad, Brer- Br Exclusive-OR Br with r REGISTER REFERENCE INSTRUCTIONS CAB 50 0101/0000 A> Bd None Copy A to Bd CBA 4E 0100/1110 Bd-A None Copy Bd to A LBI rd -- 00] r |(d -1) rd>-B Skip until not a VBI Load & immediate with rd (d =0, 9:15) (Note 6) or 33 0011|0011 -- 10] r d (any d) LEI y 33 001 1/0014 1 y > EN None Load EN Immediate (Note 7) 6- [01 10, y XABR 12 0001/0010 A> Br (0,0 > Ag,A2) None Exchange A with Br TEST INSTRUCTIONS SKC 20 0010/0000 c="1" Skip if C is True SKE 21 0010/0001 A=RAM(B) Skip if A Equals RAM SKGZ 33 0011/0011 G3.9 =0 Skip if G is Zero (all 4 bits) 21 0010/0001 SKGBZ 33 0011/0011 1st byte Skip if G Bit is Zero 0 01 0000/0001 Go =0 1 11 0001/0001 G;1=0 2nd byte 2 03 0000/0011 G2=0 3 13 0001/0011 G3=0 SKMBZ 0 01 0000/0001 RAM(B)g = 0 Skip if RAM Bit is Zero 1 11 0001/0001 RAM(B)4 =0 2 03 0000/0011 RAM(B)2 = 0 3 13 0001/0011 RAM(B)3 = 0 SKT 41 0100/0001 A time-base counter Skip on Timer (Note 3) carry has occurred since last test 16Table 2. ET9420/9421/9422.ET9320/9321/3322 Instruction Set (continued) Machine Hex Language Code Mnemonic Operand Code (Binary) Data Flow Skip Conditions Description INPUT/OUTPUT INSTRUCTIONS ING 33 00111001 1] GrA None Input G Ports to A 2A 0010/1010 ININ 33 [001 1004 1 INA None Input IN Inputs to A (Note 2) 28 0010/1 000| INIL 33 001110011 1L3, CKO, 0, ILg > A None Input {L Latches to A 29 0010/1001 (Note 3) INL 33 [0011/0011] L7:4 - RAM(B) None Input L Ports to RAM,A 2E = |0.010|11 10 L3:0 > A OBD 33 0011/0011 Bd + D None Output Bd to D Outputs 3E 0011/1110 oGl y 33 0011/0011 y>G None Output to G Ports Immediate 5- 0101) y OMG 33 0011/0011 RAM(B) ~ G None Output RAM to G Ports 3A 0011/1010 XAS | 4F 01 0o|1 11 1 A+ SIO, C > SKL None Exchange A with SIO (Note 3) Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where 0 sianifies the {east significant bit (low-order, right-most bit). For example, Ag indicates the most significant (left-most) bit of the 4-bit A register. Note 2: The ININ instruction is not available on the ET9421/ET932 and ET9422/ET9322 since these devices do not contain the IN inputs. Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below. Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The IP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the fast word of a page. Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). AJSRP may not be used when in pages 2 or 3. JSRP may not jump.to the last word in page 2. Note 6: LB! is a single-byte instruction if d = 0,9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the d data minus 7, e.g., to load the lower four bits of B (Bd) with the value 9 (10019), the lower 4 bits of the LBI instruction equal 8 (10009). To load 0, the lower 4 bits of the LBI instruction should equal 15 (11119). Note 7: Machine code for operand field y for LE! instruction should equal the binary value to be latched into EN, where a 1 or 0 in each bit of EN corresponds with the selection or deseiection of a particular function associated with each bit. (See Functional Description, EN Register.) 17 _ aThe following information is provided to assist the user in understanding the operation of several unique instruc- tions and to provide notes useful to programmers in writing ET9420/9421 programs. XAS Instruction XAS (Exchange A with SIO) exchanges the 4-bit con- tents of the accumulator with the 4-bit contents of the SIO register. The contents of SiO will contain serial-in/ serial-out shift register or binary counter data, depending on the value of the EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If SIO is selected as a shift register, an XAS instruction must be performed once every 4 instruction cycles to effect a continuous data stream. JID Instruction JID (Jump Indirect) is an indirect addressing instruction, transferring program control to a new ROM location pointed to indirectly by A and M. It loads the lower 8 bits of the ROM address register PC with the contents of ROM addressed by the 10-bit word, PCg.g, A, M. PCg and PCg are not affected by this instruction. Note that JID requires 2 instruction cycles to execute. INIL Instruction INIL (Input IL Latches to A) inputs 2 latches, ILg and ILo (see figure 10) and CKO into A. The IL3 and IL latches are set if a low-going pulse ('1 to 0) has occurred on the {N3 and INo inputs since the last INIL instruction, provided the input pulse stays low for at least two instruction times. Execution of an INIL inputs iL, and Lg into A3 and AO respectively, and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INo lines. If CKO is mask programmed as a general purpose input, an INIL will input the state of CKO into A2. If CKO has not been so programmed, a 1 will be placed in A2. A0 is always placed in A1 upon the execution of an INIL. The general purpose inputs IN3-INo are input to A upon execution of an ININ instruction. (See table 2, ININ instruction.) INIL is useful in recognizing pulses of short duration or pulses which occur too often to be read conveniently by an ININ instruction. Note: IL latches are not cleared on reset. ET9420 INp/IN3 SET Figure 10. LQID Instruction LQID (Load Q Indirect) loads the 8-bit Q register with the contents of ROM pointed to by the 10-bit word PCg, PCg. A, M. LQID can be used for table lookup or code conver- sion such as BCD to seven-segment. The LQID instruc- tion pushes the stack (PC + 1-* SA > SB ~SC) and replaces the least significant 8 bits of PC as follows: A > PC7.4, RAM(B) > PC3.9, leaving PCg and PCg unchanged. The ROM data pointed to by the new address is fetched and loaded into the Q latches. Next, the stack is popped (SC ~ SB ~- SA PC). restoring the saved value of PC to continue sequential program execution. Since LQID pushes SB > SC, the previous contents of SC are lost. Also, when LQID pops the stack, the previ- ously pushed contents of SB are left in SC. The net result is that the contents of SB are placed in SC (SB > SC). Note that LQID takes two instruction cycle times to execute. SKT Instruction The SKT (Skip On Timer) instruction tests the state of an internal 10-bit time-base counter. This counter divides the instruction cycle clock frequency by 1024 and pro- vides a latched indication of counter overflow. The SKT instruction tests this latch, executing the next program instruction if the latch is not set. if the latch has been set since the previous test, the next program instruction is skipped and the latch is reset. The features associ- ated with this instruction, therefore, allow the ET9420/9421 to generate its own time-base for real-time processing rather than relying on an external input signal. For example, using a 2.097 MHz crystal as the time-base to the clock generator, the instruction cycle clock fre- quency will be 131kHz (crystal frequency = 16) and the binary counter output pulse frequency will be 128Hz. For time-of-day or similar real-time processing, the SKT instruction can call a routine which increments a sec- onds counter every 128 ticks. Instruction Set Notes a. The first word of a ET9420/9421 program (ROM ad- dress 0) must be a CLRA (Clear A) instruction. b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of the skipped instruction. Thus all program paths take the same number of cycle times whether instructions are skipped or executed except JID and LQID. LQID and JID take two cycle times if executed and one if skipped. c. The ROM is organized into 16 pages of 64 words each. The Program Counter is an 10-bit binary counter, and will count through page boundaries. If a JP, JSRP, JID or LQID instruction is located in the last word of a page, the instruction operates as if it were in the next page. For example: a JP located in the last word of a page will jump to a location in the next page. Also, a LQID or JID located in the last word of page 3, 7, 11 or 15 will access data in the next group of four pages. 18Option List The ET9420/9421/9422 mask-programmable options are assigned numbers which correspond with the ET9420 pins. . The following is a list of ET9420 options. When specifying a ET9421 or ET9422 chip, Options 9, 10, 19, 20 and 29 must all be set to zero. When specifying a ET9422 chip. Options 21, 22, 27 and 28 must also be zero, and Option 2 must not be a 1. The options are programmed at the same time as the ROM pattern to provide the user with the hard- ware flexibility to interface to various |/O components using little or no external circuitry. Option 1=0: Ground Pin no options available Option 2: CKO Pin =0: clock generator output to crystal (0 not available if option 3=4 or 5) =1: pin is RAM power supply (Vp) input (Not available on ET9422, ET9322) =2: general purpose input with load device =3: multi-COP SYNC input =4: general purpose Hi Z input Option 3: CKI Input =0: crystal input divided by 16 =1: crystal input divided by 8 =2: TTL external clock input divided by 16 =3: TTL external clock input divided by 8 = 4: single-pin RC controlled oscillator (+4) =5: Schmitt trigger clock input (+4) Option 4: RESET Pin =0: Load devices to Voc =1: Hi-Z input Option 5: Ly; Driver =0: Standard output (figure 9D) =1: Open-Drain output (E) =2: LED direct drive output (F) =3: TRI-STATE push-pull output (G) Option 6: Lg Driver same as Option 5 Option 7: Ls Driver same as Option 5 Option 8: L4 Driver same as Option 5 Option 9: IN, Input =0: load device to Voc (H) =1: Hi-Z input (I) Option 10: IN2 Input same as Option 9 Option 11=0: Veco Pin no options available Option 12: Lg Driver same as Option 5 Option 13: Lz Driver same as Option 5 Option 14: L, Driver same as Option 5 Option 15: Lo Driver same as Option 5 Option 16: SI Input same as Option 9 Option 17: SO Driver =0: standard output (A) =1: open-drain output (B) =2: push-pull output (C) Option 18: SK Driver same as Option 17 Option 19: IN Input same as Option 9 Option 20: INg Input same as Option 9 Option 21: Gg I/O Port =0: Standard output (A) =1: Open-Drain output (B) Option 22: G, I/O Port same as Option 21 Option 23: G2 V/O Port same as Option 21 Option 24: Gs; I/O Port same as Option 21 Option 25: D3 Output =0: Standard output (A) =1: Open-Drain output (B) Option 26: Dz Output same as Option 25 Option 27: D, Output same as Option 25 Option 28: Dp Output same as Option 25 Option 29: COP Function =0Q: normal operation =1: MICGROBUS option Option 30: COP Bonding =0: 19420 (28-pin device) =1: ET9421 (24-pin device) =2: 28 and 24-pin versions =3: ET9422 (20-pin device) = 4: 28- and 20-pin versions =5: 24 and 20-pin versions =6: 28-, 24, and 20-pin versio Option 31: IN Input Levels =0: normal input levels =1: Higher voltage input leve (O = 1.2V, 1 =3.6V) Option 32: G Input Levels same as Option 31 Option 33: L Input Levels same as Option 31 Option 34: CKO Input Levels same as Option 31 Option 35: SI Input Levels same as Option 31 19TEST MODE (Non-Standard Operation) The SO output has been configured to provide for stan- dard test procedures for the custom-programmed ET9420. With SO forced to logic 1, two test modes are provided, depending upon the value of St : a. RAM and Internal Logic Test Mode (SI = 1) b. ROM Test Mode (SI = 0) These special test modes should not be employed by the user: they are intended for manufacturing test only. APPLICATION EXAMPLE : ET9420 General Con- troller Figure 9 shows an interconnect diagram for a ET9420 used as a general controller. Operation of the system is as follows : 1. The L7-L outputs are configured as LED Direct Drive outputs, allowing direct connection to the segments of the display. 3 NICAD Batteries} CC GNO ET9420 4 GENERAL va EVENT COUNTER INPUT 2) GENERAL OUTPUTS . The D3- Dp outputs drive the digits of the multiplexed display directly and scan the columns of the 4x4 keyboard matrix. . The IN3-1INg inputs are used to input the 4 rows of the keyboard matrix. Reading the IN lines in conjunction with the current value of the D outputs allows detection, debouncing, and decoding of any one of the 16 keyswitches. . CK! is configured as a single-pin oscillator input allowing system timing to be controlled by a single- pin RC network. CKO is therefore available for use as a Va RAM power supply pin. RAM data integrity is thereby assured when the main power supply is shut down (see RAM Keep-Alive Option description). . Slis selected as the input to a binary counter input. With SIO used as a binary counter. SO and SK can be used as general purpose outputs. . The 4 bidirectional G I/O ports (G3- Go) are available for use as required by the user's application. 4 OIGIT LED DISPLAY aud KEYSWITTH MATRIX *SI, SO and SK may also be used for serial I/O Figure 11. ET9420 Keyboard/Display Interface 20Physical Dimensions inches (mitlimeters) 1.470 (37.338) MAX feel _fe7]_fe5}_ fos) fea] _fe3)_f22]_fex)_ feo) fis)]_fre)_ fr} fie)_fis 0.062 (1.875) RAD 5) 0.550 -0.005 NO. + INDENT (13.970 -0.127) PIN NO. 11 NY | oe DEST Soe oe ee 0.030 (0.762) 9-060 0.050 0.600-0.620 MAX (1.524) 270) 0.130 -0.005) (15.24015.748) { { tye | | (3.302 -0.127) T J cr yr " TH 5 ty 0.009--0.015 0.625 70-025 (0.229-0.381) 0.020 om 0.015 u , Ine 0.075 0.018 | | 6.100 ' 9,018 -0.003 0.125 (0-508) +0.635 ae pee a i ae (0.125 (15.875 ) (1.905 +0.381) | ' (2,540) (0.457 -0.076) (3.175} 0.381 TYP MIN Molded Dual-In-Line Package (N) Order Number ET9420 N or ET9320 N Package Number N28A | 4.270 1 | (32.258) | MAX fe} 25) 22] eet ts) fe) re) fs} fre] fe) 0.063 (1.600) ~~ 0.540 -0.005 RAD ~ (13.716 -0.127) We eee & GW GY te oy ee 0.600-0.620 (1.905) fate 0.160 -0.005 $$ $5&a$< $s $A | . os | (15.240- 15.748) { TYP (4.064 -0.127) 1 ' | 0.015 | { (0.381) 0.009-0.015 | 0.625 72-025 (0.229-0.381) L +0. (15.975 0.381 (2.540) I (0.457 +0.076) (3.175) (1.905 +0.381) TYP MIN 0.015 j | 0.100 0.018 -0.003 0.125 ) 0.075 +0.015 = => | || Molded Dual-In-Line Package (N) Order Number ET9421N or ET9321 N Package Number N24A ot)| EUROTECHNIQUE Eurotechnique : 3, place Gustave Eiffel, Silic 209, 94518 Rungis Cedex, France, Tl. (1) 687.23.03, Telex : 201068 Eurotechnique Semiconductor Ltd : 4 th ftoor Lambourne House, 7 Western Road, Romford, Essex RM 1 3LD, UK, Tel. (708) 27.488, Telex :896683 E.T.S. Eurotechnique Semiconductor Verkaufs - GmbH, Neusser Strasse 9, D-8000 Munich 40, Germany, Tel. (89) 36.30.85/86, Telex : 528283 Headquarters, International Sales Office and Factory : Eurotechnique B.P. 2, 13790 Rousset, France, tel. (42) 23.98.01, telex : 440.306 F Eurotechnique does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and Eurotechnique reserves the right, at any time without notice, to change said circuitry 2 2