FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures GENERAL DESCRIPTION The AD9520-31 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used. 1 CP OPTIONAL REF1 REFIN REFIN CLK REF2 LF STATUS MONITOR PLL Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.72 GHz to 2.25 GHz Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Automatic/manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.6 GHz LVPECL outputs divided into 4 groups Each group of 3 outputs shares a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs < 16 ps Each LVPECL output can be configured as 2 CMOS outputs (for fOUT 250 MHz) Automatic synchronization of all outputs on power-up Manual output synchronization available SPI- and IC-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings DIVIDER AND MUXES VCO ZERO DELAY LVPECL/ CMOS DIV/ OUT0 OUT1 OUT2 DIV/ OUT3 OUT4 OUT5 DIV/ OUT6 OUT7 OUT8 DIV/ OUT9 OUT10 OUT11 SPI/I2C CONTROL PORT AND DIGITAL LOGIC EEPROM AD9520 07216-001 FEATURES SWITCHOVER AND MONITOR Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO AD9520-3 Figure 1. The AD9520 serial interface supports both SPI and IC ports. An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for power-up and chip reset. The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. If an application requires LVDS drivers instead of LVPECL drivers, refer to the AD9522. Each group of three outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase offset or coarse time delay to be set. The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage of up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V. The AD9520-3 is specified for operation over the standard industrial range of -40C to +85C. AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-3 is used, it refers to that specific member of the AD9520 family. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2008-2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9520-3 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions........................... 18 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 21 General Description ......................................................................... 1 Terminology .................................................................................... 26 Functional Block Diagram .............................................................. 1 Detailed Block Diagram ................................................................ 27 Revision History ............................................................................... 3 Theory of Operation ...................................................................... 28 Specifications..................................................................................... 4 Operational Configurations ...................................................... 28 Power Supply Requirements ....................................................... 4 Zero Delay Operation ................................................................ 42 PLL Characteristics ...................................................................... 4 Clock Distribution ..................................................................... 43 Clock Inputs .................................................................................. 7 Reset Modes ................................................................................ 49 Clock Outputs ............................................................................... 7 Power-Down Modes .................................................................. 50 Timing Characteristics ................................................................ 8 Serial Control Port ......................................................................... 51 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ............................................................ 10 SPI/I2C Port Selection................................................................ 51 Clock Output Absolute Phase Noise (Internal VCO Used) .. 11 SPI Serial Port Operation .......................................................... 54 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) .................................................................. 11 SPI Instruction Word (16 Bits) ................................................. 55 Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO) .................................................................. 11 EEPROM Operations ..................................................................... 58 I2C Serial Port Operation .......................................................... 51 SPI MSB/LSB First Transfers .................................................... 55 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) .............................................................. 12 Writing to the EEPROM ........................................................... 58 Clock Output Additive Time Jitter (VCO Divider Not Used)..................................................................................... 12 Programming the EEPROM Buffer Segment ......................... 59 Thermal Performance .................................................................... 60 Clock Output Additive Time Jitter (VCO Divider Used) ..... 12 Register Map ................................................................................... 61 Serial Control Port--SPI Mode ................................................ 13 Register Map Descriptions ............................................................ 64 Serial Control Port--I2C Mode ................................................ 14 Applications Information .............................................................. 77 PD, EEPROM, RESET, and SYNC Pins .................................. 15 Frequency Planning Using the AD9520 .................................. 77 Serial Port Setup Pins--SP1, SP0 ............................................. 15 Using the AD9520 Outputs for ADC Clock Applications .... 77 LD, STATUS, and REFMON Pins ............................................ 15 CMOS Clock Distribution ........................................................ 78 Power Dissipation ....................................................................... 16 Outline Dimensions ....................................................................... 80 Absolute Maximum Ratings.......................................................... 17 Ordering Guide .......................................................................... 80 Reading from the EEPROM ..................................................... 58 Thermal Resistance .................................................................... 17 ESD Caution ................................................................................ 17 Rev. A | Page 2 of 80 Data Sheet AD9520-3 REVISION HISTORY 8/13--Rev. 0 to Rev. A Changes to Features Section, Applications Section, and General Description Section ............................................................ 1 Changes to Table 2 ............................................................................ 4 Changes to Input Frequency Parameter; Change to Input Sensitivity, Differential Parameter Test Conditions/Comments, Table 3 ................................................................................................. 7 Change to Output Differential Voltage, VOD Parameter Test Conditions/Comments; Added Source Current and Sink Current Parameters, Table 4 ............................................................ 7 Change to Output Skew, LVPECL Outputs Parameter, Test Conditions/Comments, Table 5 ...................................................... 8 Reordered Figure 2 to Figure 4 ........................................................ 9 Change to Reset Timing, Pulse Width Low Parameter, Table 15 ...15 Change to Maximum Power, Full Operation Parameter, Internal VCO Value in Test Conditions/Comments, Table 18 .16 Change to Junction Temperature, Table 19; Reformatted Table 19 .............................................................................................17 Change to Table 21 ..........................................................................18 Deleted Figure 13, Renumbered Sequentially .............................22 Reordered Figure 31 and Figure 32; Moved Figure 34 and Figure 35 to PLL External Loop Filter Section, Page 35; Added Figure 33, Renumbered Sequentially ............................................25 Change to Mode 0--Internal VCO and Clock Distribution Section ..............................................................................................28 Change to Configuration of the PLL Section; Changes to Charge Pump (CP) Section ............................................................34 Changes to On-Chip VCO Section and PLL External Loop Filter Section; Added Figure 40; Moved Figure 41 and Figure 42 from Typical Performance Characteristics Section to PLL External Loop Filter Section; Changes to PLL Reference Inputs Section ..................................................................................35 Changes to Reference Switchover Section ...................................36 Change to Prescaler Section and A and B Counters Section; Changes to Table 29 ........................................................................37 Changes to Current Source Digital Lock Detect (CSDLD) Section ..............................................................................................38 Changes to Frequency Status Monitors Section and VCO Calibration Section .........................................................................41 Added Table 31, Renumbered Sequentially; Change to Internal Zero Delay Mode Section ................................................42 Change to External Zero Delay Mode Section ............................ 43 Change to Clock Frequency Division Section; Added Channel Divider Maximum Frequency Section ......................................... 45 Reformatted Table 36 to Table 39.................................................. 46 Change to Phase Offset or Coarse Time Delay Section ............. 47 Change to LVPECL Output Drivers Section; Changes to CMOS Output Drivers Section; Change to Power-On Reset Section ... 49 Changes to Soft Reset via the Serial Port Section and Soft Reset to Settings in EEPROM When EEPROM Pin = 0b via the Serial Port Section .............................................................. 50 Change to Pin Descriptions Section, SPI Mode Operation Section, and Write Section ............................................................. 54 Changes to SPI Instruction Word (16 Bits) Section ................... 55 Changes to EEPROM Operations Section, Writing to the EEPROM Section, and Reading from the EEPROM Section ... 58 Changes to Programming the EEPROM Buffer Segment Section and Register Section Definition Group Section; Added Operational Codes Section Heading ............................... 59 Changes to Table 50 ........................................................................ 61 Added Unused Bits to Register Map Descriptions Section; Changes to Address 0x000, Bit 5, and Added Address 0x003, Table 51; Changes to Address 0x000, Bit 5, and Added Address 0x003, Table 52 ................................................................. 64 Changes to Address 0x017, Table 54 ............................................ 66 Changes to Address 0x018, Bit 4 and Bits[2:1], Table 54 ........... 67 Change to Address 0x1A, Bit 6, Table 54 .....................................68 Changes to Address 0x01B, Bits[4:0], Table 54 ........................... 69 Changes to Address 0x191, Bit 5, and Address 0x194, Bit 5, Table 56 ............................................................................................. 72 Changes to Address 0x197, Bit 5, Table 56 .................................. 73 Changes to Address 0x19A, Bit 5, Table 56 ................................. 74 Changes to Table 60 ........................................................................ 75 Changes to Address 0xB02, Bit 0, and Address 0xB03, Bit 0, Table 61 ............................................................................................. 76 Change to Frequency Planning Using the AD9520 Section ..... 77 Added LVPECL Y-Termination and Far-End Thevenin Termination Headings; Changes to CMOS Clock Distribution Section .............................................................................................. 78 9/08--Revision 0: Initial Version Rev. A | Page 3 of 80 AD9520-3 Data Sheet SPECIFICATIONS Typical is given for VS = VS_DRV = 3.3 V 5%; VS VCP 5.25 V; TA = 25C; RSET = 4.12 k; CPRSET = 5.1 k, unless otherwise noted. Minimum and maximum values are given over full VS and TA (-40C to +85C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter POWER PINS VS VS_DRV VCP CURRENT SET RESISTORS RSET Pin Resistor CPRSET Pin Resistor Min Typ Max Unit Test Conditions/Comments 3.135 2.375 VS 3.3 3.465 VS 5.25 V V V 3.3 V 5% Nominally 2.5 V to 3.3 V 5% Nominally 3.3 V to 5.0 V 5% 4.12 5.1 k k 220 nF Sets internal biasing currents; connect to ground Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 A); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground Bypass for internal LDO regulator; necessary for LDO stability; connect to ground BYPASS PIN CAPACITOR PLL CHARACTERISTICS Table 2. Parameter VCO (ON CHIP) Frequency Range VCO Gain (KVCO) Tuning Voltage (VT) Frequency Pushing (Open-Loop) Phase Noise at 1 kHz Offset Phase Noise at 100 kHz Offset Phase Noise at 1 MHz Offset REFERENCE INPUTS Differential Mode (REFIN, REFIN) Input Frequency Min 1720 Input Frequency (DC-Coupled) Input Sensitivity (AC-Coupled with DC Offset Off) Input Sensitivity (AC-Coupled with DC Offset On) Input Logic High, DC Offset Off Input Logic Low, DC Offset Off Input Current Input Capacitance Max Unit 2250 MHz MHz/V V MHz/V dBc/Hz dBc/Hz dBc/Hz 47 0.5 VCP - 0.5 1 -55 -110 -129 0 Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFIN Input Resistance, REFIN Input Resistance, REFIN Dual Single-Ended Mode (REF1, REF2) Input Frequency (AC-Coupled) with DC Offset Off) Input Frequency (AC-Coupled with DC Offset On) Typ 250 280 1.35 1.30 4.0 4.4 1.60 1.50 4.8 5.3 MHz mV p-p Test Conditions/Comments See Figure 8 VT VS when using internal VCO f = 2000 MHz f = 2000 MHz f = 2000 MHz Differential mode (can accommodate single-ended input by ac grounding undriven input) Frequencies below about 1 MHz should be dc-coupled; be careful to match VCM (self-bias voltage) PLL figure of merit (FOM) increases with increasing slew rate (see Figure 12); the input sensitivity is sufficient for ac-coupled LVDS and LVPECL signals Self-bias voltage of REFIN 1 Self-bias voltage of REFIN1 Self-biased1 Self-biased1 Two single-ended CMOS-compatible inputs Slew rate must be >50 V/s 1.75 1.60 5.9 6.4 V V k k 250 MHz 250 MHz 0 0.55 250 3.28 MHz V p-p Slew rate must be >50 V/s, and input amplitude sensitivity specification must be met; see the input sensitivity parameter Slew rate > 50 V/s; CMOS levels VIH should not exceed VS 1.5 2.78 V p-p VIH should not exceed VS 0.8 +100 V V A pF Each pin, REFIN (REF1)/REFIN (REF2) 10 2.0 -100 2 Rev. A | Page 4 of 80 Data Sheet Parameter Pulse Width High/Low AD9520-3 Max Unit ns 33.33 30 MHz 100 45 50 1.3 2.9 6.0 MHz MHz MHz ns ns ns ICP Sink/Source High Value 4.8 mA Low Value 0.60 mA Crystal Oscillator Crystal Resonator Frequency Range Maximum Crystal Motional Resistance PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency Reference Input Clock Doubler Frequency Antibacklash Pulse Width Min 1.8 Typ 16.62 0.004 CHARGE PUMP (CP) Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD P = 2 FD P = 3 FD P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) Prescaler Output Frequency PLL N DIVIDER DELAY 000 001 010 011 100 101 110 111 PLL R DIVIDER DELAY 000 001 010 011 100 101 110 111 2.5 1 1 % k nA % 1.5 2 % % 2.7 10 300 600 900 200 1000 2400 3000 3000 300 Off 385 486 623 730 852 976 1101 MHz MHz MHz MHz MHz MHz MHz MHz MHz Test Conditions/Comments The amount of time that a square wave is high/low; determines the allowable input duty cycle Antibacklash pulse width = 1.3 ns Antibacklash pulse width = 2.9 ns Register 0x017[1:0] = 01b Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b Register 0x017[1:0] = 10b CPV is the CP pin voltage; VCP is the charge pump power supply voltage (VCP pin) Programmable With CPRSET = 5.1 k; higher ICP is possible by changing CPRSET With CPRSET = 5.1 k; lower ICP is possible by changing CPRSET CPV = VCP/2 0.5 V < CPV < VCP - 0.5 V; CPV is the CP pin voltage; VCP is the charge pump power supply voltage (VCP pin) 0.5 V < CPV < VCP - 0.5 V CPV = VCP/2 A, B counter input frequency (prescaler input frequency divided by P) Register 0x019[2:0]; see Table 54 ps ps ps ps ps ps ps Register 0x019[5:3]; see Table 54 Off 365 486 608 730 852 976 1101 ps ps ps ps ps ps ps Rev. A | Page 5 of 80 AD9520-3 Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector 2 500 kHz PFD Frequency 1 MHz PFD Frequency 10 MHz PFD Frequency 50 MHz PFD Frequency PLL Figure of Merit (FOM) Data Sheet Min Typ Max Unit 560 1060 1310 ps Test Conditions/Comments REF refers to REFIN (REF1)/REFIN (REF2) When N delay and R delay are bypassed -320 +50 +240 ps When N delay setting = 110b, and R delay is bypassed 140 630 870 ps When N delay and R delay are bypassed -460 -20 +200 ps When N delay setting = 011b, and R delay is bypassed The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider). -165 -162 -152 -144 -222 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns 3.5 ns Low Range (ABP 1.3 ns, 2.9 ns) 7 ns High Range (ABP 1.3 ns, 2.9 ns) 15 ns High Range (ABP 6.0 ns) 11 ns PLL DIGITAL LOCK DETECT WINDOW 3 Lock Threshold (Coincidence of Edges) High Range (ABP 6.0 ns) Unlock Threshold (Hysteresis)3 Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed-loop, the phase noise, as observed at the VCO output, is increased by 20 log(N); PLL figure of merit decreases with decreasing slew rate; see Figure 12 Signal available at the LD, STATUS, and REFMON pins when selected by appropriate register settings; the lock detect threshold varies linearly with the value of the CPRSET resistor Selected by Register 0x017[1:0] and Register 0x018[4] (this is the threshold to go from unlock to lock) Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b Register 0x017[1:0] = 10b; Register 0x018[4] = 0b Selected by Register 0x017[1:0] and Register 0x018[4] (this is the threshold to go from lock to unlock) Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b Register 0x017[1:0] = 10b; Register 0x018[4] = 0b The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. In-band means within the LBW of the PLL. 3 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time. 1 2 Rev. A | Page 6 of 80 Data Sheet AD9520-3 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Max Unit 01 01 2.4 2.0 GHz GHz 01 1.6 GHz Input Sensitivity, Differential Typ 150 mV p-p Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance 1 1.3 1.3 3.9 1.57 150 4.7 2 2 V p-p 1.8 1.8 V V mV p-p k pF 5.7 Test Conditions/Comments Differential input High frequency distribution (VCO divider) Distribution only (VCO divider bypassed); this is the frequency range supported by the channel divider for all divide ratios except divide-by-17 and divide-by-3 Distribution only (VCO divider bypassed); this is the frequency range supported by all channel divider ratios Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns; the input sensitivity is sufficient for ac-coupled LVDS and LVPECL signals Larger voltage swings can turn on the protection diodes and can degrade jitter performance Self-biased; enables ac coupling With 200 mV p-p signal applied; dc-coupled CLK ac-coupled; CLK ac-bypassed to RF ground Self-biased Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM. CLOCK OUTPUTS Table 4. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10, OUT11 Output Frequency, Maximum Output High Voltage, VOH Output Low Voltage, VOL Output Differential Voltage, VOD CMOS CLOCK OUTPUTS OUT0A, OUT0B, OUT1A, OUT1B, OUT2A, OUT2B, OUT3A, OUT3B, OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B, OUT7A, OUT7B, OUT8A, OUT8B, OUT9A, OUT9B, OUT10A, OUT10B, OUT11A, OUT11B Output Frequency Output Voltage High, VOH Output Voltage Low, VOL Output Voltage High, VOH Output Voltage Low, VOL Output Voltage High, VOH Output Voltage Low, VOL Min Typ Max 2400 VS_DRV - 1.07 VS_DRV - 1.95 660 VS_DRV - 0.96 VS_DRV - 1.79 820 VS_DRV - 0.84 VS_DRV - 1.64 950 Unit Test Conditions/Comments Termination = 50 to VS_DRV - 2 V Differential (OUT, OUT) MHz Using direct to output (see Figure 20); higher frequencies are possible, but the resulting amplitude does not meet the VOD specification; the maximum output frequency is limited by either the maximum VCO frequency or the frequency at the CLK inputs, depending on the AD9520 configuration V V mV VOH - VOL for each leg of a differential pair for default amplitude setting with the driver not toggling; the peak-to-peak amplitude measured using a differential probe across the differential pair with the driver toggling is roughly 2x these values (see Figure 20 for variation over frequency) Single-ended; termination = 10 pF 250 VS - 0.1 0.1 2.7 0.5 1.8 0.6 Rev. A | Page 7 of 80 MHz V V V V V V See Figure 21 1 mA load, VS_DRV = 3.3 V/2.5 V 1 mA load, VS_DRV = 3.3 V/2.5 V 10 mA load VS_DRV = 3.3 V 10 mA load, VS_DRV = 3.3 V 10 mA load, VS_DRV = 2.5 V 10 mA load, VS_DRV = 2.5 V AD9520-3 Parameter Source Current Static Dynamic Sink Current Static Dynamic Data Sheet Min Typ Max Unit Test Conditions/Comments Damage to the part can result if values are exceeded 20 16 mA mA 8 16 mA mA Typ Max Unit 130 170 ps 130 170 ps 1050 970 1.0 1280 1180 ps ps ps/C 5 16 ps Termination = 50 to VS_DRV - 2 V VS_DRV = 3.3 V 5 5 20 45 ps ps VS_DRV = 2.5 V VS_DRV = 3.3 V 5 60 190 ps ps VS_DRV = 2.5 V VS_DRV = 3.3 V and 2.5 V 750 715 965 890 960 890 1280 1100 ps ps ps ps Termination = open 20% to 80%; CLOAD = 10 pF; VS_DRV = 3.3 V 80% to 20%; CLOAD = 10 pF; VS_DRV = 3.3 V 20% to 80%; CLOAD = 10 pF; VS_DRV = 2.5 V 80% to 20%; CLOAD = 10 pF; VS_DRV = 2.5 V Clock distribution configuration 2.75 3.35 2 3.55 ns ns ps/C VS_DRV = 3.3 V VS_DRV = 2.5 V VS_DRV = 3.3 V and 2.5 V 7 85 ps VS_DRV = 3.3 V 10 10 105 240 ps ps VS_DRV = 2.5 V VS_DRV = 3.3 V 10 285 600 ps ps VS_DRV = 2.5 V VS_DRV = 3.3 V 620 ps VS_DRV = 2.5 V All settings identical; different logic type 2.48 2.50 ns ns LVPECL to CMOS on same part LVPECL to CMOS on same part Damage to the part can result if values are exceeded TIMING CHARACTERISTICS Table 5. Parameter LVPECL OUTPUT RISE/FALL TIMES Output Rise Time, tRP Min Output Fall Time, tFP PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT For All Divide Values 850 800 Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS 1 LVPECL Outputs Sharing the Same Divider LVPECL Outputs on Different Dividers All LVPECL Outputs Across Multiple Parts CMOS OUTPUT RISE/FALL TIMES Output Rise Time, tRC Output Fall Time, tFC Output Rise Time, tRC Output Fall Time, tFC PROPAGATION DELAY, tCMOS, CLK-TOCMOS OUTPUT For All Divide Values 2.1 Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS1 CMOS Outputs Sharing the Same Divider All CMOS Outputs on Different Dividers All CMOS Outputs Across Multiple Parts OUTPUT SKEW, LVPECL-TO-CMOS OUTPUTS1 Outputs Sharing the Same Divider Outputs on Different Dividers 1 1.18 1.20 1.76 1.78 Test Conditions/Comments Termination = 50 to VS_DRV - 2 V 20% to 80%, measured differentially (rise/fall times are independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V) 80% to 20%, measured differentially (rise/fall times are independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V) High frequency clock distribution configuration Clock distribution configuration The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. Rev. A | Page 8 of 80 Data Sheet AD9520-3 Timing Diagrams DIFFERENTIAL SINGLE-ENDED 80% 80% LVPECL CMOS 10pF LOAD 20% tRC Figure 2. LVPECL Timing, Differential Figure 4. CMOS Timing, Single-Ended, 10 pF Load tCLK CLK 07216-060 tPECL tCMOS tFC Figure 3. CLK/CLK to Clock Output Timing, DIV = 1 Rev. A | Page 9 of 80 07216-063 tFP tRP 07216-061 20% AD9520-3 Data Sheet CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 1 GHz Divider = 1 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset CLK = 1 GHz, Output = 200 MHz Divider = 5 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset >10 MHz Offset CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 250 MHz Divider = 4 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset >10 MHz Offset CLK = 1 GHz, Output = 50 MHz Divider = 20 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset >10 MHz Offset Min Typ -107 -117 -127 -135 -142 -145 -147 -150 Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns -122 -132 -143 -150 -156 -157 -157 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns -107 -119 -125 -134 -144 -148 -154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns -126 -133 -140 -148 -157 -160 -163 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A | Page 10 of 80 Data Sheet AD9520-3 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVPECL ABSOLUTE PHASE NOISE Min VCO = 2.25 GHz; Output = 2.25 GHz 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset VCO = 2 GHz; Output = 2 GHz 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset VCO = 1.75 GHz; Output = 1.75 GHz 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset Typ Max Unit -50 -82 -107 -126 -140 -146 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -55 -85 -110 -129 -142 -147 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -59 -89 -114 -132 -143 -147 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments Internal VCO; direct-to-LVPECL output and for loop bandwidths < 1 kHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min VCO = 1.966 GHz; LVPECL = 245.76 MHz; PLL LBW = 55 kHz Typ Max 135 308 129 293 163 323 VCO = 1.966 GHz; LVPECL = 122.88 MHz; PLL LBW = 55 kHz VCO = 1.966 GHz; LVPECL = 61.44 MHz; PLL LBW = 55 kHz Unit fs rms fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R divider = 1 Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min VCO = 1.866 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.9 kHz VCO = 1.966 GHz; LVPECL = 122.88 MHz; PLL LBW = 2.2 kHz Typ 377 386 Rev. A | Page 11 of 80 Max Unit fs rms fs rms Test Conditions/Comments Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 19.44 MHz; R divider = 162 Integration BW = 12 kHz to 20 MHz Integration BW = 12 kHz to 20 MHz AD9520-3 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min LVPECL = 245.76 MHz; PLL LBW = 125 Hz Typ Max 54 77 109 79 114 163 124 176 259 LVPECL = 122.88 MHz; PLL LBW = 125 Hz LVPECL = 61.44 MHz; PLL LBW = 125 Hz Unit fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R divider = 1 Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER Min CLK = 622.08 MHz Any LVPECL Output = 622.08 MHz Divide Ratio = 1 CLK = 622.08 MHz Any LVPECL Output = 155.52 MHz Divide Ratio = 4 CLK = 1000 MHz Any LVPECL Output = 100 MHz Divide Ratio = 10 CLK = 500 MHz Any LVPECL Output = 100 MHz Divide Ratio = 5 CMOS OUTPUT ADDITIVE TIME JITTER CLK = 200 MHz Any CMOS Output Pair = 100 MHz Divide Ratio = 2 Typ Max 46 fs rms Test Conditions/Comments Distribution section only; does not include PLL and VCO; measured at rising edge of clock signal Integration bandwidth = 12 kHz to 20 MHz 64 fs rms Integration bandwidth = 12 kHz to 20 MHz 223 fs rms Calculated from SNR of ADC method Broadband jitter 209 fs rms Calculated from SNR of ADC method Broadband jitter 325 Unit fs rms Distribution section only; does not include PLL and VCO Calculated from SNR of ADC method Broadband jitter CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER Min Typ Max Unit CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz; Channel Divider = 2; Duty-Cycle Correction = Off CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = On CMOS OUTPUT ADDITIVE TIME JITTER 230 fs rms 215 fs rms CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = Off CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz; Channel Divider = 8; Duty-Cycle Correction = Off 326 fs rms 362 fs rms Rev. A | Page 12 of 80 Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal Calculated from SNR of ADC method (broadband jitter) Calculated from SNR of ADC method (broadband jitter) Distribution section only; does not include PLL and VCO; uses rising edge of clock signal Calculated from SNR of ADC method (broadband jitter) Calculated from SNR of ADC method (broadband jitter) Data Sheet AD9520-3 SERIAL CONTROL PORT--SPI MODE Table 13. Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Min Max Unit 0.8 3 -110 V V A A 2 pF 2.0 Input Capacitance SCLK (INPUT IN SPI MODE) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (INPUT IN BIDIRECTIONAL MODE) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup and Hold, tS, tC CS Minimum Pulse Width High, tPWH Typ Test Conditions/Comments CS has an internal 30 k pull-up resistor The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor SCLK has an internal 30 k pull-down resistor in SPI mode but not in I2C mode 2.0 0.8 110 1 2 2.0 0.8 1 1 2 2.7 0.4 25 16 16 4 0 11 2 3 Rev. A | Page 13 of 80 V V A A pF V V A A pF V V MHz ns ns ns ns ns ns ns AD9520-3 Data Sheet SERIAL CONTROL PORT--IC MODE Table 14. Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 x VS and 0.9 x VS Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSPIKE SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current Output Fall Time from VIHMIN to VILMAX with a Bus Capacitance from 10 pF to 400 pF TIMING Min Typ Unit 0.3 x VS +10 V V A 50 V ns 0.4 250 V ns 0.7 x VS -10 0.015 x VS 20 + 0.1 Cb Test Conditions/Comments Cb = capacitance of one bus line in pF Note that all I2C timing values are referred to VIHMIN (0.3 x VS) and VILMAX levels (0.7 x VS) Clock Rate (SCL, fI2C) Bus Free Time Between a Stop and Start Condition, tIDLE Setup Time for a Repeated Start Condition, tSET; STR Hold Time (Repeated) Start Condition, tHLD; STR 1.3 0.6 0.6 400 kHz s s s Setup Time for Stop Condition, tSET; STP Low Period of the SCL Clock, tLOW High Period of the SCL Clock, tHIGH SCL, SDA Rise Time, tRISE SCL, SDA Fall Time, tFALL Data Setup Time, tSET; DAT 0.6 1.3 0.6 20 + 0.1 Cb 20 + 0.1 Cb 120 s s s ns ns ns Data Hold Time, tHLD; DAT 140 Capacitive Load for Each Bus Line, Cb 1 Max 300 300 880 ns 400 pF After this period, the first clock pulse is generated This is a minor deviation from the original IC specification of 100 ns minimum This is a minor deviation from the original IC specification of 0 ns minimum 1 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL falling edge. Rev. A | Page 14 of 80 Data Sheet AD9520-3 PD, EEPROM, RESET, AND SYNC PINS Table 15. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming SYNC TIMING Pulse Width Low Min Typ Max Unit 0.8 1 -110 V V A A 2 pF 2.0 Test Conditions/Comments Each pin has a 30 k internal pull-up resistor The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor 500 100 ns ns 1.3 ns High speed clock is CLK input signal Max Unit 0.25 x VS 0.65 x VS V V Test Conditions/Comments These pins do not have internal pull-up/pull-down resistors VS is the voltage on the VS pin These pins can be floated to obtain Logic Level 1/2; if floating the pin, connect a capacitor to ground SERIAL PORT SETUP PINS--SP1, SP0 Table 16. Parameter SP1, SP0 Min Logic Level 0 Logic Level 1/2 0.4 x VS Logic Level 1 0.8 x VS Typ V LD, STATUS, AND REFMON PINS Table 17. Parameter OUTPUT CHARACTERISTICS Min Output Voltage High, VOH Output Voltage Low, VOL MAXIMUM TOGGLE RATE 2.7 Max Unit 0.4 100 V V MHz 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor 1.02 MHz 8 kHz Frequency above which the monitor indicates the presence of the reference Frequency above which the monitor indicates the presence of the reference ANALOG LOCK DETECT Capacitance REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range Extended Range LD PIN COMPARATOR Trip Point Hysteresis Typ 1.6 260 V mV Rev. A | Page 15 of 80 Test Conditions/Comments When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 54, Register 0x017, Register 0x01A, and Register 0x01B Applies when mux is set to any divider or counter output or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs can couple to output when any pin is toggling AD9520-3 Data Sheet POWER DISSIPATION Table 18. Parameter POWER DISSIPATION, CHIP Typ Max Unit Power-On Default PLL Locked; One LVPECL Output Enabled 1.32 0.55 1.5 0.64 W W PLL Locked; One CMOS Output Enabled 0.52 0.62 W Distribution Only Mode; VCO Divider On; One LVPECL Output Enabled Distribution Only Mode; VCO Divider Off; One LVPECL Output Enabled Maximum Power, Full Operation 0.39 0.46 W 0.36 0.42 W 1.5 1.7 W PD Power-Down 60 80 mW PD Power-Down, Maximum Sleep 24 33 mW 4 4.8 mW 32 25 40 30 mW mW REF1, REF2 (Single-Ended) On/Off 15 20 mW VCO On/Off PLL Dividers and Phase Detector On/Off LVPECL Channel 67 51 121 104 63 144 mW mW mW LVPECL Driver CMOS Channel 51 145 73 180 mW mW CMOS Driver On/Off Channel Divider Enabled 11 40 24 57 mW mW Zero Delay Block On/Off 30 34 mW VCP Supply POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider On/Off REFIN (Differential) Off Min Test Conditions/Comments Does not include power dissipated in external resistors; all LVPECL outputs terminated with 50 to VCC - 2 V; all CMOS outputs have 10 pF capacitive loading; VS_DRV = 3.3 V No clock; no programming; default register values fREF = 25 MHz; fOUT = 250 MHz; VCO = 2 GHz; VCO divider = 2; one LVPECL output and output divider enabled; zero delay off; ICP = 4.8 mA fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 2 GHz; VCO divider = 2; one CMOS output and output divider enabled; zero delay off; ICP = 4.8 mA fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVPECL output and output divider enabled; zero delay off fCLK = 2 GHz; fOUT = 200 MHz; VCO divider bypassed; one LVPECL output and output divider enabled; zero delay off PLL on; internal VCO = 2000 MHz; VCO divider = 2; all channel dividers on; 12 LVPECL outputs at 125 MHz; zero delay on PD pin pulled low; does not include power dissipated in termination resistors PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b; power-down SYNC, Register 0x230[2] = 1b; power-down distribution reference, Register 0x230[1] = 1b PLL operating; typical closed-loop configuration Power delta when a function is enabled/disabled VCO divider not used Delta between reference input off and differential reference input mode Delta between reference inputs off and one singled-ended reference enabled; double this number if both REF1 and REF2 are powered up Internal VCO disabled; CLK input selected PLL off to PLL on, normal operation; no reference enabled No LVPECL output on to one LVPECL output on; channel divider is set to 1 Second LVPECL output turned on, same channel No CMOS output on to one CMOS output on; channel divider is set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading Additional CMOS outputs within the same channel turned on Delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by-32 Rev. A | Page 16 of 80 Data Sheet AD9520-3 ABSOLUTE MAXIMUM RATINGS Table 19. Parameter VS to GND VCP, CP to GND VS_DRV to GND REFIN, REFIN to GND RSET, LF, BYPASS to GND CPRSET to GND CLK, CLK to GND CLK to CLK SCLK/SCL, SDIO/SDA, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9, OUT10, OUT10, OUT11, OUT11 to GND SYNC, RESET, PD to GND REFMON, STATUS, LD to GND SP0, SP1, EEPROM to GND Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec) 1 Rating -0.3 V to +3.6 V -0.3 V to +5.8 V -0.3 V to +3.6 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -1.2 V to +1.2 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Thermal impedance measurements were taken on a JEDEC JESD51-5 2S2P test board in still air in accordance with JEDEC JESD51-2. See the Thermal Performance section for more details. Table 20. Package Type 64-Lead LFCSP (CP-64-4) -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V 125C -65C to +150C 300C ESD CAUTION See Table 20 for JA. Rev. A | Page 17 of 80 JA 22 Unit C/W AD9520-3 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 (OUT0A) OUT0 (OUT0B) VS_DRV OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9520 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OUT3 (OUT3A) OUT3 (OUT3B) VS_DRV OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS VS OUT8 (OUT8B) OUT8 (OUT8A) OUT7 (OUT7B) OUT7 (OUT7A) VS_DRV OUT6 (OUT6B) OUT6 (OUT6A) NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND. 07216-003 SDIO/SDA SDO GND SP1 SP0 EEPROM RESET PD OUT9 (OUT9A) OUT9 (OUT9B) VS_DRV OUT10 (OUT10A) OUT10 (OUT10B) OUT11 (OUT11A) OUT11 (OUT11B) VS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VS REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS VS CLK CLK CS SCLK/SCL Figure 5. Pin Configuration Table 21. Pin Function Descriptions Input/ Output I Pin Type Power Mnemonic VS Description 3.3 V Power Pins. O O I 3.3 V CMOS 3.3 V CMOS Power REFMON LD VCP 5 O Loop filter CP 6 7 O I 3.3 V CMOS 3.3 V CMOS STATUS REF_SEL 8 I 3.3 V CMOS SYNC 9 10 I O Loop filter Loop filter LF BYPASS 13 I CLK 14 I Differential clock input Differential clock input Reference Monitor (Output). This pin has multiple selectable outputs. Lock Detect (Output). This pin has multiple selectable outputs. Power Supply for Charge Pump (CP); VS VCP 5.25 V. VCP must still be connected to 3.3 V if the PLL is not used. Charge Pump (Output). This pin connects to an external loop filter; it can be left unconnected if the PLL is not used. Programmable Status Output. Reference Select. This pin selects REF1 (low) or REF2 (high) and has an internal 30 k pull-down resistor. Manual Synchronization and Manual Holdover. This pin initiates a manual synchronization and is used for manual holdover. Active low. This pin has an internal 30 k pull-up resistor. Loop Filter (Input). This pin connects internally to the VCO control voltage node. This pin is for bypassing the LDO to ground with a 220 nF capacitor. It can be left unconnected if the PLL is not used. Along with CLK, this pin is the differential input for the clock distribution section. Pin No. 1, 11, 12, 32, 40, 41, 49, 57, 60, 61 2 3 4 CLK Along with CLK, this pin is the differential input for the clock distribution section. If a single-ended input is connected to the CLK pin, connect a 0.1 F bypass capacitor from this pin to ground. Rev. A | Page 18 of 80 Data Sheet AD9520-3 Pin No. 15 Input/ Output I Pin Type 3.3 V CMOS Mnemonic CS 16 I 3.3 V CMOS SCLK/SCL 17 18 19, 59 20 I/O O I I SDIO/SDA SDO GND SP1 21 I 22 I 3.3 V CMOS 3.3 V CMOS GND Three-level logic Three-level logic 3.3 V CMOS 23 24 25 I I O RESET PD OUT9 (OUT9A) 26 O 27, 35, 46, 54 28 I 3.3 V CMOS 3.3 V CMOS LVPECL or CMOS LVPECL or CMOS Power OUT10 (OUT10A) 29 O 30 O 31 O 33 O 34 O 36 O 37 O 38 O 39 O 42 O 43 O 44 O 45 O LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS O SP0 EEPROM OUT9 (OUT9B) VS_DRV OUT10 (OUT10B) OUT11 (OUT11A) OUT11 (OUT11B) OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B) OUT8 (OUT8A) OUT8 (OUT8B) OUT5 (OUT5B) OUT5 (OUT5A) OUT4 (OUT4B) OUT4 (OUT4A) Description Serial Control Port Chip Select; Active Low. This pin has an internal 30 k pull-up resistor. Serial Control Port Clock Signal. This pin has an internal 30 k pull-down resistor in SPI mode but is high impedance in IC mode. Serial Control Port Bidirectional Serial Data In/Out. Serial Control Port Unidirectional Serial Data Out. Ground Pins. Select SPI or IC as the serial interface port and select the IC slave address in IC mode. Three-level logic. This pin is internally biased for the open logic level. Select SPI or IC as the serial interface port and select the IC slave address in IC mode. Three-level logic. This pin is internally biased for the open logic level. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9520 to load the hard-coded default register values at power-up/reset (unless Register 0xB02[1] is used. See the Soft Reset via the Serial Port section). This pin has an internal 30 k pull-down resistor. Note that, to guarantee proper loading of the EEPROM during startup, a high-low-high pulse on the RESET pin should occur after the power supply has stabilized. Chip Reset, Active Low. This pin has an internal 30 k pull-up resistor. Chip Power Down, Active Low. This pin has an internal 30 k pull-up resistor. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Output Driver Power Supply Pins. As a group, these pins can be set to either 2.5 V or 3.3 V. All four pins must be set to the same voltage. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output, or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Rev. A | Page 19 of 80 AD9520-3 Pin No. 47 Input/ Output O 48 O 50 O 51 O 52 O 53 O 55 O 56 O 58 O 62 O 63 I 64 I EPAD Data Sheet Pin Type LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS LVPECL or CMOS Current set resistor Current set resistor Reference input Reference input GND Mnemonic OUT3 (OUT3B) OUT3 (OUT3A) OUT2 (OUT2B) OUT2 (OUT2A) OUT1 (OUT1B) OUT1 (OUT1A) OUT0 (OUT0B) OUT0 (OUT0A) RSET CPRSET REFIN (REF2) REFIN (REF1) GND Description Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. Clock Distribution Current Set Resistor. Connect a 4.12 k resistor from this pin to GND. Charge Pump Current Set Resistor. Connect a 5.1 k resistor from this pin to GND. This resistor can be omitted if the PLL is not used. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. The exposed die pad must be connected to GND. Rev. A | Page 20 of 80 Data Sheet AD9520-3 TYPICAL PERFORMANCE CHARACTERISTICS 350 5 3 CHANNELS--6 LVPECL CURRENT FROM CP PIN (mA) CURRENT (mA) 300 3 CHANNELS--3 LVPECL 250 2 CHANNELS--2 LVPECL 200 150 4 PUMP DOWN PUMP UP 3 2 1 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) 0 07216-108 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), LVPECL Outputs Terminated 50 to VS_DRV - 2 V 07216-111 1 CHANNEL--1 LVPECL Figure 9. Charge Pump Characteristics at CPV = 3.3 V 5 240 3 CHANNELS--6 CMOS CURRENT FROM CP PIN (mA) 220 CURRENT (mA) 200 180 3 CHANNELS--3 CMOS 160 140 2 CHANNELS--2 CMOS 120 4 PUMP DOWN PUMP UP 3 2 1 100 50 100 150 200 250 FREQUENCY (MHz) 0 07216-109 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 10. Charge Pump Characteristics at CPV = 5.0 V -140 PFD PHASE NOISE REFERRED TO PFD INPUT (dBc/Hz) 70 65 60 55 50 45 40 35 30 1.8 1.9 2.0 2.1 VCO FREQUENCY (GHz) Figure 8. KVCO vs. VCO Frequency 2.2 2.3 -145 -150 -155 -160 -165 -170 0.1 07216-010 KVCO (MHz/V) 1.0 VOLTAGE ON CP PIN (V) Figure 7. Total Current vs. Frequency, CLK-to-Output (PLL Off), CMOS Outputs with 10 pF Load 25 1.7 0.5 1 10 100 PFD FREQUENCY (MHz) Figure 11. PFD Phase Noise Referred to PFD Input vs. PFD Frequency Rev. A | Page 21 of 80 07216-013 0 07216-112 1 CHANNEL--1 CMOS 80 AD9520-3 Data Sheet -208 3.5 VS_DRV = 3.3V 3.0 VS_DRV = 3.135V -212 VS_DRV = 2.5V 2.5 -214 VOH (V) PLL FIGURE OF MERIT (dBc/Hz) -210 -216 VS_DRV = 2.35V 2.0 1.5 -218 DIFFERENTIAL INPUT 1.0 -220 0.5 -222 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 INPUT SLEW RATE (V/ns) 0 10k 07216-114 -224 1k 100 RESISTIVE LOAD () 07216-118 SINGLE-ENDED INPUT Figure 15. CMOS Output VOH (Static) vs. RLOAD (to Ground) Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN 0 1.2 -10 0.8 DIFFERENTIAL OUTPUT (V) -20 POWER (dBm) -30 -40 -50 -60 -70 -80 0.4 0 -0.4 -0.8 105 110 115 120 125 130 135 140 145 FREQUENCY (MHz) -1.2 07216-116 -100 100 0 2 4 6 8 10 12 14 16 18 20 22 24 TIME (ns) Figure 13. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; fVCO = 1966.08 MHz 07216-014 -90 Figure 16. LVPECL Output (Differential) at 100 MHz 1.0 0 -10 DIFFERENTIAL SWING (V p-p) -20 POWER (dBm) -30 -40 -50 -60 -70 -80 0.6 0.2 -0.2 -0.6 122.78 122.98 123.18 123.38 FREQUENCY (MHz) Figure 14. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; fVCO = 1966.08 MHz Rev. A | Page 22 of 80 -1.0 0 0.5 1.0 1.5 TIME (ns) Figure 17. LVPECL Differential Voltage Swing at 1600 MHz 07216-015 122.58 07216-117 -90 -100 122.38 Data Sheet AD9520-3 4.0 3.2 3.5 2.8 3.0 1.6 1.2 2.5 2.0 0.8 1.0 0.4 0.5 0 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) 10pF 1.5 20pF 0 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 07216-124 AMPLITUDE (V) 2pF 2.0 07216-018 AMPLITUDE (V) 2.4 Figure 21. CMOS Output Swing vs. Frequency and Capacitive Load Figure 18. CMOS Output with 10 pF Load at 25 MHz -40 2pF LOAD 3.2 -50 2.8 -60 AMPLITUDE (V) PHASE NOISE (dBc/Hz) 10pF LOAD 2.4 2.0 1.6 1.2 0.8 -70 -80 -90 -100 -110 -120 -130 0.4 1 2 3 4 5 6 7 8 9 10 TIME (ns) -150 1k 07216-019 0 10k 100k 1M 10M 100M FREQUENCY (Hz) 07216-023 -140 0 Figure 22. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL at 1750 MHz Figure 19. CMOS Output with 2 pF and 10 pF Load at 250 MHz -40 2.0 -60 PHASE NOISE (dBc/Hz) 1.8 1.6 1.4 1.2 -70 -80 -90 -100 -110 -120 -130 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (GHz) Figure 20. LVPECL Differential Voltage Swing vs. Frequency -150 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 07216-024 -140 07216-123 DIFFERENTIAL SWING (V p-p) -50 Figure 23. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL at 2000 MHz Rev. A | Page 23 of 80 AD9520-3 Data Sheet -40 -100 -50 -110 -70 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -60 -80 -90 -100 -110 -120 -130 -120 -130 -140 -150 10k 100k 1M 10M 100M FREQUENCY (Hz) -160 10 07216-025 -150 1k -110 -120 PHASE NOISE (dBc/Hz) -150 1k 10k 100k 1M 10M 100M 100M -130 -140 -150 -170 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 25. Additive (Residual) Phase Noise, CLK-to-LVPECL at 245.76 MHz, Divide-by-1 Figure 28. Additive (Residual) Phase Noise, CLK-to-CMOS at 50 MHz, Divide-by-20 -100 -110 -110 PHASE NOISE (dBc/Hz) -100 -120 -130 -140 -120 -130 -140 -150 -150 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 07216-129 PHASE NOISE (dBc/Hz) 10M 07216-131 100 FREQUENCY (Hz) -160 10 1M -160 07216-128 -160 10 100k -160 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 29. Additive (Residual) Phase Noise, CLK-to-CMOS at 250 MHz, Divide-by-4 Figure 26. Additive (Residual) Phase Noise, CLK-to-LVPECL at 200 MHz, Divide-by-5 Rev. A | Page 24 of 80 07216-132 PHASE NOISE (dBc/Hz) -110 -140 10k Figure 27. Additive (Residual) Phase Noise, CLK-to-LVPECL at 1600 MHz, Divide-by-1 -100 -130 1k FREQUENCY (Hz) Figure 24. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL at 2250 MHz -120 100 07216-130 -140 Data Sheet AD9520-3 -80 -100 INTEGRATED RMS JITTER (12kHz TO 20MHz): 377 fs -90 -100 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -110 -120 -130 -140 -110 -120 -130 -140 -150 10k 100k 1M 10M 100M FREQUENCY (Hz) -160 1k 07216-033 -160 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 07216-034 -150 NOTES 1. THE LOOP FILTER USED TO GENERATE THIS PLOT IS SHOWN IN FIGURE 41. NOTES 1. THE LOOP FILTER USED TO GENERATE THIS PLOT IS SHOWN IN FIGURE 42. Figure 30. Phase Noise (Absolute) Clock Generation; Internal VCO at 1.966 GHz; PFD = 15.36 MHz; LBW = 40 kHz; LVPECL Output = 122.88 MHz Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 1.866 GHz; PFD = 120 kHz; LBW = 1.84 kHz; LVPECL Output = 155.52 MHz 1000 -140 -150 -160 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 31. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz Rev. A | Page 25 of 80 OC-48 OBJECTIVE MASK AD9520 100 fOBJ 10 1 NOTE: 375UI MAX AT 10Hz OFFSET IS THE MAXIMUM JITTER THAT CAN BE GENERATED BY THE TEST EQUIPMENT. FAILURE POINT IS GREATER THAN 375UI. 0.1 0.01 0.1 1 10 100 JITTER FREQUENCY (kHz) Figure 33. Telcordia GR-253 Jitter Tolerance Plot 1000 07216-134 INPUT JITTER AMPLITUDE (UI p-p) -130 07216-135 PHASE NOISE (dBc/Hz) -120 AD9520-3 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that can be attributed to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that can be attributed to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. A | Page 26 of 80 Data Sheet AD9520-3 DETAILED BLOCK DIAGRAM VS GND RSET DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP REFMON PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 OUT1 OUT1 DIGITAL LOGIC EEPROM RESET OUT2 OUT2 EEPROM OUT3 SP1 SP0 OUT3 SERIAL PORT DECODE DIVIDE BY 1 TO 32 OUT4 I2C INTERFACE OUT5 SCLK/SCL SDIO/SDA SDO CS OUT5 OUT6 OUT6 DIVIDE BY 1 TO 32 LVPECL/CMOS OUTPUT OUT4 SPI INTERFACE OUT7 OUT7 OUT8 OUT8 OUT9 OUT9 DIVIDE BY 1 TO 32 OUT10 OUT10 AD9520 OUT11 Figure 34. Rev. A | Page 27 of 80 07216-028 OUT11 AD9520-3 Data Sheet THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9520 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 50 to Table 61). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. After the desired configuration is programmed, the user can store these values in the on-board EEPROM to allow the part to power up in the desired configuration without user intervention. Mode 0--Internal VCO and Clock Distribution When the internal VCO and PLL are used, the VCO divider must also be used, in most cases, to ensure that the frequency presented to the channel dividers does not exceed its specified maximum frequency (see Table 3). The exceptions to this are the VCO direct mode and cases where the VCO frequency is 1600 MHz. The internal PLL uses an external loop filter to set the loop bandwidth. The external loop filter is also crucial to the loop stability. When the internal VCO is used, the VCO must be calibrated (Register 0x018[0] = 1b) to ensure optimal performance. For internal VCO and clock distribution applications, use the register settings shown in Table 22. Table 22. Settings When Using Internal VCO Register 0x010[1:0] = 00b 0x010 to 0x01E 0x1E1[1] = 1b 0x01C[2:0] 0x1E0[2:0] 0x1E1[0] = 0b 0x018[0] = 0b, 0x232[0] = 1b 0x018[0] = 1b, 0x232[0] = 1b Rev. A | Page 28 of 80 Description PLL normal operation (PLL on) PLL settings; select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration Select VCO as the source Enable reference inputs Set VCO divider Use the VCO divider as the source for the distribution section Clear previous VCO calibration and issue IO_UPDATE (not necessary the first time after power-up, but must be done subsequently) Initiate VCO calibration, issue IO_UPDATE Data Sheet AD9520-3 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 OUT1 OUT1 DIGITAL LOGIC EEPROM RESET OUT2 OUT2 EEPROM OUT3 SP1 SP0 OUT3 SERIAL PORT DECODE DIVIDE BY 1 TO 32 OUT4 I2C INTERFACE OUT5 SCLK/SCL SDIO/SDA SDO CS OUT5 OUT6 OUT6 DIVIDE BY 1 TO 32 LVPECL/CMOS OUTPUT OUT4 SPI INTERFACE OUT7 OUT7 OUT8 OUT8 OUT9 OUT9 DIVIDE BY 1 TO 32 OUT10 OUT10 AD9520 OUT11 Figure 35. Internal VCO and Clock Distribution (Mode 0) Rev. A | Page 29 of 80 07216-030 OUT11 AD9520-3 Data Sheet Mode 1--Clock Distribution or External VCO < 1600 MHz When the internal PLL is used with an external VCO < 1600 MHz, the PLL must be turned on. When the external clock source to be distributed or the external VCO/VCXO is <1600 MHz, a configuration that bypasses the VCO divider can be used. This is the only difference from Mode 2. Bypassing the VCO divider limits the frequency of the clock source to <1600 MHz (due to the maximum input frequency allowed at the channel dividers). Table 24. Settings for Using Internal PLL with External VCO < 1600 MHz Configuration and Register Settings 0x010[1:0] = 00b Register 0x1E1[0] = 1b For clock distribution applications where the external clock is <1600 MHz, use the register settings shown in Table 23. Table 23. Settings for Clock Distribution < 1600 MHz Register 0x010[1:0] = 01b 0x1E1[0] = 1b 0x1E1[1] = 0b Description PLL asynchronous power-down (PLL off ) Bypass the VCO divider as the source for the distribution section Select CLK as the source Description Bypass the VCO divider as the source for the distribution section PLL normal operation (PLL on) along with other appropriate PLL settings in Register 0x010 to Register 0x01E An external VCO/VCXO requires an external loop filter that must be connected between the CP pin and the tuning pin of the VCO/VCXO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO/VCXO being used. Table 25. Setting the PFD Polarity Register 0x010[7] = 0b 0x010[7] = 1b Rev. A | Page 30 of 80 Description PFD polarity positive (higher control voltage produces higher frequency) PFD polarity negative (higher control voltage produces lower frequency) Data Sheet AD9520-3 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 OUT1 OUT1 DIGITAL LOGIC EEPROM RESET OUT2 OUT2 EEPROM OUT3 SP1 SP0 OUT3 SERIAL PORT DECODE DIVIDE BY 1 TO 32 OUT4 I2C INTERFACE OUT5 SCLK/SCL SDIO/SDA SDO CS OUT5 OUT6 OUT6 DIVIDE BY 1 TO 32 LVPECL/CMOS OUTPUT OUT4 SPI INTERFACE OUT7 OUT7 OUT8 OUT8 OUT9 OUT9 DIVIDE BY 1 TO 32 OUT10 OUT10 AD9520 OUT11 Figure 36. Clock Distribution or External VCO < 1600 MHz (Mode 1) Rev. A | Page 31 of 80 07216-031 OUT11 AD9520-3 Data Sheet Mode 2--High Frequency Clock Distribution; CLK or External VCO > 1600 MHz The AD9520 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/ divide-by-4/ divide-by-5/divide-by-6). This is a distribution only mode that allows for an external input up to 2400 MHz (see Table 3). The maximum frequency that can be applied to the channel dividers is 1600 MHz; therefore, higher input frequencies must be divided down before reaching the channel dividers. When the PLL is enabled, this routing also allows the use of the PLL with an external VCO or VCXO with a frequency of less than 2400 MHz. In this configuration, the internal VCO is not used and is powered off. The external VCO/VCXO feeds directly into the prescaler. The register settings shown in Table 26 are the default values of these registers at power-up or after a reset operation. Table 26. Default Register Settings for Clock Distribution Mode Register 0x010[1:0] = 01b 0x1E0[2:0] = 000b 0x1E1[0] = 0b 0x1E1[1] = 0b When the internal PLL is used with an external VCO, the PLL must be turned on. Table 27. Settings When Using an External VCO Register 0x010[1:0] = 00b 0x010 to 0x01E 0x1E1[1] = 0b Description PLL normal operation (PLL on) PLL settings; select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration Select CLK as the source An external VCO requires an external loop filter that must be connected between CP and the tuning pin of the VCO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO being used. Table 28. Setting the PFD Polarity Register 0x010[7] = 0b 0x010[7] = 1b Description PLL asynchronous power-down (PLL off ) Set VCO divider = 2 Use the VCO divider Select CLK as the source Rev. A | Page 32 of 80 Description PFD polarity positive (higher control voltage produces higher frequency) PFD polarity negative (higher control voltage produces lower frequency) Data Sheet AD9520-3 VS RSET GND REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 OUT1 OUT1 DIGITAL LOGIC EEPROM RESET OUT2 OUT2 EEPROM OUT3 SP1 SP0 OUT3 SERIAL PORT DECODE DIVIDE BY 1 TO 32 OUT4 I2C INTERFACE OUT5 SCLK/SCL SDIO/SDA SDO CS OUT5 OUT6 OUT6 DIVIDE BY 1 TO 32 LVPECL/CMOS OUTPUT OUT4 SPI INTERFACE OUT7 OUT7 OUT8 OUT8 OUT9 OUT9 DIVIDE BY 1 TO 32 OUT10 OUT10 AD9520 OUT11 Figure 37. High Frequency Clock Distribution or External VCO > 1600 MHz (Mode 2) Rev. A | Page 33 of 80 07216-029 OUT11 AD9520-3 Data Sheet Phase-Locked Loop (PLL) VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS PROGRAMMABLE R DELAY STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN BUF REFIN BYPASS CPRSET VCP LOCK DETECT PLL REFERENCE REF_SEL HOLD STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK VS_DRV FROM CHANNEL DIVIDER 0 1 07216-064 CLK 0 Figure 38. PLL Functional Block Diagram The AD9520 includes an on-chip PLL with an on-chip VCO. The PLL blocks can be used either with the on-chip VCO to create a complete phase-locked loop or with an external VCO or VCXO. The PLL requires an external loop filter, which usually consists of a small number of capacitors and resistors. The configuration and components of the loop filter help to establish the loop bandwidth and stability of the operating PLL. The AD9520 PLL is useful for generating clock frequencies from a supplied reference frequency. This includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution. In addition, the PLL can be used to clean up jitter and phase noise on a noisy reference. The exact choice of PLL parameters and loop dynamics is application specific. The flexibility and depth of the AD9520 PLL allow the part to be tailored to function in many different applications and signal environments. Configuration of the PLL The AD9520 allows flexible configuration of the PLL, which accommodates various reference frequencies, PFD comparison frequencies, VCO frequencies, internal or external VCO/VCXO, and loop dynamics. This is accomplished by the various settings for the R divider, N divider, PFD polarity (applicable only to the external VCO/VCXO), antibacklash pulse width, charge pump current, selection of internal VCO or external VCO/ VCXO, and the loop bandwidth. These are managed through programmable register settings (see Table 50 and Table 54) and by the design of the external loop filter. Successful PLL operation and satisfactory PLL loop performance are highly dependent upon proper configuration of the PLL settings, and the design of the external loop filter is crucial to the proper operation of the PLL. Phase Frequency Detector (PFD) The PFD takes inputs from the R divider and the N divider and produces an output proportional to the phase and frequency difference between them. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. The antibacklash pulse width is set by Register 0x017[1:0]. An important limit to keep in mind is the maximum frequency allowed into the PFD. The maximum input frequency into the PFD is a function of the antibacklash pulse setting, as specified in the phase/frequency detector (PFD) parameter in Table 2. Charge Pump (CP) The charge pump is controlled by the PFD. The PFD monitors the phase and frequency relationship between its two inputs and tells the CP to pump up or pump down to charge or discharge the integrating node (part of the loop filter). The integrated and filtered CP current is transformed into a voltage that drives the tuning node of the internal VCO through the LF pin (or the tuning pin of an external VCO) to move the VCO frequency up or down. The CP can be set (Register 0x010[3:2]) for high impedance (allows holdover operation), for normal operation (attempts to lock the PLL loop), or for pump-up or pump-down (test modes). The CP current is programmable in eight steps from (nominally) 0.6 mA to 4.8 mA. The CP current LSB is set by the CPRSET resistor, which is nominally 5.1 k. The exact value of the CP current can be calculated with the following equation: ADIsimCLKTM is a free program that can help with the design and exploration of the capabilities and features of the AD9520, including the design of the PLL loop filter. Rev. A | Page 34 of 80 ICP (A) = 3.06 CPRSET () Data Sheet AD9520-3 C1 62pF C12 220nF Figure 41. Typical PLL Loop Filter Used for Clock Generation R2 3k CP C1 1.5nF C2 4.7F R1 2.1k LF C3 2.2nF BYPASS BYPASS CAPACITOR FOR LDO C12 220nF Figure 42. Typical PLL Loop Filter Used for Clock Cleanup When using the internal VCO, reference the external loop filter to the BYPASS pin for optimal noise and spurious performance. Figure 39 shows an example of an external loop filter for the PLL. This third-order design usually offers the best performance. A loop filter must be calculated for each desired PLL configuration. The component values depend upon the VCO frequency, the KVCO, the PFD frequency, the CP current, the desired loop bandwidth, and the desired phase margin. The loop filter affects the phase noise, loop settling time, and loop stability. A knowledge of PLL theory is necessary for understanding loop filter design. Available tools, such as ADIsimCLK, can help with the calculation of a loop filter according to the application requirements. LF 31pF R2 CP R1 C2 C3 07216-142 BYPASS C1 CBP = 220nF Figure 39. Example of External Loop Filter for a PLL Using the Internal VCO When using an external VCO, ensure that the external loop filter is referenced to ground. See Figure 40for an example of an external loop filter for a PLL using an external VCO. AD9520 CLK/CLK EXTERNAL VCO/VCXO R2 CP R1 C2 The AD9520 features a flexible PLL reference input circuit that allows a fully differential input, two separate single-ended inputs, or a 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip maintaining amplifier. An optional reference clock doubler can be used to double the PLL reference frequency. The input frequency range for the reference inputs is specified in Table 2. Both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals. Either a differential or a single-ended reference must be specifically enabled. All PLL reference inputs are off by default. C3 When the differential reference input is selected, the self-bias level of the two sides is offset slightly (~100 mV, see Table 2) to prevent chattering of the input buffer when the reference is slow or missing. This increases the voltage swing that is required of the driver and overcomes the offset. The differential reference input can be driven by either ac-coupled LVDS or ac-coupled LVPECL signals. The single-ended inputs can be driven by either a dc-coupled CMOS level signal or an ac-coupled sine wave or square wave. To avoid input buffer chatter when a single-ended, ac-coupled input signal stops toggling, the user can set Register 0x018[7] to 1b. This shifts the dc offset bias point down 140 mV. To increase isolation and reduce power, each single-ended input can be independently powered down. 07216-143 C1 PLL Reference Inputs The differential input and the single-ended inputs share two pins, REFIN and REFIN (REF1 and REF2, respectively). The desired reference input type is selected and controlled by Register 0x01C (see Table 50 and Table 54). AD9520 CHARGE PUMP LF C3 33pF BYPASS PLL External Loop Filter CHARGE PUMP C2 240nF R1 820 BYPASS CAPACITOR FOR LDO The on-chip VCO is powered by an on-chip, low dropout (LDO), linear voltage regulator. The LDO provides some isolation of the VCO from variations in the power supply voltage level. The BYPASS pin should be connected to ground by a 220 nF capacitor to ensure stability. This LDO employs the same technology that is used in the anyCAP(R) line of regulators from Analog Devices, Inc., making it insensitive to the type of capacitor used. Driving an external load from the BYPASS pin is not supported. VCO R2 390 CP 07216-234 The AD9520 includes an on-chip VCO covering the frequency range shown in Table 2. The calibration procedure ensures that the VCO operating voltage is centered for the desired VCO frequency. The VCO must be calibrated when the VCO loop is first set up, as well as any time the nominal VCO frequency changes. However, once the VCO is calibrated, the VCO has sufficient operating range to stay locked over temperature and voltage extremes without needing additional calibration. See the VCO Calibration section for additional information. Figure 41 and Figure 42 show the typical PLL loop filters that are used to generate the plots in Figure 30 and Figure 32, respectively. 07216-235 On-Chip VCO Figure 40. Example of External Loop Filter for a PLL Using an External VCO Rev. A | Page 35 of 80 AD9520-3 Data Sheet The differential reference input receiver is powered down when the differential reference input is not selected or when the PLL is powered down. The single-ended buffers power down when the PLL is powered down or when their respective individual power-down registers are set. When the differential mode is selected, the single-ended inputs are powered down. clock disappears. When using the reference switchover, the singleended reference inputs should be dc-coupled CMOS levels (with the AD9520 dc offset feature disabled). Alternatively, the inputs can be ac-coupled and dc offset feature enabled. In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to dc couple to these inputs. If the differential REFIN is driven by a single-ended signal, the unused side (REFIN) should be decoupled via a suitable capacitor to a quiet ground. Figure 43 shows the equivalent circuit of REFIN. Reference switchover can be performed manually or automatically. Manual switchover is performed either through Register 0x01C or by using the REF_SEL pin. Manual switchover requires the presence of a clock on the reference input that is being switched to; otherwise, the deglitching feature must be disabled in Bit 7 of Register 0x01C. The reference switching logic fails if this condition is not met, and the PLL does not reacquire. VS Automatic revertive switchover relies on the REFMON pin to indicate when REF1 disappears. By programming Register 0x01B = 0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed to be high when REF1 is invalid, which commands the switch to REF2. When REF1 is valid again, the REFMON pin goes low, and the part again locks to REF1. The STATUS pin can also be used for this function, and REF2 can be used as the preferred reference. 85k REF1 VS 10k 12k REFIN 150 REFIN 150 10k Keep in mind, however, that the minimum input amplitude for the reference inputs is greater when the dc offset is turned on. A switchover deglitch feature ensures that the PLL does not receive rising edges that are far out of alignment with the newly selected reference. For the switchover deglitch feature to work correctly, the presence of a clock is required on the reference input that is being switched to. The deglitching feature can also be disabled (Register 0x01C[7]). 10k VS REF2 85k 07216-066 Automatic nonrevertive switching is not supported. Reference Divider R Figure 43. REFIN Equivalent Circuit for Non-XTAL Mode Crystal mode is nearly identical to differential mode. The user enables a maintaining amplifier by setting the enable XTAL OSC bit, and putting a series resonant, AT fundamental cut crystal across the REFIN and REFIN pins. Reference Switchover The AD9520 supports dual single-ended CMOS inputs, as well as a single differential reference input. In the dual single-ended reference mode, the AD9520 supports automatic revertive and manual PLL reference clock switching between REF1 (on Pin REFIN) and REF2 (on Pin REFIN). This feature supports networking and other applications that require smooth switching of redundant references. When used in conjunction with the automatic holdover function, the AD9520 can achieve a worstcase reference input switchover with an output frequency disturbance as low as 10 ppm. The AD9520 features a dc offset option in single-ended mode. This option is designed to eliminate the risk of the reference inputs chattering when they are ac-coupled and the reference The reference inputs are routed to the reference divider, R. R is a 14-bit counter that can be set to any value from 0 to 16,383 by writing to Register 0x011 and Register 0x012 (both R = 0 and R = 1 give divide-by-1.) The output of the R divider goes to one of the PFD inputs to be compared with the VCO frequency divided by the N divider. The frequency applied to the PFD must not exceed the maximum allowable frequency, which depends on the antibacklash pulse setting (see Table 2). The R divider has its own reset. The R divider can be reset using the shared reset bit of the R, A, and B counters. It can also be reset by a SYNC operation. VCO/VCXO Feedback Divider N--P, A, and B The N divider is a combination of a prescaler, P, and two counters, A and B. The total divider value is N = (P x B) + A where P can be 2, 4, 8, 16, or 32. Rev. A | Page 36 of 80 Data Sheet AD9520-3 Prescaler The prescaler of the AD9520 allows for two modes of operation: a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM) mode where the prescaler divides by P and (P + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of operation are given in Table 54, Register 0x016[2:0]. Not all modes are available at all frequencies (see Table 2). When operating the AD9520 in dual modulus mode, P/(P + 1), the equation used to relate the input reference frequency to the VCO output frequency is fVCO = (fREF/R) x (P x B + A) = fREF x N/R However, when operating the prescaler in FD Mode 1, FD Mode 2, or FD Mode 3, the A counter is not used (A = 0; the divide is a fixed divide of P = 2, 4, 8, 16, or 32) and the equation simplifies to fVCO = (fREF/R) x (P x B) = fREF x N/R By using combinations of DM and FD modes, the AD9520 can achieve values of N from 1 to 262,175. Table 29 shows how a 10 MHz reference input can be locked to any integer multiple of N. Note that the same value of N can be derived in different ways, as illustrated by the case of N = 12. The user can choose a fixed divide mode of P = 2 with B = 6; use the dual modulus mode of 2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with A = 0, B = 3. A and B Counters The B counter must be 3 or bypassed, and unlike the R counter, A = 0 is actually zero. When the prescaler is in dual modulus mode, the A counter must be equal to or less than the B counter. The maximum input frequency to the A/B counter is reflected in the maximum prescaler output frequency (~300 MHz) that is specified in Table 2. This is the prescaler input frequency (VCO or CLK) divided by P. For example, a dual modulus mode of P = 8/9 is not allowed if the VCO frequency is greater than 2400 MHz because the frequency going to the A/B counter is too high. When the AD9520 B counter is bypassed (B = 1), the A counter should be set to zero, and the overall resulting divide is equal to the prescaler setting, P. The possible divide ratios in this mode are 1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an external VCO/VCXO is used because the frequency range of the internal VCO requires an overall feedback divider greater than 32. Although manual reset is not normally required, the A/B counters have their own reset bit. Alternatively, the A and B counters can be reset using the shared reset bit of the R, A, and B counters. Note that these reset bits are not self-clearing. R, A, and B Counters--SYNC Pin Reset The R, A, and B counters can be reset simultaneously through the SYNC pin. This function is controlled by Register 0x019[7:6] (see Table 54). The SYNC pin reset is disabled by default. R and N Divider Delays Both the R and N dividers feature a programmable delay cell. These delays can be enabled to allow adjustment of the phase relationship between the PLL reference clock and the VCO or CLK. Each delay is controlled by three bits. The total delay range is about 1 ns. See Register 0x019 in Table 2 and Table 54. Table 29. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N fREF (MHz) 10 10 10 10 10 10 10 10 R 1 1 1 1 1 1 1 1 P 1 2 1 1 1 2 2 2 A X1 X1 X1 X1 X1 X1 0 1 B 1 1 3 4 5 3 3 3 N 1 2 3 4 5 6 6 7 fVCO (MHz) 10 20 30 40 50 60 60 70 Mode FD FD FD FD FD FD DM DM 10 10 10 10 10 10 10 10 10 1 1 1 1 1 10 1 1 10 2 2 8 8 16 32 8 16 32 2 1 6 7 7 6 0 0 0 3 4 18 18 9 47 25 15 75 8 9 150 151 151 1510 200 240 2400 80 90 1500 1510 1510 1510 2000 2400 2400 DM DM DM DM DM DM DM DM DM 1 Description P = 1, B = 1 (A and B counters are bypassed). P = 2, B = 1 (A and B counters are bypassed). A counter is bypassed. A counter is bypassed. A counter is bypassed. A counter is bypassed. Maximum frequency into prescaler in P = 2/3 mode is 200 MHz. If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz to 300 MHz, use P = 1 and N = 7 or 11, respectively. X = don't care. Rev. A | Page 37 of 80 AD9520-3 Data Sheet By selecting the proper output through the mux on each pin, the DLD function is available at the LD, STATUS, and REFMON pins. The digital lock detect circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold). The loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). Note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lock window to occur without chattering on the lock indicator. The lock detect window timing depends on the value of the CPRSET resistor, as well as three settings: the digital lock detect window bit (Register 0x018[4]), the antibacklash pulse width bit (Register 0x017[1:0], see Table 2), and the lock detect counter (Register 0x018[6:5]). The lock and unlock detection values listed in Table 2 are for the nominal value of CPRSET = 5.11 k. Doubling the CPRSET value to 10 k doubles the values in Table 2. A lock is not indicated until there is a programmable number of consecutive PFD cycles with a time difference that is less than the lock detect threshold. The lock detect circuit continues to indicate a lock until a time difference that is greater than the unlock threshold occurs on a single subsequent cycle. For the lock detect to work properly, the period of the PFD frequency must be greater than the unlock threshold. The number of consecutive PFD cycles required for lock is programmable (Register 0x018[6:5]). Note that, in certain low (<500 Hz) loop bandwidth, high phase margin cases, the DLD may chatter during acquisition, which can cause the AD9520 to automatically enter and exit holdover. To avoid this problem, it is recommended that the user provide for a capacitor to ground on the LD pin such that current source digital lock detect (CSDLD) mode can be used. Analog Lock Detect (ALD) The AD9520 provides an ALD function that can be selected for use at the LD pin. There are two operating modes for ALD: * N-channel open-drain lock detect. This signal requires a pull-up resistor to the positive supply, VS. The output is normally high with short, low going pulses. Lock is indicated by the minimum duty cycle of the low-going pulses. P-channel open-drain lock detect. This signal requires a pull-down resistor to GND. The output is normally low with short, high going pulses. Lock is indicated by the minimum duty cycle of the high-going pulses. VS = 3.3V AD9520 R2 LD ALD R1 VOUT Current Source Digital Lock Detect (CSDLD) During the PLL locking sequence, it is normal for the DLD signal to toggle a number of times before remaining steady when the PLL is completely locked and stable. There may be applications where it is desirable to have DLD asserted only after the PLL is solidly locked. This is possible by using the current source digital lock detect function. AD9520 110A DLD LD VOUT C LD PIN COMPARATOR REFMON OR STATUS Figure 45. Current Source Digital Lock Detect The current source lock detect provides a current of 110 A when DLD is true and shorts to ground when DLD is false. If a capacitor is connected to the LD pin, it charges at a rate determined by the current source during the DLD true time but is discharged nearly instantly when DLD is false. By monitoring the voltage at the LD pin (top of the capacitor), LD = high happens only after the DLD is true for a sufficiently long time. Any momentary DLD false resets the charging. By selecting a properly sized capacitor, it is possible to delay a lock detect indication until the PLL is stably locked and the lock detect does not chatter. To use current source digital lock detect, do the following: * * * Place a capacitor to ground on the LD pin. Set Register 0x01A[5:0] = 0x04. Enable the LD pin comparator (Register 0x01D[3] = 1b). The LD pin comparator senses the voltage on the LD pin, and the comparator output can be made available at the REFMON pin control (Register 0x01B[4:0]) or the STATUS pin control (Register 0x017[7:2]). The internal LD pin comparator trip point and hysteresis are given in Table 17. The voltage on the capacitor can also be sensed by an external comparator that is connected to the LD pin. In this case, enabling the on-board LD pin comparator is not necessary. The user can asynchronously enable individual clock outputs only when CSDLD is high. To enable this feature, set the appropriate bits in the enable output on the CSDLD registers (Register 0x0FC and Register 0x0FD). C 07216-067 * The analog lock detect function requires an RC filter to provide a logic level indicating lock/unlock. The ADIsimCLK tool can be used to help the user select the right passive component values for ALD to ensure its correct operation. 07216-068 Digital Lock Detect (DLD) Figure 44. Example of Analog Lock Detect Filter Using N-Channel Open-Drain Driver Rev. A | Page 38 of 80 Data Sheet AD9520-3 External VCXO/VCO Clock Input (CLK/CLK) This differential input is used to drive the AD9520 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors. CLOCK INPUT STAGE VS CLK CLK 2.5k 2.5k 5k 07216-032 5k Figure 46. CLK Equivalent Input Circuit The CLK/CLK input can be used either as a distribution only input (with the PLL off) or as a feedback input for an external VCO/VCXO using the internal PLL when the internal VCO is not used. These inputs are also used as a feedback path for the external zero delay mode. Holdover Mode The AD9520 PLL has a holdover function. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. This function is useful when the PLL reference clock is lost. Holdover is implemented by placing the charge pump in a high impedance state. Without this function, the charge pump is placed into a constant pump-up or pump-down state, resulting in a massive VCO frequency shift. Because the charge pump is placed in a high impedance state, any leakage that occurs at the charge pump output or the VCO tuning node causes a drift of the VCO frequency. This drift can be mitigated by using a loop filter that contains a large capacitive component because this drift is limited by the current leakage-induced slew rate (ILEAK/C) of the VCO control voltage. Both a manual holdover mode, using the SYNC pin, and an automatic holdover mode are provided. To use either function, the holdover function must be enabled (Register 0x01D[0]). Manual/External Holdover Mode A manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the SYNC pin is asserted low. This operation is edge sensitive, not level sensitive. The charge pump enters a high impedance state immediately. To take the charge pump out of a high impedance state, take the SYNC pin high. The charge pump then leaves the high impedance state synchronously with the next PFD rising edge from the reference clock. This prevents extraneous charge pump events from occurring during the time between SYNC going high and the next PFD event. This also means that the charge pump stays in a high impedance state if no reference clock is present. The B counter (in the N divider) is reset synchronously with the charge pump, leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N dividers for faster settling of the PLL. Because the prescaler is not reset, this feature works best when the B and R numbers are close, resulting in a smaller phase difference for the loop to settle out. When using this mode, set the channel dividers to ignore the SYNC pin (at least after an initial SYNC event). If the dividers are not set to ignore the SYNC pin, the distribution outputs turn off when SYNC is taken low to put the part into holdover mode. The channel divider ignore SYNC function is programmed in Bit 6 of Register 0x191, Register 0x194, Register 0x197, and Register 0x19A for Channel Divider 0, Channel Divider 1, Channel Divider 2, and Channel Divider 3, respectively. Automatic/Internal Holdover Mode When enabled, this function automatically places the charge pump into a high impedance state when the loop loses lock. The assumption is that the only reason the loop loses lock is due to the PLL losing the reference clock; therefore, the holdover function puts the charge pump into a high impedance state to maintain the VCO frequency as close as possible to the original frequency before the reference clock disappeared. The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD mode. The LD comparator can be disabled (Register 0x01D[3]), which causes the holdover function to always sense LD as being high. If DLD is used, it is possible for the DLD signal to chatter while the PLL is reacquiring lock. The holdover function may retrigger, thereby preventing the holdover mode from terminating. Use of the current source lock detect mode is recommended to avoid this situation (see the Current Source Digital Lock Detect (CSDLD) section). When in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. As in the external holdover mode, the B counter (in the N divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N dividers for faster settling of the PLL and reduces frequency errors during settling. Because the prescaler is not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out. After leaving holdover, the loop then reacquires lock, and the LD pin must go high (if Register 0x01D[3] = 1b) before it can reenter holdover (CP high impedance). The holdover function always responds to the state of the currently selected reference (Register 0x01C). If the loop loses lock during a reference switchover (see the Reference Switchover section), holdover is triggered briefly until the next reference clock edge at the PFD. Rev. A | Page 39 of 80 AD9520-3 Data Sheet The following registers affect the automatic/internal holdover function: A flowchart of the automatic/internal holdover function operation is shown in Figure 47. * PLL ENABLED LOOP OUT OF LOCK. DIGITAL LOCK DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK, AS DETERMINED BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD. NO DLD == LOW YES * NO * REG 0x01D[3]: LD PIN COMPARATOR ENABLE. 0b = DISABLE; 1b = ENABLE. WHEN DISABLED, THE HOLDOVER FUNCTION ALWAYS SENSES THE LD PIN AS HIGH. WAS LD PIN == HIGH WHEN DLD WENT LOW? * YES CHARGE PUMP IS MADE HIGH IMPEDANCE. PLL COUNTERS CONTINUE OPERATING NORMALLY. HIGH IMPEDANCE CHARGE PUMP * * YES Register 0x018[6:5]--lock detect counter. This changes how many consecutive PFD cycles with edges inside the lock detect window are required for the DLD indicator to indicate lock. This impacts the time required before the LD pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be reengaged. Register 0x018[3]--disable digital lock detect. This bit must be set to 0b to enable the DLD circuit. Automatic/internal holdover does not operate correctly without the DLD function enabled. Register 0x01A[5:0]--lock detect pin control. Set these bits to 000100b to program the current source lock detect mode if using the LD pin comparator. Load the LD pin with a capacitor of an appropriate value. Register 0x01D[3]--LD pin comparator enable. 1b = enable; 0b = disable. When disabled, the holdover function always senses the LD pin as high. Register 0x01D[1]--external holdover control. Register 0x01D[0]--holdover enable. If holdover is disabled, both external and automatic/internal holdover are disabled. NO In the following example, automatic holdover is configured with CHARGE PUMP REMAINS HIGH IMPEDANCE UNTIL THE REFERENCE RETURNS. REFERENCE EDGE AT PFD? YES * * * YES RELEASE CHARGE PUMP HIGH IMPEDANCE The following registers are set (in addition to the normal PLL registers): TAKE CHARGE PUMP OUT OF HIGH IMPEDANCE. PLL CAN NOW RESETTLE. * * YES DLD == HIGH WAIT FOR DLD TO GO HIGH. THIS TAKES 5 TO 255 CYCLES (PROGRAMMING OF THE DLD DELAY COUNTER) WITH THE REFERENCE AND FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT THE PFD. THIS ENSURES THAT THE HOLDOVER FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK BEFORE THE HOLDOVER FUNCTION CAN BE RETRIGGERED. Figure 47. Flowchart of Automatic/Internal Holdover Mode * * 07216-069 NO Automatic reference switchover, prefer REF1. Digital lock detect: five PFD cycles, high range window. Automatic holdover using the LD pin comparator. * * * * * * Rev. A | Page 40 of 80 Register 0x018[6:5] = 00b; lock detect counter = five cycles. Register 0x018[4] = 0b; digital lock detect window = high range. Register 0x018[3] = 1b; disable DLD normal operation. Register 0x01A[5:0] = 000100b; program LD pin control to current source lock detect mode. Register 0x01C[4] = 1b; enable automatic switchover. Register 0x01C[3] = 0b; prefer REF1. Register 0x01C[2:1] = 11b; enable REF1 and REF2 input buffers. Register 0x01D[3] = 1b; enable LD pin comparator. Register 0x01D[1] = 0b; disable external holdover mode and use automatic/internal holdover mode. Register 0x01D[0] = 1b; enable holdover. Data Sheet AD9520-3 VS GND RSET DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF REFIN BYPASS LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP REFMON PROGRAMMABLE R DELAY REF_SEL HOLD VCO STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK FROM CHANNEL DIVIDER 0 1 VS_DRV 07216-070 CLK 0 Figure 48. Reference and VCO/CLK Frequency Status Monitors Frequency Status Monitors The AD9520 contains three frequency status monitors that are used to indicate if the PLL reference (or references, in the case of single-ended mode) and the VCO/CLK input have fallen below a threshold frequency. Note that the VCO frequency monitor becomes a CLK input frequency monitor if the CLK input is selected instead of the internal VCO. Figure 48 shows the location of the frequency status monitors in the PLL. The PLL reference monitors have two threshold frequencies: normal and extended (see Table 17). The reference frequency monitor thresholds are set in Register 0x01A[6]. VCO Calibration The AD9520 on-chip VCO must be calibrated to ensure proper operation over process and temperature. The VCO calibration is controlled by a calibration controller running off a divided REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present. The REFIN clock must come from a stable source external to the AD9520. VCO calibration can be performed two ways: automatically at power-up and manually. Automatic VCO calibration occurs when the EEPROM is set to automatically load the preprogrammed values in the EEPROM, and then automatically calibrate the VCO. For the automatic calibration to complete, a valid reference must be provided at power-up. If no valid reference is provided, the user must calibrate the VCO manually. During the first initialization after a power-up or a reset of the AD9520, a manual VCO calibration sequence is initiated by setting Register 0x018[0] = 1b. This can be done as part of the initial setup before executing an update all registers operation (IO_UPDATE, Register 0x232[0] = 1b). Subsequent to the initial setup, a VCO calibration sequence is initiated by resetting Register 0x018[0] = 0b, executing an IO_UPDATE, setting Register 0x018[0] = 1b, and executing another IO_UPDATE. A readback bit (Register 0x01F[6]) indicates when VCO calibration is finished by returning a logic true (that is, 1b). The sequence of operations for the VCO calibration follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Program the PLL registers to the proper values for the PLL loop. Note that the VCO divider (Register 0x1E0[2:0]) must not be set to static during VCO calibration. Ensure that the input reference signal is present. For initial setting of the registers after a power-up or reset, initiate a VCO calibration by setting Register 0x018[0] = 1b. Subsequently, whenever a calibration is desired, set Register 0x018[0] = 0b, update registers; and then set Register 0x018[0] = 1b, update registers. A SYNC operation is initiated internally, causing the outputs to go to a static state determined by normal SYNC function operation. VCO is calibrated to the desired setting for the requested VCO frequency. Internally, the SYNC signal is released, allowing outputs to continue clocking. The PLL loop is closed. The PLL locks. A SYNC is executed during the VCO calibration; therefore, the outputs of the AD9520 are held static during the calibration, which prevents unwanted frequencies from being produced. However, at the end of a VCO calibration, the outputs may resume clocking before the PLL loop is completely settled. Rev. A | Page 41 of 80 AD9520-3 Data Sheet The VCO calibration clock divider is set as shown in Table 54 (Register 0x018[2:1]). The calibration divider divides the PFD frequency (reference frequency divided by R) down to the calibration clock. The calibration occurs at the PFD frequency divided by the calibration divider setting. Lower VCO calibration clock frequencies result in longer times for a calibration to be done. The VCO calibration clock frequency is given by In addition, because the calibration procedure results in rapid changes in the VCO frequency, the distribution section is automatically placed in SYNC until the calibration is finished. Therefore, this temporary loss of outputs must be expected. A VCO calibration should be initiated in the following conditions: * fCAL_CLOCK = fREFIN/(R x cal_div) After changing any of the PLL R, P, B, and A divider settings, or after a change in the PLL reference clock frequency. This, in effect, means any time a PLL register or reference clock is changed such that a different VCO frequency results. When system calibration is desired. The VCO is designed to operate properly over extremes of temperature even when it is first calibrated at the opposite extreme. However, a VCO calibration can be initiated at any time, if desired. where: fREFIN is the frequency of the REFIN signal. R is the value of the R counter. cal_div is the division set for the VCO calibration divider (Register 0x018[2:1]). * Choose a calibration divider such that the calibration frequency is less than 6.25 MHz. Table 30 shows the appropriate value for the calibration divider. ZERO DELAY OPERATION Table 30. VCO Calibration Divider Values for Different Phase Detector Frequencies PFD Rate (MHz) <12 12 to 25 25 to 50 50 to 100 Recommended VCO Calibration Divider Any 4, 8, 16 8, 16 16 The VCO calibration takes 4400 calibration clock cycles. Therefore, the VCO calibration time in PLL reference clock cycles is given by Time to Calibrate VCO = 4400 x R x cal_div PLL Reference Clock Cycles Table 31. Example Time to Complete a VCO Calibration with Different fREFIN Frequencies fREFIN (MHz) 100 10 10 R Divider 1 10 100 PFD 100 MHz 1 MHz 100 kHz Time to Calibrate VCO 88 s 8.8 ms 88 ms A VCO calibration must be manually initiated, which allows for flexibility in deciding what order to program registers and when to initiate a calibration, instead of having it occur every time the values of certain PLL registers change. For example, this allows for the VCO frequency to be changed by small amounts without having an automatic calibration occur each time; this should be done with caution and only when the user knows the VCO control voltage will not exceed the nominal best performance limits. For example, a few 100 kHz steps are fine, but a few MHz may not be. Zero delay operation aligns the phase of the output clocks with the phase of the external PLL reference input. There are two zero delay modes on the AD9520: internal and external. Internal Zero Delay Mode The internal zero delay function of the AD9520 is achieved by feeding the output of Channel Divider 0 back to the PLL N divider. In Figure 49, the change in signal routing for internal zero delay mode is shown in blue. Set Register 0x01E[2:1] = 01b to select internal zero delay mode. In the default internal zero delay mode, the output of Channel Divider 0 is routed back to the PLL (N divider) through MUX3 and MUX1 (feedback path shown in blue in Figure 49). The PLL synchronizes the phase/edge of the output of Channel Divider 0 with the phase/edge of the reference input. External zero delay mode must be used if Channel Divider 1, Channel Divider 2, or Channel Divider 3 is to be used for zero delay feedback. This is accomplished by changing the value in Register 0x01E[4:3]. Because the channel dividers are synchronized to each other, the outputs of the channel divider are synchronous with the reference input. Both the R delay and the N delay inside the PLL can be programmed to compensate for the propagation delay from the output drivers and PLL components to minimize the phase offset between the clock output and the reference input to achieve zero delay. Rev. A | Page 42 of 80 Data Sheet AD9520-3 REFIN/ REFIN R DIVIDER AD9520 R DELAY PFD N DIVIDER LOOP FILTER CP N DELAY REG 0x01E[1] = 1 MUX1 MUX3 INTERNAL FEEDBACK PATH ZERO DELAY FEEDBACK CLOCK LF EXTERNAL FEEDBACK PATH REG 0x01E[2] DIVIDE BY 1, 2, 3, 4, 5, OR 6 ZERO DELAY CLK/CLK CHANNEL DIVIDER 0 OUT0 TO OUT2 CHANNEL DIVIDER 1 OUT3 TO OUT5 CHANNEL DIVIDER 2 OUT6 TO OUT8 CHANNEL DIVIDER 3 OUT9 TO OUT11 0 07216-053 1 Figure 49. Zero Delay Function External Zero Delay Mode The external zero delay function of the AD9520 is achieved by feeding one clock output back to the CLK input and ultimately back to the PLL N divider. In Figure 49, the change in signal routing for external zero delay mode is shown in red. Set Register 0x01E[2:1] = 11b to select external zero delay mode. In external zero delay mode, one of the twelve output clocks (OUT0 to OUT11) can be routed back to the PLL (N divider) through the CLK/CLK pins and through MUX3 and MUX1. This feedback path is shown in red in Figure 49. For VCO calibration to work correctly, the user must specify which channel divider is used for external zero delay mode. Channel Divider 0 is the default. Change the value in Register 0x01E[4:3] to select Channel Divider 1, Channel Divider 2, or Channel Divider 3 for zero delay feedback. The PLL synchronizes the phase/edge of the feedback output clock with the phase/edge of the reference input. Because the channel dividers are synchronized to each other, the clock outputs are synchronous with the reference input. Both the R delay and the N delay inside the PLL can be programmed to compensate for the propagation delay from the PLL components to minimize the phase offset between the feedback clock and the reference input. CLOCK DISTRIBUTION A clock channel consists of three LVPECL clock outputs or six CMOS clock outputs that share a common divider. A clock output consists of the drivers that connect to the output pins. The clock outputs have either LVPECL or CMOS at the pins. The AD9520 has four clock channels. Each channel has its own programmable divider that divides the clock frequency applied to its input. The channel dividers can divide by any integer from 1 to 32. The AD9520 features a VCO divider that divides the VCO output by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers. The VCO divider has two purposes. The first is to limit the maximum input frequency of the channel dividers to 1.6 GHz. The other is to allow the AD9520 to generate even lower frequencies than would be possible with only a simple post divider. External clock signals connected to the CLK input can also use the VCO divider. The channel dividers allow for a selection of various duty cycles, depending on the currently set division. That is, for any specific division, D, the output of the divider can be set to high for N + 1 input clock cycles and low for M + 1 input clock cycles (where D = N + M + 2). For example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide-by-5 can be high for three divider input cycles and low for two cycles. Other combinations are also possible. The channel dividers include a duty-cycle correction function that can be disabled. In contrast to the selectable duty cycle just described, this function can correct a non-50% duty cycle caused by an odd division. However, this requires that the division be set by M = N + 1. Rev. A | Page 43 of 80 AD9520-3 Data Sheet outputs. However, the LVPECL outputs may not be able to meet the VOD specification in Table 4 at the highest frequencies. In addition, the channel dividers allow a coarse phase offset or delay to be set. Depending on the division selected, the output can be delayed by up to 15 input clock cycles. For example, if the frequency at the input of the channel divider is 1 GHz, the channel divider output can be delayed by up to 15 ns. The divider outputs can also be set to start high or to start low. Either the internal VCO or the CLK can be selected as the source for the direct-to-output signal routing. To connect the LVPECL outputs directly to the internal VCO or CLK, the VCO divider must be selected as the source to the distribution section, even if no channel uses it. Operation Modes There are three clock distribution operating modes, and these are shown in Figure 50. One of these modes uses the internal VCO, whereas the other two modes bypass the internal VCO and use the signal provided on the CLK/CLK pins. Table 33. Routing VCO Divider Input Directly to the Outputs Register Setting 0x1E1[1:0] = 00b 0x1E1[1:0] = 10b 0x192[1] = 1b 0x195[1] = 1b 0x198[1] = 1b 0x19B[1] = 1b In Mode 0 (internal VCO mode), there are two signal paths available. In the first path, the VCO signal is sent to the VCO divider and then to the individual channel dividers. In the second path, the user bypasses the VCO and channel dividers and sends the VCO signal directly to the drivers. Clock Frequency Division The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the VCO or CLK to the output is the product of the VCO divider (1, 2, 3, 4, 5, and 6) and the division of the channel divider. Table 34 shows how the frequency division for a channel is set. When CLK is selected as the source, it is not necessary to use the VCO divider if the CLK frequency is less than the maximum channel divider input frequency (1600 MHz); otherwise, the VCO divider must be used to reduce the frequency going to the channel dividers. Table 32 shows how the VCO, CLK, and VCO divider are selected. Register 0x1E1[1:0] selects the channel divider source and determines whether the VCO divider is used. It is not possible to select the VCO without using the VCO divider. Table 34. Frequency Division CLK or VCO Selected CLK or VCO input CLK or VCO input CLK or VCO input CLK or VCO input CLK (internal VCO off) Table 32. Operation Modes Channel Divider Source CLK CLK VCO Not allowed VCO Divider Used Not used Used Not allowed CLK or VCO Direct-to-LVPECL Outputs It is possible to connect either the internal VCO or the CLK (whichever is selected as the input to the VCO divider) directly to the LVPECL outputs. This configuration can pass frequencies up to the maximum frequency of the VCO directly to the LVPECL CLK (internal VCO off) 1 Resulting Frequency Division 1 1 to 6 2 to 32 Disable 2 to 6 Bypass Disable (1 to 6) x (2 to 32) (2 to 6) x (1) 1 Bypass Disable VCO divider bypassed VCO divider bypassed Bypass Don't care Output static (illegal state) 1 2 to 32 Don't care 2 to 32 PLL LF DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK LF DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 0 DISTRIBUTION CLOCK Direct-toOutput Setting Enable PLL LF 1 Channel Divider Setting Don't care The bypass VCO divider (Register 0x1E1[0] = 1b) is not the same as VCO divider = 1 (divide-by-1). PLL CLK VCO Divider Setting1 1 to 6 MODE 0 (INTERNAL VCO MODE) DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK 1 CLOCK DISTRIBUTION CLK 1 0 DISTRIBUTION CLOCK CLOCK DISTRIBUTION MODE 1 (CLOCK DISTRIBUTION MODE) DISTRIBUTION CLOCK CLOCK DISTRIBUTION MODE 2 (HF CLOCK DISTRIBUTION MODE) Figure 50. Simplified Diagram of the Three Clock Distribution Operation Modes Rev. A | Page 44 of 80 0 07216-054 Mode 2 1 0 Register 0x1E1 Bit 1 Bit 0 0 0 0 1 1 0 1 1 Selection CLK is the source; VCO divider selected VCO is the source; VCO divider selected Direct-to-output OUT0, OUT1, OUT2 Direct-to-output OUT3, OUT4, OUT5 Direct-to-output OUT6, OUT7, OUT8 Direct-to-output OUT9, OUT10, OUT11 Data Sheet AD9520-3 The channel dividers feeding the output drivers contain one 2-to32 frequency divider. This divider provides for division-by-1 to division-by-32. Division-by-1 is accomplished by bypassing the divider. The dividers also provide for a programmable duty cycle, with optional duty-cycle correction when the divide ratio is odd. A phase offset or delay in increments of the input clock cycle is selectable. The channel dividers operate with a signal of up to 1600 MHz at their inputs across all channel divider ratios. The features and settings of the dividers are selected by programming the appropriate setup and control registers (see Table 50 through Table 61). VCO Divider The VCO divider provides frequency division between the internal VCO or the external CLK input and the clock distribution channel dividers. The VCO divider can be set to divide by 1, 2, 3, 4, 5, or 6 (see Table 57, Register 0x1E0[2:0]). However, when the VCO divider is set to 1, none of the channel output dividers can be bypassed. The VCO divider can also be set to static, which is useful for applications where the only desired output frequency is the VCO frequency. Making the VCO divider static increases the wide band spurious-free dynamic range (SFDR). If the VCO divider is static during VCO calibration, there is no output signal. Therefore, it is important to calibrate the VCO with the VCO divider set to a nonstatic value during VCO calibration, and then set the VCO divider to static when VCO calibration is complete. The recommended alternative to achieving the same SFDR performance is to set the VCO divider to 1 and enable VCO direct mode. This allows the user to program the EEPROM with the desired values and does not require further action after the VCO calibration is complete. Channel Dividers A channel divider drives each group of three LVPECL outputs. There are four channel dividers (0, 1, 2, and 3) driving 12 LVPECL outputs (OUT0 to OUT11). Table 35 lists the bit locations used for setting the division and other functions of these dividers. The division is set by the M and N values. The divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. The duty-cycle correction can be enabled or disabled according to the setting of the disable Divider x DCC bits. Table 35. Setting DX for the Output Dividers Divider 0 1 2 3 Low Cycles, M Value Bits 0x190[7:4] 0x193[7:4] 0x196[7:4] 0x199[7:4] High Cycles, N Value Bits 0x190[3:0] 0x193[3:0] 0x196[3:0] 0x199[3:0] Bypass Bits 0x191[7] 0x194[7] 0x197[7] 0x19A[7] Disable Divider x DCC Bits 0x192[0] 0x195[0] 0x198[0] 0x19B[0] Channel Divider Maximum Frequency The maximum frequency at which all features of the channel divider are guaranteed to work is 1.6 GHz; this is the number that appears elsewhere in the datasheet. The maximum frequency at which all features of the channel divider are guaranteed to work is 1.6 GHz; this is the number that appears elsewhere in the data sheet. However, if the divide-by-3 and divide-by-17 settings are avoided, the maximum channel divider input frequency is 2 GHz. Channel Frequency Division (0, 1, 2, or 3) For each channel (where the channel number (x) is 0, 1, 2, or 3), the frequency division, DX, is set by the values of M and N (four bits each, representing Decimal 0 to Decimal 15), where Number of Low Cycles = M + 1 Number of High Cycles = N + 1 The high and low cycles are the cycles of the clock signal that are currently routed to the input of the channel dividers (VCO divider out or CLK). When a divider is bypassed, DX = 1. Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows each channel divider to divide by any integer from 2 to 32. Duty Cycle and Duty-Cycle Correction The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: * * * * M and N values for the channel DCC enabled/disabled VCO divider enabled/bypassed CLK input duty cycle (note that the internal VCO has a 50% duty cycle) The DCC function is enabled, by default, for each channel divider. However, the DCC function can be disabled individually for each channel divider by setting the disable Divider x DCC bit for that channel. Certain M and N values for a channel divider result in a non50% duty cycle. A non-50% duty cycle can also result in an even division, if M N. The duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. Duty-cycle correction requires the following channel divider conditions: * * An even division must be set as M = N An odd division must be set as M = N + 1 When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value of (N + 1)/(N + M + 2), expressed as a percent. Rev. A | Page 45 of 80 AD9520-3 Data Sheet Table 36 to Table 39 show the output duty cycle for various configurations of the channel divider and VCO divider. Table 36. Channel Divider Output Duty Cycle with VCO Divider 1; Input Duty Cycle Is 50% VCO Divider Even Odd = 3 Odd = 5 Even, odd Even, odd DX N+M+2 Channel divider bypassed Channel divider bypassed Channel divider bypassed Even Odd Disable Divider x DCC = 1b 50% 33.3% 40% (N + 1)/(N + M + 2) (N + 1)/(N + M + 2) Output Duty Cycle Disable Divider x DCC = 0b 50% 50% 50% 50%, requires M = N 50%, requires M = N + 1 Table 37. Channel Divider Output Duty Cycle with VCO Divider 1; Input Duty Cycle Is X% VCO Divider Even Odd = 3 Odd = 5 Even Even Odd = 3 Odd = 3 Odd = 5 Odd = 5 DX N+M+2 Channel divider bypassed Channel divider bypassed Channel divider bypassed Even Odd Even Odd Even Odd Disable Divider x DCC = 1b 50% 33.3% 40% (N + 1)/(N + M + 2) (N + 1)/(N + M + 2) (N + 1)/(N + M + 2) (N + 1)/(N + M + 2) (N + 1)/(N + M + 2) (N + 1)/(N + M + 2) Output Duty Cycle Disable Divider x DCC = 0b 50% (1 + X%)/3 (2 + X%)/5 50%, requires M = N 50%, requires M = N + 1 50%, requires M = N (3N + 4 + X%)/(6N + 9), requires M = N + 1 50%, requires M = N (5N + 7 + X%)/(10N + 15), requires M = N + 1 Table 38. Channel Divider Output Duty Cycle When the VCO Divider Is Enabled and Set to 1 Input Clock Duty Cycle Any 50% X% DX N+M+2 Even Odd Odd Disable Divider x DCC = 1b (N + 1)/(M + N + 2) (N + 1)/(M + N + 2) (N + 1)/(M + N + 2) Output Duty Cycle Disable Divider x DCC = 0b 50%, requires M = N 50%, requires M = N + 1 (N + 1 + X%)/(2 x N + 3), requires M = N + 1 The channel divider must be enabled when the VCO divider = 1. Table 39. Channel Divider Output Duty Cycle When the VCO Divider Is Bypassed Input Clock Duty Cycle Any Any 50% X% DX N+M+2 Channel divider bypassed Even Odd Odd Disable Divider x DCC = 1b Same as input duty cycle (N + 1)/(M + N + 2) (N + 1)/(M + N + 2) (N + 1)/(M + N + 2) The internal VCO has a duty cycle of 50%. Therefore, when the VCO is connected directly to the output, the duty cycle is 50%. If the CLK input is routed directly to the output, the duty cycle of the output is the same as the CLK input. Phase Offset or Coarse Time Delay Each channel divider allows for a phase offset or a coarse time delay to be programmed by setting register bits (see Table 40). These settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. This delay is with respect to a nondelayed output (that is, with a phase offset of zero). The amount of the delay is set by five bits loaded into the phase offset (PO) register plus the start high (SH) bit for each channel divider. Output Duty Cycle Disable Divider x DCC = 0b Same as input duty cycle 50%, requires M = N 50%, requires M = N + 1 (N + 1 + X%)/(2 x N + 3), requires M = N + 1 When the start high bit is set, the delay is also affected by the number of low cycles (M) programmed for the divider. The SYNC function must be used to make phase offsets effective (see the Synchronizing the Outputs--SYNC Function section). Table 40. Setting Phase Offset and Division Divider 0 1 2 3 Rev. A | Page 46 of 80 Start High (SH) Bits 0x191[4] 0x194[4] 0x197[4] 0x19A[4] Phase Offset (PO) Bits 0x191[3:0] 0x194[3:0] 0x197[3:0] 0x19A[3:0] Low Cycles, M Value Bits 0x190[7:4] 0x193[7:4] 0x196[7:4] 0x199[7:4] High Cycles, N Value Bits 0x190[3:0] 0x193[3:0] 0x196[3:0] 0x199[3:0] Data Sheet AD9520-3 * Note that the value stored in the register equals the number of cycles minus one. For example, Register 0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0. Let t = delay (in seconds). c = delay (in cycles of clock signal at input to DX). TX = period of the clock signal at the input of the divider, DX (in seconds). = 16 x SH[4] + 8 x PO[3] + 4 x PO[2] + 2 x PO[1] + 1 x PO[0]. The channel divide by is set as N = high cycles and M = low cycles. Case 1 For 15, t = x TX c = t/TX = Case 2 For 16, t = ( - 16 + M + 1) x TX c = t/TX By giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle. Figure 51 shows the results of setting such a coarse offset between outputs. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CHANNEL DIVIDER INPUT Tx DIVIDER 2 SH = 0 PO = 2 1 x Tx 2 x Tx 07216-071 SH = 0 PO = 1 Figure 51. Effect of Coarse Phase Offset (or Delay) Synchronizing the Outputs--SYNC Function The AD9520 clock outputs can be synchronized to each other. Outputs can be individually excluded from synchronization. Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions. These conditions include the divider ratio and phase offsets for a given channel divider. This allows the user to specify different divide ratios and phase offsets for each of the four channel dividers. Releasing the SYNC pin allows the outputs to continue clocking with the preset conditions applied. Synchronization of the outputs is executed in the following ways: * * The most common way to execute the SYNC function is to use the SYNC pin to perform a manual synchronization of the outputs. This requires a low going signal on the SYNC pin, which is held low and then released when synchronization is desired. The timing of the SYNC operation is shown in Figure 52 (using the VCO divider) and in Figure 53 (the VCO divider is not used). There is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9520. The pipeline delay from the SYNC rising edge to the beginning of the synchronized output clocking is between 14 cycles and 15 cycles of clock at the channel divider input, plus either one cycle of the VCO divider input (see Figure 52), or one cycle of the channel divider input (see Figure 53), depending on whether the VCO divider is used. Cycles are counted from the rising edge of the signal. In addition, there is an additional 1.2 ns (typical) delay from the SYNC signal to the internal synchronization logic, as well as the propagation delay of the output driver. The driver propagation delay is approximately 100 ps for the LVPECL driver and approximately 1.5 ns for the CMOS driver. Another common way to execute the SYNC function is by setting and resetting the soft SYNC bit at Register 0x230[0]. Both setting and resetting of the soft SYNC bit require an update all registers (Register 0x232[0] = 1b) operation to take effect. CHANNEL DIVIDER OUTPUTS DIV = 4, DUTY = 50% SH = 0 DIVIDER 0 PO = 0 DIVIDER 1 * * * Synchronization of the outputs can be executed as part of the chip power-up sequence. The RESET pin is forced low and then released (chip reset). The PD pin is forced low, then released (chip power-down). When a VCO calibration is completed, an internal SYNC signal is automatically asserted at the beginning and released upon the completion of a VCO calibration. The SYNC pin is forced low and then released (manual sync). By setting and then resetting any one of the following three bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit (Register 0x000[5] [mirrored]), and the power-down distribution reference bit (Register 0x230[1]). A SYNC operation brings all outputs that have not been excluded (by the ignore SYNC bit) to a preset condition before allowing the outputs to begin clocking in synchronicity. The preset condition takes into account the settings in each of the channel's start high bit and its phase offset. These settings govern both the static state of each output when the SYNC operation is happening and the state and relative phase of the outputs when they begin clocking again upon completion of the SYNC operation. Between outputs and after synchronization, this allows for the setting of phase offsets. The AD9520 differential LVPECL outputs are four groups of three, sharing a channel divider per triplet. In the case of CMOS, each LVPECL differential pair can be configured as two singleended CMOS outputs. The synchronization conditions apply to all of the drivers that belong to that channel divider. Each channel (a divider and its outputs) can be excluded from any SYNC operation by setting the ignore SYNC bit of the channel. Channels that are set to ignore SYNC (excluded channels) do not set their outputs static during a SYNC operation, and their outputs are not synchronized with those of the included channels. Rev. A | Page 47 of 80 AD9520-3 Data Sheet CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC INPUT TO VCO DIVIDER 1 1 INPUT TO CHANNEL DIVIDER 2 3 4 5 6 7 9 8 11 10 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 07216-073 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT Figure 52. SYNC Timing Pipeline Delay When the VCO Divider Is Used--CLK or VCO Is Input CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC INPUT TO CLK INPUT TO CHANNEL DIVIDER 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 07216-074 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT Figure 53. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used--CLK Input Only Rev. A | Page 48 of 80 Data Sheet AD9520-3 LVPECL Output Drivers CMOS Output Drivers The LVPECL differential voltage (VOD) is selectable (from ~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to Register 0x0FB). The LVPECL outputs have dedicated pins for power supply (VS_DRV), allowing a separate power supply to be used. VS_DRV can be set to either 2.5 V or 3.3 V. The user can also individually configure each LVPECL output as a pair of CMOS outputs, which provides up to 24 CMOS outputs. When an output is configured as CMOS, CMOS Output A and CMOS Output B are automatically turned on. For any given differential pair, either CMOS Output A or CMOS Output B can be turned on or off independently. SW1B SW1A R2 200 R1 200 The user can also select the relative polarity of the CMOS outputs for any combination of inverting and noninverting (refer to Register 0x0F0 to Register 0x0FB). VS_DRV OUT1/ OUT1 07216-035 The LVPECL output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. Each LVPECL output can be powered down or powered up as needed. Because of the architecture of the LVPECL output stages, there is the possibility of electrical overstress and breakdown under certain power-down conditions. For this reason, the LVPECL outputs have two power-down modes: total power-down and safe power-down. Figure 55. CMOS Equivalent Output Circuit N1 Each CMOS output can be powered down, as needed, to save power. The CMOS output power-down is individually controlled by the enable CMOS output bits, Bits[6:5] in Register 0x0F0 to Register 0x0FB. The CMOS driver is in tristate when it is powered down. QN1 OUT N2 QN2 OUT 4.4mA 07216-058 SW2 Figure 54. LVPECL Output Simplified Equivalent Circuit In total power-down mode, all output drivers are shut off simultaneously. This mode must not be used if there is an external voltage bias network (such as Thevenin equivalent termination) on the output pins that causes a dc voltage to appear at the powered down outputs. However, total powerdown mode is allowed when the LVPECL drivers are terminated using only pull-down resistors. The total power-down mode is activated by setting Register 0x230[1]. The primary power-down mode is the safe power-down mode. This mode continues to protect the output devices while powered down. There are three ways to activate safe power-down mode: individually set the power-down bit for each driver, power down an individual output channel (all of the drivers associated with that channel are powered down automatically), and activate sleep mode. Note that activating a CMOS driver in the same output channel group as the LVPECL drivers may cause the LVPECL driver performance to degrade. In applications where jitter performance is critical, the user should test the desired configuration using an evaluation board, and special steps may need to be taken to ensure the desired performance. RESET MODES The AD9520 has a power-on reset (POR) and several other ways to apply a reset condition to the chip. Power-On Reset During chip power-up, a power-on reset pulse is issued when VS reaches ~2.6 V (<2.8 V) and restores the chip either to the setting that is stored in the EEPROM (with the EEPROM pin = 1b) or to the on-chip setting (with the EEPROM pin = 0b). At poweron, the AD9520 also executes a SYNC operation approximately 50 ms after the supply reaches ~2.4 V, which brings the outputs into phase alignment according to the default settings. It takes ~70 ms for the outputs to begin toggling after the power-on reset pulse signal is internally generated. Rev. A | Page 49 of 80 AD9520-3 Data Sheet Hardware Reset via the RESET Pin RESET, a hard reset (an asynchronous hard reset is executed by briefly pulling RESET low), restores the chip either to the setting stored in the EEPROM (the EEPROM pin = 1b) or to the on-chip setting (the EEPROM pin = 0b). A hard reset also executes a SYNC operation, bringing the outputs into phase alignment according to the default settings. When the EEPROM is inactive (the EEPROM pin = 0b), it takes ~2 s for the outputs to begin toggling after RESET is issued. When the EEPROM is active (the EEPROM pin = 1b), it takes ~20 ms for the outputs to toggle after RESET is brought high. Soft Reset via the Serial Port The serial port control register allows for a soft reset by setting Bit 2 and Bit 5 in Register 0x000. The function of this register is determined by the state of the EEPROM pin. When the AD9520 is in a PD power-down, the chip is in the following state: * * * * * * * * * The PLL is off (asynchronous power-down). The VCO is off. The CLK input buffer is off, but the CLK input dc bias circuit is on. In differential mode, the reference input buffer is off, but the dc bias circuit is still on. In singled-ended mode, the reference input buffer is off, and the dc bias circuit is off. All dividers are off. All CMOS outputs are tristated. All LVPECL outputs are in safe off mode. The serial control port is active, and the chip responds to commands. When Bit 2 and Bit 5 are set and the EEPROM pin is high, the chip is restored to the settings saved in the EEPROM. When Bit 2 and Bit 5 are set and the EEPROM pin is low, the chip is restored to the on-chip defaults. PLL Power-Down Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000 retains its previous value prior to reset. During the internal reset, the outputs hold static. However, the self-clearing operation does not complete until an additional serial port SCLK cycle occurs, and the AD9520 is held in reset until that happens. In asynchronous power-down mode, the device powers down as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps. The device goes into powerdown on the occurrence of the next charge pump event after the registers are updated. Soft Reset to Settings in EEPROM when EEPROM Pin = 0b via the Serial Port If the EEPROM pin is low, the serial port control register allows the chip to be reset to settings in EEPROM via Register 0xB02[1]. (Bit 1 is self-clearing.) This bit does not have any effect when the EEPROM pin is high. It takes ~20 ms for the outputs to begin toggling after the SOFT_EEPROM register is cleared. POWER-DOWN MODES Chip Power-Down via PD The AD9520 can be put into a power-down condition by pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9520. The chip remains in this power-down state until PD is brought back to logic high. When taken out of power-down mode, the AD9520 returns to the settings programmed into its registers prior to the power-down, unless the registers are changed by new programming while the PD pin is held low. Powering down the chip shuts down the currents on the chip, except for the bias current necessary to maintain the LVPECL outputs in a safe shutdown mode. The LVPECL bias currents are needed to protect the LVPECL output circuitry from damage that can be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. The AD9520 contains special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode. The PLL section of the AD9520 can be selectively powered down. There are two PLL power-down modes set by Register 0x010[1:0]: asynchronous and synchronous. Distribution Power-Down The distribution section can be powered down by writing Register 0x230[1] = 1b, which turns off the bias to the distribution section. If the LVPECL power-down mode is in normal operation (Register 0x230[1] = 0b), it is possible for a low impedance load on that LVPECL output to draw significant current during this power-down. If the LVPECL power-down mode is set to 1b, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions. Individual Clock Output Power-Down Any of the clock distribution outputs can be powered down into safe power-down mode by individually writing to the appropriate registers. The register map details the individual power-down settings for each output. These settings are found in Bit 0 of Register 0x0F0 to Register 0x0FB. Individual Clock Channel Power-Down Any of the clock distribution channels can be powered down individually by writing to the appropriate registers. Powering down a clock channel is similar to powering down an individual driver, but it saves more power because the dividers are also powered down. Powering down a clock channel also automatically powers down the drivers connected to it. The register map details the individual power-down settings for each output channel. These settings are found in Bit 2 of Register 0x192, Register 0x195, Register 0x198, and Register 0x19B. Rev. A | Page 50 of 80 Data Sheet AD9520-3 SERIAL CONTROL PORT The AD9520 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9520 serial control port is compatible with most synchronous transfer formats, including Philips IC, Motorola(R) SPI(R), and Intel(R) SSR protocols. The AD9520 IC implementation deviates from the classic IC specification on two specifications, and these deviations are documented in Table 14. The serial control port allows read/write access to all registers that configure the AD9520. SPI/IC PORT SELECTION The AD9520 has two serial interfaces, SPI and IC. Users can select either SPI or IC depending on the states of the three- level (high, open, low) logic input pins, SP1 and SP0. When both SP1 and SP0 are high, the SPI interface is active. Otherwise, IC is active with eight different IC slave address (seven bits wide) settings (see Table 41). The four MSBs of the slave address are hardware coded as 1011b; the three LSBs are programmed by SP1 and SP0. Abbreviation S Sr P A A W R Definition Start Repeated start Stop Acknowledge No acknowledge Write Read One pulse on the SCL clock line is generated for each data bit transferred. The data on the SDA line must not change during the high period of the clock. The state of the data line can change only when the clock on the SCL line is low. DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED 07216-160 Address IC, 1011000b IC, 1011001b IC, 1011010b IC, 1011011b IC, 1011100b IC, 1011101b IC, 1011110b IC, 1011111b SPI SCL Figure 56. Valid Bit Transfer A start condition is a transition from high to low on the SDA line while SCL is high. The start condition is always generated by the master to initialize the data transfer. A stop condition is a transition from low to high on the SDA line while SCL is high. The stop condition is always generated by the master to end the data transfer. IC SERIAL PORT OPERATION SDA The AD9520 IC port is based on the IC fast mode standard. The AD9520 supports both IC protocols: standard mode (100 kHz) and fast mode (400 kHz). The AD9520 IC port has a 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). In an IC bus system, the AD9520 is connected to the serial bus (data bus SDA and clock bus SCL) as a slave device, meaning that no clock is generated by the AD9520. The AD9520 uses direct 16-bit (two bytes) memory addressing instead of traditional 8-bit (one byte) memory addressing. SCL S P START CONDITION STOP CONDITION 07216-161 SP0 Low Open High Low Open High Low Open High Table 42. I2C Bus Definitions SDA Table 41. Serial Port Mode Selection SP1 Low Low Low Open Open Open High High High I2C Bus Characteristics Figure 57. Start and Stop Conditions A byte on the SDA line is always eight bits long. An acknowledge bit must follow every byte. Bytes are sent MSB first. The acknowledge bit is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. It is accomplished by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte. The no acknowledge bit is the ninth bit attached to any 8-bit data byte. A no acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. It is accomplished by leaving the SDA line high during the ninth clock pulse after each 8-bit data byte. Rev. A | Page 51 of 80 AD9520-3 MSB 2 3 TO 7 9 8 1 2 3 TO 7 9 8 S 10 P 07216-162 1 SCL ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 07216-163 ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 07216-164 SDA Data Sheet Figure 58. Acknowledge Bit SDA MSB = 0 ACKNOWLEDGE FROM SLAVE-RECEIVER 1 SCL 2 3 TO 7 9 8 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 9 8 S Figure 59. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration) MSB = 1 SDA ACKNOWLEDGE FROM MASTER-RECEIVER 1 SCL 2 3 TO 7 8 9 1 NO ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 8 S 9 Figure 60. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration) Data Transfer Process The master initiates data transfer by asserting a start condition. This indicates that a data stream follows. All IC slave devices connected to the serial bus respond to the start condition. The master then sends an 8-bit address byte over the SDA line, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0b = write, 1b = read). The peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0b, the master (transmitter) writes to the slave device (receiver). If the R/W bit is 1b, the master (receiver) reads from the slave device (transmitter). The format for these commands is described in the Data Transfer Format section. Data is then sent over the serial bus in the format of nine clock pulses, one data byte (8-bit) from either master (write mode) or slave (read mode), followed by an acknowledge bit from the receiving device. The number of bytes that can be transmitted per transfer is unrestricted. In write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes with the high address byte first. This addressing scheme gives a memory address up to 216 - 1 = 65,535. The data bytes after these two memory address bytes are register data written into the control registers. In read mode, the data bytes after the slave address byte are register data read from the control registers. When all data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop condition to end data transfer during the (10th) clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull it low during the ninth clock pulse. This is known as a no acknowledge bit. By receiving the no acknowledge bit, the slave device knows that the data transfer is finished and releases the SDA line. The master then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. A repeated start (Sr) condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time and partially transferred bytes are discarded. Rev. A | Page 52 of 80 Data Sheet AD9520-3 Data Transfer Format Send byte format--the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P Write byte format--the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P Receive byte format--the receive byte protocol is used to read the data byte(s) from RAM starting from the current address. S Slave Address R A RAM Data 0 A RAM Data 1 A A RAM Data 2 P Read byte format--the combined format of the send byte and the receive byte. S Slave Address W RAM Address High Byte A A RAM Address Low Byte A Sr Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A IC Serial Port Timing SDA tSET; DAT tFALL tLOW tFALL tHLD; STR tRISE tSPIKE tRISE tIDLE tHLD; STR tHIGH tHLD; DAT S tSET; STP tSET; STR Sr Figure 61. IC Serial Port Timing Table 43. IC Timing Definitions Parameter fI2C tIDLE tHLD; STR tSET; STR tSET; STP tHLD; DAT tSET; DAT tLOW tHIGH tRISE tFALL tSPIKE Description IC clock frequency Bus idle time between stop and start conditions Hold time for repeated start condition Setup time for repeated start condition Setup time for stop condition Hold time for data Setup time for data Duration of SCL clock low Duration of SCL clock high SCL/SDA rise time SCL/SDA fall time Voltage spike pulse width that must be suppressed by the input filter Rev. A | Page 53 of 80 P S 07216-165 SCL P AD9520-3 Data Sheet SPI SERIAL PORT OPERATION Pin Descriptions SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and the read data bits transition on the falling edge of SCLK. This pin is internally pulled down by a 30 k resistor to ground. SDIO (serial data input/output) is a dual-purpose pin and acts either as an input only (unidirectional mode) or as both an input and an output (bidirectional mode). The AD9520 defaults to the bidirectional I/O mode (Register 0x000[7] = 0b). SDO (serial data out) is used only in the unidirectional I/O mode (Register 0x000[7]) as a separate output pin for reading back data. CS (chip select bar) is an active low control that gates the read and write cycles. When CS is high, SDO and SDIO are in a high impedance state. This pin is internally pulled up by a 30 k resistor to VS. 15 SCLK/SCL 16 SDIO/SDA 17 SDO 18 AD9520 SERIAL CONTROL PORT 07216-036 CS Figure 62. Serial Control Port SPI Mode Operation In SPI mode, single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9520 serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/ SDO). By default, the AD9520 is in bidirectional mode. Short instruction mode (8-bit instructions) is not supported. Only long (16-bit) instruction mode is supported. It is possible that the serial activity on the SDIO/SDO pins may induce jitter on the PLL while data is being transmitted. A write or a read operation to the AD9520 is initiated by pulling CS low. The CS stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred (see Table 44). In this mode, the CS pin can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. CS can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. During this period, the serial control port state machine enters a wait state until all data is sent. If the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remaining transfers or by returning CS low for at least one complete SCLK cycle (but fewer than eight SCLK cycles). Raising the CS pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. In the streaming mode (see Table 44), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented (see the SPI MSB/LSB First Transfers section). CS must be raised at the end of the last byte to be transferred, thereby ending streaming mode. Communication Cycle--Instruction Plus Data There are two parts to a communication cycle with the AD9520. The first part writes a 16-bit instruction word into the AD9520, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9520 serial control port with information regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. Write If the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the AD9520. Data bits are registered on the rising edge of SCLK. The length of the transfer (one, two, or three bytes, or streaming mode) is indicated by two bits (W1:W0) in the instruction byte. When the transfer is one, two, or three bytes, but not streaming, CS can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when CS is lowered. Raising the CS pin on a nonbyte boundary resets the serial control port. During a write, streaming mode does not skip over reserved or blank registers, and the user can write 0x00 to the reserved register addresses. Because data is written into a serial control port buffer area, not directly into the actual control registers of the AD9520, an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the AD9520, thereby causing them to become active. The update registers operation consists of setting Register 0x232[0] = 1b (this bit is self-clearing). Any number of bytes of data can be changed before executing an update registers. The update registers simultaneously actuates all register changes that have been written to the buffer since any previous update. Read The AD9520 supports only the long instruction mode. If the instruction word is for a read operation, the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 3 as determined by Bits[W1:W0]. If N = 4, the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK. Rev. A | Page 54 of 80 Data Sheet AD9520-3 The default mode of the AD9520 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9520 to unidirectional mode (Register 0x000[7] = 1b and Register 0x000[0] = 1b). In unidirectional mode, the readback data appears on the SDO pin. (Bits[3:0]). This makes it irrelevant whether LSB first or MSB first is in effect. As an example of this mirroring, see the default setting for Register 0x000, which mirrors Bit 4 and Bit 3. This sets the long instruction mode, which is the default and the only mode that is supported. A readback request reads the data in the serial control port buffer area or the data in the active registers (see Figure 63). Readback of the buffer or active registers is controlled by Register 0x004[0]. When LSB first is set by Register 0x000[1] and Register 0x000[6], it takes effect immediately because it affects only the operation of the serial control port and does not require that an update be executed. The default for the AD9520 is MSB first. SDO SERIAL CONTROL PORT UPDATE REGISTERS WRITE REGISTER 0x232 = 0x001 TO UPDATE REGISTERS 07216-037 SDIO/SDA When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow in order from the high address to the low address. In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. ACTIVE REGISTERS CS SCLK/SCL BUFFER REGISTERS The AD9520 uses Register 0x000 to Register 0xB03. Figure 63. Relationship Between Serial Control Port Buffer Registers and Active Registers of the AD9520 When LSB first is active, the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. In a multibyte transfer cycle, the internal byte address generator of the serial port increments for each byte. SPI INSTRUCTION WORD (16 BITS) The MSB of the instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits (W1:W0) indicate the length of the transfer in bytes. The final 13 bits are the address (A12:A0) at which to begin the read or write operation. The AD9520 serial control port register address decrements from the register address just written toward Register 0x000 for multibyte I/O operations if the MSB first mode is active (default). If the LSB first mode is active, the register address of the serial control port increments from the address just written toward Register 0x232 for multibyte I/O operations. For a write, the instruction word is followed by the number of bytes of data indicated by Bits [W1:W0], see Table 44. Table 44. Byte Transfer Count W1 0 0 1 1 W0 0 1 0 1 Bytes to Transfer 1 2 3 Streaming mode Streaming mode always terminates when it reaches Register 0x232. Note that unused addresses are not skipped during multibyte I/O operations. Table 45. Streaming Mode (No Addresses Are Skipped) Bits[A12:A0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes decrement the address. Write Mode LSB first Address Direction Increment MSB first Decrement SPI MSB/LSB FIRST TRANSFERS Stop Sequence Register 0x230, Register 0x231, Register 0x232, stop Register 0x001, Register 0x000, Register 0x232, stop The AD9520 instruction word and byte data can be MSB first or LSB first. Any data written to Register 0x000 must be mirrored; the upper four bits (Bits[7:4]) must mirror the lower four bits Table 46. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 LSB R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Rev. A | Page 55 of 80 AD9520-3 Data Sheet CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16-BIT INSTRUCTION HEADER D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N - 1) DATA 07216-038 DON'T CARE Figure 64. Serial Control Port Write--MSB First, 16-Bit Instruction, Two Bytes of Data CS SCLK DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N - 1) DATA REGISTER (N - 2) DATA REGISTER (N - 3) DATA DON'T CARE 07216-039 SDIO Figure 65. Serial Control Port Read--MSB First, 16-Bit Instruction, Four Bytes of Data tHIGH tDS tS tLOW DON'T CARE SDIO DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 07216-040 SCLK tC tCLK tDH CS Figure 66. Serial Control Port Write--MSB First, 16-Bit Instruction, Timing Measurements CS SCLK DATA BIT N 07216-041 tDV SDIO SDO DATA BIT N - 1 Figure 67. Timing Diagram for Serial Control Port Register Read CS SCLK DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 16-BIT INSTRUCTION HEADER D5 D6 REGISTER (N) DATA D7 D0 D1 D2 D6 REGISTER (N + 1) DATA Figure 68. Serial Control Port Write--LSB First, 16-Bit Instruction, Two Bytes of Data Rev. A | Page 56 of 80 D3 D4 D5 D7 DON'T CARE 07216-042 SDIO DON'T CARE DON'T CARE Data Sheet AD9520-3 tS tC CS tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 07216-043 tDH Figure 69. Serial Control Port Timing--Write Table 47. Serial Control Port Timing Parameter tDS tDH tCLK tS tC tHIGH tLOW tDV Description Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Period of the clock Setup time between the CS falling edge and the SCLK rising edge (start of communication cycle) Setup time between the SCLK rising edge and the CS rising edge (end of communication cycle) Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state SCLK to valid SDIO and SDO (see Figure 67) Rev. A | Page 57 of 80 AD9520-3 Data Sheet EEPROM OPERATIONS The AD9520 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by users to create and store a user-defined register setting file when the power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. Note that, to guarantee proper loading of the EEPROM during startup, a high-low-high pulse on the RESET pin should occur after the power supply has stabilized. During the data transfer process, the write and read registers via the serial port are generally not available except for one readback register, STATUS_EEPROM. To determine the data transfer state through the serial port in SPI mode, users can read the value of STATUS_EEPROM (1b = in process; 0b = completed). In IC mode, the user can address the AD9520 slave port with the external IC master (send an address byte to the AD9520). If the AD9520 responds with a no acknowledge bit, the data transfer process does not take place. If the AD9520 responds with an acknowledge bit, the data transfer process is completed. The user can monitor the STATUS_EEPROM register or program the STATUS pin to monitor the status of the data transfer. WRITING TO THE EEPROM The EEPROM cannot be programmed directly through the serial port interface. To program the EEPROM and store a register setting file, do the following: 1. 2. 3. 4. 5. Program the AD9520 registers to the desired circuit state. If the user wants the PLL to lock automatically after power-up, the VCO calibration now bit (Register 0x018[0]) must be set to 1b. This allows VCO calibration to start automatically after register loading. Note that a valid input reference signal must be present during VCO calibration. Program the EEPROM buffer registers, if necessary (see the Programming the EEPROM Buffer Segment section). This step is necessary only if the user wants to use the EEPROM to control the default setting of some (but not all) of the AD9520 registers or to control the register setting update sequence during power-up or chip reset. Set the enable EEPROM write bit (Register 0xB02[0]) to 1b to enable the EEPROM. Set the REG2EEPROM bit (Register 0xB03[0]) to 1b. Set the IO_UPDATE bit (Register 0x232[0]) to 1b, which starts the process of writing data into the EEPROM to create the EEPROM setting file. This enables the AD9520 EEPROM controller to transfer the current register values, as well as the memory address and instruction bytes from the EEPROM buffer segment, into the EEPROM. After the write process is completed, the internal controller sets Register 0xB03[0] (REG2EEPROM) back to 0b. 6. The STATUS_EEPROM bit in the readback register (Register 0xB00[0]) is used to indicate the data transfer status between the EEPROM and the control registers (0b = complete/inactive; 1b = in process/active). At the start of the data transfer, STATUS_EEPROM is set to 1b by the EEPROM controller and cleared to 0b at the end of the data transfer. The STATUS_EEPROM bit can be accessed through the STATUS pin when the STATUS pin is programmed to monitor the STATUS_EEPROM bit. Alternatively, the user can monitor the STATUS_EEPROM bit directly by reading the register. When the data transfer process is done (Register 0xB00[0] = 0b), set the enable EEPROM write bit (Register 0xB02[0]) to 0b to disable writing to the EEPROM. To verify that the data transfer has completed correctly, ensure that Register 0xB01[0] = 0b. A value of 1b in this register indicates a data transfer error. When an EEPROM save/load transfer is complete, wait a minimum of 10 s before starting the next EEPROM save/load transfer. READING FROM THE EEPROM The following reset-related events can start the process of restoring the settings stored in EEPROM to control registers. When the EEPROM pin is set high, do any of the following: * * * Power up the AD9520. Perform a hardware chip reset by pulling the RESET pin low and then releasing RESET. Set the self-clearing soft reset bit (Register 0x000[5]) to 1b. When the EEPROM pin is set low, set the self-clearing SOFT_EEPROM bit (Register 0xB02[1]) to 1b. The AD9520 then starts to read the EEPROM and loads the values into the active registers. If the EEPROM pin is low during reset or power-up, the EEPROM is not active, and the AD9520 default values are loaded instead. Note that, when using the EEPROM to automatically load the AD9520 register values and lock the PLL, the VCO calibration now bit (Register 0x018[0]) must be set to 1b when the register values are written to the EEPROM. This allows VCO calibration to start automatically after register loading. A valid input reference signal must be present during VCO calibration. To verify that the data transfer has completed correctly, verify that Register 0xB01[0] = 0b. A value of 1b in this register indicates a data transfer error. When an EEPROM save/load transfer is complete, wait a minimum of 10 s before starting the next EEPROM save/load transfer. Rev. A | Page 58 of 80 Data Sheet AD9520-3 PROGRAMMING THE EEPROM BUFFER SEGMENT IO_UPDATE (Operational Code 0x80) The EEPROM buffer segment is a register space on the AD9520. The user can specify which groups of registers are stored to the EEPROM during EEPROM programming. Note that programming this register space is optional. The default power-up values for the EEPROM buffer segment allow storage of all the AD9520 register values from Register 0x000 to Register 0x231 to the EEPROM. The EEPROM controller uses this operational code to generate an IO_UPDATE signal to update the active control register bank from the buffer register bank during the download process. As an example, a user might want to load only the output driver settings from the EEPROM without disturbing the PLL register settings currently stored in the AD9520. The user can alter the EEPROM buffer segment to include only the registers that apply to the output drivers and exclude the registers that apply to the PLL configuration. There are two parts to the EEPROM buffer segment: register section definition groups and operational codes. Table 48 shows an example of the EEPROM buffer segment. Register Section Definition Group Note that the AD9520 register map is noncontiguous, and the EEPROM is only 512 bytes long. The register section definition group tells the EEPROM controller how the AD9520 register map is segmented. Each register section definition group contains the starting address and number of bytes to be written to EEPROM. At a minimum, there should be at least one IO_UPDATE operational code after the end of the final register section definition group. This code is needed so that at least one IO_UPDATE occurs after all of the AD9520 registers are loaded when the EEPROM is read. If this operational code is absent during a write to the EEPROM, the register values loaded from the EEPROM are not transferred to the active register space, and these values do not take effect after they are loaded from the EEPROM to the AD9520. End-of-Data (Operational Code 0xFF) The EEPROM controller uses this operational code to terminate the data transfer process between EEPROM and the control register during the upload and download process. The last item appearing in the EEPROM buffer segment should be either this operational code or the pseudo-end-of-data operational code. Pseudo-End-of-Data (Operational Code 0xFE) Operational Codes The AD9520 EEPROM buffer segment has 23 bytes that can contain up to seven register section definition groups. If the user wants to define more than seven register section definition groups, the pseudo-end-of-data operational code can be used. During the upload process, when the EEPROM controller receives the pseudo-end-of-data operational code, it halts the data transfer process, clears the REG2EEPROM bit, and enables the AD9520 serial port. The user can then program the EEPROM buffer segment again and reinitiate the data transfer process by setting the REG2EEPROM bit (Register 0xB03[0]) to 1b and the IO_UPDATE bit (Register 0x232[0]) to 1b. The internal IC master then begins writing to the EEPROM starting from the EEPROM address held from the last writing. There are three operational codes: IO_UPDATE, end-of-data, and pseudo-end-of-data. It is important that the EEPROM buffer segment always have either an end-of-data or a pseudo-end-ofdata operational code and that an IO_UPDATE operational code appear at least once before the end-of-data operational code. This sequence provides the user with more discrete instructions that can be written to the EEPROM than would otherwise be possible due to the limited size of the EEPROM buffer segment. It also allows for the same register to be written multiple times with a different value each time. The register section definition group defines a continuous register section for the EEPROM profile. It consists of three bytes. The first byte defines how many continuous register bytes are in this group. If the user writes 0x000 to the first byte, it means that there is only one byte in this group. If the user writes 0x001, it means that there are two bytes in this group. The maximum number of registers in one group is 128. The next two bytes are the low byte and high byte, respectively, of the 16-bit memory address of the first register in this group. Table 48. Example of the EEPROM Buffer Segment Reg Addr (Hex) Bit 7 (MSB) Start EEPROM Buffer Segment 0xA00 0 0xA01 0xA02 0xA03 0 0xA04 0xA05 0xA06 0 0xA07 0xA08 0xA09 0xA0A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Number of bytes [6:0] of the first group of registers Address [15:8] of the first group of registers Address [7:0] of the first group of registers Number of bytes [6:0] of the second group of registers Address [15:8] of the second group of registers Address [7:0] of the second group of registers Number of bytes [6:0] of the third group of registers Address [15:8] of the third group of registers Address [7:0] of the third group of registers IO_UPDATE operational code (0x80) End-of-data operational code (0xFF) Rev. A | Page 59 of 80 AD9520-3 Data Sheet THERMAL PERFORMANCE Table 49. Thermal Parameters for 64-Lead LFCSP Symbol JA JMA JMA JB JC JT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) and JEDEC JESD51-8 Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) The AD9520 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source can be used. Use the following equation to determine the junction temperature on the application PCB: Value (C/W) 22.0 19.2 17.2 11.6 1.3 0.1 Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation TJ = TA + (JA x PD) TJ = TCASE + (JT x PD) where TA is the ambient temperature (C). where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the user at the top center of the package. JT is the value from Table 49. PD is the power dissipation (see the total power dissipation in Table 18). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations. Rev. A | Page 60 of 80 Data Sheet AD9520-3 REGISTER MAP Register addresses that are not listed in Table 50 are not used, and writing to those registers has no effect. Writing to register addresses that are marked as unused also has no effect. Table 50. Register Map Overview Addr Parameter (Hex) Serial Port Configuration Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) 0x000 SDO active LSB first/ addr incr Soft reset (self-clear) Soft reset (self-clear) Unused Unused LSB first/ addr incr SDO active 0x00 Unused Unused Soft reset (self-clear) Soft reset (self-clear) 0x001 0x002 0x003 0x004 Serial port config (SPI mode) Serial port config (IC mode) Unused Reserved Part ID Readback control Unused Unused Unused Reserved Part ID (read only) Unused Read back active regs 0x00 N/A N/A 0x20 0x00 EEPROM ID 0x005 0x006 0x007 to 0x00F PLL EEPROM customer version ID 0x010 0x011 0x012 0x013 0x014 PFD charge pump EEPROM customer version ID (LSB) EEPROM customer version ID (MSB) Unused Unused PFD polarity R counter Charge pump current Charge pump mode 14-bit R counter, Bits[7:0] (LSB) 14-bit R counter, Bits[13:8] (MSB) 6-bit A counter 13-bit B counter, Bits[7:0] (LSB) Unused Unused A counter B counter 0x015 0x016 PLL_CTRL_1 0x017 PLL_CTRL_2 0x018 PLL_CTRL_3 Enable CMOS reference input dc offset 0x019 PLL_CTRL_4 0x01A PLL_CTRL_5 0x01B PLL_CTRL_6 0x01C PLL_CTRL_7 R, A, and B counters SYNC pin reset Enable STATUS Ref freq monitor pin divider threshold Enable VCO Enable frequency REF2 monitor (REFIN) frequency monitor Disable Select switchover REF2 deglitch 0x01D PLL_CTRL_8 0x01E PLL_CTRL_9 0x01F PLL_Readback (read only) Set CP pin to VCP/2 Enable STATUS_EEPROM at STATUS pin Unused Reset R counter Reset Reset all A and B counters counters STATUS pin control Lock detect counter Enable XTAL OSC VCO cal finished Digital lock detect window PLL power-down 13-bit B counter, Bits[12:8] (MSB) B counter Prescaler P bypass Disable digital lock detect VCO calibration divider VCO calibration now N path delay Use REF_SEL pin Enable clock doubler Holdover active REF2 selected VCO freq > threshold Rev. A | Page 61 of 80 0x06 0x00 REFMON pin control Enable Stay on REF2 automatic reference switchover Disable PLL Enable LD pin status comparator register External zero delay feedback channel divider select 0x00 0x00 LD pin control Enable REF1 (REFIN) frequency monitor 0x7D 0x01 0x00 0x00 0x03 0x00 0x06 Antibacklash pulse width R path delay Unused Unused 0x00 0x00 0x00 0x00 Enable REF2 Enable REF1 Enable differential reference 0x00 Unused Enable external holdover Enable holdover 0x80 Enable external zero delay REF2 freq > threshold Enable zero delay Unused 0x00 REF1 freq > threshold Digital lock detect N/A AD9520-3 Data Sheet Addr Parameter (Hex) Output Driver Control Bit 7 (MSB) Bit 6 0x0F0 OUT0 control OUT0 format 0x0F1 OUT1 control OUT1 format 0x0F2 OUT2 control OUT2 format 0x0F3 OUT3 control OUT3 format 0x0F4 OUT4 control OUT4 format 0x0F5 OUT5 control OUT5 format 0x0F6 OUT6 control OUT6 format 0x0F7 OUT7 control OUT7 format 0x0F8 OUT8 control OUT8 format 0x0F9 OUT9 control OUT9 format 0x0FA OUT10 control OUT10 format 0x0FB OUT11 control OUT11 format 0x0FC Enable output on CSDLD CSDLD en OUT7 Unused OUT0 CMOS configuration OUT1 CMOS configuration OUT2 CMOS configuration OUT3 CMOS configuration OUT4 CMOS configuration OUT5 CMOS configuration OUT6 CMOS configuration OUT7 CMOS configuration OUT8 CMOS configuration OUT9 CMOS configuration OUT10 CMOS configuration OUT11 CMOS configuration CSDLD en CSDLD en OUT6 OUT5 Unused Unused 0x0FD Bit 5 Bit 4 Bit 3 OUT0 polarity OUT1 polarity OUT2 polarity OUT3 polarity OUT4 polarity OUT5 polarity OUT6 polarity OUT7 polarity OUT8 polarity OUT9 polarity OUT10 polarity OUT11 polarity CSDLD en OUT4 Unused 0x0FE Unused to 0x18F LVPECL Channel Dividers 0x190 0x191 Divider 0 (PECL) Divider 0 bypass 0x192 0x193 0x194 Divider 1 (PECL) Divider 1 bypass 0x195 0x196 0x197 Divider 2 (PECL) Divider 2 bypass 0x198 0x199 0x19A Divider 3 (PECL) Divider 3 bypass 0x19B 0x19C to 0x1DF Unused Divider 0 low cycles Divider 0 Divider 0 ignore force high SYNC Unused Divider 1 low cycles Divider 1 Divider 1 ignore force high SYNC Unused Divider 2 low cycles Divider 2 Divider 2 ignore force high SYNC Unused Divider 3 low cycles Divider 3 Divider 3 ignore force high SYNC Unused CSDLD en OUT3 CSDLD en OUT11 Unused Bit 2 Bit 1 OUT0 LVPECL differential voltage OUT1 LVPECL differential voltage OUT2 LVPECL differential voltage OUT3 LVPECL differential voltage OUT4 LVPECL differential voltage OUT5 LVPECL differential voltage OUT6 LVPECL differential voltage OUT7 LVPECL differential voltage OUT8 LVPECL differential voltage OUT9 LVPECL differential voltage OUT10 LVPECL differential voltage OUT11 LVPECL differential voltage CSDLD en CSDLD en OUT2 OUT1 CSDLD en CSDLD en OUT10 OUT9 Bit 0 (LSB) OUT0 LVPECL power-down OUT1 LVPECL power-down OUT2 LVPECL power-down OUT3 LVPECL power-down OUT4 LVPECL power-down OUT5 LVPECL power-down OUT6 LVPECL power-down OUT7 LVPECL power-down OUT8 LVPECL power-down OUT9 LVPECL power-down OUT10 LVPECL power-down OUT11 LVPECL power-down CSDLD en OUT0 CSDLD en OUT8 Unused Divider 1 start high Unused Divider 2 start high Unused Divider 3 start high Unused Unused Rev. A | Page 62 of 80 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x00 0x00 0x00 Divider 0 high cycles Divider 0 phase offset Divider 0 start high Default Value (Hex) 0x77 0x00 Channel 0 Channel 0 powerdirect-todown output Divider 1 high cycles Divider 1 phase offset Disable Divider 0 DCC Channel 1 Channel 1 powerdirect-todown output Divider 2 high cycles Divider 2 phase offset Disable Divider 1 DCC Channel 2 Channel 2 powerdirect-todown output Divider 3 high cycles Divider 3 phase offset Disable Divider 2 DCC Channel 3 powerdown Disable Divider 3 DCC Channel 3 direct-tooutput 0x00 0x33 0x00 0x00 0x11 0x00 0x00 0x00 0x00 0x00 0x00 Data Sheet Addr Parameter (Hex) VCO Divider and CLK Input 0x1E0 0x1E1 VCO divider Input CLKs AD9520-3 Bit 7 (MSB) Unused Bit 6 Bit 5 Unused Unused (default = 01b) Bit 4 Power down clock input section 0x1E2 Unused to 0x22A System 0x230 Power-down and SYNC 0x231 Unused Update All Registers 0x232 Bit 3 Unused Power down VCO clock interface Bit 2 Power down VCO and CLK Bit 1 Bit 0 (LSB) VCO divider Select VCO or CLK Bypass VCO divider Unused Unused Disable power on SYNC 0x00 0x20 0x00 Power down SYNC Unused IO_UPDATE Default Value (Hex) Power down distribution reference Unused Unused Soft SYNC 0x00 0x00 IO_UPDATE (self-clearing) 0x00 0x233 Unused to 0x9FF EEPROM Buffer Segment Unused 0x00 0xA00 Serial port configuration 0xA01 0xA02 0xA03 EEPROM customer version ID 0xA04 0xA05 0xA06 PLL settings 0xA07 0xA08 0xA09 Output driver control 0xA0A 0xA0B 0xA0C LVPECL channel dividers 0xA0D 0xA0E 0xA0F VCO divider and CLK input 0xA10 0xA11 0xA12 Power-down and SYNC 0xA13 0xA14 0xA15 I/O update 0xA16 End of data 0xA17 Unused to 0xAFF EEPROM Control Data transfer: one byte Starting address: Address 0x000 0x00 0x00 0x00 0x02 0x00 0x04 0x0E 0x00 0x10 0x0E 0x00 0xF0 0x0B 0x01 0x90 0x01 0x01 0xE0 0x01 0x02 0x30 0x80 0xFF 0x00 0xB00 Data transfer: three bytes Starting address: Address 0x004 Data transfer: 16 bytes Starting address: Address 0x010 Data transfer: 16 bytes Starting address: Address 0x0F0 Data transfer: 12 bytes Starting address: Address 0x190 Data transfer: two bytes Starting address: Address 0x1E0 Data transfer: two bytes Starting address: Address 0x230 Action: IO_UPDATE Action: end of data Unused (available for additional EEPROM instructions) Unused Unused Unused Unused 0xB02 EEPROM status (read only) EEPROM error checking (read only) EEPROM Control 1 Unused 0xB03 EEPROM Control 2 Unused SOFT_EEPROM (self-clearing) Unused 0xB01 Rev. A | Page 63 of 80 STATUS_ EEPROM EEPROM data error Enable EEPROM write REG2EEPROM (self-clearing) 0x00 0x00 0x00 0x00 AD9520-3 Data Sheet REGISTER MAP DESCRIPTIONS Table 51 to Table 61 provide a detailed description of each of the control register functions. Table 51. SPI Mode Serial Port Configuration Reg. Addr. (Hex) 0x000 Bits 7 Name SDO active 6 LSB first/addr incr 5 Soft reset 4 [3:0] Unused Mirror[7:4] 0x003 [7:0] Part ID (read only) 0x004 [7:1] 0 Unused Read back active registers Description Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin is used for write and read; SDO pin is high impedance (default). 1: SDO pin is used for read; SDIO pin is used for write; unidirectional mode. SPI MSB or LSB data orientation. (This bit is ignored in I2C mode.) 0: data-oriented MSB first; the addressing decrements (default). 1: data-oriented LSB first; the addressing increments. Soft reset. 1 (self-clearing): if the EEPROM pin is high, soft reset loads the register values from the EEPROM. If the EEPROM pin is low, soft reset loads the register values to the on-chip defaults. Unused. Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode (see Register 0x000[6]). Set the bits as follows: Bit 0 = Bit 7 Bit 1 = Bit 6 Bit 2 = Bit 5 Bit 3 = Bit 4 Uniquely identifies the dash version (AD9520-0 to AD9520-5) of the AD9520, as follows: AD9520-0: 0x20 AD9520-1: 0x60 AD9520-2: 0xA0 AD9520-3: 0x61 AD9520-4: 0xE1 AD9520-5: 0xE0 Unused. Selects register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers. Table 52. I2C Mode Serial Port Configuration Reg. Addr. (Hex) 0x000 Bits [7:6] 5 Name Unused Soft reset Description Unused. Soft reset. 1 (self-clearing): if the EEPROM pin is high, soft reset loads the register values from the EEPROM. If the 4 [3:0] Unused Mirror[7:4] [7:0] [7:1] 0 Part ID (read only) Unused Read back active registers Unused. Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode. See Table 51, Register 0x000, Bits[3:0]. Uniquely identifies the dash version (AD9520-0 to AD9520-5) of the AD9520. See Table 51, Register 0x003. Unused. Selects register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers. EEPROM pin is low, soft reset loads the register values to the on chip defaults. 0x003 0x004 Table 53. EEPROM Customer Version ID Reg. Addr. (Hex) 0x005 Bits [7:0] 0x006 [7:0] Name EEPROM customer version ID (LSB) EEPROM customer version ID (MSB) Description 16-bit EEPROM ID[7:0]. This register, along with Register 0x006, allows the user to store a unique ID to identify which version of the AD9520 register settings is stored in the EEPROM. It does not affect AD9520 operation in any way (default: 0x00). 16-bit EEPROM ID[15:8]. This register, along with Register 0x005, allows the user to store a unique ID to identify which version of the AD9520 register settings is stored in the EEPROM. It does not affect AD9520 operation in any way (default: 0x00). Rev. A | Page 64 of 80 Data Sheet AD9520-3 Table 54. PLL Reg. Addr. (Hex) Bits 0x010 7 Name PFD polarity [6:4] CP current [3:2] CP mode [1:0] 0x011 [7:0] 0x012 [7:6] [5:0] 0x013 [7:6] [5:0] 0x014 [7:0] 0x015 [7:5] [4:0] 0x016 7 6 5 4 3 PLL power-down Description Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity; Bit 7 = 0b. 0: positive (higher control voltage produces higher frequency) (default). 1: negative (higher control voltage produces lower frequency). Charge pump current (with CPRSET = 5.1 k). Bit 6 Bit 5 Bit 4 ICP (mA) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) Charge pump operating mode. Bit 3 Bit 2 Charge Pump Mode 0 0 High impedance state. 0 1 Forces source current (pump up). 1 0 Forces sink current (pump down). 1 1 Normal operation (default). PLL operating mode. Bit 1 Bit 0 Mode 0 0 Normal operation; this mode must be selected to use the PLL. 0 1 Asynchronous power-down (default). 1 0 Unused. 1 1 Synchronous power-down. Reference divider LSBs--lower eight bits. The reference divider (also called the R divider or R counter) is 14 bits long. The lower eight bits are in this register (default: 0x01). Unused. Reference divider MSBs--upper six bits. The reference divider (also called the R divider or R counter) is 14 bits long. The upper six bits are in this register (default: 0x00). Unused. A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00). B counter (part of N divider)--lower eight bits. The N divider is also called the feedback divider (default: 0x03). 14-bit R counter, Bits[7:0] (LSB) Unused 14-bit R counter, Bits[13:8] (MSB) Unused 6-bit A counter 13-bit B counter, Bits[7:0] (LSB) Unused Unused. 13-bit B counter, B counter (part of N divider)--upper five bits. The N divider is also called the feedback divider (default: 0x00). Bits[12:8] (MSB) Set CP pin to VCP/2 Sets the CP pin to one-half of the VCP supply voltage. 0: CP normal operation (default). 1: CP pin set to VCP/2. Reset R counter Resets R counter (R divider). 0: normal (default). 1: holds R counter in reset. Reset A and B Resets A and B counters (part of N divider). counters 0: normal (default). 1: holds A and B counters in reset. Reset all counters Resets R, A, and B counters. 0: normal (default). 1: holds R, A, and B counters in reset. B counter bypass B counter bypass. This is valid only when operating the prescaler in FD mode. 0: normal (default). 1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. Rev. A | Page 65 of 80 AD9520-3 Data Sheet Reg. Addr. (Hex) Bits Name [2:0] Prescaler P Description Prescaler: DM = dual modulus; FD = fixed divide. Prescaler P is part of the feedback divider. See the VCO/VCXO Feedback Divider N--P, A, and B section of the datasheet for details. Bit Bit Bit 2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 and divide-by-3 when A 0; divide-by-2 when A = 0. 0 1 1 DM Divide-by-4 and divide-by-5 when A 0; divide-by-4 when A = 0. 1 0 0 DM Divide-by-8 and divide-by-9 when A 0; divide-by-8 when A = 0. 1 0 1 DM Divide-by-16 and divide-by-17 when A 0; divide-by-16 when A = 0. 1 1 0 DM Divide-by-32 and divide-by-33 when A 0; divide-by-32 when A = 0 (default). 1 1 1 FD Divide-by-3. 0x017 [7:2] STATUS Selects the signal that appears at the STATUS pin. Register 0x01D[7] must be 0b to reprogram the STATUS pin. pin control Level or Bit Bit Bit Bit Bit Bit Dynamic Signal 7 6 5 4 3 2 Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground (dc) (default). 0 0 0 0 0 1 DYN N divider output (after the delay). 0 0 0 0 1 0 DYN R divider output (after the delay). 0 0 0 0 1 1 DYN A divider output. 0 0 0 1 0 0 DYN Prescaler output. 0 0 0 1 0 1 DYN PFD up pulse. 0 0 0 1 1 0 DYN PFD down pulse. 0 X X X X X LVL Ground (dc). Used for all settings of these bits that are not otherwise specified in this table. The selections that follow are also used for REFMON and LD pin control. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 DYN LVL LVL LVL LVL LVL LVL LVL LVL LVL LVL LVL LVL 1 1 1 1 0 0 0 0 0 1 1 0 DYN DYN 1 1 1 1 0 0 0 1 1 0 1 0 DYN DYN 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 LVL LVL LVL LVL LVL LVL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 LVL LVL LVL LVL LVL Unselected reference to PLL (not available in differential mode). Status of selected reference (status of differential reference); active high. Status of unselected reference (not available in differential mode); active high. Status of REF1 frequency; active high. Status of REF2 frequency; active high. (Status of REF1 frequency) AND (status of REF2 frequency). (DLD) AND (status of selected reference) AND (status of VCO). Status of VCO frequency; active high. Selected reference (low = REF1, high = REF2). DLD; active high. Holdover active; active high. N/A. Do not use. VS (PLL power supply). REF1 clock (differential reference when in differential mode). REF2 clock (not available in differential mode). Selected reference to PLL (differential reference when in differential mode). Unselected reference to PLL (not available when in differential mode). Status of selected reference (status of differential reference); active low. Status of unselected reference (not available in differential mode); active low. Status of REF1 frequency; active low. Status of REF2 frequency; active low. (Status of REF1 frequency) AND (status of REF2 frequency). (DLD) AND (status of selected reference) AND (status of VCO). Status of VCO frequency; active low. Selected reference (low = REF2, high = REF1). DLD; active low. Holdover active; active low. N/A. Do not use. Rev. A | Page 66 of 80 Data Sheet Reg. Addr. (Hex) Bits Name [1:0] Antibacklash pulse width 0x018 7 Enable CMOS reference input dc offset [6:5] Lock detect counter 4 Digital lock detect window 3 Disable digital lock detect [2:1] VCO calibration divider 0 VCO calibration now 0x019 [7:6] R, A, B counters SYNC pin reset AD9520-3 Description Bit 1 Bit 0 Antibacklash Pulse Width (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9 Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost. 0: disables dc offset (default). 1: enables dc offset. Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked condition. Bit 6 Bit 5 PFD Cycles to Determine Lock 0 0 5 (default) 0 1 16 1 0 64 1 1 255 If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. 0: high range (default). The default setting is 3.5 ns. 1: low range. Digital lock detect operation. 0: normal lock detect operation (default). 1: disables lock detect. Divider used to generate the VCO calibration clock from the PLL reference clock (see the VCO Calibration section for the recommended setting of the VCO calibration divider based on the PFD rate). Bit 2 Bit 1 VCO Calibration Clock Divider 0 0 2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R. 0 1 4. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R. 1 0 8. This setting is fine for PFD frequencies < 50 MHz. 1 1 16 (default). This setting is fine for any PFD frequency, but it also results in the longest VCO calibration time. Initiates VCO calibration. This bit must be toggled from 0b to 1b in the active registers. The sequence to initiate a calibration is as follows: program to 0b, followed by an IO_UPDATE (Register 0x232[0]); then program to 1b, followed by another IO_UPDATE (Register 0x232[0]). This sequence gives complete control over when the VCO calibration occurs relative to the programming of other registers that can impact the calibration (default = 0b). Note that the VCO divider (Register 0x1E0[2:0]) must not be static during VCO calibration. Bit 7 Bit 6 Action 0 0 Does nothing on SYNC (default). 0 1 1 [5:3] R path delay [2:0] N path delay Enable STATUS 0x01A 7 pin divider 6 Ref freq monitor threshold 1 0 1 Asynchronous reset. Synchronous reset. Does nothing on SYNC. R path delay, see Table 2 (default: 0x0). N path delay, see Table 2 (default: 0x0). Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the R and N dividers. 0: divide-by-4 disabled on STATUS pin (default). 1: divide-by-4 enabled on STATUS pin. Sets the reference (REF1/REF2) frequency monitor's detection threshold frequency. This does not affect the VCO frequency monitor's detection threshold (see Table 17: REF1, REF2, and VCO frequency status monitor parameter). 0: frequency valid if frequency is above 1.02 MHz (default). 1: frequency valid if frequency is above 6 kHz. Rev. A | Page 67 of 80 AD9520-3 Data Sheet Reg. Addr. (Hex) Bits Name [5:0] LD pin control 0x01B 7 6 5 Description Selects the signal that is connected to the LD pin. Level or Bit Bit Bit Bit Bit Bit Dynamic 5 4 3 2 1 0 Signal Signal at LD Pin 0 0 0 0 0 0 LVL Digital lock detect (high = lock; low = unlock, default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ Tristate (high-Z) LD pin. 0 0 0 1 0 0 CUR Current source lock detect (110 A when DLD is true). 0 X X X X X LVL Ground (dc). Used for all settings of these bits that are not otherwise specified in this table. The selections that follow are also used for REFMON and STATUS pin control. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status of REF1 frequency; active high. 1 0 1 0 0 0 LVL Status of REF2 frequency; active high. 1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency; active high. 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL DLD; active high. 1 0 1 1 1 0 LVL Holdover active; active high. 1 0 1 1 1 1 LVL N/A. Do not use. 1 1 0 0 0 0 LVL VS (PLL power supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency; active low. 1 1 1 0 0 0 LVL Status of REF2 frequency; active low. 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency; active low. 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL DLD; active low. 1 1 1 1 1 0 LVL Holdover active; active low. 1 1 1 1 1 1 LVL N/A. Do not use. Enable VCO Enables or disables the VCO frequency monitor. frequency 0: disables the VCO frequency monitor (default). monitor 1: enables the VCO frequency monitor. Enable REF2 Enables or disables the REF2 frequency monitor. (REFIN) frequency 0: disables the REF2 frequency monitor (default). monitor 1: enables the REF2 frequency monitor. REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected by Enable REF1 (REFIN) frequency differential reference mode). monitor 0: disables the REF1 (REFIN) frequency monitor (default). 1: enables the REF1 (REFIN) frequency monitor. Rev. A | Page 68 of 80 Data Sheet AD9520-3 Reg. Addr. (Hex) Bits Name [4:0] REFMON pin control 0x01C 7 6 5 4 3 2 1 0 Description Selects the signal that is connected to the REFMON pin. Level or Bit Bit Bit Bit Bit Dynamic 4 3 2 1 0 Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 LVL Status of REF1 frequency; active high. 0 1 0 0 0 LVL Status of REF2 frequency; active high. 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 0 1 0 1 1 LVL Status of VCO frequency; active high. 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 0 1 1 0 1 LVL DLD; active high. 0 1 1 1 0 LVL Holdover active; active high. 0 1 1 1 1 LVL N/A. Do not use. 1 0 0 0 0 LVL VS (PLL power supply). 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 LVL Status of REF1 frequency; active low. 1 1 0 0 0 LVL Status of REF2 frequency; active low. 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 0 1 1 LVL Status of VCO frequency; active low. 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 0 1 LVL DLD; active low. 1 1 1 1 0 LVL Holdover active; active low. 1 1 1 1 1 LVL N/A. Do not use. Disables or enables the switchover deglitch circuit. Disable 0: enables the switchover deglitch circuit (default). switchover 1: disables the switchover deglitch circuit. deglitch If Register 0x01C[5] = 0b, selects the reference for PLL when in manual; register selected reference control. Select REF2 0: selects REF1 (default). 1: selects REF2. Use REF_SEL pin If Register 0x01C[4] = 0b (manual), sets the method of PLL reference selection. 0: uses Register 0x01C[6] (default). 1: uses REF_SEL pin. Enable automatic Automatic or manual reference switchover. Single-ended reference mode must be selected by Register 0x01C[0] = 0b. 0: manual reference switchover (default). reference 1: automatic reference switchover. Setting this bit also powers on REF1 and REF2 and overrides the settings in Register 0x01C[2:1]. switchover Stays on REF2 after switchover. Stay on REF2 0: returns to REF1 automatically when REF1 status is good again (default). 1: stays on REF2 after switchover. Does not automatically return to REF1. This bit turns the REF2 power on. This bit is overridden when automatic reference switchover is enabled. Enable REF2 0: REF2 power off (default). 1: REF2 power on. This bit turns the REF1 power on. This bit is overridden when automatic reference switchover is enabled. Enable REF1 0: REF1 power off (default). 1: REF1 power on. Enable differential Selects the PLL reference mode, differential or single-ended. Register 0x01C[2:1] should be cleared when this bit is set. reference 0: single-ended reference mode (default); 1: differential reference mode. Rev. A | Page 69 of 80 AD9520-3 Reg. Addr. (Hex) Bits 0x01D 7 Data Sheet Name Enable STATUS_EEPROM at STATUS pin Enable XTAL OSC Description Enables the Status_EEPROM signal at the STATUS pin. 0: the STATUS pin is controlled by Register 0x017[7:2] selection. 1: select STATUS_EEPROM signal at STATUS pin. This bit overrides Register 0x017[7:2] (default). Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input. 6 0: crystal oscillator maintaining amplifier disabled (default). 1: crystal oscillator maintaining amplifier enabled. Enable Enables PLL reference input clock doubler. 5 clock doubler 0: doubler disabled (default). 1: doubler enabled. Disable PLL status Disables the PLL status register readback. 4 register 0: PLL status register enabled (default). 1: PLL status register disabled. If this bit is set, Register 01F is not automatically updated. Enable LD pin Enables the LD pin voltage comparator. Used with the LD pin current source lock detect mode. When the AD9520 is in internal 3 comparator (automatic) holdover mode, this bit enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 47). Otherwise, this setting can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin. 0: disables LD pin comparator and ignore the LD pin voltage; internal/automatic holdover controller treats the LD pin as true (high, default). 1: enables LD pin comparator (use LD pin voltage to determine if the PLL was previously locked). 2 Unused Unused. Enable external 1 Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.) holdover 0: automatic holdover mode, holdover controlled by automatic holdover circuit (default). 1: external holdover mode, holdover controlled by SYNC pin. 0 Enable holdover Enables the internally controlled holdover function. 0: holdover disabled (default). 1: holdover enabled. 0x01E [7:5] Unused Unused. [4:3] External Bit 4 Bit 3 Selection of Channel Divider for Use in the External Zero-Delay Path zero delay 0 0 Selects Channel Divider 0 (default). feedback 0 1 Selects Channel Divider 1. channel divider 1 0 Selects Channel Divider 2. select 1 1 Selects Channel Divider 3 Enable external Selects which zero delay mode to use. 2 zero delay 0: enables internal zero delay mode if Register 0x01E[1] = 1 (default). 1: enables external zero delay mode if Register 0x01E[1] = 1. 1 Enable zero delay Enables zero delay function. 0: disables zero delay function (default). 1: enables zero delay function. 0 Unused Unused. 0x01F 7 Unused Unused. Readback register. Indicates the status of the VCO calibration. VCO calibration 6 0: VCO calibration not finished. finished 1: VCO calibration finished. (read only) Holdover active Readback register. Indicates if the part is in the holdover state (see Figure 47). Note that this is not the same as holdover enabled. 5 (read only) 0: not in holdover state. 1: holdover state active. REF2 selected Readback register. Indicates which PLL reference is selected as the input to the PLL. 4 (read only) 0: REF1 selected (or differential reference if in differential mode). 1: REF2 selected. VCO frequency > Readback register. Indicates if the VCO frequency is greater than the threshold (see Table 17: REF1, REF2, and VCO frequency 3 status monitor parameter). threshold 0: VCO frequency is less than the threshold. (read only) 1: VCO frequency is greater than the threshold. REF2 frequency > Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x01A[6]. 2 threshold 0: REF2 frequency is less than the threshold frequency. (read only) 1: REF2 frequency is greater than the threshold frequency. REF1 frequency > Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency set by Register 0x01A[6]. 1 threshold 0: REF1 frequency is less than the threshold frequency. (read only) 1: REF1 frequency is greater than the threshold frequency. Digital lock detect Readback register. Digital lock detect. 0 (read only) 0: PLL is not locked. 1: PLL is locked. Rev. A | Page 70 of 80 Data Sheet AD9520-3 Table 55. Output Driver Control Reg. Addr. (Hex) Bits 0x0F0 7 0x0F1 0x0F2 0x0F3 0x0F4 0x0F5 0x0F6 0x0F7 0x0F8 0x0F9 0x0FA 0x0FB 0x0FC Name OUT0 format [6:5] OUT0 CMOS configuration [4:3] OUT0 polarity [2:1] OUT0 LVPECL differential voltage 0 OUT0 LVPECL power-down [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 7 OUT1 control OUT2 control OUT3 control OUT4 control OUT5 control OUT6 control OUT7 control OUT8 control OUT9 control OUT10 control OUT11 control CSDLD en OUT7 6 5 4 3 2 1 0 0x0FD [7:4] 3 2 1 0 CSDLD en OUT6 CSDLD en OUT5 CSDLD en OUT4 CSDLD en OUT3 CSDLD en OUT2 CSDLD en OUT1 CSDLD en OUT0 Unused CSDLD en OUT11 CSDLD en OUT10 CSDLD en OUT9 CSDLD en OUT8 Description Selects the output type for OUT0. 0: LVPECL (default). 1: CMOS. Sets the CMOS output configuration for OUT0 when Register 0x0F0[7] = 1b. Bits[6:5] OUT0A OUT0B Tristate Tristate 00 Tristate On 01 On Tristate 10 On 11 (default) On Sets the output polarity for OUT0. Bit 7 Bit 4 Bit 3 Output Type OUT0A Noninverting LVPECL 0 (default) X 0 (default) Inverting LVPECL 1 X 0 Noninverting CMOS 0 (default) 0 1 Inverting CMOS 1 0 1 Noninverting CMOS 0 1 1 Inverting CMOS 1 1 1 Sets the LVPECL output differential voltage (VOD). Bit 2 Bit 1 VOD (mV) 400 0 0 600 1 0 0 (default) 780 1 (default) 960 1 1 OUT0B Inverting Noninverting Noninverting Inverting Inverting Noninverting LVPECL power-down. 0: normal operation (default). 1: safe power-down. This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0. OUT7 is enabled only if the CSDLD signal is high. CSDLD Signal Bit 7 OUT7 Enable Status Not affected by CSDLD signal (default). 0 0 Asynchronous power-down. 0 1 Asynchronously enables OUT7 if not powered down by other settings. For this feature, use current 1 1 source digital lock detect and set the enable LD pin comparator bit (Register 0x01D[3]). OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. Unused. OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. Rev. A | Page 71 of 80 AD9520-3 Data Sheet Table 56. LVPECL Channel Dividers Reg. Addr. (Hex) Bits 0x190 [7:4] [3:0] 0x191 7 Name Divider 0 low cycles Divider 0 high cycles Divider 0 bypass 6 Divider 0 ignore SYNC 5 Divider 0 force high 4 Divider 0 start high [3:0] 0x192 [7:3] 2 Divider 0 phase offset Unused Channel 0 power-down 1 Channel 0 direct-to-output 0 Disable Divider 0 DCC 0x193 [7:4] [3:0] 0x194 7 Divider 1 low cycles Divider 1 high cycles Divider 1 bypass 6 Divider 1 ignore SYNC 5 Divider 1 force high 4 Divider 1 start high [3:0] Divider 1 phase offset Description Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x7). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x7 means that the divider is high for eight input clock cycles (default: 0x7). Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: bypasses divider. Ignores SYNC. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed. 0: divider output is forced to low (default). 1: divider output is forced to the setting stored in Bit 4 of this register. Selects clock output to start high or start low. 0: starts low (default). 1: starts high. Phase offset (default: 0x0). Unused. Channel 0 powers down. 0: normal operation (default). 1: powered down. (Setting this bit puts OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 into safe powerdown mode.) Connects OUT0, OUT1, and OUT2 to Divider 0 or directly to VCO or CLK. 0: OUT0, OUT1, and OUT2 are connected to Divider 0 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0, OUT1, and OUT2. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0, OUT1, and OUT2. If Register 0x1E1[1:0] = 01b, there is no effect. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x3 means that the divider is low for four input clock cycles (default: 0x3). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x3 means that the divider is high for four input clock cycles (default: 0x3). Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: bypasses divider. Ignores SYNC. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed. 0: divider output is forced to low (default). 1: divider output is forced to the setting stored in Bit 4 of this register. Selects clock output to start high or start low. 0: starts low (default). 1: starts high. Phase offset (default: 0x0). Rev. A | Page 72 of 80 Data Sheet Reg. Addr. (Hex) Bits 0x195 [7:3] 2 Name Unused Channel 1 power-down 1 Channel 1 direct-to-output 0 Disable Divider 1 DCC 0x196 [7:4] [3:0] 0x197 7 Divider 2 low cycles Divider 2 high cycles Divider 2 bypass 6 Divider 2 ignore SYNC 5 Divider 2 force high 4 Divider 2 start high [3:0] 0x198 [7:3] 2 Divider 2 phase offset Unused Channel 2 power-down 1 Channel 2 direct-to-output 0 Disable Divider 2 DCC 0x199 [7:4] [3:0] Divider 3 low cycles Divider 3 high cycles AD9520-3 Description Unused. Channel 1 powers down. 0: normal operation (default). 1: powered down. (Setting this bit puts OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 into safe powerdown mode.) Connects OUT3, OUT4, and OUT5 to Divider 1 or directly to VCO or CLK. 0: OUT3, OUT4, and OUT5 are connected to Divider 1 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT3, OUT4, and OUT5. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT3, OUT4, and OUT5. If Register 0x1E1[1:0] = 01b, there is no effect. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x1 means that the divider is low for two input clock cycles (default: 0x1). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x1 means that the divider is high for two input clock cycles (default: 0x1). Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: bypasses divider. Ignores SYNC. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed. 0: divider output is forced to low (default). 1: divider output is forced to the setting stored in Bit 4 of this register. Selects clock output to start high or start low. 0: starts low (default). 1: starts high. Phase offset (default: 0x0). Unused. Channel 2 powers down. 0: normal operation (default). 1: powered down. (Setting this bit puts OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 into safe powerdown mode.) Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK. 0: OUT6, OUT7, and OUT8 are connected to Divider 2 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8. If Register 0x1E1[1:0] = 01b, there is no effect. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default: 0x0). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default: 0x0). Rev. A | Page 73 of 80 AD9520-3 Reg. Addr. (Hex) Bits 0x19A 7 Name Divider 3 bypass 6 Divider 3 ignore SYNC 5 Divider 3 force high 4 Divider 3 start high [3:0] 0x19B [7:3] 2 Divider 3 phase offset Unused Channel 3 power-down 1 Channel 3 direct to output 0 Disable Divider 3 DCC Data Sheet Description Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: bypasses divider. Ignores SYNC. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed. 0: divider output is forced to low (default). 1: divider output is forced to the setting stored in Bit 4 of this register. Selects clock output to start high or start low. 0: starts low (default). 1: starts high. Phase offset (default: 0x0). Unused. Channel 3 powers down. 0: normal operation (default). 1: powered down. (Setting this bit puts OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 into safe power-down mode.) Connects OUT9, OUT10, and OUT11 to Divider 3 or directly to VCO or CLK. 0: OUT9, OUT10, and OUT11 are connected to Divider 3 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT9, OUT10, and OUT11. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT9, OUT10, and OUT11. If Register 0x1E1[1:0] = 01b, there is no effect. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Table 57. VCO Divider and CLK Input Reg. Addr. (Hex) Bits 0x1E0 [2:0] Name VCO divider 0x1E1 [7:5] Unused 4 Power down clock input section 3 Power down VCO clock interface 2 Power down VCO and CLK 1 Select VCO or CLK 0 Bypass VCO divider Description Bit 2 Bit 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Bit 0 0 1 0 1 0 1 0 1 Divide 2 (default) 3 4 5 6 Output static 1 (bypass) Output static Unused. Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). 0: normal operation (default). 1: power-down. Powers down the interface block between VCO and clock distribution. 0: normal operation (default). 1: power-down. Powers down both the VCO and the CLK input. 0: normal operation (default). 1: power-down. Selects either the VCO or the CLK as the input to VCO divider. 0: selects external CLK as input to VCO divider (default). 1: selects VCO as input to VCO divider; VCO divider cannot be bypassed when this bit is set. This bit must be set to use the PLL with the internal VCO. Bypasses or uses the VCO divider. 0: uses VCO divider (default). 1: bypasses VCO divider; VCO cannot be selected as input when this bit is set. Rev. A | Page 74 of 80 Data Sheet AD9520-3 Table 58. System Reg. Addr. (Hex) Bits 0x230 [7:4] 3 2 1 0 Name Unused Disable power on SYNC Description Unused. Powers on SYNC mode. Used to disable the antiruntpulse circuitry. 0: enables the antiruntpulse circuitry (default). 1: disables the antiruntpulse circuitry. Power down SYNC Powers down the SYNC function. 0: normal operation of the SYNC function (default). 1: powers down SYNC circuitry. Power down distribution Powers down the reference for the distribution section. reference 0: normal operation of the reference for the distribution section (default). 1: powers down the reference for the distribution section. Soft SYNC The soft SYNC bit works in the same way as the SYNC pin, except that the polarity of the bit is reversed. That is, a high level forces selected channels into a predetermined static state, and a 1bto-0b transition triggers a SYNC. 0: same as SYNC pin high. 1: same as SYNC pin low. Table 59. Update All Registers Reg. Addr. (Hex) Bits 0x232 [7:1] 0 Name Unused IO_UPDATE Description Unused. This bit must be set to 1b to transfer the contents of the buffer registers into the active registers. This transfer occurs on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0b. 1 (self-clearing): updates all active registers to the contents of the buffer registers. Table 60. EEPROM Buffer Segment Reg Addr (Hex) Bits 0xA00 to 0xAFF Name EEPROM buffer segment Description The EEPROM buffer segment section stores the starting address and number of bytes that are to be stored and then read back to and from the EEPROM. Because the AD9520 register space is noncontiguous, the EEPROM controller uses the starting address and number of bytes in the AD9520 register space to store and retrieve from the EEPROM. There are two types of entries in the EEPROM buffer segment: data transfers and operational codes. For a data transfer, Bit 7 of the command byte is set to 0b. The remaining seven bits are the size of the transfer, minus 1 (that is, 0x01 indicates a 2-byte transfer). The starting address (MSB first) of the transfer is contained in the two bytes of the EEPROM buffer segment that immediately follow the data transfer command. For an operational code, Bit 7 of the command byte is set to 1b and is a special instruction for the EEPROM controller. There are two operational codes: IO_UPDATE and end of data. The IO_UPDATE operational code instructs the EEPROM controller to transfer the AD9520 register values into the active register space (and is functionally equivalent to writing 0x01 to Register 0x232). The end-ofdata operational code informs the EEPROM controller that the end of data has been reached and to terminate the transfer. The last byte of the EEPROM buffer segment must contain an end-of-data operational code. Using the on-chip default setting of the EEPROM buffer segment registers, the EEPROM controller transfers all register values to/from the EEPROM, and an IO_UPDATE is issued after transfer. Therefore, the user does not normally need to alter the EEPROM buffer segment. See the Programming the EEPROM Buffer Segment section for more information. Rev. A | Page 75 of 80 AD9520-3 Data Sheet Table 61. EEPROM Control Reg Addr (Hex) Bits Name 0xB00 [7:1] Unused 0 STATUS_EEPROM (read only) Description Unused. This read-only register indicates the status of the data transfer between the EEPROM and the buffer register bank during the writing and reading of the EEPROM. This signal is also available at the STATUS pin when Register 0x01D[7] is set. 0: data transfer is complete. 1: data transfer is not complete. 0xB01 [7:1] Unused Unused. 0 EEPROM This read-only register indicates an error during the data transfer between the EEPROM and the buffer. data error 0: no error. Data is correct. (read only) 1: incorrect data detected. 0xB02 [7:2] Unused Unused. 1 SOFT_EEPROM When the EEPROM pin is tied low, setting SOFT_EEPROM resets the AD9520 using the settings saved in the EEPROM. 1: soft reset with EEPROM settings (self-clearing). 0 Enable EEPROM Enables the user to write to the EEPROM. write 0: EEPROM write protection is enabled. User cannot write to the EEPROM (default). 1: EEPROM write protection is disabled. User can write to the EEPROM. Once an EEPROM save/load transfer is complete, the user must wait a minimum of 10 s before starting the next EEPROM save/load transfer. 0xB03 [7:1] Unused Unused. 0 REG2EEPROM Transfers data from the buffer register to the EEPROM (self-clearing). 1: setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process); it is reset by the IC master after the data transfer is complete. Once an EEPROM save/load transfer is complete, the user must wait a minimum of 10 s before starting the next EEPROM save/load transfer. Rev. A | Page 76 of 80 Data Sheet AD9520-3 APPLICATIONS INFORMATION Within the AD9520 family, lower VCO frequencies generally result in slightly better jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.4 GHz to 2.95 GHz) of the AD9520 family. If the desired frequency plan can be achieved with a version of the AD9520 that has a lower VCO frequency, choosing the lower frequency part results in the best phase noise and the lowest jitter. However, choosing a higher VCO frequency can result in more flexibility in frequency planning. When determining a starting point, choosing a nominal charge pump current in the middle of the allowable range allows the designer to increase or decrease the charge pump current and, thus, allows fine-tuning of the PLL loop bandwidth in either direction. Analog Devices has an AD9520 configuration tool that can determine the best PLL configuration, based on the user's input and output frequencies. It can also design the loop filter based on user requirements. In addition to the configuration tool, ADIsimCLK is a powerful PLL modeling tool and a very accurate tool for determining the optimal loop filter for a given application. USING THE AD9520 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of the AD9520 sampling clock. An ADC can be thought of as a sampling mixer; and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. where: fA is the highest analog frequency being digitized. tJ is the rms jitter on the sampling clock. Figure 70 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). 110 18 1 SNR = 20log 2f t A J 100 16 90 tJ = 100 70 60 14 fs tJ = 200 fs tJ = 80 400 fs 12 2ps 10 tJ = 1ps tJ = ENOB The AD9520 has four frequency dividers: the reference (or R) divider, the feedback (or N) divider, the VCO divider, and the channel divider. When trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the VCO divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. 1 SNR(dB) = 20log 2f t A J 50 40 8 tJ = 10 ps 6 30 10 100 1k fA (MHz) 07216-044 The AD9520 is a highly flexible PLL. When choosing the PLL settings and version of the AD9520, keep in mind the following guidelines. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed, approximately, by the following equation: SNR (dB) FREQUENCY PLANNING USING THE AD9520 Figure 70. SNR and ENOB vs. Analog Input Frequency For more information, see the AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter; and the AN-501 Application Note, Aperture Uncertainty and ADC System Performance. Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sampling clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. The differential LVPECL outputs of the AD9520 enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or singleended, logic level termination) should be considered when selecting the best clocking/converter solution. Rev. A | Page 77 of 80 AD9520-3 Data Sheet LVPECL Clock Distribution Far-End Thevenin Termination The LVPECL outputs of the AD9520 provide the lowest jitter clock signals available from the AD9520. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 54 shows the LVPECL output stage. Far-end Thevenin termination uses a resistor network to provide 50 termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the AD9520 should equal VS of the receiving buffer. Although the resistor combination shown results in a dc bias point of VS_DRV - 2 V, the actual common-mode voltage is VS_DRV - 1.3 V because there is additional current flowing from the AD9520 LVPECL driver through the pull-down resistor. In most applications, an LVPECL far-end Thevenin termination (see Figure 71) or Y-termination (see Figure 72) is recommended. In both cases, VS of the receiving buffer should match VS_DRV. If it does not, ac coupling is recommended (see Figure 73). CMOS CLOCK DISTRIBUTION VS_DRV 127 127 SINGLE-ENDED (NOT COUPLED) 50 The output drivers of the AD9520 can be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as inverting or noninverting. These outputs are 3.3 V or 2.5 V CMOS compatible. However, every output driver (including the LVPECL drivers) must be run at either 2.5 V or 3.3 V. The user cannot mix and match 2.5 V and 3.3 V outputs. LVPECL 83 83 Figure 71. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination VS_DRV When using single-ended CMOS clocking, consider the following guidelines: VS = VS_DRV LVPECL Z0 = 50 50 * 50 50 LVPECL 07216-047 Z0 = 50 Figure 72. DC-Coupled 3.3 V LVPECL Y-Termination VS_DRV VS 0.1nF 200 100 DIFFERENTIAL 100 (COUPLED) 0.1nF TRANSMISSION LINE LVPECL 200 * 07216-046 LVPECL Figure 73. AC-Coupled LVPECL with Parallel Transmission Line LVPECL Y-Termination LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. In the case where VS_DRV = 2.5 V, the 50 termination resistor connected to ground in Figure 72 should be changed to 19 . * Using the CMOS drivers in the same output channel group as the LVPECL drivers may result in performance degradation of the LVPECL drivers. Where possible, program the two CMOS drivers that form the same output of a differential pair to be out of phase such that one driver is high while the other is low. It is recommended that the evaluation board be used to verify the performance of the AD9520 in demanding applications where both CMOS and LVPECL drivers are in the same group, and the very best jitter performance is required. If possible, design point-to-point connections such that each driver has only one receiver. Connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths of less than 3 inches are recommended to preserve signal rise/fall times and signal integrity. CMOS 10 60.4 (1.0 INCH) CMOS MICROSTRIP 07216-076 LVPECL 50 VS 07216-045 VS_DRV The circuit is identical for the case where VS_DRV = 2.5 V, except that the pull-down resistor is 62.5 and the pull-up resistor is 250 . Figure 74. Series Termination of CMOS Output Rev. A | Page 78 of 80 Data Sheet AD9520-3 Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9520 do not supply enough current to provide a full voltage swing with a low impedance resistive, farend termination, as shown in Figure 75. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets. Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9520 offers LVPECL outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. VS 10 50 100 CMOS 100 07216-077 CMOS Figure 75. CMOS Output with Far-End Termination Rev. A | Page 79 of 80 AD9520-3 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.25 0.18 0.60 MAX 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 16 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-12-2012-B 12 MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.80 6.35 6.20 SQ 6.05 EXPOSED PAD Figure 76. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad CP-64-4 Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9520-3BCPZ AD9520-3BCPZ-REEL7 AD9520-3/PCBZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2008-2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07216-0-8/13(A) Rev. A | Page 80 of 80 Package Option CP-64-4 CP-64-4 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9520-3/PCBZ AD9520-3BCPZ AD9520-3BCPZ-REEL7