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DP83816

SNLS164E –SEPTEMBER 2005–REVISED DECEMBER 2015

DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer

(MacPhyter-II™)

1 Device Overview

1.1 Features

1(MIB II), RFC 1398 (Ether-Like MIB), IEEE 802.3

• IEEE 802.3 Compliant, PCI V2.2 Media Access LME, Reducing CPU Overhead for Management

Controller (MAC) and Bus Interface Unit (BIU)

Supports Traditional Data Rates of 10 Mb/s • Internal 2KB Transmit and 2KB Receive Data

Ethernet and 100 Mb/s Fast Ethernet (Through FIFOs

Internal PHY) • Serial EEPROM Port With Auto-Load of

• Bus Master – Burst Sizes of up to 128 Dwords Configuration Data From EEPROM at Power On

(512 Bytes) • Flash or PROM Interface for Remote Boot Support

• BIU Compliant With PC 97 and PC 98 Hardware • Fully Integrated IEEE 802.3 3.3-V CMOS Physical

Design Guides, PC 99 Hardware Design Guide Layer

Draft, ACPI v1.0, PCI Power Management • IEEE 802.3 10BASE-T Transceiver With Integrated

Specification v1.1, OnNow Device Class Power Filters IEEE 802.3u 100BASE-TX Transceiver

Management Reference Specification – Network • Fully integrated ANSI X3.263 Compliant TP-PMD

Device Class v1.0a Physical Sublayer With Adaptive Equalization and

• Wake on LAN (WoL) Support Compliant With Baseline Wander Compensation

PC98, PC99, SecureOn, and OnNow, Including • IEEE 802.3u Auto-Negotiation – Advertised

Directed Packets, Magic Packet™ VLAN Packets, Features Configurable Through EEPROM

ARP Packets, Pattern Match Packets, and PHY • Full-Duplex Support for 10- and 100-Mb/s Data

Status Change Rates

• Clkrun Function for PCI Mobile Design Guide • Single 25-MHz Reference Clock

• Virtual LAN (VLAN) and Long Frame Support • 144-pin LQFP Package

• Support for IEEE 802.3× Full-Duplex Flow Control • Low-Power 3.3-V CMOS Design With Typical

• Extremely Flexible Rx Packet Filtration Including: Consumption of 383 mW Operating, 297 mW

Single Address Perfect Filter With MSb Masking, During WoL, and 53 mW During Sleep Mode

Broadcast, 512 Entry Multicast and Unicast Hash • IEEE 802.3u MII for Connecting Alternative

Table, Deep Packet Pattern Matching for up to External Physical Layer Devices

Four Unique Patterns • 3.3-V Signaling With 5-V Tolerant I/O

• Statistics Gathered for Support of RFC 1213

1.2 Applications

• PC Motherboards • Embedded Systems

• PCI Network Interface Cards

1.3 Description

The DP83816 device is a single-chip 10/100 Mb/s ethernet controller for the PCI bus. It is targeted at low-

cost, high-volume PC motherboards, adapter cards, and embedded systems. The DP83816 device fully

implements the V2.2 33-MHz PCI bus interface for host communications with power management support.

Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The

DP83816 device can support full-duplex 10/100 Mb/s transmission and reception with minimum interframe

gap.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DP83816 LQFP (144) 20.00 mm × 20.00 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

PCI Bus

DP83816

EEPROM

Isolation

10/100 Twisted Pair

BIOS ROM

(optional) (optional)

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1.4 System Diagram

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Table of Contents

1 Device Overview ......................................... 15.4 Device Functional Modes ........................... 31

1.1 Features .............................................. 15.5 Programming........................................ 34

1.2 Applications........................................... 15.6 Register Block....................................... 65

1.3 Description............................................ 16 Application and Implementation................... 100

1.4 System Diagram...................................... 26.1 Application Information ............................ 100

2 Revision History ......................................... 36.2 Typical Application ................................. 100

3 Pin Configuration and Functions..................... 47 Power Supply Recommendations................. 106

3.1 Pin Attributes ......................................... 68 Layout................................................... 107

4 Specifications........................................... 11 8.1 Layout Guidelines.................................. 107

4.1 Absolute Maximum Ratings......................... 11 8.2 Layout Example.................................... 110

4.2 ESD Ratings ........................................ 11 9 Device and Documentation Support ............. 111

4.3 Recommended Operating Conditions............... 11 9.1 Documentation Support............................ 111

4.4 Thermal Information................................. 11 9.2 Trademarks ........................................ 111

4.5 Electrical Characteristics – DC Specifications ...... 12 9.3 Electrostatic Discharge Caution ................... 111

4.6 AC Timing Requirements ........................... 12 9.4 Glossary............................................ 111

5 Detailed Description ................................... 23 10 Mechanical Packaging and Orderable

Information............................................. 111

5.1 Overview ............................................ 23 10.1 Packaging Information ............................. 111

5.2 Functional Block Diagram........................... 23

5.3 Feature Description ................................. 24

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (September 2005) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

Support section, and Mechanical, Packaging, and Orderable Information section. ......................................... 1

• Changed the Thermal Information table values................................................................................. 11

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3 Pin Configuration and Functions

The DP83816 pins are classified into the following interface categories (pins of each interface are

described in Section 3.1.

• PCI bus interface

• Media independent interface

• 10/100 Mb/s PMD interface

• BIOS ROM and flash interface

• Clock interface

• LED Interface

• Serial EEPROM interface

• Special connections

• Power supply pins

All DP83816 signal pins are I/O cells regardless of the particular use. The tables in Section 3.1 define the

functionality of the I/O cells for each pin.

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144 MA2/LED100LNK37NC

1MA3/EEDI 108 AD10

143 MA1/LED10LNK38VSS

2MA4/EECLK 107 PCIVDD

142 MA0/LEDACT39IAUXVDD

3MA5 106 AD11

141 MD740VREF

4MDIO 105 AD12

140 MD641NU

5MDC 104 AD13

139 MD542NC

6RXCLK 103 VSS

138 MD4/EEDO43NC

7RXD0/MA6 102 AD14

137 AUXVDD44VSS

8VSS 101 AD15

136 VSS45TPRDM

9AUXVDD 100 CBEN1

135 MD346TPRDP

10RXD1/MA7 99 PAR

134 MD247IAUXVDD

11RXD2/MA8 98 SERRN

133 MD1/CFGDISN48REGEN

12RXD3/MA9 97 PERRN

132 MD049VSS

13RXOE 96 STOPN

131 MWRN50NU

14RXER/MA10 95 DEVSELN

130 MRDN51VSS

15RXDV/MA11 94 PCIVDD

129 MCSN52VSS

16VSS 93 TRDYN

128 EESEL53TPTDM

17X1 92 IRDYN

127 NU54TPTDP

18X2 91 FRAMEN

126 NC55VSS

19C1 90 VSS

125 NC56AUXVDD

20VSS 89 CBEN2

124 NC57VSS

21AUXVDD 88 AD16

123 PWRGOOD58AUXVDD

22TXD0/MA12 87 AD17

122 3VAUX59PMEN/CLKRUNN

23TXD1/MA1 86 AD18

121 AD060PCICLK

24TXD2/MA1 85 NC

120 AD161INTAN

25TXD3/MA15 84 NC

119 AD262RSTN

26VSS 83 AD19

118 AD363GNTN

27AUXVDD 82 AD20

117 PCIVDD64REQN

28COL 81 AD21

116 AD465VSS

29CRS 80 PCIVDD

115 AD566AD31

30TXEN 79 AD22

114 VSS67AD30

31TXCLK 78 AD23

113 AD668AD29

32VSS 77 VSS

112 AD769PCIVDD

33AUXVDD 76 IDSEL

111 CBEN070AD28

34NC 75 CBEN3

110 AD871AD27

35VSS 74 AD24

109 AD972AD26

36NC 73 AD25

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PGE Package

144-Pin LQFP

Top View

NC – No internal connection

NU – Make no external connection

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3.1 Pin Attributes

Table 3-1. Pin Functions, PCI Bus Interface

PIN TYPE(1) DESCRIPTION

NAME NO.

PCI Auxiliary Voltage Sense: This pin is used to sense the presence of a 3.3-V auxiliary supply

3VAUX 122 I, PD to define the PME support available. For pin connection, see Section 6.2.1.4.

66, 67, 68,

70. 71, 72,

73, 74, 78,

79, 81, 82,

83, 86, 87, Address and Data: Multiplexed address and data bus. As a bus master, the DP83816 device

88,101, drives address during the first bus phase. During subsequent phases, the DP83816 device either

102, 104,

AD[31–0] I/O reads or writes data, expecting the target to increment its address pointer. As a bus target, the

105, 106, DP83816 device decodes each address on the bus and responds if it is the target being

108, 109, addressed.

110, 112,

113, 115,

116, 118,

119, 120,

121

Bus Command and Byte Enable: During the address phase, these signals define the bus

command or the type of bus transaction that takes place. During the data phase these pins

75, 89, 100,

CBEN[3–0] I/O indicate which byte lanes contain valid data. CBEN[0] applies to byte 0 (bits 7–0) and CBEN[3]

111 applies to byte 3 (bits 31–24) in the little-endian mode. In big-endian mode, CBEN[3] applies to

byte 0 (bits 31–24) and CBEN[0] applies to byte 3 (bits 7–0).

Clock: This PCI bus clock provides timing for all bus phases. The rising edge defines the start of

PCICLK 60 I each phase. The clock frequency ranges from 0 to 33 MHz.

Device Select: As a bus master, the DP83816 device samples this signal to ensure that the

DEVSELN 95 I/O destination address for the data transfer is recognized by a PCI target. As a target, the DP83816

device asserts this signal low when it recognizes its address after FRAMEN is asserted.

Frame: As a bus master, this signal is asserted low to indicate the beginning and duration of a

bus transaction. Data transfer takes place when this signal is asserted. The signal is de-asserted

FRAMEN 91 I/O before the transaction is in its final phase. As a target, the device monitors this signal before

decoding the address to check if the current transaction is addressed.

Grant: This signal is asserted low to indicate to the DP83816 device that it has been granted

GNTN 63 I ownership of the bus by the central arbiter. This input is used when the DP83816 device is acting

as a bus master.

Initialization Device Select: This pin is sampled by the DP83816 device to identify when

IDSEL 76 I configuration read and write accesses are intended.

Interrupt A: This signal is asserted low when an interrupt condition occurs as defined in the

INTAN 61 O, OD interrupt status, interrupt mask, and interrupt enable registers.

Initiator Ready: When the DP83816 device is a bus master, this signal is asserted low when the

DP83816 device is ready to complete the current data-phase transaction. This signal is used in

IRDYN 92 I/O conjunction with the TRYDN signal. A data transaction takes place at the rising edge of PCICLK

when both IRDYN and TRDYN are asserted low. When the DP83816 device is a target, this

signal indicates that the master has put the data on the bus.

Parity: This signal indicates even parity across AD[31–0] and CBEN[3–0] including the PAR pin.

PAR 99 I/O As a master, PAR is asserted during address and write-data phases. As a target, PAR is asserted

during read-data phases.

Parity Error: The DP83816 device as a master or target asserts this signal low to indicate a

PERRN 97 I/O parity error on any incoming data (except for special cycles). As a bus master, the device

monitors this signal on all write operations (except for special cycles).

Request: The DP83816 device asserts this signal low to request ownership of the bus from the

REQN 64 O central arbiter.

Reset: When this signal is asserted, all PCI bus outputs of the DP83816 device are in te high-

RSTN 62 I impedance state and the device is put into a known state.

System Error: This signal, if enabled, is asserted low by the DP83816 device during address

SERRN 98 I/O parity errors and system errors.

Stop: This signal is asserted low by the target device to request the master device to stop the

STOPN 96 I/O current transaction.

(1) I = input, O = output, I/O = input/output, OD = open-drain, PD = pulldown

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Table 3-1. Pin Functions, PCI Bus Interface (continued)

PIN TYPE(1) DESCRIPTION

NAME NO.

Target Ready: When the DP83816 device is a bus master, this signal indicates that the target is

ready for the data during write operation or with the data during read operation. When the

DP83816 device is a target, this signal is asserted low when the (target) device is ready to

TRDYN 93 I/O complete the current data-phase transaction. This signal is used in conjunction with the IRDYN

signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN

are asserted low.

Power Management Event and Clock Run Function: This pin is a dual-function pin. The

function of this pin is determined by the CLKRUN_EN bit 0 of the CLKRUN Control and Status

PMEN/ register (CCSR). Default operation of this pin is PMEN.

59 I/O, OD

CLKRUNN Power Management Event: This signal is asserted low by the DP83816 device to indicate that a

power management event has occurred. For pin connection, see Section 6.2.1.4.

Clock Run Function: In this mode, this pin is used to indicate when the PCICLK will be stopped.

PCI Bus Power Good: Connected to PCI bus 3.3-V power, this pin is used to sense the

PWRGOOD 123 I, PD presence of PCI bus power during the D3 power-management state.

Table 3-2. Pin Functions, Media Independent Interface(1)

PIN TYPE(2) DESCRIPTION

NAME NO.

Collision Detect: The COL signal is asserted high asynchronously by the external PMD on

COL 28 I detection of a collision on the medium. It remains asserted as long as the collision condition

persists.

Carrier Sense: This signal is asserted high asynchronously by the external PMD on detection of

CRS 29 I a non-idle medium.

Management Data Clock: Clock signal with a maximum rate of 2.5 MHz used to transfer

MDC 5 O management data for the external PMD on the MDIO pin.

Management Data I/O: Bidirectional signal used to transfer management information for the

MDIO 4 I/O external PMD. (See Section 5.4.1.4 for details on connections when MII is used.)

Receive Clock: A continuous clock, sourced by an external PMD device, that is recovered from

RXCLK 6 I the incoming data. During 100-Mb/s operation RXCLK is 25 MHz, and during 10 Mb/s RXCLK is

2.5 MHz.

I: BIOS ROM Address: During external BIOS ROM access, these signals become part of the

RXD3/MA9 12 ROM address.

RXD2/MA8 11 I/O O: Receive Data: Sourced from an external PMD, that contains data aligned on nibble

RXD1/MA7 10 boundaries and are driven synchronous to RXCLK. RXD3 is the most-significant bit and RXD0 is

RXD0/MA6 7 the least-significant bit.

I: Receive Data Valid: Indicates that the external PMD is presenting recovered and decoded

nibbles on the RXD signals, and that RXCLK is synchronous to the recovered data in 100-Mb/s

operation. This signal encompasses the frame, starting with the start-of-frame delimiter (JK) and

RXDV/MA11 15 I/O excluding any end-of-frame delimiter (TR).

O: BIOS ROM Address: During external BIOS ROM access, this signal becomes part of the

ROM address.

I: Receive Error: Asserted high synchronously by the external PMD whenever it detects a media

error and RXDV is asserted in 100-Mb/s operation.

RXER/MA10 14 I/O O: BIOS ROM Address: During external BIOS ROM access, this signal becomes part of the

ROM address.

Receive Output Enable: Used to disable an external PMD while the BIOS ROM is being

RXOE 13 O accessed.

Transmit Clock: A continuous clock that is sourced by the external PMD. During 100-Mb/s

TXCLK 31 I operation this is 25 MHz ±100 ppm. During 10-Mb/s operation this clock is 2.5 MHz ±100 ppm.

TXD3/MA15 25 Transmit Data: Signals which are driven synchronously to the TXCLK for transmission to the

TXD2/MA1 24 external PMD. TXD3 is the most-significant bit and TXD0 is the least-significant bit.

TXD1/MA1 23 BIOS ROM Address: During external BIOS ROM access, these signals become part of the ROM

TXD0/MA12 22 address.

Transmit Enable: This signal is synchronous to TXCLK and provides precise framing for data

TXEN 30 O carried on TXD[3–0] for the external PMD. It is asserted when TXD[3–0] contains valid data to be

transmitted.

(1) MII is normally in the high-impedance state, unless enabled by CFG: EXT_PHY. See Section 5.6.3.2.

(2) I = input, O = output, I/O = input/output

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Table 3-3. Pin Functions, 10/100-Mb/s PMD Interface

PIN TYPE(1) DESCRIPTION

NAME NO.

Transmit Data: Differential common-output driver. This differential common output is configurable

to either 10BASE-T or 100BASE-TX signaling:

10BASE-T: Transmission of Manchester-encoded 10BASE-T packet data as well as link pulses

TPTDP 54 I/O (including fast link pulses for auto-negotiation purposes).

TPTDM 53 100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data.

The DP83816 device automatically configures this common output driver for the proper signal

type as a result of either forced configuration or auto-negotiation.

Receive Data: Differential common-input buffer. This differential common input can be configured

to accept either 100BASE-TX or 10BASE-T signaling:

10BASE-T: Reception of Manchester-encoded 10BASE-T packet data as well as normal link

TPRDP 46 I/O pulses and fast link pulses for auto-negotiation purposes.

TPRDM 45 100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3 data.

The DP83816 device automatically configures this common input buffer to accept the proper

signal type as a result of either forced configuration or auto-negotiation.

(1) I/O = input/output

Table 3-4. Pin Functions, BIOS ROM(1) or Flash Interface

PIN TYPE(2) DESCRIPTION

NAME NO.

BIOS ROM or Flash Chip Select: During a BIOS ROM or flash access, this signal is used

MCSN 129 O to select the ROM device.

MD7, MD6 141, 140,

MD5, MD4/EEDO, 139, 138,

MD3 135, I/O, PD BIOS ROM or Flash Data Bus: During a BIOS ROM or flash access, these signals are used

MD2, 134, I/O, PU to transfer data to or from the ROM or flash device.

MD1/CFGDISN, 133,

MD0 132

MA5, 3,

MA4/EECLK, 2,

MA3/EEDI, 1, BIOS ROM or Flash Address: During a BIOS ROM or flash access, these signals are used to

MA2/LED100LNK, 144, drive the ROM or flash address.

MA1/LED10LNK, 143,

MA0/LEDACT 142

BIOS ROM or Flash Write: During a BIOS ROM or flash access, this signal is used to

MWRN 131 O enable data to be written to the flash device.

BIOS ROM or Flash Read: During a BIOS ROM or flash access, this signal is used to

MRDN 130 O enable data to be read from the flash device.

(1) The DP83816 device supports the NM27LV010 EPROM for the BIOS ROM interface device.

(2) O = output, I/O = input/output, PD = pulldown, PU = pullup

Table 3-5. Pin Functions, Clock Interface

PIN TYPE(1) DESCRIPTION

NAME NO.

Crystal or Oscillator Input: This pin is the primary clock reference input for the DP83816 device

and must be connected to a 25-MHz 0.005% (50-ppm) clock source. The DP83816 device

X1 17 I supports either an external crystal resonator connected across pins X1 and X2, or an external

CMOS-level oscillator source connected to pin X1 only.

Crystal Output: This pin is used in conjunction with the X1 pin to connect to an external 25-MHz

X2 18 O crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock

source is used. For more information, see the definition for pin X1.

(1) I = input, O = output

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Table 3-6. Pin Functions, LED Interface

PIN TYPE(1) DESCRIPTION

NAME NO.

TX/RX Activity: This pin is an output indicating transmit/receive activity. This pin is driven low

LEDACT/MA0 142 O to indicate active transmission or reception, and can be used to drive a low-current LED (<6

mA). The activity event is stretched to a minimum duration of approximately 50 ms.

100 Mb/s Link: This pin is an output indicating the 100-Mb/s link status. This pin is driven low

LED100LNK/MA2 144 O to indicate good-link status for 100-Mb/s operation, and can be used to drive a low-current

LED (<6 mA).

10 Mb/s Link: This pin is an output indicating the 10-Mb/s link status. This pin is driven low to

LED10LNK/MA1 143 O indicate good-link status for 10-Mb/s operation, and can be used to drive a low-current LED

(<6 mA).

(1) O = output

Table 3-7. Pin Functions, Serial EEPROM Interface(1)

PIN TYPE(2) DESCRIPTION

NAME NO.

EESEL 128 O EEPROM Chip Select: This signal is used to enable an external EEPROM device.

EEPROM Clock: During an EEPROM access (EESEL asserted), this pin is an output used to

EECLK/MA4 2 O drive the serial clock to an external EEPROM device.

EEPROM Data In: During an EEPROM access (EESEL asserted), this pin is an output used

EEDI/MA3 1 O to drive opcode, address, and data to an external serial EEPROM device.

EEPROM Data Out: During an EEPROM access (EESEL asserted), this pin is an input used

EEDO/MD4 138 I, PU to retrieve EEPROM serial-read data.

Configuration Disable: When pulled low at power-on time, disables the loading of

MD1/CFGDISN 133 I/O configuration data from the EEPROM. Use 1 kΩto ground to disable configuration loading.

(1) The DP83816 device supports NM93C46 for the EEPROM device.

(2) I = input, O = output, I/O = input/output, PU = pullup

Table 3-8. Pin Functions, Special Connections

PIN TYPE(1) DESCRIPTION

NAME NO.

Band-Gap Reference: External current reference resistor for internal PHY band-gap circuitry.

VREF 40 I The value of this resistor is 10 kΩ1% metal film (100 ppm/°C) which must be connected from the

VREF pin to analog ground.

34, 42, 43,

36, 37, 84,

NC — No connect

85,124,

125, 126

NU 41, 50, 127 — These pins are reserved and cannot be connected to any external logic or net.

REGEN 48 PD Reserved and must not be connected to any external logic or net.

(1) I = input, PU = pulldown

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Table 3-9. Pin Functions, Power Supply Pins

PIN TYPE(1) DESCRIPTION

NAME NO.

C1 19 I Connect to GND through 10-µF and 0.1-µF external capacitors in parallel.

IAUXVDD 39, 47 I Connect to isolated Aux 3.3-V supply VDD

9, 21, 27, 33, 56, 58,

AUXVDD I Connect to Aux 3.3-V supply VDD

137

PCIVDD 69, 80, 94, 107, 117 I PCI VDD – connect to PCI bus 3.3-V VDD

8, 16, 20, 26, 32, 35,

38, 44, 49, 51, 52, 55,

VSS I VSS

57, 65, 77, 90, 103,

114, 136

(1) I = input

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4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VDD Supply voltage –0.5 3.6 V

VIN DC input voltage –0.5 5.5 V

VOUT DC output voltage –0.5 VDD + 0.5 V

PDPower dissipation 504 mW

Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±1000

Electrostatic

V(ESD) V

discharge Machine model ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) RZAP = 1.5 kΩ, CZAP = 120 pF

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VDD Supply voltage 3.3 0.3 V

TANormal operating temperature 0 70 °C

4.4 Thermal Information

DP83816

THERMAL METRIC(1) PGE (LQFP) UNIT

144 PINS

RθJA Junction-to-ambient thermal resistance 47.2 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 10.5 °C/W

RθJB Junction-to-board thermal resistance 28.3 °C/W

ψJT Junction-to-top characterization parameter 0.2 °C/W

ψJB Junction-to-board characterization parameter 27.8 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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4.5 Electrical Characteristics – DC Specifications

TA= 0°C to 70°C, VDD = 3.3 V ±0.3 V (unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH Minimum high-level output voltage IOH = –6 mA(1) VDD – 0.5 V

VOL Maximum low-level output voltage IOL = 6 mA(1) 0.4 V

VIH Minimum high-level input voltage See (1) 2 V

VIL Maximum low-level input voltage See (1) 0.8 V

IIN Input current VIN = VDD or GND –10 10 µA

VOUT = VDD or GND, high-

IOZ Output leakage current –10 10 µA

impedance state

IDD Operating supply current IOUT = 0 mA (2) 116 140 mA

WOL standby 90 105 mA

Sleep mode 16 20 mA

RINdiff Differential input resistance From TPRDP to TPRDM 5 6 kΩ

VTPTD_100 100-Mb/s transmit voltage From TPTDP to TPTDM 0.95 1 1.05 V

VTPTDsym 100-Mb/s transmit voltage symmetry From TPTDP to TPTDM ±2%

VTPTD_10 10-Mb/s transmit voltage From TPTDP to TPTDM 2.2 2.5 2.8 V

CIN CMOS input capacitance 8 pF

COUT CMOS output capacitance 8 pF

SDTHon 100BASE-TX signal detect turnon threshold From TPRDP to TPRDM 1000 mV diff pk-pk

SDTHoff 100BASE-TX signal detect turnoff threshold From TPRDP to TPRDM 200 mV diff pk-pk

VTH1 10BASE-T receive threshold From TPRDP to TPRDM 300 585 mV

(1) These values ensure 3.3-V and 5-V compatibility.

(2) For IDD measurements, outputs are not loaded.

4.6 AC Timing Requirements

PARAMETER MIN TYP MAX UNIT

PCI CLOCK TIMING (See Figure 4-1)

t1PCICLK low time 12 ns

t2PCICLK high time 12 ns

t3PCICLK cycle time 30 ∞ns

CLOCK TIMING (See Figure 4-2)

t1X1 low time 16 ns

t2X1 high time 16 ns

t3X1 cycle time 40 40 ns

POWER-ON RESET (PCI ACTIVE) (See Figure 4-3)

t1RSTN active duration from PCICLK stable 1 ms

EE enabled 1500

t2Reset disable to first PCI cycle µs

EE disabled 1

NON-POWER-ON RESET (See Figure 4-4)

t1RSTN to output float 40 ns

POR PCI INACTIVE (See Figure 4-5)

VDD stable to EE access VDD indicates the digital supply (AUX power plane, except PCI bus

t160 µs

power)

t2EE configuration load duration 2000 µs

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AC Timing Requirements (continued)

PARAMETER MIN TYP MAX UNIT

PCI BUS CYCLES (See Figure 4-6 through Figure 4-14)

t1Input setup time 7 ns

t2Input hold time 0 ns

t3Output valid delay 2 11 ns

t4Output float delay (toff time) 28 ns

t5Output valid delay for REQN – point to point 2 12 ns

t6Input setup time for GNTN – point to point 10 ns

EEPROM AUTO-LOAD (See Figure 4-15)

t1EECLK cycle time 4 µs

t2EECLK delay from EESEL valid 1 µs

t3EECLK low to EESEL invalid 2 µs

t4EECLK to EEDO valid 2 µs

t5EEDI setup time to EECLK 2 µs

t6EEDI hold time from EECLK 2 µs

BOOT PROM OR FLASH (See Figure 4-16)

t1Data setup time to MRDN invalid 20 ns

t2Address setup time to MRDN valid 30 ns

t3Address hold time from MRDN invalid 0 ns

t4Address invalid from MWRN valid 180 ns

t5MRDN pulse duration 180 ns

t6Data hold time from MRDN invalid 0 ns

t7Data invalid from MWRN invalid 60 ns

t8Data valid to MWRN valid 30 ns

t9Address setup time to MWRN valid 30 ns

t10 MRDN invalid to MWRN valid 150 ns

t11 MWRN pulse width 150 ns

t12 Address and MRDN cycle time 210 ns

t13 MCSN valid to MRDN valid 30 ns

t14 MCSN invalid to MRDN invalid 0 ns

t15 MCSN valid to MWRN valid 30 ns

t16 MWRN invalid to MCSN invalid 30 ns

t17 MCSN valid to address valid 0 ns

100BASE-TX TRANSMIT (See Figure 4-17)

T2.8.1 100-Mb/s TPTDP, TPTDM rise and fall times 3 4 6 ns

100-Mb/s rise and fall mismatch 500 ps

T2.8.2 100 Mb/s TPTDP, TPTDM transmit jitter 1.4 ns

10BASE-T TRANSMIT END OF PACKET (See Figure 4-18)

T2.14.1 End-of-packet high time (with 0 ending bit) 300 ns

T2.14.2 End-of-packet high time (with 1 ending bit) 250 ns

10-Mb/s JABBER TIMING (See Figure 4-19)

T2.18.1 Jabber activation time 85 ms

T2.18.2 Jabber deactivation time 500 ms

10BASE-T NORMAL LINK PULSE (See Figure 4-20)

T2.19.1 Pulse duration 100 ns

T2.19.2 Pulse period 16 ms

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1st PCI Cycle

Reset Complete

Power Stable

RSTN

PCICLK

T2T1 T2

T3T3

PCICLK

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AC Timing Requirements (continued)

PARAMETER MIN TYP MAX UNIT

AUTO-NEGOTIATION FAST LINK PULSE (FLP) (See Figure 4-21)

T2.20.1 Clock data-pulse duration 100 ns

T2.20.2 Clock-pulse to clock-pulse period 125 µs

T2.20.3 Clock-pulse to data-pulse period 62.5 µs

T2.20.4 Burst duration 2 ms

T2.20.5 FLP-burst to FLP-burst period 16 ms

MEDIA-INDEPENDENT INTERFACE (MII) (See Figure 4-22)

t1MDC to MDIO valid 0 300 ns

t2MDIO to MDC setup 10 10 ns

t3MDIO from MDC hold 10 ns

t4RXD to RXCLK setup 10 ns

t5RXD from RXCLK hold 10 ns

t6RXDV, RXER to RXCLK setup 10 ns

t7RXDV, RXER from RXCLK hold 10 ns

t8TXCLK to TXD valid 0 25 ns

t9TXCLK to TXEN valid 0 25 ns

Figure 4-1. PCI Clock Timing (see PCI CLOCK TIMING in Section 4.6)

Figure 4-2. Clock Timing (see CLOCK TIMING in Section 4.6)

Note: Minimum reset complete time is a function of the PCI-, transmit-, and receive-clock frequencies.

Note: Minimum access after reset is dependent on PCI clock frequency. Accesses to the DP83816 device during this period

are ignored.

Note: EE is disabled for non-power-on reset.

Figure 4-3. Power-On Reset (PCI Active) (see POWER-ON RESET (PCI ACTIVE) in Section 4.6)

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PCICLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr

Data

IDSEL

T1 T2

T1 T2 T4

T1 T2

Cmd BE

EESEL

TPRD

VDD

1st PCI Cycle

RSTN

Output

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Note: Minimum reset-complete time is a function of the PCI-, transmit-, and receive-clock frequencies.

Figure 4-4. Non-Power-On Reset (see NON-POWER-ON RESET) in Section 4.6)

Figure 4-5. POR PCI Inactive (see POR PCI INACTIVE in Section 4.6)

Figure 4-6. PCI Configuration Read (see PCI BUS CYCLES in Section 4.6)

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PCICLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr

Data

T3 T3

Cmd BE

T1 T2

T3 T3 T4

PCICLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr Data

IDSEL

Cmd BE

T2 T1

T1 T2

T3 T4

T1 T2

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Figure 4-7. PCI Configuration Write (see PCI BUS CYCLES in Section 4.6)

Figure 4-8. PCI Bus Master Read (see PCI BUS CYCLES in Section 4.6)

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PCICLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr

Data

T1 T2

T1 T2 T4

T1 T2

Cmd BE

PCICLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr

Data

Cmd BE

T3 T4

T3 T3 T4

T1 T2

T3 T4

T1 T2

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Figure 4-9. PCI Bus Master Write (see PCI BUS CYCLES in Section 4.6)

Figure 4-10. PCI Target Read (see PCI BUS CYCLES in Section 4.6)

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PCICLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr

Cmd BE

T1 T2

T3 T4

Data Data Data

PCICLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr Data

Cmd BE

T1 T2

T3 T4

T1 T2

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Figure 4-11. PCI Target Write (see PCI BUS CYCLES in Section 4.6)

Figure 4-12. PCI Bus Master Burst Read (see PCI BUS CYCLES in Section 4.6)

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T1T1

EECLK

EESEL

EEDO

EEDI

PCICLK

REQN

GNTN

PCICLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr

Data

Cmd BE

T3 T4

T3 T3 T4

T1 T2

T3 T4

Data Data

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Figure 4-13. PCI Bus Master Burst Write (see PCI BUS CYCLES in Section 4.6)

Figure 4-14. PCI Bus Arbitration (see PCI BUS CYCLES in Section 4.6)

See the NM93C46 data sheet

Figure 4-15. EEPROM Auto-Load (see EEPROM AUTO-LOAD in Section 4.6)

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PMD Output Pair

T2.8.1

+1 rise

+1 fall

-1 fall -1 rise

eye pattern

T2.8.2

90%

10%

90%

PMD Output Pair

MCSN

MRDN

MA[15:0]

MD[7:0]

MWRN

T3 T4

T10

T11T12

T13

T15 T16

T14

T17

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Note: Timings are based on a 30-ns clock period.

Figure 4-16. Boot PROM or Flash (see BOOT PROM OR FLASH in Section 4.6)

Note: Normal mismatch is the difference between the maximum and minimum of all rise and fall times.

Note: Rise and fall times taken at 10% and 90% of the +1 or –1 amplitude.

Note: Carrier sense on delay is determined by measuring the time from the first bit of the J code group to the assertion of

carrier sense.

Note: 1 bit time = 10 ns in 100-Mb/s mode.

Note: The ideal window recognition region is ±4 ns.

Figure 4-17. 100BASE-TX Transmit (see100BASE-TX TRANSMIT in Section 4.6)

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T2.19.2

T2.19.1

Normal Link Pulse(s)

TXE

PMD Output Pair

COL

T2.18.2

T2.18.1

TX_CLK

TX_EN

PMD Output Pair 0 0

1 1

PMD Output Pair

T2.14.1

T2.14.2

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Figure 4-18. 10BASE-T Transmit End of Packet (see10BASE-T TRANSMIT END OF PACKET in

Section 4.6)

Figure 4-19. 10-Mb/s Jabber Timing (see10-Mb/s JABBER TIMING in Section 4.6)

Note: These specifications represent both transmit and receive timings.

Figure 4-20. 10BASE-T Normal Link Pulse (see10BASE-T NORMAL LINK PULSE in Section 4.6)

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MDC

MDIO(output)

MDIO(input)

RXCLK

RXD[3:0]

RXDV, RXER

TXCLK

TXD[3:0]

TXEN

T2 T3

clock

pulse data

pulse clock

pulse

FLP Burst FLP Burst

Fast Link Pulse(s)

T2.20.1

T2.20.2

T2.20.3

T2.20.4

T2.20.5

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Note: These specifications represent both transmit and receive timings.

Figure 4-21. Auto-Negotiation Fast Link Pulse (FLP) (see AUTO-NEGOTIATION FAST LINK PULSE (FLP)

in Section 4.6)

Figure 4-22. Media Independent Interface (MII) (see MEDIA-INDEPENDENT INTERFACE (MII) in

Section 4.6)

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MAC/BIU

Interface

SRAM

25-MHZ Clk

MII RX

MII TX

MII Mgt

BIOS ROM Cntl

BIOS ROM Data

BROM/EE

PCI AD

PCI CNTL

PCI CLK

3-V DSP Physical Layer

Logic

RX-2 KB

SRAM

TX-2 KB

TPRDP/M

EEPROM/LEDs

MII TX

MII RX

MII Mgt

Test data in

Test data out

MII TX

MII RX

MII Mgt

TPTDP/M

DP83816

Tx Addr

Tx wr data

Rx Addr

Rx wr data

Rx rd data

Tx rd data

RAM

BIST

Logic

SRAM

RXFilter

0.5 KB

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5 Detailed Description

5.1 Overview

The DP83816 device consists of a MAC and BIU (media access controller and bus interface unit), a

physical layer interface, SRAM, and miscellaneous support logic. The MAC and BIU include the PCI bus,

BIOS ROM and EEPROM interfaces, and an 802.3 MAC. The physical layer interface used is a single-port

version of the 3.3-V DsPhyterII.internal memory consists of one 0.5KB and two 2KB SRAM blocks.

5.2 Functional Block Diagram

Figure 5-1. DP83816 Functional Block Diagram

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Tx Buffer Manager

MIB

Tx MAC

Rx MAC

PCI Bus

Data FIFO

Physical Layer Interface

93C46

Serial

EEPROM

MAC/BIU

Rx Filter

Pkt Recog

Logic

SRAM

Rx Buffer Manager

Data FIFO

Boot ROM/

Flash

PCI Bus

Interface

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Figure 5-2. MAC and BIU Functional Block Diagram

5.3 Feature Description

This section includes information on the various configurable features available with the DP83816 device.

The configuration features described include:

• MAC and BIU

• Wake on LAN

• Receive filter logic

• CLKRUNN function

• Physical layer

• Auto-negotiation

• LED interface

• PHY loopback

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Byte 3Byte 2Byte 1Byte 0

0781516

232431

MSB

C/BE[0]C/BE[1]C/BE[2]C/BE[3]

LSB

Byte 0Byte 1Byte 2Byte 3

0781516

232431

LSB

C/BE[0]C/BE[1]C/BE[2]C/BE[3]

MSB

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5.3.1 MAC and BIU

The MAC and BIU design has been optimized to improve logic efficiency and enhanced to add features

consistent with current market needs and specification compliance. The MAC and BIU design blocks are

discussed in this section.

5.3.1.1 PCI Bus Interface

This block implements PCI v2.2 bus protocols and configuration space. The block supports bus master

reads and writes to CPU memory and CPU access to on-chip register space. Additional functions provided

include: configuration control, serial EEPROM access with auto configuration load, interrupt control, and

power management control with support for PME or CLKRUN functionality.

5.3.1.1.1 Byte Ordering

The DP83816 device can be configured to order the bytes of data on the AD[31:0] bus to conform to little

endian or big endian ordering through the use of configuration register, bit 0 (CFG:BEM). By default, the

device is in little endian ordering. Byte ordering only affects data FIFOs. Register information remains bit

aligned (that is, AD[31] maps to bit 31 in any register space, AD[0] maps to bit 0, and so forth).

Little Endian (CFG:BEM = 0): The byte orientation for receive and transmit data in system memory is as

follows:

Big Endian (CFG:BEM = 1): The byte orientation for receive and transmit data in system memory is as

follows:

5.3.1.1.2 PCI Bus Interrupt Control

PCI bus interrupts for the DP83816 device are asynchronously performed by asserting pin INTAN. This

pin is an open-drain output. The source of the interrupt can be determined by reading the Interrupt Status

CAUTION

Reading of the ISR clears ALL bits. Masking of specified interrupts can be

accomplished by using the Interrupt Mask Register (IMR).

5.3.1.1.3 Timer

The Latency Timer described in CFGLAT:LAT defines the minimum number of bus clocks that the device

holds the bus.= When the device gains control of the bus and issues FRAMEN, the latency timer begins

counting down. If GNTN is de-asserted before the DP83816 device has finished with the bus, the device

maintains ownership of the bus until the timer reaches zero (or has finished the bus transfer). The timer is

an 8-bit counter.

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5.3.1.2 Tx MAC

This block implements the transmit portion of 802.3 media access control. The Tx MAC retrieves packet

data from the Tx buffer manager and sends it out through the transmit portion. Additionally, the Tx MAC

provides MIB control information for transmit packets.

5.3.1.3 Rx MAC

This block implements the receive portion of 802.3 media access control. The Rx MAC retrieves packet

data from the receive portion and sends it to the Rx buffer manager. Additionally, the Rx MAC provides

MIB control information and packet address data for the Rx filter.

5.3.2 Wake on LAN

The Wake on LAN logic provides several mechanisms for bringing the DP83816 device out of a low-power

state. Wake on ARP, wake on broadcast, wake on multicast hash and wake on PHY Interrupt are enabled

by setting the corresponding bit in the wake command and status register, WCSR. Before the hardware is

programmed to a low-power state, the software must write a null receive descriptor pointer to the receive

descriptor pointer register (RXDP) to ensure wake packets are buffered in the RX fifo. See the description

of the RXDP register for this procedure.

When a qualifying packet is received, the Wake on LAN logic generates a Wake event and pulses the

PMEN PCI signal to request a power management state change. The software must then bring the

hardware out of low-power mode and, if the power management state was D3hot, reinitialize Configuration

occurred and a packet was received. The software must then write a valid receive descriptor pointer to

RXDP. The incoming packet can then be transferred into host memory for processing. Note that the wake

packet is retained for processing - this is a feature of the DP83816 device. In addition to the above Wake

on LAN features, the DP83816 device also provides Wake on Pattern Matching, Wake on DA match and

Wake on Magic Packet.

5.3.3 Wake on Pattern Matching

Wake on Pattern Matching is an extension of the Pattern Matching feature provided by the receive filter

logic. When one or more of the Wake on Pattern Match bits are set in the WCSR, a packet generates a

wake event if it matches the associated pattern buffer. The pattern count and the pattern buffer memory

are accessed in the same way as in Pattern Matching for packet acceptance. The minimum pattern count

is 2 bytes and the maximum pattern count is 64 bytes for patterns 0 and 1, and 128 bytes for patterns 2

and 3. Packets are compared on a byte by byte basis and bytes may be masked in pattern memory, thus

allowing for don’t cares. See Section 5.5.2 for programming examples.

5.3.4 CLKRUNN Function

CLKRUNN is a dual-function optional signal. It is used by the central PCI clock resource to indicate clock

status (that is, PCI clock running normally or slowed or stopped), and it is used by PCI devices to request

that the central resource restart the PCI clock or keep it running normally.

In the DP83816 device, CLKRUNN shares a pin with PMEN (pin 59). This means the chip cannot be

simultaneously PCI power management and PCI Mobile Design Guide- compliant; however, it is unlikely

that a system would use both of these functions simultaneously. The function of the PMEN/CLKRUNN pin

is selected with the CLKRUN_EN bit of CCSR.

CCSR bits 15 and 8 (PMESTS and PMEEN) are mirrored from PCI configuration space to allow them to

be accessed by software. The functionality of these bits is the same as in the PCI configuration register

PMCSR.

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As an output, CLKRUNN is open-drain like PMEN, that is, it can only drive low. CLKRUNN is an input

unless one of the following two conditions occurs:

• The system drives CLKRUNN high, but the DP83816 device is not ready for the PCI clock to be

stopped.

• The PCI clock is stopped or slowed (CLKRUNN is pulled high by the system) and the DP83816 device

requires the use of the PCI bus.

Situation 1 is a “clock continue” event and can occur if the DP83816 device has not completed a pending

packet transmit or receive. Situation 2 is a “clock start” event and can occur if the DP83816 device has

been programmed to a WOL state and it receives a wake packet, or the PCI clock has simply been

stopped and the receiver has data ready to DMA. In either of these situations, the DP83816 device

asserts CLKRUNN until it detects two rising edges of the PCI clock; it then releases assertion of

CLKRUNN. At this point, the central resource is driving CLKRUNN low, and cannot drive it high again until

at least four rising edges of the PCI clock have occurred since the initial CLKRUNN assertion by the

DP83816 device. Also in either situation, the DP83816 device must have detected CLKRUNN de-asserted

for two consecutive rising edges of the PCI clock before it is allowed to assert CLKRUNN.

NOTE

• If a clock start or continue event has completed but a PCI interrupt has not been serviced

yet, the CLKRUN logic does not prevent the system from stopping the PCI clock.

• If PMEEN is not set, the DP83816 device cannot assert CLKRUNN to request a clock

start or continue. In this case, if the system is going to stop the PCI clock, software must

shut down the internal PHY to prevent receive errors.

• If another CLKRUN-enabled device in the system encounters a clock start or continue

event, the cycle of assertions and de-assertions of CLKRUNN causes the DP83816 clock

multiplexer to switch the clock to the RX block back and forth between the PCI clock and

the X1 clock until the event completes.

5.3.5 Physical Layer

The DP83816 device has a full featured physical layer device with integrated PMD sub-layers to support

both 10BASE-T and 100BASE-TX Ethernet protocols. The physical layer is designed for easy

implementation of 10/100 Mb/s Ethernet home or office solutions. It interfaces directly to twisted pair

media via an external transformer. The physical layer uses on-chip digital signal processing (DSP)

technology and digital PLLs for robust performance under all operating conditions, enhanced noise

immunity, and lower external component count when compared to analog solutions.

5.3.5.1 Half Duplex vs Full Duplex

The DP83816 device supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex is the standard, traditional mode of operation which relies on the CSMA/CD protocol to handle

collisions and network access. In half-duplex mode, CRS responds to both transmit and receive activity to

maintain compliance with IEEE 802.3 specification.

Because the DP83816 device is designed to support simultaneous transmit and receive activity it is

capable of supporting fullduplex switched applications with a throughput of up to 200 Mb/s per port when

operating in 100BASE-TX mode. Because the CSMA/CD protocol does not apply to full-duplex operation,

the DP83816 device disables its own internal collision sensing and reporting functions.

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It is important to understand that while full auto-negotiation with the use of fast link pulse code words can

interpret and configure to support full-duplex, parallel detection can not recognize the difference between

full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. Therefore, as specified

in 802.3u, if a far-end link partner is transmitting forced full duplex 100BASE-TX for example, the parallel

detection state machine in the receiving station would be unable to detect the full duplex capability of the

far-end link partner and would negotiate to a half duplex 100BASE-TX configuration (same scenario for 10

Mb/s).

For full duplex operation, the following register bits must also be set:

• TXCFG:CSI (Carrier Sense Ignore)

• TXCFG:HBI (HeartBeat Ignore)

• RXCFG:ATX (Accept Transmit Packets)

Additionally, the auto-negotiation select bits in the configuration register must show full duplex support:

• CFG:ANEG_SEL

5.3.6 Auto-Negotiation

The auto-negotiation function provides a mechanism for exchanging configuration information between

two ends of a link segment and automatically selecting the highest performance mode of operation

supported by both devices. Fast link pulse (FLP) bursts provide the signaling used to communicate auto-

negotiation abilities between two devices at each end of a link segment. For further detail regarding auto-

negotiation, see Clause 28 of the IEEE 802.3u specification. The DP83816 device supports four different

Ethernet protocols (10 Mb/s half-duplex, 10 Mb/s full-duplex, 100 Mb/s half-duplex, and 100 Mb/s full-

duplex), so the inclusion of auto-negotiation ensures that the highest-performance protocol is selected

based on the advertised ability of the link partner. The auto-negotiation function within the DP83816

device is controlled by internal register access. Auto-negotiation is set at power up or reset, and also when

a link status (up or valid) change occurs.

5.3.6.1 Auto-Negotiation Register Control

When auto-negotiation is enabled, the DP83816 device transmits the abilities programmed into the auto-

negotiation advertisement register (ANAR) through FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s,

half-duplex, and full-duplex modes may be selected. The default setting of bits [8:5] in the ANAR and bit

12 in the BMCR register are determined at power-up.

The BMCR provides software with a mechanism to control the operation of the DP83816 device. Bits 1

and 2 of the PHYSTS register are only valid if auto-negotiation is disabled or after Auto-Negotiation is

complete. The auto-negotiation protocol compares the contents of the ANLPAR and ANAR registers and

uses the results to automatically configure to the highest performance protocol common to the local and

far-end port. The results of auto-negotiation may be accessed in register C0h (PHYSTS), bit 4: auto-

negotiation Complete, bit 2: duplex status and bit 1: Speed status.

Auto-Negotiation Priority Resolution:

1. 100BASE-TX Full Duplex (Highest Priority)

2. 100BASE-TX Half Duplex

3. 10BASE-T Full Duplex

4. 10BASE-T Half Duplex (Lowest Priority)

The basic mode control register (BMCR) provides control for enabling, disabling, and restarting the auto-

negotiation process. When auto-negotiation is disabled the speed selection bit in the BMCR (bit 13)

controls switching between 10 Mb/s or 100 Mb/s operation, and the duplex mode bit (bit 8) controls

switching between full duplex operation and half duplex operation. The speed selection and duplex mode

bits have no effect on the mode of operation when the auto-negotiation enable bit (bit 12) is set.

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The basic mode status register (BMSR) indicates the set of available abilities for technology types, Auto-

negotiation ability, and extended register capability. These bits are permanently set to indicate the full

functionality of the DP83816 device (only the 100BASE-T4 bit is not set because the DP83816 device

does not support that function).

The BMSR also provides status on:

• Auto-Negotiation complete (bit 5)

• Link Partner advertising that a remote fault has occurred (bit 4)

• Valid link has been established (bit 2)

• Support for Management Frame Preamble suppression (bit 6)

The Auto-Negotiation Advertisement Register (ANAR) indicates the auto-negotiation abilities to be

advertised by the DP83816 device. All available abilities are transmitted by default, but any ability can be

suppressed by writing to the ANAR. Updating the ANAR to suppress an ability is one way for a

management agent to change (force) the technology that is used.

The Auto-Negotiation Link Partner Ability Register (ANLPAR) is used to receive the base link code word

as well as all next page code words during the negotiation. Furthermore, the ANLPAR is updated to either

0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s, respectively.

The auto-negotiation expansion register (ANER) indicates additional auto-negotiation status. The ANER

provides status on:

• Parallel detect fault occurrence (bit 4)

• Link Partner support of the next page function (bit 3)

• DP83816 support of the next page function (bit 2). The DP83816 device supports the next page

function.

• Current page being exchanged by auto-negotiation has been received (bit1)

• Link Partner support of auto-negotiation (bit 0)

5.3.6.2 Auto-Negotiation Parallel Detection

The DP83816 device supports the parallel-detection function as defined in the IEEE 802.3u specification.

Parallel detection requires both the 10 Mb/s and 100 Mb/s receivers to monitor the receive signal and

report link status to the auto-negotiation function. Auto-negotiation uses this information to configure the

correct technology in the event that the link partner does not support auto-negotiation yet is transmitting

link signals that the 100BASE-TX or 10BASE-T PMAs (physical medium attachments) recognize as valid

link signals.

If the DP83816 device completes auto-negotiation as a result of Parallel Detection, bits 5 and 7 within the

ANLPAR register are updated to reflect the mode of operation present in the link partner. Note that bits

4:0 of the ANLPAR are also set to 00001 based on a successful parallel detection to indicate a valid 802.3

selector field. Software may determine that negotiation completed through parallel detection by reading

the ANER (98h) register with bit 0, link partner auto-negotiation Able bit, being reset to a zero, when the

auto-negotiation complete bit, bit 5 of the BMSR (84h) register is set to 1. If configured for parallel detect

mode, and any condition other than a single good link occurs, then the parallel detect fault bit, bit 4 of the

ANER register (98h), is set to 1.

5.3.6.3 Auto-Negotiation Restart

When auto-negotiation has completed, it may be restarted at any time by setting bit 9 (restart auto-

negotiation) of the BMCR to one. If the mode configured by a successful auto-negotiation loses a valid

link, then the auto-negotiation process resumes and attempst to determine the configuration for the link.

This function ensures that a valid configuration is maintained if the cable becomes disconnected.

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VDD

LED10N

453 Ω

LEDACTN

453 Ω

LED100N

453 Ω

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A renegotiation request from any entity, such as a management agent, causes the DP83816 device to halt

any transmit data and link pulse activity until the break_link_timer expires (≈1500 ms). Consequently, the

link partner goes into link fail and normal auto-negotiation resumes. The DP83816 device resumes auto-

negotiation after the break_link_timer has expired by issuing FLP (fast link pulse) bursts.

5.3.6.4 Enabling Auto-Negotiation Through Software

It is important to note that if the DP83816 device has been initialized on power-up as a non-auto-

negotiating device (forced technology), and it is then required that auto-negotiation or re-auto-negotiation

be initiated through software, bit 12 (auto-negotiation enable) of the basic mode control register must first

be cleared and then set for any auto-negotiation function to take effect.

5.3.6.5 Auto-Negotiation Complete Time

Parallel detection and auto-negotiation take approximately 2–3 seconds to complete. In addition, auto-

negotiation with next page should take approximately 2–3 seconds to complete, depending on the number

of next pages sent.

See Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to auto-

negotiation.

5.3.7 LED Interfaces

The DP83816 device has parallel outputs to indicate the status of activity (transmit or receive), 100 Mb/s

link, and 10 Mb/s link.

The LEDACT pin indicates the presence of transmit or receive activity. The standard CMOS driver goes

low when RX or TX activity is detected in either 10-Mb/s or 100-Mb/s operation.

The LED100LNK pin indicates a good link at the 100-Mb/s data rate. The standard CMOS driver goes low

when this occurs. In 100BASE-T mode, link is established as a result of input receive amplitude compliant

with TP-PMD specifications which result in internal generation of signal detect. This signal asserts after

the internal signal detect has remained asserted for a minimum of 500 µs. The signal de-asserts

immediately following the de-assertion of the internal signal detect.

The LED10LNK pin indicates a good link at the 10-Mb/s data rate. The standard CMOS driver goes low

when this occurs. The 10-Mb/s Link is established as a result of the reception of at least seven

consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This causes the assertion of

this signal. The signal de-asserts in accordance with the Link Loss Timer as specified in IEEE 802.3.

The DP83816 LED pins are capable of 6 mA. Connection of these LED pins should ensure this is not

overloaded. Using 2-mA LED devices the connection for the LEDs could be as shown in Figure 5-3.

Figure 5-3. LED Loading Example

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5.3.7.1 Status Information

The 10-Mb/s link is established as a result of the reception of at least seven consecutive normal link

pulses or the reception of a valid 10BASE-T packet. LED10LNK de-asserts in accordance with the link

loss timer specified in IEEE 802.3.

The 100BASE-T Link is established as a result of an input receive amplitude compliant with TP-PMD

specifications, which results in the internal generation of signal detect. LED100LNK asserts after the

internal signal detect has remained asserted for a minimum of 500 μs. LED100LNK de-asserts

immediately following the de-assertion of the internal signal detect.

5.3.8 PHY Loopback

The DP83816 device includes a PHY loopback test mode for easy board diagnostics. The Loopback mode

is selected through bit 14 (Loopback) of the basic mode control register (BMCR). Writing 1 to this bit

enables transmit data to be routed to the receive path early in the physical layer cell. Loopback status may

be checked in bit 3 of the PHY status register (C0h). While in loopback mode, the data is not transmitted

onto the media. This is true for either 10-Mb/s or 100-Mb/s data.

In 100BASE-TX loopback mode the data is routed through the PCS and PMA layers into the PMD

sublayer before it is looped back. Therefore, in addition to serving as a board diagnostic, this mode serves

as quick functional verification of the device.

NOTE

A Mac Loopback can be performed through setting bit 29 (Mac Loopback) in the Tx

Configuration Register.

5.4 Device Functional Modes

5.4.1 802.3u MII

The DP83816 device incorporates the media independent interface (MII) as specified in Clause 22 of the

IEEE 802.3u standard. This interface may be used to connect 10/100 Mb/s PHY devices. This section

describes the MII configuration steps as well as the serial MII management interface and nibble wide MII

data interface.

5.4.1.1 MII Access Configuration

The DP83816 device must be specifically configured for accessing the MII. This is done by first connecting

pin 133 (MD1/CFGDISN) to GND through a 1-kΩresistor. Then setting bit 12 (EXT_PHY) of the CFG

disabled, as reported by bit 9 (PHY_DIS) of the CFG register. The MII must then be initialized, as

described in Serial Management Access Protocol, before the external PHY can be detected.

If external MII is not selected through the register setting as described, then the internal PHY is used and

the MII pins of the MacPhyter-II can be left unconnected.

5.4.1.2 MII Serial Management

The MII serial management interface allows for the configuration and control of PHY registers, gathering

of status, error information, and the determination of the type and capabilities of the attached PHYs.

The MII serial management specification defines a set of thirty-two 16-bit status and control registers that

are accessible through the management interface pins MDC and MDIO. A description of the serial

management interface access and access protocol follows.

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5.4.1.3 MII Serial Management Access

Management access to the PHYs is done through management data clock (MDC) and management data

input/output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is

bi-directional and may be shared by up to 32 devices.

The internal PHY counts as one of these 32 devices. The internal PHY has the advantage of having direct

the MII.

Access and control of the MDC and MDIO pins is done via the MII/EEPROM Access Register (MEAR).

The clock (MDC) is created by alternating writes of 0 then 1 to the MDC bit (bit 6). Control of data

direction is done by the MDDIR bit (bit 5). Data is either recorded or written by the MDIO bit (bit 4). Setting

the MDDIR bit to a 1 allows the DP83816 device to drive the MDIO pin. Setting the MDDIR bit to a 0

allows the MDIO bit to reflect the value of the MDIO pin. See Section 5.5.3.3.

This bit-bang access of the MDC and MDIO pins thus requires 64 accesses to the MEAR register to

complete a single PHY register transaction. Because a PHY device is typically self configuring and

adaptive this serial management access is usually only required at initialization time and therefore is not

time critical.

5.4.1.4 Serial Management Access Protocol

The serial control interface clock (MDC) has a maximum clock rate of 25 MHz and no minimum rate. The

MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown in

Table 5-1. If external PHY devices may be attached and removed from the MII there should be a 15 kΩ

pulldown resistor on the MDIO signal.

If the PHY is always to be connected, then there should be a 1.5-kΩpullup resistor which, during IDLE

and turnaround, pulls MDIO high. To initialize the MDIO interface, the DP83816 device sends a sequence

of 32 contiguous logic ones on MDIO provides the PHYs with a sequence that can be used to establish

synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC

clock cycles, or by simply allowing the MDIO pullup resistor to pull the MDIO pin high during which time 32

MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if

an invalid start, opcode, or turnaround bit is detected.

Table 5-1. Typical MDIO Frame Format

MII Management <idle><start><op code><device add><reg addr><turnaround><data><idle>

Serial Protocol

Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>

Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>

The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle

line state.

Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field.

To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the

first bit of Turnaround. The addressed PHY drives the MDIO with a zero for the second bit of turnaround

and follows this with the required data. Figure 5-4 shows the timing relationship between MDC and the

MDIO as driven and received by the DP83816 device and a PHY for a typical register read access.

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MDC

MDIO

0 0 01 1 1 1 0 0 0 0 0 0 0

(STA)

Idle Start Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR) TA Register Data

Z00 0 0 0 0 0 0 0 0 0 0 0 0 Z

Idle

1 0 0 0

MDC

MDIO

0 0 01 1 1 1 0 0 0 0 0 0 0

(STA)

Idle Start Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR) TA Register Data

MDIO

(PHY)

Z00 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 Z

Idle

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Figure 5-4. Typical MDC and MDIO Read Operation

For write transactions, the DP83816 device writes data to the addressed PHY thus eliminating the

requirement for MDIO turnaround. The turnaround time is filled by the DP83816 device by inserting <10>.

Figure 5-5 shows the timing relationship for a typical MII register write access.

5.4.1.5 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the media independent interface. This interface include

separate dedicated receive and transmit busses. These two data busses, along with various control and

indication signals, allow for the simultaneous exchange of data between the DP83816 device and PHYs.

Figure 5-5. Typical MDC and MDIO Write Operation

The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RXER, a receive

data valid flag RXDV, and a receive clock RXCLK for synchronous transfer of the data. The receive clock

can operate at 2.5 MHz to support 10-Mb/s operation modes or at 25 MHz to support 100-Mb/s

operational modes.

The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal TXEN,

and a transmit clock TXCLK which runs at 2.5 MHz or 25 MHz.

Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The

CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in

half duplex mode. The COL signal asserts as an indication of a collision which can occur during half-

duplex operation when both a transmit and receive operation occur simultaneously.

5.4.1.6 Collision Detection

For half duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels

are active simultaneously. Collisions are reported by the COL signal on the MII.

If the PHY is transmitting in 10-Mb/s mode when a collision is detected, the collision is not reported until

seven bits have been received while in the collision state. This prevents a collision being reported

incorrectly due to noise on the network. The COL signal remains set for the duration of the collision.

If a collision occurs during a receive operation, it is immediately reported by the COL signal.

When heartbeat is enabled (only applicable to 10-Mb/s operation), approximately 1 µs after the

transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is

generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of

the MII.

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5.4.1.7 Carrier Sense

Carrier sense (CRS) is asserted due to receive activity when valid data is detected during 10-Mb/s

operation. During 100-Mb/s operation, CRS is asserted when a valid link (SD) and two non-contiguous

zeros are detected.

For 10- or 100-Mb/s half-duplex operation, CRS is asserted during either packet transmission or reception.

For 10- or 100-Mb/s full duplex operation, CRS is asserted only due to receive activity.

CRS is de-asserted following an end of packet.

5.4.2 Sleep Mode

Sleep mode is a system-level function that allows a device to be placed in a lower power mode than WOL

mode. In sleep mode, the device is not able to detect wake events or signal the system that it needs

service.

5.4.2.1 Entering Sleep Mode

The following steps are required to enter sleep mode:

1. Disable the receiver by writing a 1 to the receiver disable bit in the command register (CR:RXD).

2. Write 0 to the receive descriptor pointer register (RXDP)

3. Force the receiver to reread the descriptor pointer by writing a 1 to the receiver enable bit in the

command register (CR:RXE).

4. Do not configure any wake events in WCSR.

5. Write a 0 to PME enable, and set the desired power state in PMCSR. These can be done in one

operation. An ACPI-compatible operating system should handle this step.

6. If the power management state is D3cold, the system asserts PCI reset, stops the PCI clock, and

removes power from the PCI bus.

5.4.2.2 Exiting Sleep Mode

The following steps are required to bring the DP83816 device out of Sleep Mode:

1. If the power management state is D3cold, the system asserts PCI reset, restores PCI bus power, and

restarts the PCI clock. This also returns the power state to D0. The PCI configuration registers (that is.

base addresses, bus master enable, and so forth) must be reinitialized.

2. Write a 0 to power state bits [0:1] in the PMCSR (in case the sleep power state was not D3hot or

D3cold).

3. If the sleep power state was D3hot or D3cold, reinitialize addresses, bus master enable, and so forth).

An ACPI-compatible operating system should handle this step. Note that operational registers are not

accessible until this step is completed.

4. Disable the receiver by writing a 1 to the receiver disable bit in the command register (CR:RXD).

5. Write a valid receive descriptor pointer to the receive descriptor pointer register (RXDP)

6. Enable the receiver by writing a 1 to the receiver enable bit in the command register (CR:RXE).

5.5 Programming

5.5.1 Architecture

This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each

operation consists of several functional blocks and described in the following:

• 100BASE-TX Transmitter

• 100BASE-TX Receiver

• 10BASE-T Transceiver Module

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4B5B CODE-GROUP

ENCODER &

INJECTOR

SCRAMBLER

NRZ TO NRZI

ENCODER

5B PARALLEL

TO SERIAL

PMD OUTPUT PAIR

TX_CLK TXD[3:0] /

TX_EN

BINARY

TO MLT-3 /

COMMON

DRIVER

125MHZ CLOCK

BP_SCR MUX

100BASE-TX

LOOPBACK

MLT[1:0]

DIVIDE

BY 5

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• Buffer Management

5.5.1.1 100BASE-TX Transmitter

The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble

data, to a scrambled MLT-3 125-Mb/s serial data stream. Because the 100BASE-TX TP-PMD is

integrated, the differential output pins, TPTDP and TPTDM, can be directly routed to the magnetics.

The block diagram in Figure 5-6 provides an overview of each functional block within the 100BASE-TX

transmit section.

The Transmitter section consists of the following functional blocks:

• Code-group Encoder and Injection block (bypass option)

• Scrambler block (bypass option)

• NRZ to NRZI encoder block

• Binary to MLT-3 converter and common driver

The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for

applications such as 100-Mb/s repeaters where data conversion is not always required. The DP83816

device implements the 100BASETX transmit state machine diagram as specified in the IEEE 802.3u

Standard, Clause 24.

Figure 5-6. 100BASE-TX Transmit Block Diagram

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binary_in

binary_plus

binary_minus

binary_in

binary_plus

binary_minus

Common

Driver MLT-3

differential MLT-3

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5.5.1.1.1 Code-group Encoding and Injection

The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups

for transmission. This conversion is required to allow control data to be combined with packet data code-

groups. See Table 5-2 for 4B to 5B code-group mapping details. The code-group encoder substitutes the

first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) on transmission.

The code-group encoder continues to replace subsequent 4B preamble and data nibbles with

corresponding 5B code-groups. At the end of the transmit packet, on the de-assertion of Transmit Enable

signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111) indicating

the end of frame.

After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data

stream until the next transmit packet is detected (re-assertion of Transmit Enable).

5.5.1.1.2 Scrambler

The scrambler is required to control the radiated emissions at the media connector and on the twisted pair

cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is

randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and

on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (that is,

continuous transmission of IDLEs).

The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit

polynomial. The output of the closed loop LFSR is XORed with the serial NRZ data from the code-group

encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated

emissions at certain frequencies by as much as 20 dB.

5.5.1.1.3 NRZ to NRZI Encoder

After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded to

comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 un-shielded twisted pair

cable. There is no ability to bypass this block within the DP83816 device.

5.5.1.1.4 Binary to MLT-3 Convertor and Common Driver

The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from

the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary

streams are then fed to the twisted pair output driver which converts the voltage to current and alternately

drives either side of the transmit transformer primary winding, resulting in a minimal current (20 mA max)

MLT-3 signal. See Figure 5-7.

Figure 5-7. Binary to MLT-3 Conversion

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Table 5-2. 4B5B Code-Group Encoding and Decoding

NAME PCS 5B CODE-GROUP DESCRIPTION OR 4B VALUE

DATA CODES

0 11110 0000

1 01001 0001

2 10100 0010

3 10101 0011

4 01010 0100

5 10110 0101

6 01110 0110

7 01111 0111

8 10010 1000

9 10011 1001

A 10110 1010

B 10111 1011

C 11010 1100

D 11011 1101

E 11100 1110

F 11101 1111

IDLE AND CONTROL CODES

H 00100 HALT code-group - Error code

I 11111 Inter-Packet IDLE - 0000

J 11000 First Start of Packet - 0101

K 10001 Second Start of Packet - 0101

T 01101 First End of Packet - 0000

R 00111 Second End of Packet - 0000

INVALID CODES

V 00000

V 00001

V 00010

V 00011

V 00101

V 00110

V 01000

V 01100

V 10000

V 11001

The 100BASE-TX MLT-3 signal sourced by the TPTDM and TPTDP common-driver output pins is slew

rate controlled. This should be considered when selecting ac-coupling magnetics to ensure TP-PMD

Standard compliant transition times (3 ns ≤Tr < 5 ns).

The 100BASE-TX transmit TP-PMD function within the DP83816 device is capable of sourcing only MLT-3

encoded data. Binary output from the TPTDM and TPTDP outputs is not possible in 100-Mb/s mode.

5.5.1.2 100BASE-TX Receiver

The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125-

Mb/s serial data stream to synchronous 4-bit nibble data that is provided to the MAC. Because the

100BASE-TX TP-PMD is integrated, the differential input pins, TPRDP and TPRDM, can be directly routed

from the ac-coupling magnetics.

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See Figure 5-8 for a block diagram of the 100BASE-TX receive function. This provides an overview of

each functional block within the 100BASE-TX receive section.

The Receive section consists of the following functional blocks:

• ADC

• Input and BLW Compensation

• Signal Detect

• Digital Adaptive Equalization

• MLT-3 to Binary Decoder

• Clock Recovery Module

• NRZI to NRZ Decoder

• Serial to Parallel

• De-scrambler (bypass option)

• Code Group Alignment

• 4B/5B Decoder (bypass option)

• Link Integrity Monitor

• Bad SSD Detection

The bypass option for the functional blocks within the 100BASE-TX receiver provides flexibility for

applications such as 100-Mb/s repeaters where data conversion is not always required.

5.5.1.2.1 Input and Base Line Wander Compensation

Unlike the DP83223V Twister, the DP83816 device requires no external attenuation circuitry at its receive

inputs, TPRDP and TPRDM. It accepts TP-PMD compliant waveforms directly, requiring only a 100-Ω

termination plus a simple 1:1 transformer.

The DP83816 device is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW)

compensation. The BLW compensation block can successfully recover the TP-PMD defined killer pattern

and pass it to the digital adaptive equalization block.

BLW can generally be defined as the change in the average dc content, over time, of an ac-coupled digital

transmission over a given transmission medium (that is, copper wire).

BLW results from the interaction between the low-frequency components of a transmitted bit stream and

the frequency response of the ac-coupling components within the transmission system. If the low-

frequency content of the digital bit stream goes below the low-frequency pole of the ac-coupling

transformers, then the droop characteristics of the transformers dominate, resulting in potentially serious

BLW.

The digital oscilloscope plot provided in Figure 5-9 illustrates the severity of the BLW event that can

theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately

800 mV of dc offset for a period of 120 µs. Left uncompensated, events such as this can cause packet

loss.

5.5.1.2.2 Signal Detect

The signal detect function of the DP83816 device is incorporated to meet the specifications mandated by

the ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage

thresholds and timing parameters.

Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-

Negotiation by the 100BASE-TX receiver do not cause the DP83816 device to assert signal detect.

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4B/5B DECODER

DESCRAMBLER

MLT-3 TO BINARY

DECODER

RX_CLK RXD[3:0] / RX_ER

NRZI TO NRZ

DECODER

CODE GROUP

ALIGNMENT

SERIAL TO

PARALLEL

RX_DV/CRS

RX_DATA VALID

SSD DETECT

RD +/−

SIGNAL

DETECT

LINK

INTEGRITY

MONITOR

DIGITAL

SIGNAL

PROCESSOR

ANALOG

FRONT

END

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Figure 5-8. 100BASE-TX Receive Block Diagram

Figure 5-9. 100BASE-TX BLW Event Diagram

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5.5.1.2.3 Digital Adaptive Equalization

When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation

becomes a concern. In high-speed twisted pair signaling, the frequency content of the transmitted signal

can vary greatly during normal operation based primarily on the randomness of the scrambled data

stream. This variation in signal attenuation caused by frequency variations must be compensated for to

ensure the integrity of the transmission.

To ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt

to various cable lengths and cable types depending on the installed environment. The selection of long

cable lengths for a given implementation requires significant compensation, which overcompensates for

shorter, less attenuating lengths. Conversely, the selection of short or intermediate cable lengths requiring

less compensation causes serious undercompensation for longer-length cables. Therefore, the

compensation or equalization must be adaptive to ensure proper conditioning of the received signal

independent of the cable length.

The DP83816 device uses an extremely robust equalization scheme referred to herein as digital adaptive

equalization. Traditional designs use a pseudo adaptive equalization scheme that determines the

approximate cable length by monitoring signal attenuation at certain frequencies. This attenuation value

was compared to the internal receive input reference voltage. This comparison would indicate the amount

of equalization to use. Although this scheme is used successfully on the DP83223V twister, it is sensitive

to transformer mismatch, resistor variation and process induced offset. The DP83223V also required an

external attenuation network to help match the incoming signal amplitude to the internal reference.

The Digital Equalizer removes ISI (Inter Symbol Interference) from the receive data stream by

continuously adapting to provide a filter with the inverse frequency response of the channel. When used in

conjunction with a gain stage, this enables the receive eye pattern to be opened sufficiently to allow very

reliable data recovery.

Traditionally, adaptive equalizers selected 1 of N filters in an attempt to match the cables characteristics.

This approach typically leaves holes at certain cable lengths, where the performance of the equalizer is

not optimized. The DP83816 equalizer is truly adaptive.

The curves given in Figure 5-10 illustrate attenuation at certain frequencies for given cable lengths. This is

derived from the worst-case frequency versus attenuation figures as specified in the EIA/TIA Bulletin TSB-

36. These curves indicate the significant variations in signal attenuation that must be compensated for by

the receive adaptive equalization circuit.

Figure 5-11 represents a scrambled IDLE transmitted over zero meters of cable as measured at the AII

(Active Input Interface) of the receiver. Figure 5-12 and Figure 5-13 represent the signal degradation over

50 and 100 meters of category V cable respectively, also measured at the AII. These plots show the

extreme degradation of signal integrity and indicate the requirement for a robust adaptive equalizer.

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Figure 5-11. MLT-3 Signal Measured at AII After 0 Meters

Figure 5-10. EIA/TIA Attenuation vs Frequency for 0, 50, of CAT V Cable

100, 130 and 150 Meters of CAT V Cable

5.5.1.2.4 Line Quality Monitor

It is possible to determine the amount of Equalization being used by accessing certain test registers with

the DSP engine. This provides a crude indication of connected cable length. This function allows for a

quick and simple verification of the line quality in that any significant deviation from an expected register

value (based on a known cable length) would indicate that the signal quality has deviated from the

expected nominal case.

Figure 5-12. MLT-3 Signal Measured at AII After 50 Meters of Figure 5-13. MLT-3 Signal Measured at AII After 100 Meters of

CAT V Cable CAT V Cable

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5.5.1.2.5 MLT-3 to NRZI Decoder

The DP83816 device decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary

NRZI data.

5.5.1.2.6 Clock Recovery Module

The Clock Recovery Module (CRM) accepts 125-Mb/s MLT-3 data from the equalizer. The DPLL locks

onto the 125-Mb/s data stream and extracts a 125-MHz recovered clock. The extracted and synchronized

clock and data are used as required by the synchronous receive operations as generally depicted in

Figure 5-8.

The CRM is implemented using an advanced all digital Phase Locked Loop (PLL) architecture that

replaces sensitive analog circuitry. Using digital PLL circuitry allows the DP83816 device to be

manufactured and specified to tighter tolerances.

5.5.1.2.7 NRZI to NRZ

In a typical application, the NRZI to NRZ decoder is required to present NRZ formatted data to the de-

scrambler (or to the code-group alignment block, if the de-scrambler is bypassed, or directly to the PCS, if

the receiver is bypassed).

5.5.1.2.8 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols

to the PCS Rx state machine.

5.5.1.2.9 Descrambler

A serial de-scrambler is used to de-scramble the received NRZ data. The de-scrambler has to generate

an identical data scrambling sequence (N) to recover the original unscrambled data (UD) from the

scrambled data (SD) as represented in the equations:

SD = (UD ⊕N) (1)

UD = (SD ⊕N) (2)

Synchronization of the de-scrambler to the original scrambling sequence (N) is achieved based on the

knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the de-

scrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group in

5B NRZ is equal to five consecutive ones (11111), it synchronizes to the receive data stream and

generates unscrambled data in the form of unaligned 5B code groups.

To maintain synchronization, the de-scrambler must continuously monitor the validity of the unscrambled

data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor

the synchronization status. On synchronization of the de-scrambler, the hold timer starts a 722-µs

countdown. On detection of sufficient IDLE code-groups (58 bit times) within the 722 µs period, the hold

timer resets and begins a new countdown. This monitoring operation continues indefinitely, given a

properly operating network connection with good signal integrity. If the line state monitor does not

recognize sufficient unscrambled IDLE code-groups within the 722 µs period, the entire de-scrambler is

forced out of the current state of synchronization and reset to re-acquire synchronization.

5.5.1.2.10 Code-group Alignment

The code-group alignment module operates on unaligned 5-bit data from the de-scrambler (or, if the de-

scrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5

bits). Code-group alignment occurs after the J/K code-group pair is detected. When the J/K code-group

pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.

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5.5.1.2.11 4B/5B Decoder

The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B

nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and

replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble

pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the

duration of the entire packet. This conversion ceases on the detection of the T/R code-group pair denoting

the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.

5.5.1.2.12 100BASE-TX Link Integrity Monitor

The 100 Base-TX Link monitor ensures that a valid and stable link is established before enabling both the

Transmit and Receive PCS layer.

Signal detect must be valid for 395 µs to allow the link monitor to enter the Link Up state, and enable the

transmit and receive functions.

Signal detect can be forced active by setting Bit 1 of the PCSR.

Signal detect can be optionally ANDed with the de-scrambler locked indication by setting bit 8 of the

PCSR. When this option is enabled, then descrambler locked is required to enter the Link Up state, but

only Signal detect is required to maintain the link in the link Up state

5.5.1.2.13 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle

code-groups which is not prefixed by the code-group pair J/K.

If this condition is detected, the DP83816 device asserts RXER and presents RXD[3:0] = 1110 to the MAC

for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are

detected. In addition, the False Carrier Event Counter is incremented by one.

When at least two IDLE code groups are detected, the error is reported to the MAC.

5.5.1.3 10BASE-T Transceiver Module

The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,

heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not

required on the 10BASE-T interface because this is integrated inside the DP83816 device. This section

focuses on the general 10BASE-T system level operation.

5.5.1.3.1 Operational Modes

The DP83816 device has two basic 10BASE-T operational modes:

•Half-Duplex Mode – In half-duplex mode, the DP83816 device functions as a standard IEEE 802.3

10BASE-T transceiver supporting the CSMA/CD protocol.

•Full-Duplex Mode – In full-duplex mode, the DP83816 device is capable of simultaneously

transmitting and receiving without reporting a collision. The DP83816 10-Mb/s ENDEC is designed to

encode and decode simultaneously.

5.5.1.3.2 Smart Squelch

The smart squelch is responsible for determining when valid data is present on the differential receive

inputs (TPRDP and TPRDM). The DP83816 device implements an intelligent receive squelch to ensure

that impulse noise on the receive inputs is not mistaken for a valid signal. Smart squelch operation is

independent of the 10BASE-T operational mode.

The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the

IEEE 802.3 10BASE-T standard) to determine the validity of data on the twisted pair inputs (see

Figure 5-14).

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end of packet

start of packet

SQ-(reduced)

SQ-

SQ+(reduced)

SQ+

<150 ns <150 ns >150 ns

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The signal at the start of packet is checked by the smart squelch, and any pulses not exceeding the

squelch level (either positive or negative, depending on polarity) are rejected. When this first squelch level

is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally, the signal

must again exceed the original squelch level within a 150 ns to ensure that the input waveform is not

rejected. This checking procedure results in the loss of typically three preamble bits at the beginning of

each packet.

Only after all these conditions have been satisfied is a control signal generated to indicate to the

remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.

Valid data is considered to be present until the squelch level has not been generated for a time longer

than 150 ns, indicating the End of Packet. When good data has been detected the squelch levels are

reduced to minimize the effect of noise causing premature End of Packet detection.

Figure 5-14. 10BASE-T Twisted Pair Smart Squelch Operation

5.5.1.3.3 Collision Detection

When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active

simultaneously. Collisions are reported to the MAC. Collisions are also reported when a jabber condition is

detected.

If the ENDEC is receiving when a collision is detected it is reported immediately (through the COL signal).

When heartbeat is enabled, approximately 1 µs after the transmission of each packet, a Signal Quality

Error (SQE) signal of approximately 10 bit times is generated to indicate successful transmission.

The SQE test is inhibited when the physical layer is set in full duplex mode. SQE can also be inhibited by

setting the HEARTBEAT_DIS bit in the TBTSCR register.

5.5.1.3.4 Normal Link Pulse Detection and Generation

The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link

pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data.

Link pulses are used to check the integrity of the connection with the remote end. If valid link pulses are

not received, the link detector disables the 10BASE-T twisted pair transmitter, receiver and collision

detection functions.

When the link integrity function is disabled (FORCE_LINK_10 of the TBTSCR register), good link is

forced, and the 10BASE-T transceiver operates regardless of the presence of link pulses.

5.5.1.3.5 Jabber Function

The jabber function monitors the DP83816 output and disables the transmitter if it attempts to transmit a

packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if

the transmitter is active for approximately 20–30 ms.

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When disabled by the jabber function, the transmitter stays disabled for the entire time that the internal

transmit enable of the ENDEC module is asserted. This signal has to be de-asserted for approximately

400 ms–600 ms (the unjab time) before the jabber function re-enables the transmit outputs.

The Jabber function is only meaningful in 10BASE-T mode.

5.5.1.3.6 Automatic Link Polarity Detection

The DP83816 10BASE-T transceiver module incorporates an automatic link polarity detection circuit.

When seven consecutive link pulses or three consecutive receive packets with inverted End-of-Packet

pulses are received, bad polarity is reported.

A polarity reversal can be caused by a wiring error at either end of the cable, usually at the Main

Distribution Frame (MDF) or patch panel in the wiring closet.

The bad polarity condition is latched. The DP83816 10BASE-T transceiver module corrects for this error

internally and continues to decode received data correctly. This eliminates the need to correct the wiring

error immediately.

5.5.1.3.7 10BASE-T Internal Loopback

When the LOOPBACK bit in the BMCR register is set, 10BASE-T transmit data is looped back in the

ENDEC to the receive channel. The transmit drivers and receive input circuitry are disabled in transceiver

loopback mode, isolating the transceiver from the network.

Loopback is used for diagnostic testing of the data path through the transceiver without transmitting on the

network or being interrupted by receive traffic. This loopback function causes the data to loopback just

prior to the 10BASE-T output driver buffers such that the entire transceiver path is tested.

5.5.1.3.8 Transmit and Receive Filtering

External 10BASE-T filters are not required when using the DP83816 device, as the required signal

conditioning is integrated into the device.

Only isolation and step-up transformers and impedance matching resistors are required for the 10BASE-T

transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit

signal are attenuated by at least 30 dB.

5.5.1.3.9 Transmitter

The encoder begins operation when the transmit enable input to the physical layer is asserted and

converts NRZ data to pre-emphasized Manchester data for the transceiver. For the duration of assertion,

the serialized transmit data is encoded for the transmit-driver pair (TPTDP and TPTDM). The last

transition is always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the

bit cell if the last bit is a zero.

5.5.1.3.10 Receiver

The decoder consists of a differential receiver and a PLL to separate a Manchester encoded data stream

into internal clock signals and data. The differential input must be externally terminated with a differential

100-Ωtermination network to accommodate UTP cable. The internal impedance of TPRDP and TPRDM

(typically 1.1 kΩ) is in parallel with two 54.9-Ωresistors to approximate the 100-Ωtermination.

The decoder detects the end of a frame when no more mid-bit transitions are detected.

5.5.1.3.11 Far End Fault Indication

Auto-Negotiation provides a mechanism for transferring information from the Local Station to the Link

Partner that a remote fault has occurred for 100BASE-TX.

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A remote fault is an error in the link that one station can detect while the other cannot. An example of this

is a disconnected fiber at the transmitter of a station. This station receives valid data and detects that the

link is good though the link integrity monitor, but is not able to detect that its transmission is not

propagating to the other station.

If three or more FEFI IDLE patterns are detected by the DP83816 device, then bit 4 of the basic mode

status register is set to one until read by management, additionally bit 7 of the PHY status register is also

set.

The first FEFI IDLE pattern may contain more than 84 ones as the pattern may have started during a

normal IDLE transmission, which is actually quite likely to occur. However, because FEFI is a repeating

pattern, this does not cause a problem with the FEFI function.

NOTE

Receipt of the FEFI IDLE pattern does not cause a Carrier Sense error to be reported.

If the FEFI function has been disabled via FEFI_EN (bit 3) of the PCSR Configuration register, then the

DP83816 device does not send the FEFI IDLE pattern.

5.5.1.4 Buffer Management

The buffer management scheme used on the DP83816 allows quick, simple and efficient use of the frame

buffer memory. Frames are saved in similar formats for both transmit and receive. The buffer

management scheme also uses separate buffers and descriptors for packet information. This allows

effective transfers of data from the receive buffer to the transmit buffer by simply transferring the

descriptor from the receive queue to the transmit queue.

The format of the descriptors allows the packets to be saved in a number of configurations. A packet can

be stored in memory with a single descriptor per single packet, or multiple descriptors per single packet.

This flexibility allows the user to configure the DP83816 device to maximize efficiency. Architecture of the

specific buffer memory of the system, as well as the nature of network traffic, determines the most-suitable

configuration of packet descriptors and fragments. See the Buffer Management Section 5.5.5 for more

information.***

5.5.1.4.1 Tx Buffer Manager

This block DMAs packet data from PCI memory space and places it in the 2KB transmit FIFO, and pulls

data from the FIFO to send to the Tx MAC. Multiple packets (4) may be present in the FIFO, allowing

packets to be transmitted with minimum interframe gap. The way in which the FIFO is emptied and filled is

controlled by the FIFO threshold values in the TXCFG register: FLTH (Tx Fill Threshold) and DRTH (Tx

Drain Threshold). These values determine how full or empty the FIFO must be before the device requests

the bus. Additionally, when the DP83816 device requests the bus, it attempts to empty or fill the FIFO as

allowed by the MXDMA setting in the TXCFG register.

5.5.1.4.2 Rx Buffer Manager

This block retrieves packet data from the Rx MAC and places it in the 2KB receive data FIFO, and pulls

data from the FIFO for DMA to PCI memory space. The Rx buffer manager maintains a status FIFO,

allowing up to 4 packets to reside in the FIFO at once. Similar to the transmit FIFO, the receive FIFO is

controlled by the FIFO threshold value in the RXCFG register: DRTH (Rx Drain Threshold). This value

determines the number of long words written into the FIFO from the MAC unit before a DMA request for

system memory access occurs. When the DP83816 device gets the bus, it continues to transfer the long

words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the

packet, or the max DMA burst size is reached (RXCFG:MXDMA).

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5.5.1.4.3 Packet Recognition

The Receive packet filter and recognition logic allows software to control which packets are accepted

based on destination address and packet type. Address recognition logic includes support for broadcast,

multicast hash, and unicast addresses. The packet recognition logic includes support for WOL, Pause,

and programmable pattern recognition.

The standard 802.3 Ethernet packet consists of the following fields: Preamble (PA), Start of Frame

Delimiter (SFD), Destination Address (DA), Source Address (SA), Length (LEN), Data and Frame Check

Sequence (FCS). All fields are fixed length except for the data field. During reception, the PA, SFD and

FCS are stripped. During transmission, the DP83816 device generates and appends the PA, SFD and

FCS.

Table 5-3. Ethernet Packet Format

PA SFD DA SA LEN Data FCS

60b 4b 6B 6B 2B 46B–1500B 4B

Note: B = Bytes

b = bits

5.5.1.4.4 MIB

The MIB block contains counters to track certain media events required by the management specifications

RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), and IEEE 802.3 LME. The counters provided are for

events which are either difficult or impossible to be intercepted directly by software. Not all counters are

implemented, however required counters can be calculated from the counters provided.

5.5.2 Receive Filter Logic

The receive filter logic supports a variety of techniques for qualifying incoming packets. The most-basic

filtering options include accept all broadcast, accept all multicast and accept all unicast packets. These

options are enabled by setting the corresponding bit in the receive filter control register, RFCR. accept on

perfect match, accept on pattern match, accept on multicast hash and accept on unicast hash are more

robust in their filtering capabilities, but require additional programming of the receive filter registers and the

internal filter RAM.

5.5.2.1 Packet Filtering

When the PME enable bit is set to 1, incoming packets are filtered based on settings in the receive filter

control register (RFCR - offset 48h in operational registers) and the wake command and status register

(WCSR - offset 40h in operational registers). In other words, a packet must pass both filters to be

accepted. This is a desirable feature in WOL mode, because it prevents non-wake packets from filling the

receive FIFO. However, it is not desirable in normal operating mode because it does not allow non-wake

packets from being received. Therefore, the driver should ensure that the PME enable bit is set to 0 for

normal operation.

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5.5.2.2 Accept on Perfect Match

When enabled, the perfect match register is used to compare against the DA for packet acceptance. The

perfect match register is a 6-byte register accessed indirectly through the RFCR. The address of the

internal receive filter register to be accessed is programmed through bits 8:0 of the RFCR. The receive

filter data register, RFDR, is used for reading or writing the actual data.

RX Filter Address: 000h - Perfect Match octets 1-0

002h - Perfect Match octets 3-2

004h - Perfect Match octets 5-4

Octet 0 of the perfect match register corresponds to the first octet of the packet as it appears on the wire.

Octet 5 corresponds to the last octet of the DA as it appears on the wire.

The following steps are required to program the RFCR to accept packets on a perfect match of the DA.

Example: Destination Address of 08-00-17-07-28-55

iow l $RFCR (0000) perfect match register, octets 1-0

iow l $RFDR (0008) write address, octets 1-0

iow l $RFCR (0002) perfect match register, octets 3-2

iow l $RFDR (0717) write address, octets 3-2

iow l $RFCR (0004) perfect match register, octets 5-4

iow l $RFDR (5528) write address, octets 5-4

iow l $RFDR

($RFEN|$APM) enable filtering, perfect match

5.5.2.3 Accept on Pattern Match

The receive filter logic provides access to 4 separate internal RAM-based pattern buffers to be used as

additional perfect match address registers. Pattern buffers 0 and 1 are 64 bytes deep, allowing perfect

match on the first 64 bytes of a packet, and pattern buffers 2 and 3 are 128 bytes deep, allowing perfect

match on the first 128 bytes of a packet.

When one or more of the pattern match enable bits are set in the RFCR, a packet is accepted if it

matches the associated pattern buffer. As indicated above, the pattern buffers are 64 and 128 bytes deep

organized as 32 or 64 words, where a word is 18 bits. Bits 17 and 18 of a respective word are mask bits

for byte 0 and byte 1 of the 16-bit data word (bits 15:0). An incoming packet is compared to each enabled

pattern buffer on a byte by byte basis for a specified count. Masking a pattern byte results in a byte match

regardless of its value (a don’t care). A count value must be programmed for each pattern buffer to be

used for comparison. The minimum valid count is 2 (2 bytes) and the maximum valid count is 32 for

pattern buffers 0 and 1, and 64 for pattern buffers 2 and 3. The pattern count registers are internal receive

filter registers accessed through the RFCR and the RFDR The Receive Filter memory is also accessed

through the RFCR and the RFDR. A memory map of the internal pattern RAM is shown in Figure 5-15.

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Byte1

Mask Bit

Byte0

Mask Bit

Pattern3Word7F byte1 byte0 3FE

Pattern2Word7F byte1 byte0 3FC

Pattern3Word7E byte1 byte0 3FA

Pattern2Word7E byte1 byte0 3F8

....................

Pattern3Word1 byte1 byte0 306

Pattern2Word1 byte1 byte0 304

Pattern3Word0 byte1 byte0 302

Pattern2Word0 byte1 byte0 300

Pattern1Word3F byte1 byte0 2FE

Pattern0Word3F byte1 byte0 2FC

Pattern1Word3E byte1 byte0 2FA

Pattern0Word3E byte1 byte0 2F8

....................

Pattern1Word1 byte1 byte0 286

Pattern0Word1 byte1 byte0 284

Pattern1Word0 byte1 byte0 282

Pattern0Word0 byte1 byte0 280

Bit# 17 16 15 8 7 0

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Figure 5-15. Pattern Buffer Memory – 180h Words (Word = 18 Bits)

Example: Pattern match on the following destination addresses:

02-00-03-01-04-02

12-10-13-11-14-12

22-20-23-21-24-22

32-30-33-31-34-32

set $PATBUF01 = 280

set $PATBUF23 = 300

# write counts

iow l $RFCR (0006) # pattern count registers 1, 0

iow l $RFDR (0406) # count 1 = 4, count 0= 6

iow l $RFCR (0008) # pattern count registers 3, 2

iow l $RFDR (0406) # count 3 = 4, count 2 = 6

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# write data pattern into buffer 0

iow l $RFCR ($PATBUF01)

iow l $RFDR (0002)

iow l $RFCR ($PATBUF01 + 4)

iow l $RFDR (0103)

iow l $RFCR ($PATBUF01 + 8)

iow l $RFDR (0204)

# write data pattern into buffer 1

iow l $RFCR ($PATBUF01 + 2)

iow l $RFDR (1012)

iow l $RFCR ($PATBUF01 + 6)

iow l $RFDR (1113)

iow l $RFCR ($PATBUF01 + a)

iow l $RFDR (1214)

# write data pattern into buffer 2

iow l $RFCR ($PATBUF23)

iow l $RFDR (2022)

iow l $RFCR ($PATBUF23 + 4)

iow l $RFDR (2123)

iow l $RFCR ($PATBUF23 + 8)

iow l $RFDR (2224)

# write data pattern into buffer 3

iow l $RFCR ($PATBUF23 +2)

iow l $RFDR (3032)

iow l $RFCR ($PATBUF23 + 6)

iow l $RFDR (3133)

iow l $RFCR ($PATBUF23 + a)

iow l $RFDR (3234)

#enable receive filter on all patterns

iow l $RFCR ($RFEN|$APAT0|$APAT1|$APAT2|$APAT3)

Example of how to mask out a byte in a pattern:

# write data pattern into buffer 0

iow l $RFCR ($PATBUF01)

iow l $RFDR (10002) #mask byte 0 (value = 02)

iow l $RFCR ($PATBUF01 + 4)

iow l $RFDR (20103) #mask byte 1 (value = 01)

iow l $RFCR ($PATBUF01 + 8)

iow l $RFDR (30204) #mask byte 0 and 1

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Unused

X X byte63 byte62 23E

X X byte61 byte60 23C

..............

X X byte5 byte4 204

X X byte3 byte2 202

X X byte1 byte0 200

Bit# 17 16 15 8 7 0

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5.5.2.4 Accept on Multicast or Unicast Hash

Multicast and unicast addresses may be further qualified by use of the receive filter hash functions. An

internal 512 bit (64 byte) RAM-based hash table is used to perform imperfect filtering of multicast or

unicast packets. By enabling either multicast hashing or unicast hashing in the RFCR, the receive filter

logic uses the nine least-significant bits of the destination address’ CRC as an index into the Hash Table

memory. The upper 4 bits represent the word address and the lower 5 bits select the bit within the word. If

the corresponding bit is set, then the packet is accepted, otherwise the packet is rejected. The hash table

memory is accessed through the RFCR and the RFDR. See Figure 5-16 for a memory map. Example

code for setting or clearing a bit in the hash table follows.

Figure 5-16. Hash Table Memory - 40h Bytes Addressed on Word Boundaries

spacer

set HASH_TABLE = 200

crc $DA # compute the CRC of the destination address

set index = ($crc >> 3)

set bit = ($crc & 01f) # lower 5 bits select which bit in 32 bit word

# write word address into RFCR

iow l $RFCR ($HASH_TABLE + $index)

# select bit to set/clear

if ($bit > f) set bit = ($bit - 010h) # use 16 bit register interface into 32bit RAM

set hash_bit = (0001 << $bit)

# read indexed word from table

ior l $RFDR

if ($SetBit) then

set hash_word = ($rc | $hash_bit)

iow l $RFDR ($hash_word)

else set hash_bit = (~$hash_bit)

set hash_word = ($rc & $hash_bit)

iow l $RFDR ($hash_word)‘

endif

iow l $RFCR ($RFEN|$MHEN|$UHEN) # enable multicast and/or unicast

# address hashing

5.5.3 Wake-On-LAN (WoL) Mode

WoL mode is a system-level function that allows a network device to alert the system that a wake event

has occurred. It works in conjunction with the PCI power management states detailed in the previous

section. The DP83816 device supports several wake events including, but not limited to, wake on PHY

Interrupt (that is, link change), wake on Magic Packet, and wake on pattern match. The supported wake

events appear in the device’s Wake Command and Status Register (WCSR).

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5.5.3.1 Definitions of Terms in WOL Mode

The following lists contains definitions of terms used in the WoL section:

• Power management – a PCI specification that defines power-saving states of PCI devices and

systems. A spec-compliant device implements two PCI Configuration registers to control and report

status for its power management function.

• Wake event – an event that causes a PCI device in power management mode to signal the system.

• PME enable (PMEEN) – bit 8 of the power management control and status register (PMCSR - offset

44h in the PCI configuration space). Setting this bit to 1 allows the device to assert the PMEN pin

when it detects a wake event.

• Sleep mode – a device is in sleep mode if it is programmed to a power management state other than

the fully operational state and is not allowed to signal a wake event to the system. In this mode, the

PME Enable bit is 0.

• WoL mode – a device is in WoL mode if it is programmed to a power management state other than the

fully operational state and is allowed to signal a wake event to the system. In this mode, the PME

Enable bit is 1.

• PMEN (pin59) – this pin is similar in function to a system interrupt (INTAN pin). When asserted, it

signals the system that a wake event has occurred.

• PME status – bit 15 of PMCSR. When 1, indicates the device detected a wake event. If PME Enable is

also set to 1, the device asserts PMEN whenever PME Status is 1. Software writes a 1 to this bit to

clear it.

• Magic Packet – a specific packet of information sent to remotely wake up a sleeping or powered off PC

on a network, it is handled in the LAN controller. The Magic Packet must contain a specific data

sequence which can be located anywhere within the packet but must be preceded by a

synchronization stream. The packet must also meet the basic requirements for the LAN technology

chosen (for example, ethernet frame). The specific data sequence consists of 16 duplications of the

MAC address of the machine to be awakened. The synchronization stream is defined as 6 bytes of

FFh.

• ACPI-compatible operating system – An operating system that takes advantage of the PCI power

management interface. These include Windows 98 (when installed with ACPI), Windows 2000, and

Windows ME (when installed with ACPI).

5.5.3.2 Entering WoL Mode

The following steps are required to place the DP83816 device into WoL mode:

1. Disable the receiver by writing a 1 to the receiver disable bit 3 (RXD) in the command register (CR -

offset 00h in operational registers).

2. Write 0 to the receive descriptor pointer register (RXDP - offset 30h in operational registers) to reset

the receive pointer.

3. Enable the receiver (now in silent receive mode) by writing a 1 to the receiver enable bit 2 in the

command register (CR:RXE).

4. Configure the receive filter control register (RFCR) to enable the receive filter (RFCR:RFEN - bit 31)

and accept the desired type of wakeup packets. Note that the receive filter enable bit must be set to 1

for wake on PHY Interrupt as well.

5. If wake on PHY Interrupt is desired, additionally configure registers MICR (offset C4h in operational

registers) and MISR (offset C8h in operational registers).

6. Configure the wake command and status register (WCSR) with the desired type of wake events. An

ACPI-compatible operating system should notify the driver of these events.

7. Write a 1 to PME enable, and set the desired power state in PMCSR. These can be done in one

operation, or PME Enable can be written first. An ACPI-compatible operating system should handle

this step.

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8. If the power management state is D3cold, the system asserts PCI reset, stops the PCI clock, and

removes power from the PCI bus.

The following two examples show the corresponding register settings for wake on Magic Packet mode and

wake on PHY Interrupt mode respectively:

Entering Wake on Magic Packet Mode

1. CR = 00000008h (disable the receiver)

2. RXDP = 00000000h (reset the receive pointer)

3. CR = 00000004h (enable the receiver)

4. RFCR = F0000000h (enables the receive filter and allows broadcast, multicast and unicast packets to

be received - a Magic Packet could be any of those.)

5. WCSR = 00000200h (sets the wake on Magic Packet bit)

6. PMCSR = 00008103h (clears the PME status bit 15, sets the PME enable bit 8 and sets the power

state bits [1:0] to D3hot)

Entering Wake on PHY Interrupt Mode

1. CR = 00000008h (disable the receiver)

2. RXDP = 00000000h (reset the receive pointer)

3. CR = 00000004h (enable the receiver)

4. RFCR = 80000000h (enables the receive filter)

5. MICR = 00000002h (sets the interrupt enable bit 1)

6. MISR = 00000000h (unmasks the change of link status event)

7. WCSR = 00000001h (sets the wake on PHY interrupt bit)

8. PMCSR = 00008103h (clears the PME status bit 15, sets the PME enable bit 8 and sets the power

state bits [1:0] to D3hot)

5.5.3.3 Wake Events

If the device detects a wake event while in WOL mode, it asserts the PMEN pin low to signal the system

that a wake event has occurred. The system should then bring the device out of WOL mode as described

below.

5.5.3.4 Exiting WOL Mode

The following steps are required to bring the device out of WOL mode (with or without an accompanying

wake event):

1. If the power management state is D3cold, the system asserts PCI reset, restores PCI bus power, and

restarts the PCI clock. This also returns the power state to D0. The PCI configuration registers (that is,

base addresses, bus master enable, and so forth) must be reinitialized.

2. Write a 0 to Power State bits [0:1] in the PMCSR (in case the WOL Power State was not D3hot or

D3cold) and PME enable. These can be done in one operation, or Power State can be written first.

Turning off PME Enable causes the device to de-assert the PMEN pin, if it was asserted.

3. If the WOL power state was D3hot or D3cold, reinitialize the PCI configuration registers (that is, base

addresses, bus master enable, and so forth). An ACPI-compatible operating system should handle this

step. Note that operational registers are not accessible until this step is completed.

4. If a wake event occurred, read the WCSR to determine what the event was.

5. Write a 1 to PME status. This clear any wake event in the device. An ACPI-compatible operating

system performs this write to the PMCSR; a driver can perform this write using the clockrun control

and status register (CCSR).

6. If the wake event was a PHY interrupt from an internal PHY, clear the event in the PHY registers. See

the MISR in Section 5.6.4.11.

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7. Clear all bits in WCSR.

8. Disable the receiver by writing a 1 to the receiver disable bit in the command register (CR:RXD).

9. Reconfigure RFCR as appropriate for normal operation.

10. Write a valid receive descriptor pointer to the receive descriptor pointer register (RXDP).

11. Enable the receiver by writing a 1 to the receiver enable bit in the command register (CR:RXE). If the

wake event was a packet, this is now emptied from the receive FIFO through DMA.

5.5.4 Power Management

The power management specification presents a low-level hardware interface to PCI devices for the

purpose of saving power. The DP83816 device supports power states D0, D1, D2, D3hot, and D3cold as

defined in the PCI power management specification. These states provide increasing power reduction in

the order they are listed. Table 5-4 lists the different power management modes and the methods of

power reduction in DP83816 devices.

Table 5-4. Power Management Modes

PME ENABLE POWER PHYSICAL LAYER

POWER STATE WAKE CONDITIONS PCICLK

(PMEEN) MANAGEMENT MODE CELL

D0 (SW sets to 0) Unconfigured Normal On On

D1 Don’t Care Don’t Care WOL On On

D2 Don’t Care Don’t Care WOL May be Off On

D3hot Off Don’t Care Sleep May be Off Off

D3hot Don’t Care Unconfigured Sleep May be Off Off

D3hot On Configured WOL May be Off On

D3cold Off Don’t Care Sleep Off Off

D3cold Don’t Care Unconfigured Sleep Off Off

D3cold On Configured WOL Off On

5.5.4.1 D0 State

The D0 state is the normal operational state of the device. The PME Enable bit should be set to 0 to

prevent packet filtering based on the settings in the wake control and status register (WCSR). It is also

advisable to turn off all WOL conditions in WCSR to prevent unnecessary PME interrupts.

5.5.4.2 D1 State

The D1 state is the least-power-saving power management state, and might not be used by the operating

system. The device only responds to PCI configuration transactions and therefore does not transmit data.

The only bus activity the device can initiate is the assertion of the PMEN pin (assuming the PME enable

bit is set to 1); no DMA activity or interrupts occurs. The device continues to receive packets up to the limit

of the receive FIFO size. On returning to the D0 state, the system must re-enable I/O and memory space

in the device and turn on bus master capability.

5.5.4.3 D2 State

The D2 state has the same features as the D1 state, and the system may turn off the PCI clock, further

reducing power. The device continues to receive packets up to the limit of the receive FIFO size. Like the

D1 state, the D2 state might not be used by the operating system.

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5.5.4.4 D3hot State

The D3hot state is often known as the standby state. If the PME Enable bit is 0, or WOL is unconfigured,

the device saves power by turning off the physical layer cell (PHY). The system may turn off the PCI

clock. To receive packets in the D3hot state, both WOL mode and PME Enable must be turned on. Like

the D2 and D1 states, the device responds to PCI configuration transactions as long as the PCI clock is

running.

When the device exits the D3hot state, all PCI configuration registers except for the PME enable and PME

status bits are reset to their default values. This means the operating system must reinitialize PCI

configuration registers of the device with valid base addresses, and so forth. If PME enable or WOL mode

were not turned on, the device must be fully reinitialized.

5.5.4.5 D3cold State

The D3cold state is the highest power-saving state; it is often known as the hibernate state. The PCI bus

is turned off, as is the PCI clock. If the PME enable bit or WOL is turned off, the PHY is turned off. This

allows the device to consume the least amount of power. The device must be fully reinitialized after exiting

this mode.

5.5.5 Buffer Management

The buffer management scheme used on the DP83816 device allows quick, simple and efficient use of the

frame buffer memory. Frames are saved in similar formats for both transmit and receive. The buffer

management scheme also uses separate buffers and descriptors for packet information. This allows

effective transfers of data from the receive buffer to the transmit buffer by simply transferring the

descriptor from the receive queue to the transmit queue.

The format of the descriptors allows the packets to be saved in a number of configurations. A packet can

be stored in memory with a single descriptor and a single packet fragment, or multiple descriptors each

with a single fragment. This flexibility allows the user to configure the DP83816 device to maximize

efficiency. Architecture of the specific system’s buffer memory, as well as the nature of network traffic,

determines the most-suitable configuration of packet descriptors and fragments.

5.5.5.1 Overview

The buffer management design has the following goals:

• Simplicity

• Efficient use of the PCI bus (the overhead of the buffer management technique is minimal)

• Low CPU utilization

• Flexibility

Descriptors may be either per-packet or per-packet-fragment. Each descriptor may describe one packet

fragment. Receive and transmit descriptors are symmetrical.

5.5.5.1.1 Descriptor Format

The DP83816 device uses a symmetrical format for transmit and receive descriptors. In bridging and

switching applications this symmetry allows software to forward packets by simply moving the list of

descriptors that describe a single received packet from the receive list of one MAC to the transmit list of

another. Descriptors must be aligned on an even long word (32-bit) boundary.

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Table 5-5. DP83816 Device Descriptor Format

OFFSET TAG DESCRIPTION

0000h link 32-bit link field to the next descriptor in the linked list. Bits 1-0 must be 0, as descriptors must be aligned on 32-bit

boundaries.

0004h cmdsts 32-bit Command and Status field (bit-encoded).

0008h bufptr 32-bit pointer to the first fragment or buffer. In transmit descriptors, the buffer can begin on any byte boundary. In

receive descriptors, the buffer must be aligned on a 32-bit boundary.

The original DP83810A descriptor format supported multiple fragments per descriptor. The DP83816

device only supports a single fragment per descriptor. By default, the DP83816 device uses the descriptor

format shown in Table 5-5. By setting CFG:EUPHCOMP, software may force compatibility with the

previous DP83810A Descriptor format (although still only single fragment descriptors are supported).

When CFG:EUPHCOMP is set, then bufptr is at offset 0Ch, and the 32-bit bufcnt field at offset 08h is

ignored.

Some of the bit definitions in the cmdsts field are common to both receive and transmit descriptors:

Table 5-6. cmdsts Common Bit Definitions

BIT TAG DESCRIPTION USAGE

31 OWN Descriptor Set to 1 by the data producer of the descriptor to transfer ownership to the data

ownership consumer of the descriptor. Set to 0 by the data consumer of the descriptor to return

ownership to the data producer of the descriptor. For transmit descriptors, the driver is

the data producer, and the DP83816 device is the data consumer. For receive

descriptors, the DP83816 device is the data producer, and the driver is the data

consumer.

30 MORE More descriptors Set to 1 to indicate that this is NOT the last descriptor in a packet (there are MORE to

follow). When 0, this descriptor is the last descriptor in a packet. Completion status bits

are only valid when this bit is zero.

29 INTR Interrupt Set to 1 by software to request a descriptor interrupt when the DP83816 device transfers

the ownership of this descriptor back to software.

28 SUPCRC Suppress CRC/ In transmit descriptors, this indicates that CRC should not be appended by the MAC. On

INCCRC Include CRC receives, this bit is always set, as the CRC is always copied to the end of the buffer by

the hardware.

27 OK Packet OK In the last descriptor in a packet, this bit indicates that the packet was either sent or

received successfully.

26-16 — The usage of these bits differ in receive and transmit descriptors. See below for details.

15-12 (reserved)

11-0 SIZE Descriptor Byte Set to the size in bytes of the data.

Count

Table 5-7. Transmit Status Bit Definitions

BIT TAG DESCRIPTION USAGE

26 TXA Transmit Abort Transmission of this packet was aborted.

25 TFU Transmit FIFO Transmit FIFO was exhausted during the transmission of this packet.

Underrun

24 CRS Carrier Sense Lost Carrier was lost during the transmission of this packet. This condition is not reported if

TXCFG:CSI is set.

23 TD Transmit Deferred Transmission of this packet was deferred.

22 ED Excessive Deferral The length of deferral during the transmission of this packet was excessive (> 3.2 ms),

indicating transmission failure.

21 OWC Out of Window The MAC encountered an out-of-window collision during the transmission of this packet.

Collision

20 EC Excessive The number of collisions during the transmission of this packet was excessive, indicating

Collisions transmission failure.

If TXCFG register ECRETRY=0, this bit is set after 16 collisions.

If TXCFG register ECRETRY=1, this bit is set after 4 Excessive Collision events (64

collisions).

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Table 5-7. Transmit Status Bit Definitions (continued)

BIT TAG DESCRIPTION USAGE

19-16 CCNT Collision Count If TXCFG register ECRETRY=0, this field indicates the number of collisions encountered

during the transmission of this packet.

If TXCFG register ECRETRY=1,

CCNT[3:2] = Excessive Collisions (0-3)

CCNT[1] = Multiple Collisions

CCNT[0] = Single Collision

Note that Excessive Collisions indicate 16 attempts failed, while multiple and single

collisions indicate collisions in addition to any excessive collisions. For example,a collision

count of 33 includes two Excessive Collisions and also sets the Single Collision bit.

Table 5-8. Receive Status Bit Definitions

BIT TAG DESCRIPTION USAGE

26 RXA Receive Aborted Set to 1 by the DP83816 device when the receive was aborted, the value of this bit always

equals RXO. Exists for backward compatibility.

25 RXO Receive Overrun Set to 1 by the DP83816 device to indicate that a receive overrun condition occurred. RXA

is also set.

24-23 DEST Destination Class When the receive filter is enabled, these bits indicate the destination address class as

follows: 00 - Packet was rejected

01 - Destination is a Unicast address

10 - Destination is a Multicast address

11 - Destination is a Broadcast address

If the Receive Filter is enabled, 00 indicates that the packet was rejected. Normally packets

that are rejected do not cause any bus activity, nor do they consume receive descriptors.

However, this condition could occur if the packet is rejected by the Receive Filter later in

the packet than the receive drain threshold (RXCFG:DRTH).

Note: The DEST bits may not represent a correct DA class for runt packets received with

less than 6 bytes.

22 LONG Too Long Packet If RXCFG:ALP=0, this flag indicates that the size of the receive packet exceeded 1518

Received bytes.

If RXCFG:ALP=1, this flag indicates that the size of the receive packet exceeded 2046

bytes.

21 RUNT Runt Packet The size of the receive packet was less than 64 bytes (inc. CRC).

Received

20 ISE Invalid Symbol Error (100 Mb/s only) An invalid symbol was encountered during the reception of this packet.

19 CRCE CRC Error The CRC appended to the end of this packet was invalid.

18 FAE Frame Alignment The packet did not contain an integral number of octets.

Error

17 LBP Loopback Packet The packet is the result of a loopback transmission.

16 COL Collision Activity The receive packet had a collision during reception.

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link

ptr

MAC hdr netwk hdr data

114

multiple descriptor / single fragment

link

ptr

120

link

ptr

030

link

ptr

MAC hdr

netwk hdr

data

064

single descriptor / single fragment

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5.5.5.1.2 Single Descriptor Packets

To represent a packet in a single descriptor, the MORE bit in the cmdsts field is set to 0.

Figure 5-17. Single Descriptor Packets

5.5.5.1.3 Multiple Descriptor Packets

A single packet may also cross descriptor boundaries. This is indicated by setting the MORE bit in all

descriptors except the last one in the packet. Ethernet applications (bridges, switches, routers, and so

forth) can optimize memory utilization by using a single small buffer per receive descriptor, and allowing

the DP83816 hardware to use the minimum number of buffers necessary to store an incoming packet.

5.5.5.1.4 Descriptor Lists

Descriptors are organized in linked lists using the link field. The system designer may also choose to

implement a ring of descriptors by linking the last descriptor in the list back to the first. A list of descriptors

may represent any number of packets or packet fragments.

Figure 5-18. Multiple Descriptor Packets

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Transmit Descriptor

Current Tx Desc Ptr

Software/Memory Hardware

Tx Data FIFO

link

cmdsts

ptr

Tx DMA

Packet

ptr

cmdsts

link

Tx Desc Cache

TxHead

10180

addr 10140

10140

addr 10100

101C0

addr 10180

10100

addr 101C0

Descriptors Organized in a Ring

10180

addr 10140

10140

addr 10100

101C0

addr 10180

00000

addr 101C0

Descriptors Organized in a Linked List

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Figure 5-19. List and Ring Descriptor Organization

5.5.5.2 Transmit Architecture

Figure 5-20 illustrates the transmit architecture of the DP83816 10/100 ethernet controller.

Figure 5-20. Transmit Architecture

When the CR:TXE bit is set to 1 (regardless of the current state), and the DP83816 transmitter is idle,

then the DP83816 device reads the contents of the current transmit descriptor into the TxDescCache. The

DP83816 TxDescCache can hold a single fragment pointer and count combination.

5.5.5.2.1 Transmit State Machine

The transmit state machine has the following states:

txIdle The transmit state machine is idle.

txDescRefr Waiting for the refresh transfer of the link field of a completed descriptor from the PCI

bus.

txDescRead Waiting for the transfer of a complete descriptor from the PCI bus into the

TxDescriptorCache.

txFifoBlock Waiting for free space in the TxDataFIFO to reach TxFillThreshold.

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txFragRead Waiting for the transfer of a fragment (or portion of a fragment) from the PCI bus to the

TxDataFIFO.

txDescWrite Waiting for the completion of the write of the cmdsts field of an intermediate transmit

descriptor (cmdsts.MORE == 1) to host memory.

txAdvance (transitory state) Examine the link field of the current descriptor and advance to the next

descriptor if link is not NULL.

The transmit state machine manipulates the following internal data spaces:

TXDP A 32-bit register that points to the current transmit descriptor.

CTDD An internal bit flag that is set when the current transmit descriptor has been completed,

and ownership has been returned to the driver. It is cleared whenever TXDP is loaded

with a new value (either by the state machine, or the driver).

TxDescCache An internal data space equal to the size of the maximum transmit descriptor supported.

descCnt Count of bytes remaining in the current descriptor

fragPtr Pointer to the next unread byte in the current fragment.

txFifoCnt Current amount of data in the txDataFifo in bytes.

txFifoAvail Current amount of free space in the txDataFifo in bytes (size of the txDataFifo –

txFifoCnt).

Inputs to the transmit state machine include the following events:

CR:TXE Driver asserts the TXE bit in the command register (similar to SONIC).

XferDone Completion of a PCI bus transfer request.

FifoAvail TxFifoAvail is greater than TxFillThreshold.

Table 5-9. Transmit State Tables

STATE EVENT NEXT STATE ACTIONS

txIdle CR:TXE && !CTDD txDescRead Start a burst transfer at address TXDP and a length derived from TXCFG.

CR:TXE && CTDD txDescRefr Start a burst transfer to refresh the link field of the current descriptor.

txDescRefr XferDone txAdvance

txDescRead XferDone && OWN txFIFOblock

XferDone && !OWN txIdle Set ISR:TXIDLE.

txFIFOblock FifoAvail txFragRead Start a burst transfer into the TxDataFIFO from fragPtr. The length is the

minimum of txFifoAvail and descCnt.

Decrement descCnt accordingly.

(descCnt == 0) && txDescWrite Start a burst transfer to write the status back to the descriptor, clearing the

MORE OWN bit.

(descCnt == 0) && txAdvance Write the value of TXDP to the txDataFIFO as a handle.

!MORE

txFragRead XferDone txFIFOblock

txDescWrite XferDone txAdvance

txAdvance link != NULL txDescRead TXDP <- txDescCache.link. Clear CTDD. Start a burst transfer at address

TXDP with a length derived from TXCFG.

link == NULL txIdle Set CTDD. Set ISR:TXIDLE. Clear CR:TXE.

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txDescRefr

txIdle

txDescRead

txFifoBlocktxDescWrite

txAdvance

txFragRead

CR:TXE && CTDD

CR:TXE && !CTDD

link = NULL

XferDone

XferDone && OWN

XferDone && !OWN

link != NULL

descCnt == 0 && !(cmdsts & MORE)

descCnt == 0 && (cmdsts & MORE)

FifoAvail

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Figure 5-21. Transmit State Diagram

5.5.5.2.2 Transmit Data Flow

In the DP83816 transmit architecture, packet transmission involves the following steps:

1. The device driver receives packets from an upper layer.

2. An available DP83816 transmit descriptor is allocated. The fragment information is copied from the

NOS specific data structures to the DP83816 transmit descriptor.

3. The driver adds this descriptor to the internal list of transmit descriptors awaiting transmission and sets

the OWN bit.

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Receive Descriptor List

Rx Descriptor Cache

Software/Memory Hardware

Rx Data FIFO

link

cmdsts

ptr

Rx DMA

link

cmdsts

ptr

link

cmdsts

ptr

link

cmdsts

ptr

RxHead

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4. If the internal list was empty (this descriptor represents the only outstanding transmit packet), then the

driver must set the TXDP register to the address of this descriptor, else the driver appends this

descriptor to the end of the list.

5. The driver sets the TXE bit in the CR register to insure that the transmit state machine is active.

6. If idle, the transmit state machine reads the descriptor into the TxDescriptorCache.

7. The state machine then moves through the fragment described within the descriptor, filling the

TxDataFifo with data. The hardware handles all aspects of byte alignment; no alignment is assumed.

Fragments may start and/or end on any byte address. The transmit state machine uses the fragment

pointer and the SIZE field from the cmdsts field of the current descriptor to keep the TxDataFifo full. It

also uses the MORE bit and the SIZE field from the cmdsts field of the current descriptor to know when

packet boundaries occur.

8. When a packet has completed transmission (successful or unsuccessful), the state machine updates

the upper half of the cmdsts field of the current descriptor in main memory, relinquishing ownership,

and indicating the packet completion status. This update is done by a bus master transaction that

transfers only the upper 2 bytes to the descriptor being updated. If more than one descriptor was used

to describe the packet, then completion status is updated only in the last descriptor. Intermediate

descriptors only have the OWN bits modified.

9. If the link field of the descriptor is non-zero, the state machine advances to the next descriptor and

continues.

10. If the link field is NULL, the transmit state machine suspends, waiting for the TXE bit in the CR

the state machine examines CTDD. If CTDD is set, the state machine refreshes the link field of the

current descriptor. It then follows the link field to any new descriptors that have been added to the end

of the list. If CTDD is clear (implying that TXDP has been written to), the state machine starts by

reading in the descriptor pointed to by TXDP.

5.5.5.3 Receive Architecture

The receive architecture is as symmetrical to the transmit architecture as possible. The receive buffer

manager prefetches receive descriptors to prepare for incoming packets. When the amount of receive

data in the RxDataFIFO is more than the RxDrainThreshold, or the RxDataFIFO contains a complete

packet, then the state machine begins filling received buffers in host memory.

Figure 5-22. Receive Architecture

When the RXE bit is set to 1 in the CR register (regardless of the current state), and the DP83816 receive

state machine is idle, then DP83816 device reads the contents of the descriptor referenced by RXDP into

the Rx descriptor cache. The Rx descriptor cache allows the DP83816 device to read an entire descriptor

in a single burst, and reduces the number of bus accesses required for fragment information to 1. The

DP83816 Rx Descriptor Cache holds a single buffer pointer and count combination.

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5.5.5.3.1 Receive State Machine

The receive state machine has the following states:

rxidle The receive state machine is idle.

rxDescRefr Waiting for the refresh transfer of the link field of a completed descriptor from the PCI

bus.

rxDescRead Waiting for the transfer of a descriptor from the PCI bus into the RxDescCache.

rxFifoBlock Waiting for the amount of data in the RxDataFifo to reach the RxDrainThreshold or to

represent a complete packet.

rxFragWrite Waiting for the transfer of data from the RxDataFIFO via the PCI bus to host memory.

rxDescWrite Waiting for the completion of the write of the cmdsts field of a receive descriptor.

The receive state machine manipulates the following internal data spaces:

RXD[ A 32-bit register that points to the current receive descriptor.

CRDD An internal bit flag that is set when the current receive descriptor has been completed,

and ownership has been returned to the driver. It is cleared whenever RXDP is loaded

with a new value (either by the state machine, or the driver).

RxDescCache An internal data space equal to the size of the maximum receive descriptor supported.

descCnt Count of bytes available for storing receive data in all fragments described by the current

descriptor.

fragPtr Pointer to the next unwritten byte in the current fragment.

rxPktCnt Number of packets in the rxDataFifo. Incremented by the MAC (the fill side of the FIFO).

Decremented by the receive state machine as packets are processed.

rxPktBytes Number of bytes in the current packet being drained from the rxDataFifo, that are in fact

currently in the rxDataFifo (Note: For packets that contain more bytes than the FIFO's

size, this number will never be greater than the FIFO size).

Inputs to the receive state machine include the following events:

CR:RXE The RXE bit in the Command Register has been set.

XferDone Completion of a PCI bus transfer request.

FifoReady (rxPktCnt > 0) or (rxPktBytes > rxDrainThreshold)... in other words, if we have a

complete packet in the FIFO (regardless of size), or the number of bytes that we do have

is greater than the rxDrainThreshold, then we are ready to begin draining the rxDataFifo.

Table 5-10. Receive State Tables

STATE EVENT NEXT STATE ACTIONS

rxIdle CR:RXE && !CRDD rxDescRead Start a burst transfer at address RXDP and a length derived from RXCFG.

CR:RXE && CRDD rxDescRefr Start a burst transfer to refresh the link field of the current descriptor.

rxDescRefr XferDone rxAdvance

rxDescRead XferDone && !OWN rxFIFOblock

XferDone && OWN rxIdle Set ISR:RXIDLE.

rxFIFOblock FifoReady rxFragWrite Start a burst transfer from the RxDataFIFO to host memory at fragPtr. The length

is the minimum of rxPktBytes, and descCnt. Decrement descCnt accordingly.

(descCnt == 0) && rxDescWrite Start a burst transfer to write the status back to the descriptor, setting the OWN

(rxPktBytes > 0) bit, and setting the MORE bit. The PHY/PCI bus controller will continue the

packet in the next descriptor.

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rxDescRefr

rxIdle

rxDescRead

rxFifoBlockrxDescWrite

rxAdvance

rxFragWrite

CR:RXE && CRDD

CR:RXE && !CRDD

link = NULL

XferDone

XferDone && !OWN

XferDone && OWN

link != NULL

(descCnt == 0) && (rxPktBytes > 0)

FifoReady

rxPktBytes == 0

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Table 5-10. Receive State Tables (continued)

STATE EVENT NEXT STATE ACTIONS

rxPktBytes == 0 rxDescWrite Start a transfer to write the cmdsts back to the descriptor, setting the OWN bit

and clearing the MORE bit, and filling in the final receive status (CRC, FAE,

SIZE, and so forth).

rxFragWrite XferDone rxFIFOblock

rxDescWrite XferDone rxAdvance

rxAdvance link!= NULL rxDescRead RXDP <- rxDescCache.link. Clear CRDD. Start a burst transfer at address RXDP

with a length derived from RXCFG:MXDMA.

link == NULL rxIdle Set CRDD. Set ISR:RXIDLE.

Figure 5-23. Receive State Diagram

5.5.5.3.2 Receive Data Flow

With a bus mastering architecture, some number of buffers and descriptors for received packets must be

pre-allocated when the DP83816 device is initialized. The number allocated directly affects system

tolerance to interrupt latency. The more buffers that you pre-allocate, the longer the system can survive an

incoming burst without losing receive packets if receive descriptor processing is delayed or preempted.

Buffers sizes should be allocated in 32-byte multiples.

1. Prior to packet reception, receive buffers must be described in a receive descriptor list (or ring, if

preferred). In each descriptor, the driver assigns ownership to the hardware by clearing the OWN bit.

Receive descriptors may describe a single buffer.

2. The address of the first descriptor in this list is then written to the RXDP register. As packets arrive,

they are placed in available buffers. A single packet may occupy one or more receive descriptors, as

required by the application. The device reads in the first descriptor into the RxDescCache.

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3. As data arrives in the RxDataFIFO, the receive buffer management state machine places the data in

the receive buffer described by the descriptor. This continues until either the end of packet is reached,

or the descriptor byte count for this descriptor is reached.

4. If end of packet was reached, the status in the descriptor (in main memory) is updated by setting the

OWN bit and clearing the MORE bit, by updating the receive status bits as indicated by the MAC, and

by updating the SIZE field. The status bits in cmdsts are only valid in the last descriptor of a packet

(with the MORE bit clear). Also for the last descriptor of a packet, the SIZE field is updated to reflect

the actual amount of data written to the buffer (which may be less the full buffer size allocated by the

descriptor).

If the receive buffer management state machine runs out of descriptors while receiving a packet, data is

buffered in the receive FIFO. If the FIFO overflows, the driver is interrupted with an RxOVR error.

5.6 Register Block

This section includes information on the registers in the DP83816 device. The registers are classified by

the following categories:

• Configuration registers

• Operational registers

• Internal PHY registers

5.6.1 Register Definition

In the register definitions under the default heading, the following definitions hold true:

•R/W =Read Write access

•RO =Read Only access

•WO =Write Only access

5.6.2 Configuration Registers

The DP83816 device implements a PCI version 2.2 configuration register space. This allows a PCI BIOS

to soft-configure the DP83816 device. Software Reset has no effect on configuration registers. Hardware

Reset returns all configuration registers to their hardware reset state. For all unused registers, writes are

ignored, and reads return 0.

Table 5-11. Configuration Register Map

OFFSET TAG DESCRIPTION ACCESS

00h CFGID Configuration Identification Register RO

04h CFGCS Configuration Command and Status Register R/W

08h CFGRID Configuration Revision ID Register RO

0Ch CFGLAT Configuration Latency Timer Register RO

10h CFGIOA Configuration IO Base Address Register R/W

14h CFGMA Configuration Memory Address Register R/W

18h–28h RESERVED RESERVED (reads return zero) RO

2Ch CFGSID Configuration Subsystem Identification Register RO

30h CFGROM Boot ROM configuration register R/W

34h CAPPTR Capabilities Pointer Register RO

38h RESERVED RESERVED (reads return zero) RO

3Ch CFGINT Configuration Interrupt Select Register R/W

40h PMCAP Power Management Capabilities Register RO

44h PMCSR Power Management Control and Status Register R/W

48h–FFh RESERVED RESERVED (reads return zero) RO

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5.6.2.1 Configuration Identification Register (CFGID)

This register identifies the DP83816 controller to PCI system software.

Table 5-12. Configuration Identification Register (CFGID) Address 00h

BIT BIT NAME DEFAULT DESCRIPTION

31:16 DEVID <0000 0000 0010 Device ID

0000>, RO This field is read-only and is set to the device ID assigned to the DP83816 device, which is

0020h.

15:0 VENID <0001 0000 0000 Vendor ID

1011>, RO This field is read-only and is set to a value of 100Bh which is the PCI Vendor ID.

5.6.2.2 Configuration Command and Status Register (CFGCS)

The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. A status bit is

reset whenever the register is written, and the corresponding bit location is a 1. The lower 16-bits (15-0)

are devoted to command and are used to configure and control the device.

Table 5-13. Configuration Command and Status Register (CFGCS) Address 04h

BIT BIT NAME DEFAULT DESCRIPTION

31 DPERR <02900000h>0, Detected Parity Error

R/W See the description in the PCI V2.2 specification.

30 SSERR 0, R/W Signaled SERR

See the description in the PCI V2.2 specification.

29 RMABT 0, R/W Received Master Abort

See the description in the PCI V2.2 specification.

28 RTABT 0, R/W Received Target Abort

See the description in the PCI V2.2 specification.

27 STABT 0, R/W Sent Target Abort

See the description in the PCI V2.2 specification.

26:25 DSTIM <01>, R/W DEVSELN Timing

This field is always set to 01, indicating that DP83816 device supports medium DEVSELN

timing.

24 DPD 0, R/W Data Parity Detected

See the description in the PCI V2.2 specification.

23 FBB 1, R/W Fast Back-to-Back Capable

The DP83816 device sets this bit to 1.

22:21 RESERVED <00>, RO RESERVED

(reads return 0)

20 NCPEN 1, R/W New Capabilities Enable

When set, this bit indicates that the Capabilities Pointer contains a valid value and new

capabilities such as power management are supported. When clear, new capabilities

(CAPPTR, PMCAP, PMCS) are disabled. This bit is loaded from a strap option, MD0 pin

132. A subsequent load of the configuration data from the EEPROM overwrites any pre-

existing value.

19:16 RESERVED <0000>, RO RESERVED

(reads return 0)

15:10 RESERVED <0000 00>, RO RESERVED

(reads return 0)

9 FBBEN 0, R/W Fast Back-to-Back Enable

Set to 1 by the PCI BIOS to enable the DP83816 device to do Fast Back-to-Back transfers

(FBB transfers as a master is not implemented in the current revision).

8 SERREN 0, R/W SERRN Enable

When SERREN and PERRSP are set, the DP83816 device generates SERRN during target

cycles when an address parity error is detected from the system. Also, when SERREN and

PERRSP are set and CFG:PESEL is reset, master cycles detecting data parity errors

generate SERRN.

7 RESERVED 0, RO RESERVED

(reads return 0)

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Table 5-13. Configuration Command and Status Register (CFGCS) Address 04h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

6 PERRSP 0, R/W Parity Error Response

When set, the DP83816 device asserts PERRN on the detection of a data parity error when

acting as the target, and samples PERRN when acting as the initiator. Also, setting

PERRSP allows SERREN to enable the assertion of SERRN. When reset, all address and

data parity errors are ignored and neither SERRN nor PERRN are asserted.

5:3 RESERVED <00 0>, RO RESERVED

(reads return 0)

2 BMEN 0, R/W Bus Master Enable

When set, the DP83816 device is allowed to act as a PCI bus master. When reset, the

DP83816 device is prohibited from acting as a PCI bus master.

1 MSEN 0, R/W Memory Space Address

When set, the DP83816 device responds to memory space accesses. When reset, the

DP83816 device ignores memory space accesses.

0 I/OSEN 0, R/W I/O Space Access

When set, the DP83816 device responds to I/O space accesses. When reset, the DP83816

device ignores I/O space accesses.

5.6.2.3 Configuration Revision ID Register (CFGRID)

This register stores the silicon revision number, revision number of software interface specification and

lets the configuration software know that it is an Ethernet controller in the class of network controllers.

Table 5-14. Configuration Revision ID Register (CFFRID) Address 08h

BIT BIT NAME DEFAULT DESCRIPTION

31:24 BASECL <0000 0010>, RO Base Class

Returns 02h which specifies a network controller.

23:16 SUBCL <0000 0000>, RO Sub Class

Returns 00h which specifies an Ethernet controller.

15:8 PROGIF <0000 0000>, RO Programming IF

Returns 00h, which specifies the first release of the DP83816 software interface

specification.

7:0 REVID <0000 0000>, RO Silicon Revision

Returns 00h which specifies the silicon revision.

5.6.2.4 Configuration Latency Timer Register (CFGLAT)

This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache

line size.

Table 5-15. Configuration Latency Timer Register (CFGLAT) Address 0Ch

BIT BIT NAME DEFAULT DESCRIPTION

31 BISTCAP 0, R/W BIST Capable

Reads always return 0.

30 BISTEN 0, RO BIST Enable

Reads return a 0, writes are ignored.

29:16 RESERVED <00 0000 0000 RESERVED

0000>, RO Reads return a 0, writes are ignored.

15:8 LAT <0000 0000>, Latency Timer

R/W Set by software to the number of PCI clocks that the DP83816 device may hold the PCI bus.

7:0 CLS <0000 0000>, Cache Line Size

R/W Ignored by the DP83816 device.

DP83816 bus master operations:

Independent of cache line size, the DP83816 device uses the following PCI commands for bus mastered

transfers:

0110 - Mem read for all read cycles,

0111 - Mem write for all write cycles.

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5.6.2.5 Configuration I/O Base Address Register (CFGIOA)

This register specifies the base I/O address which is required to build an address map during

configuration. It also specifies the number of bytes required as well as an indication that it can be mapped

into I/O space.

Table 5-16. Configuration I/O Base Address Register (CFGIOA) Address 10h

BIT BIT NAME DEFAULT DESCRIPTION

31:8 IOBASE <0000 0000 Base I/O Address

0000 0000 0000 This is set by software to the base I/O address for the Operational Register Map.

0000>, R/W

7:2 IOSIZE <0000 00>, RO Size indication

Read back as 0. This allows the PCI bridge to determine that the DP83816 device requires

256 bytes of I/O space.

1 RESERVED 0, RO RESERVED

(reads return 0).

0 IOIND 1, RO I/O Space Indicator

Set to 1 by the DP83816 device to indicate that the DP83816 device is capable of being

mapped into I/O space. Read Only.

5.6.2.6 Configuration Memory Address Register (CFGMA)

This register specifies the base memory address which is required to build an address map during

configuration. It also specifies the number of bytes required as well as an indication that it can be mapped

into memory space.

Table 5-17. Configuration Memory Address Register (CFGMA) Address 14h

BIT BIT NAME DEFAULT DESCRIPTION

31:12 MEMBASE <0000 0000 Memory Base Address

0000 0000 This is set by software to the base address for the operational register map.

0000>, R/W

11:4 MEMSIZE <0000 0000>, Memory Size

RO These bits return 0, which indicates that the DP83816 requires 4096 bytes of memory space

(the minimum recommended allocation).

3 MEMPF 0, RO Prefetchable

Set to 0 by the DP83816 device. Read-only.

2:1 MEMLOC <00>, RO Location Selection

Set to 00 by the DP83816 device. This indicates that the base register is 32-bits wide and can

be placed anywhere in the 32-bit memory space. Read Only.

0 MEMIND 0, RO Memory Space Indicator

Set to 0 by the DP83816 device to indicate that the DP83816 device is capable of being

mapped into memory space. Read Only.

5.6.2.7 Configuration Subsystem Identification Register (CFGSID)

The CFGSID allows system software to distinguish between different subsystems based on the same PCI

silicon. The values in this register can be loaded from the EEPROM if configuration is enabled.

Table 5-18. Configuration Subsystem Identification Register (CFGSID) Address 2Ch

BIT BIT NAME DEFAULT DESCRIPTION

31:16 SDEVID <0000 0000 Subsystem Device ID

0000 0000>, Set to 0 by the DP83816 device.

15:0 SVENID <0000 0000 Subsystem Vendor ID

0000 0000>, Set to 0 by the DP83816 device.

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5.6.2.8 Boot ROM Configuration Register (CFGROM)

Table 5-19. Boot ROM Configuration Register (CFGROM) Address 30h

BIT BIT NAME DEFAULT DESCRIPTION

31:16 ROMBASE <0000 0000 ROM Base Address

0000 0000>, RO Set to the base address for the boot ROM.

15:11 ROMSIZE <0000 0>, RO ROM Size

Set to 0 indicating a requirement for 64K bytes of Boot ROM space. Read only.

10:1 RESERVED 0, RO RESERVED

(reads return 0)

0 ROMEN 0, RO ROM Enable

This is used by the PCI BIOS to enable accesses to boot ROM. This allows the DP83816

device to share the address decode logic between the boot ROM and itself. The BIOS

copies the contents of the boot ROM to system RAM before executing it. Set to 1 enables

the address decode for boot ROM disabling access to operational target registers.

5.6.2.9 Capabilities Pointer Register (CAPPTR)

This register stores the capabilities linked list offset into the PCI configuration space.

Table 5-20. Capabilities Pointer Register (CAPPTR) Address 34h

BIT BIT NAME DEFAULT DESCRIPTION

31:8 RESERVED 0, RO RESERVED

(reads return 0)

7:0 CLOFS <0000 0100>, RO Capabilities List Offset

Offset into PCI configuration space for the location of the first item in the Capabilities

Linked List, set to 40h to point to the PMCAP register.

5.6.2.10 Configuration Interrupt Select Register (CFGINT)

This register stores the interrupt line number as identified by the POST software that is connected to the

interrupt controller, as well as the DP83816 desired settings for maximum latency and minimum grant.

Maximum latency and minimum latency can be loaded from the EEPROM.

Table 5-21. Configuration Interrupt Select Register (CFGINT) Address 3Ch

BIT BIT NAME DEFAULT DESCRIPTION

31:24 MXLAT <0011 0100>, Maximum Latency

R/W The DP83816 desired setting for Max Latency. The DP83816 device initializes this field to

52d (13 µs). The value in this register can be loaded from the EEPROM.

23:16 MNGNT <0000 1011>, Minimum Grant

R/W The DP83816 desired setting for minimum grant. The DP83816 device initializes this field

to 11d (2.75 µs). The value in this register can be loaded from the EEPROM.

15:8 IPIN <0000 0001>, RO Interrupt Pin

Read Only, always return 0000 0001 (INTA).

7:0 ILINE <0000 0000>, Interrupt Line

R/W Set to which line on the interrupt controller that the DP83816 interrupt pin is connected to.

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5.6.2.11 Power Management Capabilities Register (PMCAP)

This register provides information on the capabilities of the functions related to power management. This

management. This register is only visible if CFGCS[4] is set.

Table 5-22. Power Management Capabilities Register (PMCAP) Address 40h

BIT BIT NAME DEFAULT DESCRIPTION

31:27 PMES <1111 1>, PME Support

R/W This 5-bit field indicates the power states in which DP83816 device may assert PMEN. A 1

indicates PMEN is enabled for that state, a 0 indicates PMEN is inhibited in that state.

XXXX1 - PMEN can be asserted from state D0

XXX1X - PMEN can be asserted from state D1

XX1XX - PMEN can be asserted from state D2

X1XXX - PMEN can be asserted from state D3hot

1XXXX - PMEN can be asserted from state D3cold

The DP83816 device only reports PME support for D3cold if auxiliary power is detected on the

3VAUX pin. In addition, this value can be loaded from the EEPROM when in the D3cold state.

26 D2S 1, R/W D2 Support

This bit is set to a 1 when the DP83816 device supports the D2 state.

25 D1S 1, R/W D1 Support

This bit is set to a 1 when the DP83816 supports the D1 state.

24:22 AUX_ <1 10>, R/W Aux_Current

CURRENT This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.

If PMEN generation from D3cold is not supported by the function(PMCAP[31]), this field

returns a value of 000b when read.

Bit 3.3Vaux

24 23 22 b

1 1 0 320 mA

0 0 0 0 (self powered)

21 DSI 0, R/W Device Specific Initialization

This bit is set to 1 to indicate to the system that initialization of the DP83816 device is required

(beyond the standard PCI configuration header) before the generic class device driver is able

to use it. A 1 indicates that the DP83816 device requires a DSI sequence following transition to

the D0 uninitialized state. This bit can be loaded from the EEPROM.

20 RESERVED 0, RO RESERVED

(reads return 0)

19 PMEC 0, RO PME Clock

Returns 0 to indicate PCI clock not needed for PMEN.

18:16 PMV <010>, RO Power Management Version

This bit field indicates compliance to a specific PM specification rev level. Currently set to

010b.

15:8 NLIPTR <0000 0000>, Next List Item Pointer

RO Offset into PCI configuration space for the location of the next item in the Capabilities Linked

List. Returns 00h as no other capabilities are offered.

7:0 CAPID <0000 0001>, Capability ID

RO Always returns 01h for Power Management ID.

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5.6.2.12 Power Management Control and Status Register (PMCSR)

This register contains PM control and status information.

Table 5-23. Power Management Control and Status Register (PMCSR) Address 44h

BIT BIT NAME DEFAULT DESCRIPTION

31:24 RESERVED 0, RO RESERVED

Reads return 0.

23:16 BSE <0000 0000>, Bridge Support Extensions

RO Unused – reads return 0.

15 PMESTS 0, RO PME Status

Sticky bit which represents the state of the PME logic, regardless of the state of the PMEEN

bit.

14:9 RESERVED 0, RO RESERVED

(reads return 0)

8 PMEEN 0, R/W PME Enable

When set to 1, this bit enables the assertion of the PME function on the PMEN pin. When 0,

the PMEN pin is forced to be inactive. This value can be loaded from the EEPROM.

7:2 RESERVED 0, RO RESERVED

(reads return 0)

1:0 PSTATE <00>, R/W Power State

This 2 bit field is used to determine the current power state of the DP83816 device, and to set

a new power state.

00–D0 10 - D2

01–D1 11 - D3hot/cold

5.6.3 Operational Registers

The DP83816 device provides the following set of operational registers mapped into PCI memory space or

I/O space. Writes to reserved register locations are ignored. Reads to reserved register locations return

undefined values.

Table 5-24. Operational Register Map

OFFSET TAG DESCRIPTION ACCESS

MAC and BIU REGISTERS

00h CR Command Register R/W

04h CFG Configuration Register R/W

08h MEAR EEPROM Access Register R/W

0Ch PTSCR PCI Test Control Register R/W

10h ISR Interrupt Status Register RO

14h IMR Interrupt Mask Register R/W

18h IER Interrupt Enable Register R/W

1Ch IHR Interrupt Holdoff Register R/W

20h TXDP Transmit Descriptor Pointer Register R/W

24h TXCFG Transmit Configuration Register R/W

28h–2Ch Reserved Reserved

30h RXDP Receive Descriptor Pointer Register R/W

34h RXCFG Receive Configuration Register R/W

38 Reserved Reserved

3Ch CCSR CLKRUN Control and Status Register R/W

40h WCSR Wake on LAN Control and Status Register R/W

44h PCR Pause Control and Status Register R/W

48h RFCR Receive Filter and Match Control Register R/W

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Table 5-24. Operational Register Map (continued)

OFFSET TAG DESCRIPTION ACCESS

4Ch RFDR Receive Filter and Match Data Register R/W

50h BRAR Boot ROM Address R/W

54h BRDR Boot ROM Data R/W

58h SRR Silicon Revision Register RO

5Ch MIBC Management Information Base Control Register R/W

60–78h MIB Management Information Base Data Registers RO

7Ch Reserved Reserved

INTERNAL PHY REGISTERS

80h BMCR Basic Mode Control Register R/W

84h BMSR Basic Mode Status Register RO

88h PHYIDR1 PHY Identifier Register No. 1 RO

8Ch PHYIDR2 PHY Identifier Register No. 2 RO

90h ANAR Auto-Negotiation Advertisement Register R/W

94h ANLPAR Auto-Negotiation Link Partner Ability Register R/W

98h ANER Auto-Negotiation Expansion Register R/W

9Ch ANNPTR Auto-Negotiation Next Page TX R/W

A0-BCh Reserved Reserved

C0h PHYSTS PHY Status Register RO

C4h MICR MII Interrupt Control Register R/W

C8h MISR MII Interrupt Status Register R/W

CCh Reserved Reserved

D0h FCSCR False Carrier Sense Counter Register R/W

D4h RECR Receive Error Counter Register R/W

D8h PCSR 100 Mb/s PCS Configuration and Status R/W

DCh–E0h Reserved Reserved

E4h PHYCR PHY Control Register R/W

E8h TBTSCR 10Base-T Status and Control Register R/W

ECh-FCh Reserved Reserved

5.6.3.1 Command Register (CR)

This register is used for issuing commands to the DP83816 device. These commands are issued by

setting the corresponding bits for the function. A global software reset along with individual reset and

enable or disable for transmitter and receiver are provided here.

Table 5-25. Command Register (CR) Address 0000h

BIT BIT NAME DEFAULT DESCRIPTION

31-9 RESERVED 0, RO RESERVED

(reads return 0)

8 RST 0, R/W Reset

Set to 1 to force the DP83816 device to a soft reset state which disables the transmitter and

receiver, reinitializes the FIFOs, and resets all affected registers to their soft reset state. This

operation implies both a TXR and a RXR. This bit reads back a 1 during the reset operation,

and be cleared to 0 by the hardware when the reset operation is complete. EEPROM

configuration information is not loaded here.

7 SWI 0, R/W Software Interrupt

Setting this bit to a 1 forces the DP83816 device to generate a hardware interrupt. This interrupt

is mask-able via the IMR.

6 RESERVED 0, RO RESERVED

(reads return 0)

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Table 5-25. Command Register (CR) Address 0000h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

5 RXR 0, R/W Receiver Reset

When set to a 1, this bit causes the current packet reception to be aborted, the receive data

and status FIFOs to be flushed, and the receive state machine to enter the idle state (RXE goes

to 0). This is a write-only bit and is always read back as 0.

4 TXR 0, R/W Transmit Reset

When set to a 1, this bit causes the current transmission to be aborted, the transmit data and

status FIFOs to be flushed, and the transmit state machine to enter the idle state (TXE goes to

0). This is a write-only bit and is always read back as 0.

3 RXD 0, R/W Receiver Disable

Disable the receive state machine after any current packets in progress. When this operation

has been completed the RXE bit is cleared to 0. This is a write-only bit and is always read back

as 0. The driver should not set both RXD and RXE in the same write, the RXE is ignored, and

RXD has precedence.

2 RXE 0, R/W Receiver Enable

When set to a 1, and the receive state machine is idle, then the receive machine becomes

active. This bit reads back as a 1 whenever the receive state machine is active. After initial

power-up, software must insure that the receiver has completely reset before setting this bit

(See ISR:RXRCMP).

1 TXD 0, R/W Transmit Disable

When set to a 1, halts the transmitter after the completion of the current packet. This is a write-

only bit and is always read back as 0. The driver should not set both TXD and TXE in the same

write, because TXE is ignored, and TXD has precedence.

0 TXE 0, R/W Transmit Enable

When set to a 1, and the transmit state machine is idle, then the transmit state machine

becomes active. This bit reads back as a 1 whenever the transmit state machine is active. After

initial power-up, software must insure that the transmitter has completely reset before setting

this bit (See ISR:TXRCMP).

5.6.3.2 Configuration and Media Status Register (CFG)

This register allows configuration of a variety of device and PHY options, and provides PHY status

information.

Table 5-26. Configuration and Media Status Register (CFG) Address 0004h

BIT BIT NAME DEFAULT DESCRIPTION

31 LNKSTS 0, RO Link Status

Link status of the internal PHY. Asserted when link is good.

30 SPEED100 0, RO Speed 100 Mb/s

Speed 100-Mb/s indicator for internal PHY. Asserted when speed is set or has negotiated to

100 Mb/s. De-asserted when speed has been set or negotiated to 10 Mb/s.

29 FDUP 0, RO Full Duplex

Full Duplex indicator for internal PHY. Asserted when duplex mode is set or has negotiated to

FULL. De- asserted when duplex mode has been set or negotiated to HALF.

28 POL 0, RO 10-Mb/s Polarity Indication

Twisted pair polarity indicator for internal PHY. Asserted when operating and 10 Mb/s and the

polarity have been detected as reversed. De-asserted when polarity is normal or PHY is

operating at 100 Mb/s.

27 ANEG_DN 0, RO Auto-negotiation Done

Auto-negotiation done indicator from internal PHY. Asserted when auto-negotiation process

has completed or is not active.

26-24 RESERVED 0, RO RESERVED

(reads return 0)

23-18 PHY_CFG 0, RO PHY Configuration

Miscellaneous internal PHY Power-On-Reset configuration control bits.

17 PINT_ACEN 0, R/W PHY Interrupt Auto Clear Enable

When set to a 1, this bit allows the PHY interrupt source to be automatically cleared

whenever the ISR is read. When this bit is 0, the PHY interrupt source must be manually

cleared via access of the PHY registers.

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Table 5-26. Configuration and Media Status Register (CFG) Address 0004h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

16 PAUSE_ADV 0, R/W Pause Advertise

This bit is loaded from EEPROM at power-up and is used to configure the internal PHY to

advertise the capability of 802.3x pause during auto-negotiation. Setting this bit to 1 causes

the pause function to be advertised if the PHY has also been configured to advertise full-

duplex capability (See the ANEG_SEL bits in this table).

15-13 ANEG_SEL <000>, R/W Auto-negotiation Select

These bits are loaded from EEPROM at power-up and are used to define the default state of

the internal PHY auto-negotiation logic. These bits are encoded as follows:

000 Auto-negotiation disabled, force 10 Mb/s half-duplex

010 Auto-negotiation disabled, force 100 Mb/s half-duplex

100 Auto-negotiation disabled, force 10 Mb/s full-duplex

110 Auto-negotiation disabled, force 100 Mb/s full-duplex

001 Auto-negotiation enabled, advertise 10 Mb/s half- and full-duplex

011 Auto-negotiation enabled, advertise 10/100 Mb/s half-duplex

101 Auto-negotiation enabled, advertise 100 Mb/s half- and full-duplex

111 Auto-negotiation enabled, advertise 10/100 Mb/s half- and full-duplex

12 EXT_PHY 0, R/W External PHY Support

Act as a stand-alone MAC. When set, this bit enables the MII and disables the internal PHY

(sets bit 9).

11 RESERVED 0, RO RESERVED

(reads return 0)

10 PHY_RST 0, R/W Reset internal PHY

Asserts reset to internal PHY. Can be used to cause PHY to reload options from the CFG

9 PHY_DIS 0, R/W Disable internal PHY

When set to a 1, this bit forces the internal PHY to its low-power state.

8 EUPHCOMP 0, R/W DP83810 Descriptor Compatibility

When set, the DP83816 device uses DP83810 compatible (but single-fragment) descriptor

format. Descriptors are four 32-bit words in length, but the fragment count field is ignored.

When clear, the DP83816 device only fetches three 32-bit words in descriptor fetches with

the third word being the fragment pointer.

7 REQALG 0, R/W PCI Bus Request Algorithm

Selects mode for making requests for the PCI bus. When set to 0 (default), the DP83816

device uses an aggressive request scheme. When set to 1, the DP83816 device uses a more

conservative scheme.

6 SB 0, R/W Single Back-off

Setting this bit to 1 forces the transmitter back-off state machine to always back-off for a

single 802.3 slot time instead of following the 802.3 random back-off algorithm. A 0 (default)

allows normal transmitter back-off operation.

5 POW 0, R/W Program Out of Window Timer

This bit controls when the Out of Window collision timer begins counting its 512 bit slot time.

A 0 causes the timer to start after the SFD is received. A 1 causes the timer to start after the

first bit of the preamble is received.

4 EXD 0, R/W Excessive Deferral Timer disable

Setting this bit to 1 inhibits transmit errors due to excessive deferral. This inhibits the setting

of the ED status, and the logging of the TxExcessiveDeferral MIB counter.

3 PESEL 0, R/W Parity Error Detection Action

This bit controls the assertion of SERR when a data parity error is detected while the

DP83816 device is acting as the bus master. When set, parity errors do not result in the

assertion of SERR. When reset, parity errors result in the assertion of SERR, indicating a

system error. This bit should be set to a one by software if the driver can handle recovery

from and reporting of data parity errors.

2 BROM_DIS 0, R/W Disable Boot ROM interface

When set to 1, this bit inhibits the operation of the Boot ROM interface logic.

1 RESERVED 0, RO RESERVED

(reads return 0)

0 BEM 0, R/W Big Endian Mode

When set, the DP83816 device performs bus-mastered data transfers in big-endian mode.

Note that access to register space is unaffected by the setting of this bit. .

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5.6.3.3 EEPROM Access Register (MEAR)

The EEPROM access register provides an interface for software access to the NMC9306 style EEPROM

The default values given assume that the EEDO line has a pullup resistor to VDD.

Table 5-27. EEPROM Access Register (MEAR) Address 0008h

BIT BIT NAME DEFAULT DESCRIPTION

31-7 RESERVED 0, RO RESERVED

(reads return 0)

6 MDC 0, R/W MII Management Clock

Controls the value of the MDC pin. When set, the MDC pin is 1; when clear the MDC pin is

5 MDDIR 0, R/W MII Management Direction

Controls the direction of the MDIO pin. When set, the DP83816 device drives the MDIO pin.

When clear, the MDIO bit reflects the current state of the MDIO pin.

4 MDIO 0, R/W MII Management Data

Software access to the MDIO pin (see MDDIR above).

3 EESEL 0, R/W EEPROM Chip Select

Controls the value of the EESEL pin. When set, the EESEL pin is 1; when clear the EESEL

pin is 0.

2 EECLK 0, R/W EEPROM Serial Clock

Controls the value of the EECLK pin. When set, the EECLK pin is 1; when clear the EECLK

pin is 0.

1 EEDO 1, RO EEPROM Data Out

Returns the current state of the EEDO pin. When set, the EEDO pin is 1; when clear the

EEDO pin is 0.

0 EEDI 0, R/W EEPROM Data In

Controls the value of the EEDI pin.

5.6.3.3.1 EEPROM Map

Table 5-28. EEPROM Register Map

EEPROM ADDRESS CONFIGURATION and OPERATION REGISTER BITS DEFAULT VALUE (16 BITS)

0000h CFGSID[0:15] D008h

0001h CFGSID[16:31] 0400h

0002h CFGINT[24:31], CFGINT[16:23] 2CD0h

0003h CFGCS[20], PMCAP[31], PMCAP[21], PMCSR[8], CFG[13:16], CFG[18:23], CF82h

CR[2], SOPAS[0]

0004h SOPAS[1:16] 0000h

0005h SOPAS[17:32] 0000h

0006h SOPAS[33:47], PMATCH[0] 000Nh(1)

0007h PMATCH[1:16] NNNNh(1)

0008h PMATCH[17:32] NNNNh(1)

0009h PMATCH[33:47], WCSR[0] NNNNh(1)

000Ah WCSR[1:4], WCSR[9:10], RFCR[20], RFCR[22], RFCR[27:31], 000b (3 bits) A098h

000Bh checksum value XX55(2)

(1) N denotes the value is dependent on the ethernet MAC ID Number.

(2) X denotes the value is dependent on the checksum value.

PMATCH[47:0] can be accessed through the combination of the RFCR (offset 0048h) and RFDR (offset

004Ch) registers. PMATCH holds the Ethernet address info. See Section 5.5.2.2.

The lower 8 bits of the checksum value should be 55h. For the upper 8 bits, add the top 8 data bits to the

lower 8 data bits for each address. Sum the resultant 8 bit values for all addresses and then add 55h.

Take the 2’s complement of the final sum. This 2’s complement number should be the upper 8 bits of the

checksum value in the last address.

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As an example, consider an EEPROM with two addresses. EEPROM address 0000h contains the data

1234h. EEPROM address 0001h contains the data 5678h.

12h + 34h = 46h

56h + 78h = CEh

46h + CEh + 55h = 69h

The 2’s complement of 69h is 97h so the checksum value entered into EEPROM address 0002h would be

9755h.

5.6.3.4 PCI Test Control Register (PTSCR)

Table 5-29. PCI Test Control Register (PTSCR) Address 000Ch

BIT BIT NAME DEFAULT DESCRIPTION

31:13 RESERVED 0, RO RESERVED

(reads return 0)

12 RESERVED 0, RO Reserved for TI internal use only.

Must be written as a 0 otherwise.

11 RESERVED 0, RO RESERVED

(reads return 0)

10 RBIST_RST 0, R/W SRAM BIST Reset

Setting this bit to 1 allows the SRAM BIST engine to be reset.

9:8 RESERVED 0, RO Reserved for TI internal use only.

Must be written as a 00 otherwise.

7 RBIST_EN 0, R/W SRAM BIST Enable

Setting this bit to 1 starts the SRAM BIST engine.

6 RBIST_DONE 0, RO SRAM BIST Done

This bit is set to one when the BIST has completed its current test. It is cleared when

either the BIST is active or disabled.

5 RBIST_RXFAIL 0, RO RX FIFO BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in the RX FIFO SRAM.

4 RBIST_TXFAIL 0, RO TX FIFO Fail

This bit is set to 1 if the SRAM BIST detects a failure in the TX FIFO SRAM.

3 RBIST_RXFFAIL 0, RO RX Filter RAM BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in the RX Filter SRAM.

2 EELOAD_EN 0, R/W Enable EEPROM Load

This bit is set to a 1 to manually initiate a load of configuration information from

EEPROM. A 1 is returned while the configuration load from EEPROM is active

(approximately 1500 µs).

1 EEBIST_EN 0, R/W Enable EEPROM BIST

This bit is set to a 1 to initiate EEPROM BIST, which verifies the EEPROM data and

checksum without reloading configuration values to the device. A 1 is returned while

the EEPROM BIST is active.

0 EEBIST_FAIL 0, RO EE BIST Fail indication

This bit is set to a 1 on completion of the EEPROM BIST (EEBIST_EN returns 0) if

the BIST logic encountered an invalid checksum.

5.6.3.5 Interrupt Status Register (ISR)

This register indicates the source of an interrupt when the INTA pin goes active. Enabling the

corresponding bits in the interrupt mask register (IMR) allows bits in this register to produce an interrupt.

When an interrupt is active, one or more bits in this register are set to 1. The interrupt status register

reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR.

Reading the ISR clears all interrupts. Writing to the ISR has no effect.

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Table 5-30. Interrupt Status Register (ISR) Address 0010h

BIT BIT NAME DEFAULT DESCRIPTION

31:26 RESERVED 0, RO RESERVED

(reads return 0)

25 TXRCMP 1, RO Transmit Reset Complete

Indicates that a requested transmit reset operation is complete.

24 RXRCMP 1, RO Receive Reset Complete

Indicates that a requested receive reset operation is complete.

23 DPERR 0, RO Detected Parity Error

This bit is set whenever CFGCS:DPERR is set, but cleared (like all other ISR bits)

when the ISR register is read.

22 SSERR 0, RO Signaled System Error

The DP83816 device signaled a system error on the PCI bus.

21 RMABT 0, RO Received Master Abort

The DP83816 device received a master abort generated as a result of target not

responding.

20 RTABT 0, RO Received Target Abort

The DP83816 device received a target abort on the PCI bus.

19:17 RESERVED 0, RO RESERVED

(reads return 0)

16 RXSOVR 0, RO Rx Status FIFO Overrun

Set when an overrun condition occurs on the Rx Status FIFO.

15 HIBERR 1, RO High-Bits Error Set

A logical OR of bits 25-16.

14 PHY 0, RO PHY interrupt

Set to 1 when internal PHY generates an interrupt.

13 PME 0, RO Power Management Event

Set when WOL conditioned detected.

12 SWI 0, RO Software Interrupt

Set whenever the SWI bit in the CR register is set.

11 MIB 0, RO MIB Service

Set when one of the enabled management statistics has reached its interrupt

threshold. (See Section 4.2.24)

10 TXURN 0, RO Tx Underrun

Set when a transmit data FIFO underrun condition occurs.

9 TXIDLE 0, RO Tx Idle

This event is signaled when the transmit state machine enters the idle state from a

non-idle state. This happens whenever the state machine encounters an end-of-list

condition (NULL link field or a descriptor with OWN clear).

8 TXERR 0, RO Tx Packet Error

This event is signaled after the last transmit descriptor in a failed transmission attempt

has been updated with valid status.

7 TXDESC 0, RO Tx Descriptor

This event is signaled after a transmit descriptor when the INTR bit in the CMDSTS

field has been updated.

6 TXOK 0, RO Tx Packet OK

This event is signaled after the last transmit descriptor in a successful transmission

attempt has been updated with valid status.

5 RXORN 0, RO Rx Overrun

Set when a receive data FIFO overrun condition occurs.

4 RXIDLE 0, RO Rx Idle

This event is signaled when the receive state machine enters the idle state from a

running state. This happens whenever the state machine encounters an end-of-list

condition (NULL link field or a descriptor with OWN set).

3 RXEARLY 0, RO Rx Early Threshold

Indicates that the initial Rx Drain Threshold has been met by the incoming packet,

and the transfer of the number of bytes specified by the DRTH field in the RXCFG

occurs only once per packet.

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Table 5-30. Interrupt Status Register (ISR) Address 0010h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

2 RXERR 0, RO Rx Packet Error

This event is signaled after the last receive descriptor in a failed packet reception has

been updated with valid status.

1 RXDESC 0, RO Rx Descriptor

This event is signaled after a receive descriptor with the INTR bit set in the CMDSTS

field has been updated.

0 RXOK 0, RO Rx OK

Set by the receive state machine following the update of the last receive descriptor in

a good packet.

5.6.3.6 Interrupt Mask Register (IMR)

This register masks the interrupts that can be generated from the ISR. Writing a 1 to the bit enables the

corresponding interrupt. During a hardware reset, all mask bits are cleared. Setting a mask bit allows the

corresponding bit in the ISR to cause an interrupt. ISR bits are always set to 1, however, if the condition is

present, regardless of the state of the corresponding mask bit.

Table 5-31. Interrupt Mask Register (IMR) Address 0014h

BIT BIT NAME DEFAULT DESCRIPTION

31:26 RESERVED 0, RO RESERVED

(reads return 0)

25 TXRCMP 0, R/W Transmit Reset Complete

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

24 RXRCMP 0, R/W Receive Reset Complete

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

23 DPERR 0, R/W Detected Parity Error

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

22 SSERR 0, R/W Signaled System Error

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

21 RMABT 0, R/W Received Master Abort

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

20 RTABT 0, R/W Received Target Abort

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

19:17 RESERVED 0, RO RESERVED

(reads return 0)

16 RXSOVR 0, R/W Rx Status FIFO Overrun

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

15 HIERR 0, R/W High Bits Error

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

14 PHY 0, R/W PHY interrupt

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

13 PME 0, R/W Power Management Event

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

12 SWI 0, R/W Software Interrupt

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

11 MIB 0, R/W MIB Service

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

10 TXURN 0, R/W Tx Underrun

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

9 TXIDLE 0, R/W Tx Idle

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

8 TXERR 0, R/W Tx Packet Error

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

7 TXDESC 0, R/W Tx Descriptor

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

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Table 5-31. Interrupt Mask Register (IMR) Address 0014h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

6 TXOK 0, R/W Tx Packet OK

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

5 RXORN 0, R/W Rx Overrun

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

4 RXIDLE 0, R/W Rx Idle

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

3 RXEARLY 0, R/W Rx Early Threshold

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

2 RXERR 0, R/W Rx Packet Error

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

1 RXDESC 0, R/W Rx Descriptor

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

0 RXOK 0, R/W Rx OK

When this bit is 0, the corresponding bit in the ISR does not cause an interrupt.

5.6.3.7 Interrupt Enable Register (IER)

The interrupt enable register controls the hardware INTR signal.

Table 5-32. Interrupt Enable Register (IER) Address 0018h

BIT BIT NAME DEFAULT DESCRIPTION

31:1 RESERVED 0, RO RESERVED

(reads return 0)

0 IE 0, R/W Interrupt Enable

When set to 1, the hardware INTR signal is enabled. When set to 0, the hardware

INTR signal is masked, and no interrupts are generated. The setting of this bit has

no effect on the ISR or IMR. This provides the ability to disable the hardware

interrupt to the host with a single access (eliminating the need for a read-modify-write

cycle). The actual enabling of interrupts can be delayed based on the Interrupt

Holdoff Register defined in the following section. If IE = 0, the interrupt holdoff timer

does not start.

5.6.3.8 Interrupt Holdoff Register (IHR)

The interrupt holdoff register provides interrupt holdoff support. This allows interrupts to be delayed based

on a programmable delay timer.

Table 5-33. Interrupt Holdoff Register (IHR) Address 001Ch

BIT BIT NAME DEFAULT DESCRIPTION

31:9 RESERVED 0, RO RESERVED

(reads return 0)

8 IHCTL 0, R/W Interrupt Holdoff Control

If this bit is set, the interrupt holdoff timer starts when the first interrupt event occurs

and interrupts are enabled. When this bit is not set, the interrupt holdoff timer starts

as soon as the timer is loaded and interrupts are enabled. In other words, when not

set, the timer delays the interrupt enable.

7:0 IH <0000 0000>, R/W Interrupt Holdoff

The register contains a counter value for use in preventing interrupt assertion for a

programmed amount of time. When the ISR is read, the interrupt holdoff timer is

loaded with this value. It begins to count down to 0 based on the setting of the IHCTL

bit. When it reaches 0, interrupts are enabled. The counter value is in units of 100 µs.

When Interrupts are enabled IE = 1, and IH contains a value other than 00h, IHCTL determines when the

Interrupt Holdoff timer begins its countdown as such:

IHCTL = 1: The timer does not begin until an interrupt event occurs.

The reporting of an interrupt event is delayed for a fixed amount of time from when

the interrupt occurs.

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IHCTL = 0: The timer begins immediately without waiting for an interrupt event.

The reporting of an interrupt event is delayed for a non-fixed amount of time from

when the interrupt occurs

When IH = 00h (default), there is no delay applied regardless of what IHCTL is set to.

5.6.3.9 Transmit Descriptor Pointer Register (TXDP)

This register points to the current transmit descriptor.

Table 5-34. Transmit Descriptor Pointer Register (TXDP) Address 0020h

BIT BIT NAME DEFAULT DESCRIPTION

31:2 TXDP <0000 0000 0000 Transmit Descriptor Pointer

0000 0000 0000 000 The current value of the transmit descriptor pointer. When the transmit state

00>, R/W machine is idle, software must set TXDP to the address of a completed transmit

descriptor. While the transmit state machine is active, TXDP follows the state

machine as it advances through a linked list of active descriptors. If the link field of

the current transmit descriptor is NULL (signifying the end of the list), TXDP does

not advance, but remains on the current descriptor. Any subsequent writes to the

TXE bit of the CR register cause the transmit state machine to reread the link field of

the current descriptor to check for new descriptors that may have been appended to

the end of the list. Transmit descriptors must be aligned on an even 32-bit boundary

in host memory (A1-A0 must be 0).

1:0 RESERVED 0, RO RESERVED

(reads return 0)

5.6.3.10 Transmit Configuration Register (TXCFG)

This register defines the transmit configuration for the DP83816 device. It controls such functions as

loopback, heartbeat, auto transmit padding, programmable Interframe Gap, fill and drain Thresholds, and

maximum DMA burst size.

Table 5-35. Transmit Configuration Register (TXCFG) Address 0024h

BIT BIT NAME DEFAULT DESCRIPTION

31 CSI 0, R/W Carrier Sense Ignore

Setting this bit to 1 causes the transmitter to ignore carrier sense activity, which

inhibits reporting of CRS status to the transmit status register. When this bit is 0

(default), the transmitter monitors the CRS signal during transmission and reflects

valid status in the transmit status register and MIB counter block. This bit must be

set to enable full-duplex operation.

30 HBI 0, R/W HeartBeat Ignore

Setting this bit to 1 causes the transmitter to ignore the heartbeat (CD) pulse which

follows the packet transmission and inhibits logging of TXSQEErrors in the MIB

counter block. When this bit is set to 0 (default), the transmitter monitors the

heartbeat pulse and log TXSQEErrors to the MIB counter block. This bit must be set

to enable full-duplex operation

29 MLB 0, R/W MAC Loopback

Setting this bit to a 1 places the DP83816 MAC into a loopback state which routes

all transmit traffic to the receiver, and disables the transmit and receive interfaces of

the MII. A 0 in this bit allows normal MAC operation. The transmitter and receiver

must be disabled before enabling the loopback mode. (Packets received during MLB

mode reflect loopback status in the receive cmdsts.LBP field of the descriptor.)

28 ATP 0, R/W Automatic Transmit Padding

Setting this bit to 1 causes the MAC to automatically pad small (runt) transmit

packets to the Ethernet minimum size of 64 bytes. This allows driver software to

transfer only actual packet data. Setting this bit to 0 disables the automatic padding

function, forcing software to control runt padding.

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Table 5-35. Transmit Configuration Register (TXCFG) Address 0024h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

27–26 IFG <00>, R/W Interframe Gap Time

This field allows the user to adjust the interframe gap time below the standard 9.6 µs

at 10 Mb/s and 960 ns at 100 Mb/s. The time can be programmed from 9.6 µs to 8.4

µs at 10 Mb/s and 960 ns to 840 ns at 100 Mb/s. Note that any value other than

zero may violate the IEEE 802.3 standard. The formula for the interframe gap is:

9.6 µs – 0.4 (IFG[1:0]) µs at 10 Mb/s

960 ns – 40 (IFG[1:0]) ns at 100 Mb/s

25:24 RESERVED <00>, R/W Reserved for TI internal use only.

Must be written as a 00 otherwise.

23 ECRETRY 0, R/W Excessive Collision Retry Enable

This bit enables automatic retries of excessive collisions. If set, the transmitter

retries the packet up to four excessive collision counts, for a total of 64 attempts. If

the packet still does not complete successfully, then the transmission is aborted

after the 64th attempt. If this bit is not set, then the transmit is aborted after the 16th

attempt. Note that setting this bit changes how collisions are reported in the status

field of the transmit descriptor.

22:20 MXDMA <000>, R/W Max DMA Burst Size per Tx DMA Burst

This field sets the maximum size of transmit DMA data bursts according to the

following table:

000 = 128 32-bit words (512 bytes)

001 = 1 32-bit word (4 bytes)

010 = 2 32-bit words (8 bytes)

011 = 4 32-bit words (16 bytes)

100 = 8 32-bit words (32 bytes)

101 = 16 32-bit words (64 bytes)

110 = 32 32-bit words (128 bytes)

111 = 64 32-bit words (256 bytes)

NOTE: The MXDMA setting value must not be greater than the TXCFG:FLTH (Tx

Fill Threshold) value.

19 RESERVED 0, RO RESERVED

(reads return 0)

18 RESERVED 1, R/W Reserved for TI internal use only.

Must be set to 1. Setting this bit to 0 selects a non-standard back-off algorithm that

could increase the likelihood of excessive collisions.

17:14 RESERVED 0, RO RESERVED

(reads return 0)

13:8 FLTH <00 0001>, R/W Tx Fill Threshold

Specifies the fill threshold in units of 32 bytes. When the number of available bytes

in the transmit FIFO reaches this level, the transmit bus master state machine is

allowed to request the PCI bus for transmit packet fragment reads. A value of 0 in

this field produces unexpected results and must not be used.

NOTE: The FLTH value should be greater than the TXCFG:MXDMA value, but less

than (txFIFOsize–TXCFG:DRTH). To prevent FIFO pointer overlap internal to the

device, the sum of the FLTH and TXCFG:DRTH values should not exceed 2016

Bytes.

7:6 RESERVED 0, RO RESERVED

(reads return 0)

5:0 DRTH <00 0010>, R/W Tx Drain Threshold

Specifies the drain threshold in units of 32 bytes. When the number of bytes in the

FIFO reaches this level (or the FIFO contains at least one complete packet), the

MAC transmit state machine begins the transmission of a packet.

NOTE: To prevent a deadlock condition from occurring, the DRTH value should

always be less than (txFIFOsize–TXCFG:FLTH). A value of 0 in this field produces

unexpected results and must not be used. Also, to prevent FIFO pointer overlap

internal to the device, the sum of the DRTH and TXCFG:FLTH values should not

exceed 2016 Bytes.

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5.6.3.11 Receive Descriptor Pointer Register (RXDP)

This register points to the current receive descriptor.

Table 5-36. Receive Descriptor Pointer Register (RXDP) Address 0030h

BIT BIT NAME DEFAULT DESCRIPTION

31:2 RXDP <0000 0000 0000 Receive Descriptor Pointer

0000 0000 0000 The current value of the receive descriptor pointer. When the receive state machine

0000 00>, R/W is idle, software must set RXDP to the address of an available receive descriptor.

While the receive state machine is active, RXDP follows the state machine as it

advances through a linked list of available descriptors. If the link field of the current

receive descriptor is NULL (signifying the end of the list), RXDP does not advance,

but remains on the current descriptor. Any subsequent writes to the RXE bit of the

CR register cause the receive state machine to reread the link field of the current

descriptor to check for new descriptors that may have been appended to the end of

the list. Software should not write to this register unless the receive state machine is

idle. Receive descriptors must be aligned on 32-bit boundaries (A1–A0 must be

zero). A 0 written to RXDP followed by a subsequent write to RXE causes the

receiver to enter silent RX mode, for use during WOL. In this mode packets are

received and buffered in FIFO, but no DMA to system memory occurs. The packet

data may be recovered from the FIFO by writing a valid descriptor address to RXDP

and then strobing RXE.

1:0 RESERVED 0, RO RESERVED

(reads return 0)

5.6.3.12 Receive Configuration Register (RXCFG)

This register is used to set the receive configuration for the DP83816 device. Receive properties such as

accepting error packets, runt packets, setting the receive drain threshold and so forth, are controlled here.

Table 5-37. Receive Configuration Register (RXCFG) Address 0034h

BIT BIT NAME DEFAULT DESCRIPTION

31 AEP 0, R/W Accept Errored Packets

When set to 1, all packets with CRC, alignment, and/or collision errors are accepted.

When set to 0, all packets with CRC, alignment, and/or collision errors are rejected if

possible. Note that depending on the type of error, some packets may be received

with errors, regardless of the setting of AEP. These errors are indicated in the

CMDSTS field of the last descriptor in the packet.

30 ARP 0, R/W Accept Runt Packets

When set to 1, all packets under 64 bytes in length without errors are accepted.

When this bit is 0, all packets less than 64 bytes in length are rejected if possible.

29 RESERVED 0, RO RESERVED

(reads return 0)

28 ATX 0, R/W Accept Transmit Packets

When set to 1, data received simultaneously to a local transmission (such as during

a PMD loopback or full duplex operation) is accepted as valid received data.

Additionally, when set to 1, the receiver ignores collision activity. When set to 0

(default), all data receive simultaneous to a local transmit is rejected. This bit must

be set to 1 for PMD loopback and full duplex operation.

27 ALP 0, R/W Accept Long Packets

When set to 1, all packets > 1518 bytes in length and <= 2046 bytes are treated as

normal receive packets, and are not tagged as long or error packets. All packets >

2046 bytes in length are truncated at 2046 bytes and either rejected from the FIFO,

or tagged as long packets. Care must be taken when accepting long packets to

ensure that buffers provided are of adequate length. When ALP is set to 0, packets

larger than 1518 bytes (CRC inclusive) are truncated at 1514 bytes and rejected if

possible.

26 RESERVED 0, RO RESERVED

(reads return 0)

25:23 RESERVED 0, RO RESERVED

(reads return 0)

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Table 5-37. Receive Configuration Register (RXCFG) Address 0034h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

22:20 MXDMA <000>, R/W Max DMA Burst Size per Rx DMA Burst

This field sets the maximum size of receive DMA data bursts according to the

following table:

000 = 128 32-bit words (512 bytes)

001 = 1 32-bit word (4 bytes)

010 = 2 32-bit words (8 bytes)

011 = 4 32-bit words (16 bytes)

100 = 8 32-bit words (32 bytes)

101 = 16 32-bit words (64 bytes)

110 = 32 32-bit words (128 bytes)

111 = 64 32-bit words (256 bytes)

19:6 RESERVED 0, RO RESERVED

(reads return 0)

5:1 DRTH <0 001>, R/W Rx Drain Threshold

Specifies the drain threshold in units of 8 bytes. When the number of bytes in the

receive FIFO reaches this value (times 8), or the FIFO contains a complete packet,

the receive bus master state machine begins the transfer of data from the FIFO to

host memory. Care must be taken when setting DRTH to a value lower than the

number of bytes needed to determine if packet should be accepted or rejected. In

this case, the packet might be rejected after the bus master operation to begin

transferring the packet into memory has begun. When this occurs, neither the OK bit

or any error status bit in the cmdsts of the descriptor is set. A value of 0 is invalid,

and the results are undefined.

This value is also used to compare with the accumulated packet length for early

receive indication. When the accumulated packet length meets or exceeds the

DRTH value, the RXEARLY interrupt condition is generated.

0 RESERVED 0, RO RESERVED

(reads return 0)

5.6.3.13 CLKRUN Control and Status Register (CCSR)

This register mirrors the read and write control of the PMESTS and PMEEN from the PCI configuration

Table 5-38. CLKRUN Control and Status Register (CCSR) Address 003Ch

BIT BIT NAME DEFAULT DESCRIPTION

31:16 RESERVED 0, RO RESERVED

(reads return 0)

15 PMESTS 0, R/W PME Status

Sticky bit which represents the state of the PME and CLKRUN logic, regardless of

the state of the PMEEN bit. Mirrored from PCI configuration register PMCSR.

Writing a 1 to this bit clears it.

14:9 RESERVED 0, RO RESERVED

(reads return 0)

8 PMEEN 0, R/W PME Enable

When set to 1, this bit enables the assertion of the PMEN/CLKRUNN pin. When 0,

the PMEN/CLKRUNN pin is forced to be inactive. This value can be loaded from

the EEPROM. Mirrored from PCI configuration register PMCSR.

7:1 RESERVED 0, RO RESERVED

(reads return 0)

0 CLKRUN_EN 0, R/W Clkrun Enable

When set to 1, this bit enables the CLKRUNN functionality of the PMEN/CLKRUNN

pin. When 0, normal PMEN functionality is active.

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5.6.3.14 Wake Command and Status Register (WCSR)

The WCSR register is used to configure and control and monitor the DP83816 WoL logic. The WoL logic

is used to monitor the incoming packet stream while in a low-power state, and provide a wake event to the

system if the desired packet type, contents, or Link change are detected.

Table 5-39. Wake Command and Status Register (WCSR) Address 0040h

BIT BIT NAME DEFAULT DESCRIPTION

31 MPR 0, R/W Magic Packet Received

Set to 1 if a Magic Packet has been detected and the WKMAG bit is set. RO,

cleared on read.

30 PATM3 0, R/W Pattern 3 match

Associated bit set to 1 if a pattern 3 match is detected and the WKPAT3 bit is set.

RO, cleared on read.

29 PATM2 0, R/W Pattern 2 match

Associated bit set to 1 if a pattern 2 match is detected and the WKPAT2 bit is set.

RO, cleared on read.

28 PATM1 0, R/W Pattern 1 match

Associated bit set to 1 if a pattern 1 match is detected and the WKPAT1 bit is set.

RO, cleared on read.

27 PATM0 0, R/W Pattern 0 match

Associated bit set to 1 if a pattern 0 match is detected and the WKPAT0 bit is set.

RO, cleared on read.

26 ARPR 0, R/W ARP Received

Set to 1 if an ARP packet has been detected and the WKARP bit is set. RO,

cleared on read.

25 BCASTR 0, R/W Broadcast Received

Set to 1 if a broadcast packet has been detected and the WKBCP bit is set. RO,

cleared on read.

24 MCASTR 0, R/W Multicast Received

Set to 1 if a multicast packet has been detected and the WKMCP bit is set. RO,

cleared on read.

23 UCASTR 0, R/W Unicast Received

Set to 1 if a unicast packet has been detected the WKUCP bit is set. RO, cleared

on read.

22 PHYINT 0, R/W PHY Interrupt

Set to 1 if a PHY interrupt was detected and the WKPHY bit is set. RO, cleared on

read.

21 RESERVED 0, RO RESERVED

(reads return 0)

20 SOHACK 0, R/W SecureOn Hack Attempt

Set to 1 if the MPSOE and WKMAG bits are set, and a Magic Packet is receive

with an invalid SecureOn password value. RO, Cleared on read.

19:11 RESERVED 0, RO RESERVED

(reads return 0)

10 MPSOE 0, R/W Magic Packet SecureOn Enable

Enable Magic Packet SecureOn feature. Only applicable when bit 9 is set.

9 WKMAG 0, R/W Wake on Magic Packet

Enable wake on Magic Packet detection.

8 WKPAT3 0, R/W Wake on Pattern 3 match

Enable wake on match of pattern 3.

7 WKPAT2 0, R/W Wake on Pattern 2 match

Enable wake on match of pattern 2.

6 WKPAT1 0, R/W Wake on Pattern 1 match

Enable wake on match of pattern 1.

5 WKPAT0 0, R/W Wake on Pattern 0 match

Enable wake on match of pattern 0.

4 WKARP 0, R/W Wake on ARP

Enable wake on ARP packet detection.

3 WKBCP 0, R/W Wake on Broadcast

Enable wake on broadcast packet detection.

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Table 5-39. Wake Command and Status Register (WCSR) Address 0040h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

2 WKMCP 0, R/W Wake on Multicast

Enable wake on multicast packet detection.

1 WKUCP 0, R/W Wake on Unicast

Enable wake on unicast packet detection.

0 WKPHY 0, R/W Wake on PHY Interrupt

Enable wake on PHY Interrupt. The PHY interrupt can be programmed for Link

Change and a variety of other Physical Layer events.

5.6.3.15 Pause Control and Status Register (PCR)

The PCR register is used to control and monitor the DP83816 pause-frame reception logic. The pause-

frame reception logic is used to accept 802.3x pause frames, extract the pause length value, and initiate a

TX MAC pause interval of the specified number of slot times.

Table 5-40. Pause Control and Status Register (PCR) Address 0044h

BIT BIT NAME DEFAULT DESCRIPTION

31 PSEN 0, R/W Pause Enable

Manually enables reception of 802.3x pause frames This bit is ORed with the

PSNEG bit to enable pause reception. If pause reception has been enabled via

PSEN bit (PSEN = 1), setting this bit to 0 causes any active pause interval to be

terminated.

30 PS_MCAST 0, R/W Pause on Multicast

When set to 1, this bit enables reception of 802.3x pause frames which use the

802.3x designated multicast address in the DA (01-80-C2-00-00-01). When this

mode is enabled, the RX filter logic performs a perfect match on the above

multicast address. No other address filtration modes (including multicast hash) are

required for pause frame reception.

29 PS_DA 0, R/W Pause on DA

When set to 1, this bit enables reception of a pause frame based on a DA match

with either the perfect match register, or one of the pattern match buffers.

28:24 RESERVED 0, RO RESERVED

(reads return 0)

23 PS_ACT 0, RO Pause Active

This bit is set to a 1 when the TX MAC logic is actively timing a pause interval.

22 PS_RCVD 0, RO Pause Frame Received

This bit is set to a 1 when a pause frame has been received. This bit remains set

until the TX MAC has completed the pause interval.

21 PSNEG 0, RO Pause Negotiated

Status bit indicating that the 802.3x pause function has been enabled via auto-

negotiation. This bit is only set if the DP83816 device advertises pause capable by

setting bit 16 in the CFG register.

20:17 RESERVED 0, RO RESERVED

(reads return 0)

16 MLD_EN 0, WO Manual Load Enable

Setting this bit to 1 causes the value of bits 15–0 to be written to the pause count

This bit is not sticky, and reads always return 0.

15:0 PAUSE_CNT <0000 0000 0000 Pause Counter Value

0000>, R/W READ: These bits represent the current real-time value of the TX MAC pause

counter register.

WRITE: If no pause count interval is in progress (PS_RCVD=0, PS_ACT=0), and

MLD_EN=1 this value is written to the pause count register, and causes pause

count interval to be manually initiated.

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5.6.3.16 Receive Filter and Match Control Register (RFCR)

The RFCR register is used to control and configure the DP83816 receive-filter control logic. The receive-

filter control logic is used to configure destination address filtering of incoming packets.

Table 5-41. Receive Filter and Match Control Register (RFCR) Address 0048h

BIT BIT NAME DEFAULT DESCRIPTION

31 RFEN 0, R/W Rx Filter Enable

When this bit is set to 1, the Rx Filter is enabled to qualify incoming packets. When

set to a 0, receive packet filtering is disabled (that is, all receive packets are

rejected). This bit must be 0 for the other bits in this register to be configured.

30 AAB 0, R/W Accept All Broadcast

When set to a 1, this bit causes all broadcast address packets to be accepted.

When set to 0, no broadcast address packets are accepted.

29 AAM 0, R/W Accept All Multicast

When set to a 1, this bit causes all multicast address packets to be accepted. When

set to 0, multicast destination addresses must have the appropriate bit set in the

multicast hash table mask in order for the packet to be accepted.

28 AAU 0, R/W Accept All Unicast

When set to a 1, this bit causes all unicast address packets to be accepted. When

set to 0, the destination address must match the node address value specified

through some other means in order for the packet to be accepted.

27 APM 0, R/W Accept on Perfect Match

When set to 1, this bit allows the perfect match register to be used to compare

against the DA for packet acceptance. When this bit is 0, the perfect match register

contents are not used for DA comparison.

26:23 APAT <000 0>, R/W Accept on Pattern Match

When one or more of these bits is set to 1, a packet is accepted if the first n bytes (n

is the value defined in the associated pattern count register) match the associated

pattern buffer memory contents. When a bit is set to 0, the associated pattern buffer

is not used for packet acceptance.

22 AARP 0, R/W Accept ARP Packets

When set to 1, this bit allows all ARP packets (packets with a TYPE and LEN field

set to 806h) to be accepted, regardless of the DA value. When set to 0, ARP

packets are treated as normal packets and must meet other DA match criteria for

acceptance.

21 MHEN 0, R/W Multicast Hash Enable

When set to 1, this bit allows hash table comparison for multicast addresses; that is,

a hash table hit for a multicast-addressed packet is accepted. When set to 0,

multicast hash hits are not used for packet acceptance.

20 UHEN 0, R/W Unicast Hash Enable

When set to 1, this bit allows hash table comparison for unicast addresses; that is, a

hash table hit for a unicast addressed packet is accepted. When set to 0, unicast

hash hits are not used for packet acceptance.

19 ULM 0, R/W U/L bit Mask

When set to 1, this bit causes the U/L bit (2nd MSb) of the DA to be ignored during

comparison with the perfect match register.

18:10 RESERVED 0, RO RESERVED

(reads return 0)

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Table 5-41. Receive Filter and Match Control Register (RFCR) Address 0048h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

9:0 RFADDR <00 0000 0000>, R/W Receive Filter Extended Register Address

Selects which internal receive filter register is accessible via RFDR:

Perfect Match Register (PMATCH)

000h - PMATCH octets 1-0

002h - PMATCH octets 3-2

004h - PMATCH octets 5-4

Pattern Count Registers (PCOUNT)

006h - PCOUNT1, PCOUNT0

008h - PCOUNT3, PCOUNT2

SecureOn Password Register (SOPAS)

00Ah - SOPAS octets 1-0

00Ch - SOPAS octets 3-2

00Eh - SOPAS octets 5-4

Filter Memory

200h-3FE - Rx filter memory (Hash table and pattern buffers)

5.6.3.17 Receive Filter and Match Data Register (RFDR)

The RFDR register is used for reading from and writing to the internal receive filter registers, the pattern

buffer memory, and the hash table memory.

Table 5-42. Receive Filter and Match Data Register (RFDR) Address 004Ch

BIT BIT NAME DEFAULT DESCRIPTION

31:18 RESERVED 0, RO RESERVED

(reads return 0)

17:16 BMASK <00>, R/W Byte mask

Used as byte mask values for pattern match template data.

15:0 RFDATA <0000 0000 0000 Receive Filter Data

0000>, R/W

5.6.3.18 Boot ROM Address Register (BRAR)

The BRAR is used to set up the address for an access to an external ROM and FLASH device.

Table 5-43. Boot ROM Address Register (BRAR) Address 0050h

BIT BIT NAME DEFAULT DESCRIPTION

31 AUTOINC 1, R/W Auto-Increment

When set, the contents of ADDR auto-increment with every 32-bit access to the

BRDR register.

30:16 RESERVED 0, RO RESERVED

(reads return 0)

15:0 ADDR <1111 1111 1111 Boot ROM Address

1111>, R/W 16-bit address used to access the external Boot ROM.

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5.6.3.19 Boot ROM Data Register (BRDR)

The BRDR is used to read and write ROM and FLASH data from the data from/to an external ROM and

FLASH device.

Table 5-44. Boot ROM Data Register (BRDR) Address 0054h

BIT BIT NAME DEFAULT DESCRIPTION

31:0 DATA 0, R/W Boot ROM Data

Access port to external Boot ROM. Software can use BRAR and BRDR to read (and write if

FLASH memory is used) the external Boot ROM. All accesses must be 32-bits wide and

aligned on 32-bit boundaries.

5.6.3.20 Silicon Revision Register (SRR)

Table 5-45. Silicon Revision Register (SRR) Address 0058h

BIT BIT NAME DEFAULT DESCRIPTION

31:16 RESERVED 0, RO RESERVED

(reads return 0)

15:0 ADDR <0000 0101 0000 Revision Level

0101>, RO SRR register value for the DP83816 silicon.

Hex: DP83816AVNG 00000505h

5.6.3.21 Management Information Base Control Register (MIBC)

The MIBC register is used to control access to the statistics block and the warning bits and to control the

collection of management information statistics.

Table 5-46. Management Information Base Control Register (MIBC) Address 005ch

BIT BIT NAME DEFAULT DESCRIPTION

31:4 RESERVED 0, RO RESERVED

(reads return 0)

3 MIBS 0, R/W MIB Counter Strobe

Writing a 1 to this bit location causes the counters in all enabled blocks to increment by 1,

providing a single-step test function. The MIBS bit is always read back as 0. This bit is

used for test purposes only and should be set to 0 for normal counter operation.

2 ACLR 0, WO Clear all counters

When set to a 1, this bit forces all counters to be reset to 0. This bit is always read back as

1 FRZ 1, R/W Freeze all counters

When set to a 1, this bit forces count values to be frozen such that a read of the statistic

block represents management statistics at a given instant in time. When set to 0, the

counters increment normally and may be read individually while counting. While frozen,

events are not recorded.

0 WRN 0, RO Warning Test Indicator

This field is read only. This bit is set to 1 when statistic counters have reached their

respective overflow warning condition. WRN is cleared after one or more of the statistic

counters have been cleared.

5.6.3.22 Management Information Base Registers

The counters provide a set of statistics compliant with the following management specifications: MIB II,

Ether-like MIB, and IEEE MIB. The values provided are accessed through the various registers as shown

below. All MIB counters are cleared to 0 when read.

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Due to cost and space limitations, the counter bit widths provided in the DP83816 MIB are less than the

bit widths called for in the above specifications. It is assumed that management agent software maintains

a set of fully compliant statistic values (software counters), utilizing the hardware counters to reduce the

frequency at which these software counters must be updated. Sizes for specific hardware statistic

counters were chosen such that the count values do not roll over in less than 15 ms if incremented at the

theoretical maximum rates described in the above specifications. However, given that the theoretical

maximum counter rates do not represent realistic network traffic and events, the actual rollover rates for

the hardware counters are more likely to be on the order of several seconds. The hardware counters are

updated automatically by the MAC on the occurrence of each event.

Table 5-47. MIB Registers

WARNING

OFFSET TAG SIZE DESCRIPTION

(MS BITS)

0060h RXErroredPkts 16 8 Packets received with errors. This counter is incremented for each packet

received with errors. This count includes packets which are automatically

rejected from the FIFO due to both wire errors and FIFO overruns.

0064h RXFCSErrors 8 4 Packets received with frame check sequence errors. This counter is

incremented for each packet received with a Frame Check Sequence error

(bad CRC).

Note: For the MII interface, an FCS error is defined as a resulting invalid CRC

after CRS goes invalid and an even number of bytes have been received.

0068h RXMsdPktErrors 8 4 Packets missed due to FIFO overruns. This counter is incremented for each

receive aborted due to data or status FIFO overruns (insufficient buffer space).

006Ch RXFAErrors 8 4 Packets received with frame alignment errors. This counter is incremented for

each packet received with a Frame Check Sequence error (bad CRC).

Note: For the MII interface, an FAE error is defined as a resulting invalid CRC

on the last full octet, and an odd number of nibbles have been received

(Dribble nibble condition with a bad CRC).

0070h RXSymbolErrors 8 4 Packets received with one or more symbol errors. This counter is incremented

for each packet received with one or more symbol errors detected.

Note: For the MII interface, a symbol error is indicated by the RXER signal

becoming active for one or more clocks while the RXDV signal is active (during

valid data reception).

0074h RXFrameTooLon 4 2 Packets received with length greater than 1518 bytes (too long packets). This

g counter is incremented for each packet received with greater than the 802.3

standard maximum length of 1518 bytes.

0078h TXSQEErrors 4 2 Loss of collision heartbeat during transmission. This counter is incremented

when the collision heartbeat pulse is not detected by the PMD after a

transmission.

5.6.4 Internal PHY Registers

The Internal PHY registers are only 16 bits wide. Bits [31:16] are not used. In the following register

definitions under the default heading, the following definitions hold true:

• R/W = Read/write access

• RO = Read-only access

• LL = Latched low and held until read, based on the occurrence of the corresponding event

• LH = Latched high and held until read, based on the occurrence of the corresponding event

• SC = Register sets on event occurrence and self-clears when event ends

• P = Register bit is permanently set to a default value

• COR = Clear on read

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5.6.4.1 Basic Mode Control Register (BMCR)

Table 5-48. Basic Mode Control Register (BMCR) Address 0080h

BIT BIT NAME DEFAULT DESCRIPTION

15 Reset 0, R/W Reset: Default: 0, R/W / SC

1 = Initiate software Reset / Reset in Process

0 = Normal operation

This self-clearing bit returns a value of one until the reset process is complete. A reset causes all

PHY registers to return to their default values (in some cases registers defaults are defined by

related bits in the CFG register, offset 04h).

14 Loopback 0, R/W Loopback: Default: 0

1 = Loopback enabled

0 = Normal operation

The loopback function enables MII transmit data to be routed to the MII receive data path.

Setting this bit may cause the de-scrambler to lose synchronization and produce a 500 µs dead

time before any valid data appears at the MII receive outputs.

13 Speed Selection 0, R/W Speed Select: Default: dependent on the setting of the ANEG_SEL bits in the CFG register

When auto-negotiation is disabled writing to this bit allows the port speed to be selected.

1 = 100 Mb/s

0 = 10 Mb/s

12 Auto- 0, R/W Auto-Negotiation Enable: Default: dependent on the setting of the ANEG_SEL bits in the CFG

Negotiation register

Enable 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode.

11 Power Down 0, R/W Power Down: Default: 0

1 = Power down

0 = Normal operation

Setting this bit powers down the port.

10 Isolate 0, R/W Isolate: Default: 0

1 = Isolates the port from the MII with the exception of the serial management.

0 = Normal operation

9 Restart Auto- 0, R/W Restart Auto-Negotiation: Default: 0, R/W / SC

Negotiation 1 = Restart Auto-Negotiation

0 = Normal operation

When this bit is set, it re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit

12 =0), this bit is ignored. This bit is self-clearing and retains a value of 1 until auto-negotiation is

initiated, whereupon it self-clears. Operation of the Auto-Negotiation process is not affected by the

management entity clearing this bit.

8 Duplex Mode 0, R/W Duplex Mode: Default: dependent on the setting of the ANEG_SEL bits in the CFG register.

When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected.

1 = Full Duplex operation

0 = Half Duplex operation

7 Collision Test 0, R/W Collision Test: Default: 0

1 = Collision test enabled

0 = Normal operation

When set, this bit causes the COL signal to be asserted in response to the assertion of TXEN within

512-bit times. The COL signal is de-asserted within 4-bit times in response to the de-assertion of

TXEN.

6:0 RESERVED 0, RO RESERVED

(reads return 0)

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5.6.4.2 Basic Mode Status Register (BMSR)

Table 5-49. Basic Mode Status Register (BMSR) Address 0084h

BIT BIT NAME DEFAULT DESCRIPTION

15 100BASE-T4 <7849h>, RO 100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.

14 100BASE-TX Full 1, RO 100BASE-TX Full Duplex Capable:

Duplex 1 = Device able to perform 100BASE-TX in full duplex mode

13 100BASE-TX Half 1, RO 100BASE-TX Half Duplex Capable:

Duplex 1 = Device able to perform 100BASE-TX in half duplex mode.

12 10BASE-T Full 1, RO 10BASE-T Full Duplex Capable:

Duplex 1 = Device able to perform 10BASE-T in full duplex mode

11 10BASE-T Half 1, RO 10BASE-T Half Duplex Capable:

Duplex 1 = Device able to perform 10BASE-T in half duplex mode

10:7 RESERVED 0, RO RESERVED

(reads return 0)

6 Preamble 1, RO Preamble suppression Capable:

Suppression 1 = Device able to perform management transaction with preamble suppressed, 32-bits of

preamble needed only once after reset, invalid opcode or invalid turnaround.

0 = Normal management operation

5 Auto- Negotiation 0, RO Auto-Negotiation Complete:

Complete 1 = Auto-Negotiation process complete

0 = Auto-Negotiation process not complete

4 Remote Fault 0, LH Remote Fault:

1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End

Fault Indication or notification from Link Partner of Remote Fault.

0 = No remote fault condition detected

3 Auto- Negotiation 1, RO Auto Configuration Ability:

Ability 1 = Device is able to perform Auto-Negotiation

0 = Device is not able to perform Auto-Negotiation

2 Link Status 0, LL Link Status:

1 = Valid link established (for either 10- or 100-Mb/s operation)

0 = Link not established

The criteria for link validity is implementation specific. The occurrence of a link failure

condition causes the Link Status bit to clear. When cleared, this bit may only be set by

establishing a good link condition and a read via the management interface.

1 Jabber Detect 0, LH Jabber Detect:

1 = Jabber condition detected

0 = No Jabber

This bit is implemented with a latching function, such that the occurrence of a jabber

condition causes it to set until it is cleared by a read to this register by the management

interface or by a reset.

This bit only has meaning in 10-Mb/s mode.

0 Extended Capability 1, RO Extended Capability:

1 = Extended register capabilities

0 = Basic register set capabilities only

5.6.4.3 PHY Identifier Register No. 1 (PHYIDR1)

The PHY identifier registers No. 1 and No. 2 together form a unique identifier for the PHY section of this

device. The identifier consists of a concatenation of the organizationally unique identifier (OUI), the vendor

model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of

the PHY Identifier if desired. The PHY Identifier is intended to support network management. Texas

Instruments' IEEE-assigned OUI is 080017h.

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Table 5-50. PHY Identifier Register No. 1 (PHYIDR1) Address 0088h

BIT BIT NAME DEFAULT DESCRIPTION

15:0 OUI_MSB <0010 0000 0000 OUI Most-Significant Bits:

0000> , RO Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most-

significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and

2).

5.6.4.4 PHY Identifier Register No. 2 (PHYIDR2)

Table 5-51. PHY Identifier Register No. 2 (PHYIDR2) Address 008Ch

BIT BIT NAME DEFAULT DESCRIPTION

15:10 OUI_LSB <01 0111>, RO OUI Least-Significant Bits:

Bits 19 to 24 of the OUI (080017h) are mapped to bits 15 to 10 of this register respectively.

9:4 VNDR_MDL <00 0010> , RO Vendor Model Number:

The six bits of vendor model number are mapped to bits 9 to 4 (most-significant bit to bit 9).

3:0 mdl_rev <0001>, RO Model Revision Number:

Four bits of the vendor model revision number are mapped to bits 3 to 0 (most-significant bit

to bit 3). This field is incremented for all major device changes.

5.6.4.5 Auto-Negotiation Advertisement Register (ANAR)

This register contains the advertised abilities of this device as they are transmitted to its link partner during

auto-negotiation.

Table 5-52. Auto-Negotiation Advertisement Register (ANAR) Address 0090h

BIT BIT NAME DEFAULT DESCRIPTION

15 NP 0, R/W Next Page Indication:

0 = Next Page Transfer not desired

1 = Next Page Transfer desired

14 RESERVED 0, RO Reserved by IEEE: Writes ignored, Read as 0

13 RF 0, R/W Remote Fault:

1 = Advertises that this device has detected a Remote Fault

0 = No Remote Fault detected

12:11 RESERVED 0, RO Reserved for Future IEEE use: Write as 0, Read as 0

10 PAUSE 0, R/W PAUSE:

1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer

and the pause function as specified in clause 31 and annex 31B of 802.3u.

0 = No MAC based full duplex flow control

9 T4 0, RO 100BASE-T4 Support:

1= 100BASE-T4 is supported by the local device

0 = 100BASE-T4 not supported

8 TX_FD 1, R/W 100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the local device

0 = 100BASE-TX Full Duplex not supported

7 TX_HD 1, R/W 100BASE-TX Support:

1 = 100BASE-TX is supported by the local device

0 = 100BASE-TX not supported

6 10_FD 1. R/W 10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the local device

0 = 10BASE-T Full Duplex not supported

5 10_HD 1, R/W 10BASE-T Support:

1 = 10BASE-T is supported by the local device

0 = 10BASE-T not supported

4:0 Selector <0 0001>, RO Protocol Selection Bits:

These bits contain the binary encoded protocol selector supported by this port.

<00001> indicates that this device supports IEEE 802.3u.

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5.6.4.6 Auto-Negotiation Link Partner Ability Register (ANLPAR)

This register contains the advertised abilities of the link partner as received during auto-negotiation. The

content changes after the successful auto-negotiation if next-pages are supported.

Table 5-53. Auto-Negotiation Link Partner Ability Register (ANLPAR) Address 0094h

BIT BIT NAME DEFAULT DESCRIPTION

15 NP 0, RO Next Page Indication:

0 = Link Partner does not desire Next Page Transfer

1 = Link Partner desires Next Page Transfer

14 ACK 0, RO Acknowledge:

1 = Link Partner acknowledges reception of the ability data word

0 = Not acknowledged

The auto-negotiation state machine of the device automatically controls this bit based on the

incoming FLP bursts.

13 RF 0, RO Remote Fault:

1 = Remote Fault indicated by Link Partner

0 = No Remote Fault indicated by Link Partner.

12:10 RESERVED 0, RO Reserved for Future IEEE use: Write as 0, Read as 0

9 T4 0, RO 100BASE-T4 Support:

1= 100BASE-T4 is supported by the Link Partner

0 = 100BASE-T4 not supported by the Link Partner

8 TX_FD 0, RO 100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported b the Link Partner

0 = 100BASE-TX Full Duplex not supported by the Link Partner

7 TX_HD 0, RO 100BASE-TX Support:

1 = 100BASE-TX is supported by the Link Partner

0 = 100BASE-TX not supported by the Link Partner

6 10_FD 0, RO 10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the local device

0 = 10BASE-T Full Duplex not supported

5 10_HD 0, RO 10BASE-T Support:

1 = 10BASE-T is supported by the Link Partner

0 = 10BASE-T not supported by the Link Partner

4:0 Selector 0, RO Protocol Selection Bits:

Link Partners’s binary encoded protocol selector.

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5.6.4.7 Auto-Negotiate Expansion Register (ANER)

This register contains additional local device and link partner status information.

Table 5-54. Auto-Negotiate Expansion Register (ANER) Address 0098h

BIT BIT NAME DEFAULT DESCRIPTION

15:5 RESERVED 0, RO RESERVED

(reads return 0)

4 PDF 0, RO Parallel Detection Fault:

1 = A fault has been detected via the Parallel Detection function

0 = A fault has not been detected

3 LLP_NP_ABLE 0, RO Link Partner Next Page Able:

1 = Link Partner does support Next Page

0 = Link Partner does not support Next Page.

2 NP_ABLE 1, RO Next Page Able:

1 = Indicates local device is able to send additional “Next Pages”

1 PAGE_RX 0, RO/COR Link Code Word Page Received:

1= Link Code Word has been received, cleared on a read

0 = Link Code Word has not been received

0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able:

1 = Indicates that the Link Partner supports Auto-Negotiation

0 = Indicates that the Link Partner does not support Auto-Negotiation

5.6.4.8 Auto-Negotiation Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its link partner during auto-

negotiation.

Table 5-55. Auto-Negotiation Next Page Transmit Register (ANNPTR) Address 009Ch

BIT BIT NAME DEFAULT DESCRIPTION

15 NP 0, RO Next Page Indication:

1 = No other next-page transfer desired

0 = Another next-page desired

14 RESERVED 0, RO RESERVED

(reads return 0)

13 MP 1, RO Message Page:

1 = Message Page

0 = Unformatted Page

12 ACK2 0, RO Acknowledge2:

1 = Will comply with message

0 = Cannot comply with message

11 TOG_TX 0, RO Toggle:

1= Value of toggle bit in previously transmitted Link Code Word was 0

0 = Value of toggle bit in previously transmitted Link Code Word was 1

Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization

with the Link Partner during Next Page exchange. This bit shall always take the opposite value

of the Toggle bit in the previously exchanged Link Code Word.

10:0 CODE <000 0000 Code Field:

0001>, RO This field represents the code field of the next page transmission. If the MP bit is set (bit 13

of this register), then the code shall be interpreted as a Message Page, as defined in annex

28C of IEEE 802.3u. Otherwise, the code shall be interpreted as an Unformatted Page, and

the interpretation is application-specific.

The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE

802.3u.

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5.6.4.9 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed

information.

Table 5-56. PHY Status Register (PHYSTS) Address 00C0h

BIT BIT NAME DEFAULT DESCRIPTION

15:14 RESERVED 0, RO RESERVED

(reads return 0)

13 Receive Error 0, RO Receive Error Latch:

Latch This bit is cleared on a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT (address 0xD4)

0 = No receive error event has occurred

12 Polarity 0, RO Polarity Status:

Status This bit is a duplication of bit 4 in the TBTSCR register. This bit is cleared on a read of the

TBTSCR register, but not on a read of the PHYSTS register.

1 = Inverted Polarity detected

0 = Correct Polarity detected

11 False Carrier 0, RO/LH False Carrier Sense Latch:

Sense Latch This bit is cleared on a read of the FCSCR register.

1 = False Carrier event has occurred since last read of FCSCR (address 0xD0)

0 = No False Carrier event has occurred

10 Signal Detect 0, RO/LL Signal Detect:

100BASE-TX unconditional Signal Detect from PMD.

9 De-scrambler 0, RO/LL De-scrambler Lock:

Lock 100BASE-TX De-scrambler Lock from PMD.

8 Page 0, RO Link Code Word Page Received:

Received This is a duplicate of the Page Received bit in the ANER register, but this bit is not cleared

on a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address

0x98, bit 1)

0 = Link Code Word Page has not been received

7 MII Interrupt 0, RO/LH MII Interrupt Pending

1 = Indicates that an internal interrupt is pending, cleared by the current read

0 = No interrupt pending

6 Remote Fault 0, RO Remote Fault: 1 = Remote Fault condition detected (cleared on read of BMSR (address

0x84) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via

Auto-Negotiation

0 = No remote fault condition detected

5 Jabber 0, RO Jabber Detect: This bit only has meaning in 10-Mb/s mode

Detect This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not

cleared on a read of the PHYSTS register.

1 = Jabber condition detected

0 = No Jabber

4 Auto-Neg. 0, RO Auto-Negotiation Complete:

Complete 1 = Auto-Negotiation complete

0 = Auto-Negotiation not complete

3 Loopback 0, RO Loopback:

Status 1 = Loopback enabled

0 = Normal operation

2 Duplex 0, RO Duplex:

Status This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes.

1 = Full duplex mode

0 = Half duplex mode

Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid

link or if Auto-Negotiation is disabled and there is a valid link.

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Table 5-56. PHY Status Register (PHYSTS) Address 00C0h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

1 Speed Status 0, RO Speed10:

This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced

Modes.

1 = 10-Mb/s mode

0 = 100-Mb/s mode

Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid

link or if Auto-Negotiation is disabled and there is a valid link.

0 Link Status 0, RO Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register, except that it is not cleared

on a read of the PHYSTS register.

1 = Valid link established (for either 10- or 100-Mb/s operation)

0 = Link not established

5.6.4.10 MII Interrupt Control Register (MICR)

This register implements the MII interrupt PHY specific control register. Sources for interrupt generation

include: link state change, jabber event, remote fault, auto-negotiation complete or any of the counters

becoming half-full. Note that the TINT bit operates independently of the INTEN bit. In other words, INTEN

does not need to be active to generate the test interrupt.

Table 5-57. MII Interrupt Control Register (MICR) Address 00C4h

BIT BIT NAME DEFAULT DESCRIPTION

15:2 RESERVED 0, RO RESERVED

(reads return 0)

1 INTEN 0, R/W Interrupt Enable:

1 = Enable event based interrupts

0 = Disable event based interrupts

0 TINT 0, R/W Test Interrupt:

Forces the PHY to generate an interrupt at the end of each management read to facilitate

interrupt testing.

1 = Generate an interrupt

0 = Do not generate interrupt

5.6.4.11 MII Interrupt Status and Misc. Control Register (MISR)

This register implements the MII interrupt PHY control and status information. These interrupts are PHY

based events. When any of these events occurs and its respective bit is not masked, and MICR:INTEN is

enabled, the interrupt is signaled in ISR:PHY.

Table 5-58. Register Description

BIT BIT NAME DEFAULT DESCRIPTION

15 MINT 0, RO/COR MII Interrupt Pending:

1 = Indicates that an interrupt is pending and is cleared by the current read.

0 = no interrupt pending

14 MSK_LINK 0, R/W Mask Link: When this bit is 0, the change of link status event causes the interrupt to be

seen by the ISR.

13 MSK_JAB 0, R/W Mask Jabber: When this bit is 0, the Jabber event causes the interrupt to be seen by the

ISR.

12 MSK_RF 0, R/W Mask Remote Fault: When this bit is 0, the Remote Fault event causes the interrupt to be

seen by the ISR.

11 MSK_ANC 0, R/W Mask Auto-Neg. Complete: When this bit is 0, the Auto-negotiation complete event causes

the interrupt to be seen by the ISR.

10 MSK_FHF 0, R/W Mask False Carrier Half Full: When this bit is 0, the False Carrier Counter Register half-full

event causes the interrupt to be seen by the ISR.

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Table 5-58. Register Description (continued)

BIT BIT NAME DEFAULT DESCRIPTION

9 MSK_RHF 0, R/W Mask Rx Error Half Full: When this bit is 0, the Receive Error Counter Register half-full

events cause the interrupt to be seen by the ISR.

8:0 RESERVED 0, RO RESERVED

(reads return 0)

5.6.4.12 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the FalseCarriers attribute within the MAU

managed object class of Clause 30 of the IEEE 802.3u specification.

Table 5-59. False Carrier Sense Counter Register (FCSCR) Address 00D0h

BIT BIT NAME DEFAULT DESCRIPTION

15:8 RESERVED 0, RO RESERVED

(reads return 0)

7:0 FCSCNT[7:0] <0000 0000>, False Carrier Event Counter:

R/W / COR This 8-bit counter increments on every false carrier event. This counter sticks when it reaches

its max count (FFh).

5.6.4.13 Receiver Error Counter Register (RECR)

This counter provides information required to implement the SymbolErrorDuringCarrier attribute within the

PHY managed object class of Clause 30 of the IEEE 802.3u specification.

Table 5-60. Receiver Error Counter Register (RECR) Address 00D4h

BIT BIT NAME DEFAULT DESCRIPTION

15:8 RESERVED 0, RO RESERVED

(reads return 0)

7:0 RXERCNT[7:0] <0000 0000>, RXER Counter:

R/W / COR This 8-bit counter increments for each receive error detected. when a valid carrier is present

and there is at least one occurrence of an invalid data symbol. This event can increment

only once per valid carrier event. If a collision is present, the attribute does not increment.

The counter sticks when it reaches its max count.

5.6.4.14 100-Mb/s PCS Configuration and Status Register (PCSR)

Table 5-61. 100-Mb/s PCS Configuration and Status Register (PCSR) Address 00D8h

BIT BIT NAME DEFAULT DESCRIPTION

15:13 RESERVED 0, RO RESERVED

(reads return 0)

12 BYP_4B5B 0, R/W Bypass 4B/5B Encoding:

1 = 4B5B encoder functions bypassed

0 = Normal 4B5B operation

11 FREE_CLK 0, R/W Receive Clock:

1 = RX_CK is free-running

0 = RX_CK phase adjusted based on alignment

10 TQ_EN 0, R/W 100-Mb/s True-Quiet Mode Enable:

1 = Transmit True Quiet Mode

0 = Normal Transmit Mode

9 SD_FORCE_B 0, R/W Signal Detect Force:

1 = Forces Signal Detection

0 = Normal SD operation

8 SD_OPTION 0, R/W Signal Detect Option:

1 = Enhanced signal detect algorithm

0 = Reduced signal detect algorithm

7:6 RESERVED 0, RO RESERVED

(reads return 0)

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Table 5-61. 100-Mb/s PCS Configuration and Status Register (PCSR) Address 00D8h (continued)

BIT BIT NAME DEFAULT DESCRIPTION

5 FORCE_100_OK 0, R/W Force 100-Mb/s Good Link:

1 = Forces 100-Mb/s good link

0 = Normal 100-Mb/s operation

4:3 RESERVED 0, RO RESERVED

(reads return 0)

2 NRZI_BYPASS 0, R/W NRZI Bypass Enable:

1 = NRZI Bypass Enabled

0 = NRZI Bypass Disabled

1:0 RESERVED 0, RO RESERVED

(reads return 0)

5.6.4.15 PHY Control Register (PHYCR)

Table 5-62. PHY Control Register (PHYCR) Address 00E4h

BIT BIT NAME DEFAULT DESCRIPTION

15:12 RESERVED 0, RO RESERVED

(reads return 0)

11 PSR_15 0, R/W BIST Sequence select: Selects length of LFSR used in BIST

1 = PSR15 selected

0 = PSR9 selected

10 BIST_STATUS 0, R/W BIST Test Status: Default: 0, LL/RO

1 = BIST pass

0 = BIST fail. Latched, cleared by write to BIST start bit.

9 BIST_START 0, R/W BIST Start: BIST runs continuously until stopped. Minimum time to run should be 1 ms.

1 = BIST start

0 = BIST stop

8 BP_STRETCH 0, R/W Bypass LED Stretching:

This bypasses the LED stretching, and the LEDs reflect the internal value.

1 = Bypass LED stretching

0 = Normal operation

7 PAUSE_STS 0, RO Pause Compare Status:

0 = Local Device and the Link Partner are not Pause capable

1 = Local Device and the Link Partner are both Pause capable

6:5 RESERVED 0, RO RESERVED

(reads return 0)

4:0 PHYADDR[4:0] <1 1111>, R/W PHY Address: PHY address for the port.

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5.6.4.16 10BASE-T Status and Control Register (TBTSCR)

Table 5-63. 10BASE-T Status and Control Register (TBTSCR) Address 00E8h

BIT BIT NAME DEFAULT DESCRIPTION

15:9 RESERVED <0000 10>, RESERVED

R/W

8 LOOPBACK_10_DIS 0, R/W 10BASE-T Loopback Disable:

This bit is ORed with bit 14 (Loopback) in the BMCR.

1 = 10-Mb/s loopback is enabled

0 = 10-Mb/s loopback is disabled

7 LP_DIS 0, R/W Normal Link Pulse Disable:

1 = Transmission of NLPs is disabled

0 = Transmission of NLPs is enabled

6 FORCE_LINK_10 0, R/W Force good 10-Mb/s link

1 = Forced good 10-Mb/s link

0 = Normal link status

5 FORCE_POL_COR 0, R/W Force 10-Mb/s polarity correction:

1 = Force inverted polarity

0 = Normal polarity

4 POLARITY 0, R/W 10 Mb/s polarity status: RO/LH

This bit is a duplication of bit 12 in the PHYSTS register. Both bits are cleared on a

read of either register.

1 = Inverted Polarity detected

0 = Correct Polarity detected

3 AUTOPOL_DIS 0, R/W Auto Polarity Detection & Correction Disable:

1 = Polarity Sense & Correction disabled

0 = Polarity Sense & Correction enabled

2 RESERVED 1, RO RESERVED: This bit must be written as a one.

1 HEARTBEAT_DIS 0, R/W Heartbeat disable: This bit only has influence in half-duplex 10-Mb/s mode.

1 = Heartbeat function disabled

0 = Heartbeat function enabled

When the device is operating at 100 Mb/s or configured for full-duplex, this bit is

ignored – the heartbeat function is disabled.

0 JABBER_DIS 0, R/W Jabber disable:

Applicable only in 10BASE-T Full Duplex.

1 = Jabber function disabled

0 = Jabber function enabled

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DP83816PCI Bus Controller PCI

Clock Status

LED

EEPROM ROM/

Flash

Device

Magenetics

10BASE-T

100BASE-TX

RJ45

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6 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

6.1 Application Information

The DP83816 device is a MAC layer integrated with a physical layer Ethernet transceiver. Typical

operating voltage is 3.3 V with power consumption less than 500 mW. When using the device for Ethernet

applications, it is necessary to meet certain requirements for normal operation of the DP83816 device.

The following typical application and design requirements can be used for selecting appropriate

component values for the DP83816 device.

6.2 Typical Application

Figure 6-1. Typical Application Schematic

6.2.1 Design Requirements

The design requirements for the DP83816 device are:

• VIN = 3.3 V

• VOUT = VCC – 0.5 V

• Clock Input = 25 MHz

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1:1

1:1 RJ45

RD-

RD+

TD-

TD+

0.1PF*

PF*

0.1 PF

Vdd

49.9 :

TPRDM

TDRDP

TPTDM

TPTDP

0.1

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6.2.1.1 TPI Network Circuit

Figure 6-2 shows the recommended circuit for a 10/100-Mb/s twisted pair interface. Following is a partial

list of recommended transformers. It is important that the user realize that variations with PCB and

component characteristics require that the application be tested to ensure that the circuit meets the

requirements of the intended application.

• Pulse H1102

• Pulse H2019

• Pulse J0011D21

• Pulse J0011D21B

* Place capacitors close to the transformer center taps.

Figure 6-2. 10/100-Mb/s Twisted Pair Interface

NOTE

See the following regarding Figure 6-2:

• Common mode chokes may be required.

• Center tap is pulled to VDD.

• Place resistor and capacitors close to the device.

• All values are typical and are ±1%.

6.2.1.2 Clock IN (X1) Recommendations

The DP83816 device supports an external CMOS level oscillator source or a crystal resonator device.

6.2.1.2.1 Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

The CMOS oscillator specifications for the DP83816 device are listed in Table 6-1.

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X1 X2

CL2

CL1

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Table 6-1. 25-MHz Oscillator Specification

PARAMETER CONDITION MIN TYP MAX UNIT

Frequency 25 MHz

Frequency Tolerance Operational Temperature 50 ppm

Frequency Stability 1 year aging 50 ppm

Rise and Fall Time 20%–80% 6 ns

Jitter Short term 800(1) psec

Jitter Long term 800(1) psec

Symmetry Duty Cycle 40% 60%

(1) This limit is provided as a guideline for component selection and not ensured by production testing. See SNLA091,PHYTER 100 Base-

TX Reference Clock Jitter Tolerance, for details on jitter performance.

6.2.1.2.2 Crystal

A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 6-3

shows a typical connection for a crystal resonator circuit. The load capacitor values vary with the crystal

vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of

100 µW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting

resistor should be placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, set

CL1 and CL2 at 33 pF, and set R1 at 0 Ω.

Specification for 25-MHz crystal are listed in Table 6-2.

Figure 6-3. Crystal Oscillator Circuit

Table 6-2. 25-MHz Crystal Specification

PARAMETER CONDITION MIN TYP MAX UNIT

Frequency 25 MHz

Frequency Tolerance Operational Temperature 50 ppm

Frequency Stability 1 year aging 50 ppm

Load Capacitance 25 40 pF

6.2.1.3 Magnetics

The magnetics have a large impact on the PHY performance as well. While several components are listed

below, others may be compatible following the requirements listed in Table 6-3. TI recommends that the

magnetics include both an isolation transformer and an integrated common mode choke to reduce EMI.

When doing the layout, do not run signals under the magnetics. This could cause unwanted noise

crosstalk. Likewise void the planes under discrete magnetics, this helps prevent common-mode noise

coupling. To save board space and reduce component count, an RJ-45 with integrated magnetics may be

used.

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Table 6-3. Magnetics Requirements

PARAMETER CONDITION TYP UNIT

Turn Ratio ±2% 1:1 —

Insertion Loss 1–100 MHz –1 dB

1–30 MHz –16 dB

Return Loss 30–60 MHz –12 dB

60–80 MHz 10 dB

1–50MHz –30 dB

Differential to Common Rejection Ratio 50–150 MHz –20 dB

30 MHz –35 dB

Crosstalk 60 MHz –30 dB

Isolation HPOT 1,500 dB

6.2.1.4 Pin Configuration for Power Management

See Table 6-4 for proper pin connection for power management configuration:

Table 6-4. PM Pin Configuration

PIN NAME PIN NO. POWER MGT NO POWER MGT

PMEN 59 *PME# 3.3V

3VAUX 122 *3.3Vaux GND

6.2.2 Detailed Design Procedure

6.2.2.1 MAC Interface (MII)

The media independent interface (MII) connects the DP83816 MacPhyter-II to an external PHY device. On

the MII signals, the IEEE specification states the bus should be 68-Ωimpedance.

6.2.2.1.1 Termination Requirement

To reduce digital signal energy, 50-Ωseries termination resistors are recommended for all MII output

signals (including RXCLK, TXCLK, and RX Data signals.)

6.2.2.1.2 Recommended Maximum Trace Length

Although MII is a synchronous bus architecture, there are a number of factors limiting signal trace lengths.

With a longer trace, the signal becomes more attenuated at the destination and thus more susceptible to

noise interference. Longer traces also act as antennas, and if run on the surface layer, can increase EMI

radiation. If a long trace is running near and adjacent to a noisy signal, the unwanted signals could be

coupled in as cross talk. TI recommends keeping the signal trace lengths as short as possible. Ideally,

keep the traces under 6 inches. Trace length matching, to within 2 inches on the MII bus is recommended.

Significant differences in the trace lengths can cause data timing issues. As with any high-speed data

signal, good design practices dictate that impedance should be maintained and stubs should be avoided

throughout the entire data path.

6.2.2.2 Calculating Impedance

The following equations can be used to calculate the differential impedance of the board. For microstrip

traces, a solid ground plane is needed under the signal traces. The ground plane helps keep the EMI

localized and the trace impedance continuous. Because stripline traces are typically sandwiched between

the ground and supply planes, they have the advantage of lower EMI radiation and less noise coupling.

The trade off of using strip line is lower propagation speed.

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Zdiff = 2 × Zo×F1F0.48 le@F0.96 S

HApG

Zo=F60

¥ErGln F1.98 × l2 × H + T

0.8 × W + TpG

Zo=F87

¥Er+ (1.41)Gln l5.98 H

0.8 W + Tp

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6.2.2.2.1 Microstrip Impedance – Single-Ended

Figure 6-4 illustrates the single-ended microstrip impedance. Use Equation 3 to calculate Zo.

(3)

W = Width of the trace

H = Height of dielectric above the return plane

T = Trace thickness

Er = Relative permittivity of the dielectric

Figure 6-4. Microstrip Impedance – Single-Ended

6.2.2.2.2 Stripline Impedance – Single-Ended

Figure 6-5 illustrates the single-ended stripline impedance. Use Equation 4 to calculate Zo.

(4)

W = Width of the trace

H = Height of dielectric above the return plane

T = Trace thickness

Er = Relative permittivity of the dielectric

Figure 6-5. Stripline Impedance – Single-Ended

6.2.2.2.3 Microstrip Impedance – Differential

Figure 6-6 illustrates the differential microstrip impedance. Use Equation 5 to calculate Zdiff.

(5)

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HApG

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W = Width of the trace

H = Height of dielectric above the return plane

T = Trace thickness

Er = Relative permittivity of the dielectric

Figure 6-6. Microstrip Impedance – Differential

6.2.2.2.4 Stripline Impedance – Differential

Figure 6-7 illustrates the differential stripline impedance. Use Equation 6 to calculate Zdiff.

(6)

W = Width of the trace

H = Height of dielectric above the return plane

T = Trace thickness

Er = Relative permittivity of the dielectric

Figure 6-7. Stripline Impedance – Differential

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PHY

Component

Optional 0 :

or Bead

Ground Pin

Vdd

PCB Via

Vdd

PCB

Via 0.1 PF

DP83816

SNLS164E –SEPTEMBER 2005–REVISED DECEMBER 2015

www.ti.com

6.2.3 Application Curves

Figure 6-8. Sample 100-Mb/s Waveform (MLT-3) Figure 6-9. Sample 10-Mb/s Waveform

7 Power Supply Recommendations

The device VDD supply pins should be bypassed with low-impedance 0.1-μF surface mount capacitors. To

reduce EMI, the capacitors should be places as close as possible to the component VDD supply pins,

preferably between the supply pins and the vias connecting to the power plane. In some systems it may

be desirable to add 0-Ωresistors in series with supply pins, as the resistor pads provide flexibility if adding

EMI beads becomes necessary to meet system level certification testing requirements (see Figure 8-4). TI

recommends the PCB have at least one solid ground plane and one solid VDD plane to provide a low-

impedance power source to the component. This also provides a low-impedance return path for non-

differential digital bus and clock signals. A 10.0-μF capacitor should also be placed near the DP83816

device for local bulk bypassing between the VDD and ground planes.

Figure 7-1. VDD Bypass Layout

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Avoid

Stubs

Does Not Maintain Parallelism

Ground or Power Plane

DP83816

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SNLS164E –SEPTEMBER 2005–REVISED DECEMBER 2015

8 Layout

8.1 Layout Guidelines

TI recommends placing the 49.9-Ω,1% termination resistors, and 0.1-μF decoupling capacitor near the

TPTDP, TPRDM and TPTDP, TPRDM pins. Connect the termination resistors to the VDD plane with a via

close to the resistors.

Stubs should be avoided on all signal traces, especially the differential signal pairs. See Figure 8-1. Within

the pairs (for example, TPTDP and TPTDM) the trace lengths should be run parallel to each other and

matched in length. Matched lengths minimize delay differences, avoiding an increase in common mode

noise and increased EMI. See Figure 8-1.

Figure 8-1. Differential Signal Pair - Stubs

Ideally, there should be no crossover or via on the signal paths. Vias present impedance discontinuities

and should be minimized. Route an entire trace pair on a single layer if possible. PCB trace lengths

should be kept as short as possible.

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Avoid

Stubs

Does Not Maintain Parallelism

Ground or Power Plane

DP83816

SNLS164E –SEPTEMBER 2005–REVISED DECEMBER 2015

www.ti.com

Signal traces should not be run such that they cross a plane split. See Figure 8-2. A signal crossing a

plane split may cause unpredictable return path currents and would likely impact signal quality as well,

potentially creating EMI problems.

Figure 8-2. Differential Signal Pair-Plane Crossing

MDI signal traces should have 50 Ωto ground or 100-Ωdifferential controlled impedance. Many tools are

available online to calculate this.

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8.1.1 PCB Layer Stacking

To meet signal integrity and performance requirements, at minimum a 4-layer PCB is recommended for

implementing PHYTER components in end user systems. The following layer stack-ups are recommended

for four, six, and eight-layer boards, although other options are possible.

Figure 8-3. PCB Stripline Layer Stacking

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Plane Coupling

Component

PHY

Component

Note:Power/

Ground Planes

Voided under

Transformer

RJ45

Connector

Transformer

(if not

Integrated in

RJ45)

System Power/Ground

Planes Chassis Ground

Plane

Termination

Components

Plane Coupling

Component

DP83816

SNLS164E –SEPTEMBER 2005–REVISED DECEMBER 2015

www.ti.com

Within a PCB it may be desirable to run traces using different methods, microstrip vs. stripline, depending

on the location of the signal on the PCB. For example, it may be desirable to change layer stacking where

an isolated chassis ground plane is used. Figure 8-4 illustrates alternative PCB stacking options.

Figure 8-4. Alternative PCB Stripline Layer Stacking

8.2 Layout Example

Figure 8-5. Layout Example

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation see the following:

•AN-1351 MAC Address Programming for DP83816 MacPHYTER-II and DP83815 MacPHYTER,

SNLA070

•AN-1323 Updating DP83815 MacPHYTER Hardware Designs to DP83816 MacPHYTER-II,SNLA063

•AN-1287 DP83815 MacPHYTER and DP83816 MacPHYTER-II High Data Rate Stress Testing,

SNLA057

•AN-1548 PHYTER 100 Base-TX Reference Clock Jitter Tolerance SNLA091

9.2 Trademarks

Magic Packet is a trademark of Advanced Micro Devices, Inc.

All other trademarks are the property of their respective owners.

9.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.4 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical Packaging and Orderable Information

10.1 Packaging Information

The following pages include mechanical packaging and orderable information. This information is the

most-current data available for the designated device. This data is subject to change without notice and

without revision of this document. For browser-based versions of this data sheet, see the left-hand

navigation pane.

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PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DP83816AVNG NRND LQFP PGE 144 60 Non-RoHS

& Green Call TI Call TI 0 to 70 DP83816AVNG

DP83816AVNG/NOPB NRND LQFP PGE 144 60 RoHS & Green SN Level-3-260C-168 HR 0 to 70 DP83816AVNG

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MECHANICAL DATA

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK

4040147/C 10/96

0,27

0,17

0,13 NOM

0,25

0,75

0,45

0,05 MIN

Seating Plane

Gage Plane

108

109

144

22,20

21,80

19,80

17,50 TYP

20,20

1,35

1,45

1,60 MAX

0,08

0°–7°

0,08

0,50

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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