1
FEATURES
APPLICATIONS
DESCRIPTION
VCC − Supply Voltage − V
0
5
10
15
20
25
30
35
5 10 15 20 25
PO − Output Power − W
G009
THD+N = 1%
THD+N = 10%
f = 1 kHz
RL = 8 Ω (BTL)
Gain = 3 dB
TAS5102
TAS5103
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.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
20-W/15-W STEREO DIGITAL AMPLIFIER POWER STAGE
A low-cost, high-fidelity audio system can be builtusing a TI chipset, comprising a modulator (e.g.,2
•2 × 20 W at 10% THD+N Into 8- ΩBTL at 18 V
TAS5086) and the TAS5102/TAS5103. This system(With Heatsink for TAS5102)
only requires a simple passive LC demodulation filter•2 × 15 W at 10% THD+N Into 8- ΩBTL at 15.5 V
to deliver high-quality, high-efficiency audiofor TAS5103
amplification with proven EMI compliance. Thesedevices require two power supplies, at 3.3 V for•2 × 10 W at 10% THD+N Into 8- ΩBTL at 13 V
VREG, and up to 23 V for PVDD. The•>100-dB SNR (A-Weighted)
TAS5102/TAS5103 does not require power-up•< 0.1% THD+N at 1 W
sequencing due to internal power-on reset. Theefficiency of this digital amplifier is greater than 90%•Thermally Enhanced Package: 32-pin HTSSOP
into 8 Ω, which enables the use of smaller power– DAD (TAS5102) Pad Up
supplies and heatsinks.– DAP (TAS5103) Pad Down
The TAS5102/3 has an innovative protection system•High-Efficiency Power Stage (>90%) With
integrated on chip, safeguarding the device against a180-m ΩOutput MOSFETs
wide range of fault conditions that could damage the•Wide PVDD Range from 8V to 23V
system. These safeguards are short-circuit protection,overcurrent protection, undervoltage protection, and•Power-On Reset for Protection on Power Up
overtemperature protection. The TAS5102/TAS5103Without Any Power-Supply Sequencing
has a new proprietary current-limiting circuit that•Integrated Self-Protection Circuits Including
reduces the possibility of device shutdown duringUndervoltage, Overtemperature, Overcurrent,
high-level music transients.Short Circuit
BTL OUTPUT POWER•Built-In Regulator for Gate Drive Supply
vsSUPPLY VOLTAGE•Error Reporting
•EMI Compliant When Used WithRecommended System Design
•Televisions
•Mini/Micro Audio Systems•DVD Receivers
•Home Theaters
The TAS5102/TAS5103 are integrated stereo digitalamplifier power stages with an advanced protectionsystem. The TAS5102/TAS5103 are capable ofdriving an 8- Ωbridge-tied load (BTL) at up to 20W/15 W per channel with low integrated noise at theoutput, low THD+N performance, and low idle powerdissipation.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DEVICE INFORMATION
Pin Assignment
OUT_B
PVDD_A
PGND_CD
BST_A
BST_C
PGND_AB
PGND_AB
PVDD_B
OUT_A
BST_B
PVDD_C
PGND_CD
OUT_C
PVDD_D
OUT_D
BST_D
OTW
VREG
FAULT
GVDD_AB
PWM_B
GND
SSTIMER
RESET
AGND
PWM_A
PWM_C
OC_ADJ
PWM_D
M2
M1
GVDD_CD
OUT_C
PVDD_D
PGND_AB
BST_D
BST_B
PGND_CD
PGND_CD
PVDD_C
OUT_D
BST_C
PVDD_B
PGND_AB
OUT_B
PVDD_A
OUT_A
BST_A
PWM_D
M2
SSTIMER
GVDD_CD
PWM_A
OC_ADJ
FAULT
PWM_C
M1
PWM_B
RESET
GND
OTW
VREG
AGND
GVDD_AB
MODE Selection Pins
Package Heat Dissipation Ratings
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
The TAS5102/TAS5103 are available in a thermally enhanced package:•TAS5102 Pad Up 32-pin HTSSOP PowerPAD™ package (DAD)•TAS5103 Pad Down 32-pin HTSSOP PowerPAD™ package (DAP)
DAD PACKAGE DAP PACKAGE(TOP VIEW) (TOP VIEW)
Mode
PWM INPUT OUTPUT CONFIGURATION PROTECTION SCHEMEM2 M1
0 0 2N
(1)
AD/BD modulation 2 channels BTL output BTL mode
(2)
0 1 1N
(1)
AD modulation 2 channels BTL output BTL mode
(2)
Protection works similarly to BTL mode
(2)
. Only1 0 1N
(1)
AD modulation 4 channels SE output difference in SE mode is that OUT_X is Hi-Z insteadof a pulldown through internal pulldown resistor.1 1 Reserved
(1) The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specificmode.
(2) An overcurrent protection (OC) occurring on A or B causes all channels to shut down. An OC on C or D works similarly. Global errorslike overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.
PARAMETER TAS5102DAD TAS5103DAP
R
θJC
( ° C/W) 1.69 1.69R
θJA
( ° C/W) See Note
(1)
23.5
(1) The TAS5102 package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the devicewith the pad exposed to ambient air as the only means for heat dissipation for higher power applications.For this reason, R
θJA
, a system parameter that characterizes the thermal treatment, is provided in the Application Information section ofthe data sheet. An example and discussion of typical system R
θJA
values are provided in the Thermal Information section. This exampleprovides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate theheat dissipation ratings for a specific application. TI application engineering provides technical support to design heatsinks if needed.Also, for additional general information on PowerPad packages, see TI document SLMA002 B.
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ABSOLUTE MAXIMUM RATINGS
(1)
TAS5102
TAS5103
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.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
over operating free-air temperature range (unless otherwise noted)
UNIT
PVDD_X to GND_X DC -0.3 to 23 VPVDD_X to GND_X
(2)
– 0.3 to 32 VOUT_X to GND_X
(2)
– 0.3 to 32 VBST_X to GND_X
(2)
– 0.3 to 43.2 VVREG to AGND – 0.3 to 4.2 VGVDD to GND -0.3 to 13.2 VGND_X to GND – 0.3 to 0.3 VGND_X to AGND – 0.3 to 0.3 VGND to AGND – 0.3 to 0.3 VPWM_X, OC_ADJ, M1, M2 to AGND – 0.3 to 4.2 VRESET_X, FAULT, OTW to AGND – 0.3 V to 7 VMaximum continuous sink current ( FAULT, OTW) 9 mAT
J
Maximum operating junction temperature range, 0 to 150 ° CT
STG
Storage temperature range – 65 to 150 ° CMinimum pulse duration, low 50 ns
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION
T
A
PACKAGE
(1)
DESCRIPTION
TAS5102DAD 32-pin HTSSOP0 ° C to 70 ° C
TAS5103DAP 32-pin HTSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
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TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
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Pin Functions
PIN
FUNCTION
(1)
DESCRIPTIONNAME TAS5102 TAS5103NO. NO
AGND 3 14 P Analog groundBST_A 32 17 P HS bootstrap supply (BST). External capacitor to OUT_A required.BST_B 25 24 P HS bootstrap supply (BST). External capacitor to OUT_B required.BST_C 24 25 P HS bootstrap supply (BST). External capacitor to OUT_C required.BST_D 17 32 P HS bootstrap supply (BST). External capacitor to OUT_D required.FAULT 12 5 O Device error signal (shutdown); open drainGND 4 13 P GroundPGND_AB 29 20 P Power ground for half-bridges A and BPGND_AB 28 21 P Power ground for half-bridges A and BPGND_CD 21 28 P Power ground for half-bridges C and DPGND_CD 20 29 P Power ground for half-bridge DGVDD_AB 1 16 P Gate-drive voltage supply. Requires 1- µF capacitor to GND.GVDD_CD 16 1 P Gate-drive voltage supply. Requires 1- µF capacitor to GND.Mode selection 2, connect to either AGND or VREG, no pull-up or pull-downM2 15 2 I
resistors
Mode selection 1, connect to either AGND or VREG, no pull-up or pull-downM1 14 3 I
resistorsOC_ADJ 13 4 O Analog overcurrent programming. Requires resistor to ground.OTW 6 11 O Overtemperature warning signal, push-pull, active highOUT_A 30 19 O Output, half-bridge AOUT_B 27 22 O Output, half-bridge BOUT_C 22 27 O Output, half-bridge COUT_D 19 30 O Output, half-bridge DPower supply input for half-bridge A. Requires close decoupling of 0.1- µFPVDD_A 31 18 P
capacitor to GND_A.Power supply input for half-bridge B. Requires close decoupling of 0.1- µFPVDD_B 26 23 P
capacitor to GND_B.Power supply input for half-bridge C. Requires close decoupling of 0.1- µFPVDD_C 23 26 P
capacitor to GND_C.Power supply input for half-bridge D. Requires close decoupling of 0.1- µFPVDD_D 18 31 P
capacitor to GND_D.PWM_A 8 9 I Input signal for half-bridge APWM_B 9 8 I Input signal for half-bridge BPWM_C 10 7 I Input signal for half-bridge CPWM_D 11 6 I Input signal for half-bridge DRESET 7 10 I PWM is not active if RESET goes low.Controls start/stop time of PWM modulation. Requires 2.2 nF capacitor to GNDSSTIMER 5 12 I for AD BTL. Leave pin floating (NC) for BD BTL mode. Also, leave pin floating(NC) for SE mode.VREG 2 15 P Digital regulator supply filter. Requires 0.1- µF capacitor to AGND.
(1) I = input, O = output, P = power
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2nd-OrderL-C
OutputFilter
forEach
Half-Bridge
Bootstrap
Capacitors
2-Channel
H-Bridge
BTL Mode
System
Microcontroller
OUT_A
OUT_B
OUT_C
OUT_D
BST_A
BST_B
BST_C
BST_D
RESET
System
Power
Supply
Hardwire
Mode
Control
PVDD
VREG
GND
Hardwire
OCLimit
M1
PVDD
GVDD
Power
Supply
Decoupling
8V-23V
3.3V
GND
VAC
PWM_A
PWM_C
PWM_D
PWM_B
VALID
M2
Left-
Channel
Output
Right-
Channel
Output
Input
H-Bridge1
Input
H-Bridge2
VREG
PowerSupply
Decoupling
2
PVDD_A,B,C,D
GND_A,B,C,D
4
GND
VREG
AGND
OC_ADJ
Bootstrap
Capacitors
2nd-OrderL-C
OutputFilter
forEach
Half-Bridge
FAULT
OTW
Output
H-Bridge2
Output
H-Bridge1
OTW
FAULT
TAS5508
GVDD_AB,CD
4
TAS5102
TAS5103
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.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
SYSTEM BLOCK DIAGRAM
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Temp.
Sense
M1
M2
VALID
FAULT
OTW
AGND
OC_ADJ
VREG
Power
On
Reset
Under-
voltage
Protection
GND
PWM_D OUT_D
GND_D
PVDD_D
BST_D
Gate
Drive
PWM
Rcv.
Overload
Protection Isense
4
Protection
and
I/OLogic
PWM_C OUT_C
GND_C
PVDD_C
BST_C
Timing Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_CD
PWM_B OUT_B
GND_B
PVDD_B
BST_B
Timing Gate
Drive
Ctrl.
PWM
Rcv.
PWM_A OUT_A
GND_A
PVDD_A
BST_A
Timing Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_AB
Ctrl.
BTL/PBTL−Configuration
Pulldown Resistor
BTL/PBTL−Configuration
PulldownResistor
BTL/PBTL−Configuration
PulldownResistor
BTL/PBTL−Configuration
PulldownResistor
InternalPullup
ResistorstoVREG
4
GVDD_CD
Regulator
GVDD_AB
Regulator
Timing
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
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FUNCTIONAL BLOCK DIAGRAM
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RECOMMENDED OPERATING CONDITIONS
AC Characteristics (BTL)
TAS5102
TAS5103
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.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
MIN TYP MAX UNIT
Half-bridge supply, PVDD_X DC supply voltage 8 18 23 VV
SS
Supply for Protection and I/O Logic, VREG DC supply voltage 3 3.3 3.6 VR
L
(BTL) 6-8Output filter: L = 10 µH, C = 470 nF.R
L
(SE) Load impedance Output AD modulation, switching 3-4 Ωfrequency > 350 kHzR
L
(PBTL) 3-4L
O
(BTL) 200Minimum output inductance underL
O
(SE) Output-filter inductance 200 nHshort-circuit conditionL
O
(PBTL) 200F
PWM
PWM frame rate 192 384 432 kHzT
J
Junction temperature 0 125 ° C
PVDD_X = 18 V, BTL mode, R
L
= 8 Ω, R
OC
= 22 K Ω, C
BST
= 33-nF, audio frequency = 1 kHz, AES17 filter,F
PWM
= 384 kHz, ambient temperature = 25 ° C (unless otherwise noted). Audio performance is recorded as a chipset, usingTAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance withrecommended operating conditions, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PVDD = 18 V, 10% THD 20PVDD = 18 V, 7% THD 18P
O
Power output per channel WPVDD = 12 V, 10% THD 9PVDD = 12 V, 7% THD 8PVDD = 18V, Po =10 W (half-power) 0.15THD+N Total harmonic distortion + noise PVDD = 12V, Po =4.5 W (half-power) 0.18 %1 W 0.05V
n
Output integrated noise A-weighted 50 µVSNR Signal-to-noise ratio
(1)
A-weighted 94 105 dBA-weighted, input level = – 60 dBFS usingDNR Dynamic range 94 105 dBTAS5086 modulatorP
D
Power dissipation due to idle losses (IPVDD_X) P
O
= 0 W, 4 channels switching
(2)
0.6 W
(1) SNR is calculated relative to 0-dBFS input level.(2) Actual system idle losses are affected by core losses of output inductors.
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AC Characteristics (Single-Ended Output)
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
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PVDD_X = 18 V, SE mode, R
L
= 4 Ω, R
OC
= 22 k Ω, C
BST
= 33-nF, audio frequency = 1 kHz, AES17 filter, F
PWM
= 384 kHz,ambient temperature = 25 ° C (unless otherwise noted). Audio performance is recorded as a chipset, using TAS5086 PWMprocessor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operatingconditions, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PVDD = 18 V, 10% THD 10PVDD = 18 V, 7% THD 9P
O
Power output per channel WPVDD = 12 V, 10% THD 4.5PVDD = 12 V, 7% THD 4PVDD = 18V, Po =5 W (half-power) 0.2THD+
Total harmonic distortion + noise %N
PVDD = 12V, Po =2.25 W (half-power) 0.2V
n
Output integrated noise A-weighted 50 µVSNR Signal-to-noise ratio
(1)
A-weighted 105 dBDNR Dynamic range A-weighted, input level = – 60 dBFS using TAS5086 modulator 105 dBPower dissipation due to idleP
D
P
O
= 0 W, 4 channels switching
(2)
0.6 Wlosses (IPVDD_X)
(1) SNR is calculated relative to 0-dBFS input level.(2) Actual system idle losses are affected by core losses of output inductors.
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DC Characteristics
TAS5102
TAS5103
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.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
R
L
= 8 Ω, F
PWM
= 384 kHz (unless otherwise noted). All performance is in accordance with recommended operatingconditions, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal Voltage Regulator and Current Consumption
V
SS
Digital Input Supply Voltage, VREG 3 3.3 3.6 VOperating, 50% duty cycle 6.5 10I
(VREG)
Supply current, VREG mAReset mode, no switching 6.5 1050% duty cycle, without output filter or load 35 50I
(PVDD_X)
Total Half-bridge idle current mAReset mode, no switching 5 6.3
Output Stage MOSFETs
Drain-to-source resistance, LS T
J
= 25 ° C, includes metallization resistance 180 m ΩR
DS(on)
Drain-to-source resistance, HS T
J
= 25 ° C, includes metallization resistance 180 m Ω
I/O Protection
Undervoltage protection limit, GVDD_X,V
uvp,G
5.7 Vvoltage risingUndervoltage protection limit, GVDD_X,V
uvp,G
5.5 Vvoltage fallingOTW
(1)
Overtemperature warning 125 ° CTemperature drop needed below OTWOTW
HYST
(1)
temperature for OTW to be inactive after 25 ° Cthe OTW eventOTE
(1)
Overtemperature error 150 ° COTE-OTW
(1)
OTE-OTW differential 25 ° CA RESET must occur to exit shutdownOTE
HYST
(1)
and to release FAULT following an OTE 30 ° Cevent.OCPC Overcurrent protection counter F
PWM
= 384 kHz 0.63 msResistor — programmable, max. current,I
OC
Overcurrent limit protection 4.5 AR
OCP
= 22 k Ω
I
OCT
Overcurrent response time 150 nsResistor tolerance = 5% for typical value; the 24 k ΩR
OCP
OC programming resistor range 20 22minimum resistance should not be less than 20k Ω.Internal pulldown resistor at the output of Connected when RESET is active to provideR
PD
3 k Ωeach half-bridge bootstrap capacitor charge. Not used in SE mode
(1) Specified by design
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TYPICAL CHARACTERISTICS
f − Frequency − Hz
20
VCC = 8 V
RL = 8 Ω (BTL)
Gain = 3 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G001
1PO = 0.5 W
0.01
PO = 1 W
PO = 2.5 W
f − Frequency − Hz
20
VCC = 12 V
RL = 8 Ω (BTL)
Gain = 3 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G002
1
PO = 0.5 W
PO = 5 W
0.01 PO = 2.5 W
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
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DC Characteristics (continued)R
L
= 8 Ω, F
PWM
= 384 kHz (unless otherwise noted). All performance is in accordance with recommended operatingconditions, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Digital Specifications
V
IH
High-level input voltage 2 VPWM_A, PWM_B, PWM_C, PWM_D, M1, M2,RESETV
IL
Low-level input voltage 0.8 VStatic, High PWM_A, PWM_B, PWM_C, PWM_D,
100M1, M2, RESETI
lkg
Input leakage current µAStatic, Low PWM_A, PWM_B, PWM_C, PWM_D,
– 10 10M1, M2, RESET
FAULT
R
INT_PU
Internal pullup resistance, FAULT 20 26 32 k Ω
Internal pullup resistor 3 3.3 3.6V
OH
High-level output voltage VExternal pullup of 4.7 k Ωto 5 V 5.5V
OL
Low-level output voltage I
O
= 4 mA 0.25 0.5 V
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY
Figure 1. Figure 2.
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f − Frequency − Hz
20
VCC = 18 V
RL = 8 Ω (BTL)
Gain = 3 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G003
1
0.01
PO = 10 W
PO = 5 W PO = 1 W
PO − Output Power − W
0.01
VCC = 8 V
RL = 8 Ω (BTL)
Gain = 3 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G004
1
f = 20 Hz
f = 1 kHz
f = 10 kHz
PO − Output Power − W
0.01
VCC = 12 V
RL = 8 Ω (BTL)
Gain = 3 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G005
1
f = 20 Hz
f = 1 kHz
f = 10 kHz
PO − Output Power − W
0.01
VCC = 18 V
RL = 8 Ω (BTL)
Gain = 3 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G006
1
f = 20 Hz
f = 1 kHz
f = 10 kHz
TAS5102
TAS5103
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.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY OUTPUT POWER
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsOUTPUT POWER OUTPUT POWER
Figure 5. Figure 6.
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PO − Total Output Power − W
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30 35 40 45 50
ICC − Supply Current − A
G008
f = 1 kHz
RL = 8 Ω (BTL)
Gain = 3 dB
VCC = 8 V
VCC = 12 V
VCC = 18 V
PO − Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25
Efficiency − %
G007
f = 1 kHz
RL = 8 Ω (BTL)
Gain = 3 dB
VCC = 18 V
VCC = 12 V
VCC = 8 V
VCC − Supply Voltage − V
0
5
10
15
20
25
30
35
5 10 15 20 25
PO − Output Power − W
G009
THD+N = 1%
THD+N = 10%
f = 1 kHz
RL = 8 Ω (BTL)
Gain = 3 dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
f − Frequency − Hz
Crosstalk − dB
G010
20 100 1k 10k 20k
Left to Right
Right to Left
VCC = 18 V
RL = 8 Ω (BTL)
PO = 0.25 W
Gain = 3 dB
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY SUPPLY CURRENTvs vsOUTPUT POWER TOTAL OUTPUT POWER
Figure 7. Figure 8.
OUTPUT POWER CROSSTALKvs vsSUPPLY VOLTAGE FREQUENCY
Figure 9. Figure 10.
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f − Frequency − Hz
20
VCC = 12 V
RL = 4 Ω (SE)
Gain = 3 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G011
1
0.01
PO = 2.5 W
PO = 1 W PO = 0.5 W
f − Frequency − Hz
20
VCC = 18 V
RL = 4 Ω (SE)
Gain = 3 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G012
1
0.01
PO = 2.5 W
PO = 5 W
PO = 0.5 W
VCC − Supply Voltage − V
0
3
6
9
12
15
18
5 10 15 20 25
PO − Output Power − W
G014
THD+N = 1%
THD+N = 10%
f = 1 kHz
RL = 4 Ω (SE)
Gain = 3 dB
PO − Output Power − W
0.01
f = 1 kHz
RL = 4 Ω (SE)
Gain = 3 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G013
1
VCC = 12 V
VCC = 18 V
TAS5102
TAS5103
www.ti.com
.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY
Figure 11. Figure 12.
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWERvs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 13. Figure 14.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TAS5102 TAS5103
PO − Total Output Power − W
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0
ICC − Supply Current − A
G015
f = 1 kHz
RL = 4 Ω (SE)
Gain = 3 dB
VCC = 8 V
VCC = 12 V
VCC = 18 V
VCC − Supply Voltage − V
−100.0
−80.0
−60.0
−40.0
−20.0
0.0
5.0 10.0 15.0 20.0 25.0
A-Weighted Noise − dBv
G016
f = 1 kHz
RL = 4 Ω (SE)
Gain = 3 dB
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Crosstalk − dB
G018
20 100 1k 10k 20k
Left to Right
Right to Left
RL = 4 Ω (SE)
PO = 0.25 W
Gain = 3 dB
VCC = 18 V
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT A-WEIGHTED NOISEvs vsTOTAL OUTPUT POWER SUPPLY VOLTAGE
Figure 15. Figure 16.
CROSSTALK
vsFREQUENCY
Figure 17.
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5102 TAS5103
2N-BTL
TAS5102
22k
*2200pF
50V
*ADmodeonly.
LeaveopenforBD
modeandSE.
0.1uF
16V
0.1uF
16V
1uF
16V
1uF
50V
0.1uF
50V
0.033uF
50V
0.033uF
50V
0.033uF
50V
0.033uF
50V
0.1uF
50V
0.1uF
50V
0.1uF
50V
1uF
50V
1uF
50V
10uH
10uH
10uH
10uH
0.47uF
50V
0.47uF
50V
0.47uF
50V
0.47uF
50V
3.3
3.3
3.3
3.3
10nF
50V
10nF
50V
10nF
50V
10nF
50V
220uF
35V
220uF
35V
330uF
35V
1uF
50V
10
TAS5102
TAS5103
www.ti.com
.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
Figure 18. Typical Differential (2N) BTL Application With AD Modulation Filters
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TAS5102 TAS5103
1N-BTL
TAS5102
22k
*2200pF
50V
*ADmodeonly.
LeaveopenforBD
modeandSE.
0.1uF
16V
0.1uF
16V
1uF
16V
1uF
50V
0.1uF
50V
0.033uF
50V
0.033uF
50V
0.033uF
50V
0.033uF
50V
0.1uF
50V
0.1uF
50V
0.1uF
50V
1uF
50V
1uF
50V
10uH
10uH
10uH
10uH
0.47uF
50V
0.47uF
50V
0.47uF
50V
0.47uF
50V
3.3
3.3
3.3
3.3
10nF
50V
10nF
50V
10nF
50V
10nF
50V
220uF
35V
220uF
35V
330uF
35V
1uF
50V
10
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
www.ti.com
Figure 19. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5102 TAS5103
THEORY OF OPERATION
POWER SUPPLIES
INTEGRATED GATE DRIVE SUPPLY (GVDD)
SYSTEM POWER-UP/POWER-DOWN
Powering Up
TAS5102
TAS5103
www.ti.com
.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
compliance, and system reliability, it is important thateach PVDD_X pin is decoupled with a 100-nFceramic capacitor placed as close as possible toTo facilitate system design, the TAS5102/3 needs
each supply pin. It is recommended to follow the PCBonly a 3.3-V supply in addition to the (typical) 18-V
layout of the TAS5102/3 reference design. Forpower-stage supply. An internal voltage regulator
additional information on recommended power supplyprovides suitable voltage levels for the gate drive
and required components, see the applicationcircuitry. Additionally, all circuitry requiring a floating
diagrams given previously in this data sheet.voltage supply, e.g., the high-side gate drive, is
The 3.3-V supply should be from a low-noise,accommodated by built-in bootstrap circuitry requiring
low-output-impedance voltage regulator. Likewise, theonly a few external capacitors.
18-V power-stage supply is assumed to have lowIn order to provide outstanding electrical and
output impedance and low noise. The power-supplyacoustical characteristics, the PWM signal path for
sequence is not critical as facilitated by the internalthe output stage is designed as identical,
power-on-reset circuit. Moreover, the TAS5102/3 isindependent half-bridges. For this reason, each
fully protected against erroneous power-stage turnonhalf-bridge has separate bootstrap pins (BST_X), and
due to parasitic gate charging.power-stage supply pins (PVDD_X). The gate drivevoltages (GVDD_AB and GVDD_CD) are derivedfrom the PVDD voltage. Separate, internal voltageregulators reduce and regulate the PVDD voltage to a The TAS5103 has an integrated gate drive supply,voltage appropriate for efficient gave drive operation. which eliminates the need for an external regulator. IfFurthermore, an additional pin (VREG) is provided as the PVDD is 12 V (i.e., max PVDD < 13.2 V), it issupply for all common logic circuits. Special attention possible to connect the PVDD to the GVDD through ashould be paid to placing all decoupling capacitors as ten ohm resistor. This will allow the power stage toclose to their associated pins as possible. In general, operate as low a 7 V during dips. Otherwise theinductance between the power supply pins and GVDD undervoltage protection will shutdown thedecoupling capacitors must be avoided. (See outputs when the supply drops to 8 V. Care must bereference board documentation for additional taken to not connect GVDD and PVDD together ininformation.) this manner if the operating voltage is higher than12 V.For a properly functioning bootstrap circuit, a smallceramic capacitor must be connected from eachbootstrap pin (BST_X) to the power-stage output pin
SEQUENCE(OUT_X). When the power-stage output is low, thebootstrap capacitor is charged through an internaldiode connected between the gate-drive power--supply pin (GVDD_X) and the bootstrap pin. When
The outputs of the H-bridges remain in athe power-stage output is high, the bootstrap
high-impedance state until the internal gate-drivecapacitor potential is shifted above the output
supply voltage (GVDD_XY) and external VREGpotential and thus provides a suitable voltage supply
voltages are above the undervoltage protection (UVP)for the high-side gate driver. In an application with
voltage threshold (see the Electrical CharacteristicsPWM switching frequencies in the range from 352
section of this data sheet). Although not specificallykHz to 384 kHz, it is recommended to use 33-nF
required, it is recommended to hold RESET in a lowceramic capacitors, size 0603 or 0805, for the
state while powering up the device. This allows anbootstrap supply. These 33-nF capacitors ensure
internal circuit to charge the external bootstrapsufficient energy storage, even during minimal PWM
capacitors by enabling a weak pulldown of theduty cycles, to keep the high-side power stage FET
half-bridge output. The output impedance is(LDMOS) fully turned on during the remaining part of
approximately 3K Ωunder this condition, unless modethe PWM cycle. In an application running at a
1, 0 (Single-ended Mode), is used. This means thatreduced switching frequency, generally 192 kHz, the
the TAS5102/3 should be held in reset for at leastbootstrap capacitor might need to be increased in
200 µS to ensure that the bootstrap capacitors arevalue.
charged. This also assumes that the recommended0.033- µF bootstrap capacitors are used. Changes toSpecial attention should be paid to the power-stage
bootstrap capacitor values will change the bootstrappower supply; this includes component selection,
capacitor charge time. To avoid pops and clicks,PCB placement, and routing. As indicated, each
follow the recommended timing diagram in Figure 20 .half-bridge has independent power-stage supply pins(PVDD_X). For optimal electrical performance, EMI
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TAS5102 TAS5103
Transitionto50%dutycycle
andholdfor10ms
Transitionto50%dutycycle
andholdfor10ms
Powering Down
ERROR REPORTING
DEVICE PROTECTION SYSTEM
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
www.ti.com
When the TAS5102/3 is being used with TI PWMmodulators such as the TAS5086, no specialattention to the state of RESET is required, providedthat the chipset is configured as recommended.
Figure 20. Power-Down/Power-Up Timing Diagram
Table 1. (continued)
FAULT OTW DESCRIPTIONThe device remains fully operational as long as the
1 0 Junction temperature lower thangate-drive supply voltage and VREG voltages are
125 ° C and no faults (normaloperation)above the undervoltage protection (UVP) voltagethreshold (see the Electrical Characteristics section of
1 1 Junction temperature higher thanthis data sheet). Although not specifically required, it 125 ° C (overtemperature warning)is a good practice to hold RESET low during power
Note that asserting either RESET low forces thedown, thus preventing audible artifacts, including
FAULT signal high, independent of faults beingpops or clicks. To avoid pops and clicks, follow the
present. TI recommends monitoring the OTW signalrecommended timing diagram in Figure 20 .
using the system microcontroller and responding toWhen the TAS5102/3 is being used with TI PWM
an overtemperature warning signal by, e.g., turningmodulators such as the TAS5086, no special
down the volume to prevent further heating of theattention to the state of RESET is required, provided
device, resulting in device shutdown (OTE).that the chipset is configured as recommended.
To reduce external component count, an internalpullup resistor to 3.3 V is provided on the FAULToutput. Level compliance for 5-V logic can beThe FAULT pin is an active-low, open-drain output.
obtained by adding external pullup resistors to 5 VThe OTW pin is a push-pull, active-high output. Their
(see the Electrical Characteristics section of this datafunction is for protection-mode signaling to a PWM
sheet for further specifications).controller or other system-control device.
Any fault resulting in device shutdown is signaled bythe FAULT pin going low. Likewise, OTW goes high
The TAS5102/3 contains advanced protectionwhen the device junction temperature exceeds 125 ° C
circuitry carefully designed to facilitate system(see Table 1 ).
integration and ease of use, as well as to safeguardthe device from permanent failure due to a wideTable 1.
range of fault conditions such as short circuits,overtemperature, and undervoltage. The TAS5102/3FAULT OTW DESCRIPTION
responds to a fault by immediately setting the power0 0 Overcurrent (OC) or undervoltage
stage in a high-impedance (Hi-Z) state and asserting(UVP) warning or overtemperatureerror (OTE)
the FAULT pin low. In situations other thanovercurrent (OC) and overtemperature error (OTE),0 1 Overtemperature warning (OTW) orovercurrent (OC) or undervoltage
the device automatically recovers when the fault(UVP)
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5102 TAS5103
Overtemperature Protection
Use of TAS5102/3 in High-Modulation-Index
Undervoltage Protection (UVP) and Power-On
DEVICE RESETOvercurrent (OC) Protection With Current
TAS5102
TAS5103
www.ti.com
.............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
condition has been removed. For highest possiblereliability, recovering from an overcurrent fault
The TAS5102/3 has a two-levelrequires external reset of the device (see the Device
temperature-protection system that asserts anReset section of this data sheet) no sooner than 300
active-high warning signal (OTW) when the devicems after the shutdown.
junction temperature exceeds 125 ° C (nominal) and, ifthe device junction temperature exceeds 150 ° C(nominal), the device is put into thermal shutdown,Capable Systems
resulting in all half-bridge outputs being set in theThis device requires at least 50 ns of low time on the high-impedance (Hi-Z) state and FAULT beingoutput per 384-kHz PWM frame rate in order to keep asserted low. OTE is latched in this case. To clearthe bootstrap capacitors charged. As an example, if the OTE latch, RESET must be asserted. Thereafter,the modulation index is set to 99.2% in the TAS5086, the device resumes normal operation.this setting allows PWM pulse durations down to 20ns. This signal, which does not meet the 50-ns
Reset (POR)requirement, is sent to the PWM_X pin, and thislow-state pulse time does not allow the bootstrap
The UVP and POR circuits of the TAS5102/3 fullycapacitor to stay charged. In this situation, the low
protect the device in any power-up/down andvoltage across the bootstrap capacitor can cause the
brownout situation. While powering up, the PORbootstrap UVP circuitry to activate and shutdown the
circuit resets the overload circuit (OLP) and ensuresdevice. The TAS5102/3 device requires limiting the
that all circuits are fully operational when theTAS5086 modulation index to 96.1% to keep the
GVDD_XY and VREG supply voltages reach 5.7 Vbootstrap capacitor charged under all signals and
(typical) and 2.7 V, respectively. Although GVDD_XYloads.
and VREG are independently monitored, a supplyvoltage drop below the UVP threshold on VREG orTherefore, TI strongly recommends using a TI PWM
either GVDD_XY pin results in all half-bridge outputsprocessor, such as TAS5508 or TAS5086, with the
immediately being set in the high-impedance (Hi-Z)modulation index set at 96.1% to interface with
state and FAULT being asserted low. The deviceTAS5102/3. This is done by writing 0x04 to the
automatically resumes operation when all supplyModulation Limit Register (0x10) in the TAS5086 or
voltages have increased above the UVP threshold.0x04 to the Modulation Limit Register (0x16) in theTAS5508.
One reset pin is provided for control of half-bridgesLimiting
A/B/C/D. When RESET is asserted low, all fourThe device has independent, fast-reacting current
power-stage FETs in half-bridges A, B, C, and D aredetectors on all high-side and low-side power-stage
forced into a high-impedance (Hi-Z) state. Thus, theFETs. The detector outputs are closely monitored by
reset pin is well suited for hard-muting the powertwo protection systems. The first protection system
stage if needed.controls the power stage in order to prevent the
In BTL modes, to accommodate bootstrap chargingoutput current further increasing, i.e., it performs a
prior to switching start, asserting the reset input lowcycle-by-cycle current-limiting function, rather than
enables weak pulldown of the half-bridge outputs. Inprematurely shutting down during combinations of
the SE mode, the weak pulldowns are not enabled,high-level music transients and extreme speaker load
and it is therefore recommended to ensure bootstrapimpedance drops. If the high-current condition
capacitor charging by providing a low pulse on thesituation persists, i.e., the power stage is being
PWM inputs when reset is asserted high.overloaded, a second protection system triggers alatching shutdown, resulting in the power stage being
Asserting the reset input low removes any faultset in the high-impedance (Hi-Z) state. Current
information to be signaled on the FAULT output, i.e.,limiting and overcurrent protection are not
FAULT is forced high.independent for half-bridges A and B and,
A rising-edge transition on the reset input allows therespectively, C and D. That is, if the bridge-tied load
device to resume operation after an overcurrent fault.between half-bridges A and B causes an overcurrentfault, half-bridges A, B, C, and D are shut down.
The overcurrent protection threshold is set by aresistor to ground from the OC_ADJ pin. A value of22k Ωwill result in an overcurrent threshold of 4.5 A.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TAS5102 TAS5103
SSTIMER FUNCTIONALITY
THERMAL INFORMATION
TAS5102
TAS5103
SLLS801A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................
www.ti.com
and heat can be continually removed from the IC.Because of the efficiency of the TAS5102, heatsinksThe SSTIMER pin uses a capacitor connected
can be used which are much smaller than thosebetween this pin and ground to control the output
required for linear amplifiers of equivalentduty cycle when a transition occurs on the RESET
performance.pin. The capacitor on the SSTIMER pin is slowlycharged through an internal current source, and the R
θJA
is a system thermal resistance from junction tocharge time determines the rate at which the output ambient air. As such, it is a system parameter withtransitions from a near zero duty cycle to the duty roughly the following components: R
θJC
(the thermalcycle that is present on the inputs. This allows for a resistance from junction to case, or in this instancesmooth transition with no audible pop or click noises the metal pad), thermal grease thermal resistance,when the RESET pin transitions from high-to-low or and heatsink thermal resistance. R
θJC
has beenlow-to-high. provided in the Device Information section. Thethermal grease thermal resistance can be calculatedFor a high-to-low transition of the RESET pin
from the exposed pad area and the thermal grease(shutdown case), it is important for the modulator to
manufacturer ' s area thermal resistance (expressed inremain switching for a period of at least 10 ms (if
° C-in
2
/W). The area thermal resistance of theusing a 2.2 nF capacitor). Larger capacitors will
example thermal grease with a 0.001-inch thick layerincrease the start-up/shutdown time, while capacitors
is about 0.054 ° C-in
2
/W. The approximate exposedsmaller than 2.2 nF will decrease the
pad area is 0.01164 in
2
. Dividing the example thermalstart-up/shutdown time. The inputs MUST remain
grease area resistance by the area of the pad givesswitching on the shutdown transition to allow the
the actual resistance through the thermal grease , 3.3outputs to slowly ramp down the duty cycle to near
° C/W.zero before completely shutting off. The SSTIMERpin should be left floating for BD modulation and also Heatsink thermal resistance is generally predicted byfor SE (single-ended) mode. the heatsink vendor, modeled using a continuous flowdynamics (CFD) model, or measured.
Thus for a single IC, the system R
θJA
= R
θJC
+ thermalgrease resistance + heatsink resistance.The thermally augmented package provided with theTAS5102 is designed to be interfaced directly to a
Thermal information for the TAS5103 Pad Downheatsink using a thermal interface compound (for
design can be found in TI document SLMA002 B.example, Wakefield Engineering type 126 thermal
PowerPAD Thermally Enhanced Package Applicationgrease.) The heatsink then absorbs heat from the IC
Report . Additional material regarding thermal metricsand couples it to the local air. If the heatsink is
can be found in TI document SPRA953A, IC Packagecarefully designed, this process can reach equilibrium
Thermal Metrics (Rev. A).
20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5102 TAS5103
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TAS5102DAD ACTIVE HTSSOP DAD 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5102DADG4 ACTIVE HTSSOP DAD 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5102DADR ACTIVE HTSSOP DAD 32 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5102DADRG4 ACTIVE HTSSOP DAD 32 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5103DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5103DAPG4 ACTIVE HTSSOP DAP 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5103DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5103DAPRG4 ACTIVE HTSSOP DAP 32 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jul-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TAS5102DADR HTSSOP DAD 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1
TAS5103DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jul-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5102DADR HTSSOP DAD 32 2000 346.0 346.0 41.0
TAS5103DAPR HTSSOP DAP 32 2000 346.0 346.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jul-2008
Pack Materials-Page 2
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