PIC18F242-I/SP - Microchip Technology

PIC18FXX2

The PIC18FXX2 Rev. C1 parts you have received

conform functionally to the Device Data Sheet

(DS39564B), except for the anomalies described

below.

All the issues listed here will be addressed in future

revisions of the PIC18FXX2 silicon.

The following silicon errata apply only to

PIC18FXX2 devices with these Device/Revision

IDs:

1. Module: Core (Program Memory Space)

Performing table read operations above the user

program memory space (addresses over

1FFFFFh) may yield erroneous results at the

extreme low end of the device’s rated temperature

range (-40°C).

This applies specifically to addresses above

1FFFFFh, including the user ID locations

(200000h-200007h), the configuration bytes

(300000h-30000Dh) and the device ID locations

(3FFFFEh and 3FFFFFh). User program memory

is unaffected.

Work around

Three possible work arounds are presented. Other

solutions may exist.

1. Do not perform table read operations on areas

above the user memory space at -40°C.

2. Insert NOP instructions (specifically, literal

FFFFh) around any table read instructions.

The suggested optimal number is 4 instruc-

tions before and 8 instructions after each table

read. This may vary depending upon the

particular application and should be optimized

by the user.

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: Data EEPROM

When reading the data EEPROM, the contents of

the EEDATA register may be corrupted if the RD

bit (EECON1<0>) is set immediately following a

write to the address byte (EEADR). The actual

contents of the data EEPROM remain unaffected.

Work around

Do not set EEADR immediately before the

execution of a read. Write to EEADR at least one

instruction cycle before setting the RD bit. The

instruction between the write to EEADR and the

read can be any valid instruction, including a NOP.

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F242 00 0100 100 00111

PIC18F252 00 0100 000 00111

PIC18F442 00 0100 101 00111

PIC18F452 00 0100 001 00111

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

PIC18FXX2 Rev. C1 Silicon/Data Sheet Errata

PIC18FXX2

3. Module: MSSP (All I2C™ and

SPI™ Modes)

The Buffer Full (BF) flag bit of the SSPSTAT

cleared even when the SSPBUF register has not

been read. This will occur only when the following

two conditions occur simultaneously:

• The four Least Significant bits of the BSR

and

• Any instruction that contains C9h in its 8 Least

Significant bits (i.e., register file addresses,

literal data, address offsets, etc.) is executed.

Work around

All work arounds will involve setting the contents of

BSR<3:0> to some value other than 0Fh.

In addition to those proposed below, other

solutions may exist.

1. When developing or modifying code, keep

these guidelines in mind:

• Assign 12-bit addresses to all variables.

This allows the assembler to know when

access banking can be used.

• Do not set the BSR to point to Bank 15

(BSR = 0Fh).

• Allow the assembler to manipulate the

access bit present in most instructions.

Accessing the SFRs in Bank 15 will be done

through the Access Bank. Continue to use

the BSR to select all GPR Banks.

2. If accessing a part of Bank 15 is required and

the use of access banking is not possible,

consider using indirect addressing.

3. If pointing the BSR to Bank 15 is unavoidable,

review the absolute file listing. Verify that no

instructions contain C9h in the 8 Least

Significant bits while the BSR points to Bank 15

(BSR = 0Fh).

Date Codes that pertain to this issue:

All engineering and production devices.

4. Module: Core (Instruction Set)

The Decimal Adjust W register instruction, DAW,

may improperly clear the Carry bit (STATUS<0>)

when executed.

Work around

Test the Carry bit state before executing the DAW

instruction. If the Carry bit is set, increment the

next higher byte to be added using an instruction

such as INCFSZ (this instruction does not affect

any Status flags and will not overflow a BCD nib-

ble). After the DAW instruction has been executed,

process the Carry bit normally (see Example 1).

EXAMPLE 1: PROCESSING THE CARRY

BIT DURING BCD ADDITIONS

5. Module: Reset

It has been observed that in certain Reset condi-

tions, including power-up, the first GOTO instruction

at address 0x0000 may not be executed. This

occurrence is rare and affects very few applications.

To determine if your system is affected, test a

statistically significant number of applications across

the operating temperature, voltage and frequency

ranges of the application. Affected systems will

repeatably fail normal testing. Systems not affected

will continue to not be affected over time.

Work around

Insert a NOP instruction at address 0x0000.

Date Codes that pertain to this issue:

All engineering and production devices.

MOVLW 0x80 ; .80 (BCD)

ADDLW 0x80 ; .80 (BCD)

BTFSC STATUS,C ; test C

INCFSZ byte2 ; inc next higher LSB

DAW

BTFSC STATUS,C ; test C

INCFSZ byte2 ; inc next higher LSB

This is repeated for each DAW instruction.

PIC18FXX2

6. Module: Program Memory

A very small number of applications are

experiencing a low failure rate when using self-

write through code types of applications. The most

common of these are bootloader operations. This

failure mechanism is characterized by a few bytes

in program memory not being written as expected.

If this failure is going to occur, it will occur during a

self-write operation. If a failure is not immediately

observed, then there will be no data retention

issues. The failure does not occur when using an

external programmer through In-Circuit Serial

Programming™ (ICSP™).

This failure mechanism is dependent on the

sequence of instructions executed after self-

writes. Good power supply decoupling minimizes

this issue. It is recommended that you use a 0.1 μF

decoupling capacitor with each power pin pair. The

decoupling capacitor should be placed very close

to the power pins.

It is recommended that you perform statistically

significant testing within your application’s

operating range (i.e., temperature and voltage)

with devices from multiple lots.

Work around

1. This work around only applies to PIC18F252

and PIC18F452 devices.

The program memory is divided into discrete

panels and the failure has only been observed

when a table write is executed from the same

panel it is programming. The table write (self-

write) within the same memory panel (0x0000

to 0x3FFF and 0x4000 to 0x7FFF) initiates a

condition that can cause a failure. The

firmware work around is to duplicate the partial

bootloader (two instantiations of write

functions) in two panels and ensure that the

bootloader code always programs a different

panel from where it resides. To accomplish

this, do the following:

• Receive data from communication channel

(normal operation for the bootloader).

• Identify address to be written.

• If writing to an address within the same

memory panel that you are executing from

(0x0000 to 0x3FFF and 0x4000 to 0x7FFF),

then jump to the opposite memory panel. If

the bootloader resides between location

0x0000 to 0x3FFF, and writing to an

address between 0x0000 to 0x3FFF, then

jump to another instantiation of the code

located between 0x4000 to 0x7FFF and

vice versa.

• Always load holding latches (loading of

TABLAT and then TBLWT*) from the oppo-

site panel. This will require duplicate code in

each panel to load data.

• Always initiate write from the opposite

panel. This will require duplicate code in

each panel for the unlock sequence and

setting up the write bit.

• At the end of the successful write, code can

return to the primary panel to get the next

data.

2. Use a similar device from the PIC18F4520

family.

PIC18FXX2

Clarifications/Corrections to the

Data Sheet:

In the Device Data Sheet (DS39564B), the following

clarifications and corrections should be noted.

1. Module: DC Characteristics

The values for parameters, D005, D010A,

D022A and D022B, shown in Section 22.1 “DC

Characteristics” of the Device Data Sheet have

changed (modified text is shown in bold):

22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended)

PIC18LFXX2 (Industrial)

PIC18LFXX2

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

PIC18FXX2

(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

VBOR Brown-out Reset Voltage

D005 PIC18LFXX2

BORV1:BORV0 = 11 1.96 2.06 2.16 V 85°C ≥ T ≥ 25°C

BORV1:BORV0 = 10 2.64 2.78 2.92 V

BORV1:BORV0 = 01 4.11 4.33 4.55 V

BORV1:BORV0 = 00 4.41 4.64 4.87 V

D005 PIC18FXX2

BORV1:BORV0 = 1x N.A. —N.A. VNot in operating voltage range of device

BORV1:BORV0 = 01 4.16 —4.5 V

BORV1:BORV0 = 00 4.45 —4.83 V

D005 PIC18FXX2

BORV1:BORV0 = 1x N.A. —N.A. VExtended devices operating at 125°C

BORV1:BORV0 = 01 4.07 —4.59 V

BORV1:BORV0 = 00 4.36 —4.92 V

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM

data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and

all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

PIC18FXX2

IDD Supply Current(2,4)

D010A PIC18LFXX2

—1430μA

LP osc, FOSC = 32 kHz, WDT disabled

VDD = 2.0V, -40°C to +85°C

D010A PIC18FXX2

—

150

180

μA

LP osc, FOSC = 32 kHz, WDT disabled

VDD = 4.2V, -40°C to +85°C

VDD = 4.2V, -40°C to +125°C

Module Differential Current

D022A ΔIBOR Brown-out Reset

PIC18LFXX2

—

μA

VDD = 2.0V, +25°C

VDD = 2.0V, -40°C to +85°C

VDD = 4.2V, -40°C to +85°C

D022A Brown-out Reset

PIC18FXX2

—

μA

VDD = 4.2V, +25°C

VDD = 4.2V, -40°C to +85°C

VDD = 4.2V, -40°C to +125°C

D022B ΔILVD Low-Voltage Detect

PIC18LFXX2

—

μA

VDD = 2.0V, +25°C

VDD = 2.0V, -40°C to +85°C

VDD = 4.2V, -40°C to +85°C

D022B Low-Voltage Detect

PIC18FXX2

—

μA

VDD = 4.2V, +25°C

VDD = 4.2V, -40°C to +85°C

VDD = 4.2V, -40°C to +125°C

22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended)

PIC18LFXX2 (Industrial) (Continued)

PIC18LFXX2

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

PIC18FXX2

(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM

data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and

all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

PIC18FXX2

2. Module: Low-Voltage Detect

Characteristics

Some of the values for parameter D420 in

Table 22-1 of the Device Data Sheet have been

updated (modified text is shown in bold).

TABLE 22-1: LOW-VOLTAGE DETECT CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

-40°C ≤ T

A ≤ +125°C for extended

Param

No. Symbol Characteristic Min Typ Max Units Conditions

D420 VLVD LVD Voltage on

VDD transition

high-to-low

LVV = 0001 1.96 2.06 2.16 VT ≥ 25°C

LVV = 0010 2.16 2.27 2.38 VT ≥ 25°C

LVV = 0011 2.35 2.47 2.59 VT ≥ 25°C

LVV = 0100 2.43 2.56 2.69 V

LVV = 0101 2.64 2.78 2.92 V

LVV = 0110 2.75 2.89 3.03 V

LVV = 0111 2.95 3.1 3.26 V

LVV = 1000 3.24 3.41 3.58 V

LVV = 1001 3.43 3.61 3.79 V

LVV = 1010 3.53 3.72 3.91 V

LVV = 1011 3.72 3.92 4.12 V

LVV = 1100 3.92 4.13 4.34 V

LVV = 1101 4.11 4.33 4.55 V

LVV = 1110 4.41 4.64 4.87 V

PIC18FXX2

3. Module: Packaging (Pinout and Product

Identification)

PIC18F442 and PICF452 devices are now offered

in 44-pin, near chip scale micro lead frame pack-

ages (commonly known as “QFN”). This packag-

ing type has been added to the product line since

the latest revision of the Device Data Sheet.

The addition of this option requires the following

additions to the Device Data Sheet (DS39564B).

The referenced figures and tables follow this text.

1. The “Pin Diagrams” on pages 2-3 of the Data

Sheet are amended with the addition of the

44-pin QFN pinout, shown in Figure 1.

2. Table 1-3 of Section 1.0 “Device Overview”

is replaced with an updated version which

adds a column for QFN pin assignments. A row

is also added for previously unlisted NC pins.

All new information is indicated in bold.

3. Section 24.1 “Package Marking Information”

is amended to include a marking template and

example for 44-pin QFN devices. These are

shown in Figure 2.

4. Section 24.2 “Package Details” is amended

to include the mechanical drawing of the 44-pin

QFN package, shown in Figure 3.

5. In the “PIC18FXX2 Product Identification

System” (page 329), the “Package” options

are amended to include the new line item:

ML = QFN

6. For the sake of completeness, it is also noted

that the package designation “MLF” is now

replaced by “QFN” in all occurrences through-

out the Device Data Sheet. “MLF” should be

considered an obsoleted term.

FIGURE 1: PINOUT DIAGRAM FOR PIC18F442/452, 44-PIN QFN PACKAGE

FIGURE 2: PACKAGE MARKING TEMPLATE FOR PIC18F442/452, 44-PIN QFN

PIC18F442

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

MCLR/VPP

RB3/CCP2*

RB7/PGD

RB6/PGC

RB5/PGM

RB4

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2*

RC0/T1OSO/T1CKI

OSC2/CLKO/RA6

OSC1/CLKI

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4/SS/LVDIN

RA4/T0CKI

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

VDD

RB0/INT0

RB1/INT1

RB2/INT2

QFN

PIC18F452

*RB3 is the alternate pin for the CCP2 pin multiplexing.

XXXXXXXXXX

44-Lead QFN

XXXXXXXXXX

YYWWNNN

PIC18F442

Example

-I/ML

0510017

PIC18FXX2

TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number Pin

Type

Buffer

Type Description

DIP PLCC QFN TQFP

MCLR/VPP

MCLR

VPP

1218 18

Master Clear (input) or high-voltage ICSP™

programming enable pin.

Master Clear (Reset) input. This pin is an active

low Reset to the device.

High-voltage ICSP programming enable pin.

NC — 32 — — These pins should be left unconnected.

OSC1/CLKI

OSC1

CLKI

13 14 33 30

CMOS

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source

input. ST buffer when configured in RC mode,

CMOS otherwise.

External clock source input. Always associated

with pin function OSC1. (See related

OSC1/CLKI, OSC2/CLKO pins.)

OSC2/CLKO/RA6

OSC2

CLKO

RA6

14 15 31

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal

or resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO, which

has 1/4 the frequency of OSC1 and denotes the

instruction cycle rate.

General purpose I/O pin.

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

2319 19

I/O

TTL

Analog

Digital I/O.

Analog input 0.

RA1/AN1

RA1

AN1

3420 20

I/O

TTL

Analog

Digital I/O.

Analog input 1.

RA2/AN2/VREF-

RA2

AN2

VREF-

4521 21

I/O

TTL

Analog

Digital I/O.

Analog input 2.

A/D Reference Voltage (Low) input.

RA3/AN3/VREF+

RA3

AN3

VREF+

5622 22

I/O

TTL

Analog

Digital I/O.

Analog input 3.

A/D Reference Voltage (High) input.

RA4/T0CKI

RA4

T0CKI

6723 23

I/O

ST/OD

Digital I/O. Open-drain when configured as output.

Timer0 external clock input.

RA5/AN4/SS/LVDIN

RA5

AN4

LVDIN

7824 24

I/O

TTL

Analog

Digital I/O.

Analog input 4.

SPI™ Slave Select input.

Low-Voltage Detect input.

RA6 (See the OSC2/CLKO/RA6 pin.)

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

OD = Open-Drain (no P diode to VDD)

PIC18FXX2

PORTB is a bidirectional I/O port. PORTB can be

software programmed for internal weak pull-ups on

all inputs.

RB0/INT0

RB0

INT0

33 36 98

I/O

TTL

Digital I/O.

External Interrupt 0.

RB1/INT1

RB1

INT1

34 37 10 9

I/O

TTL

Digital I/O.

External Interrupt 1.

RB2/INT2

RB2

INT2

35 38 11 10

I/O

TTL

Digital I/O.

External Interrupt 2.

RB3/CCP2

RB3

CCP2

36 39 12 11

I/O

TTL

Digital I/O.

Capture2 input, Compare2 output, PWM2 output.

RB4 37 41 14 14 I/O TTL Digital I/O. Interrupt-on-change pin.

RB5/PGM

RB5

PGM

38 42 15 15

I/O

TTL

Digital I/O. Interrupt-on-change pin.

Low-voltage ICSP™ programming enable pin.

RB6/PGC

RB6

PGC

39 43 16 16

I/O

TTL

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming

clock pin.

RB7/PGD

RB7

PGD

40 44 17 17

I/O

TTL

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data

pin.

TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

DIP PLCC QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

OD = Open-Drain (no P diode to VDD)

PIC18FXX2

PORTC is a bidirectional I/O port.

RC0/T1OSO/T1CKI

RC0

T1OSO

T1CKI

15 16 34 32

I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2

RC1

T1OSI

CCP2

16 18 35 35

I/O

CMOS

Digital I/O.

Timer1 oscillator input.

Capture2 input, Compare2 output,

PWM2 output.

RC2/CCP1

RC2

CCP1

17 19 36 36

I/O

Digital I/O.

Capture1 input/Compare1 output/

PWM1 output.

RC3/SCK/SCL

RC3

SCK

SCL

18 20 37 37

I/O

Digital I/O.

Synchronous serial clock input/output for

SPI™ mode.

Synchronous serial clock input/output for

I2C™ mode.

RC4/SDI/SDA

RC4

SDI

SDA

23 25 42 42

I/O

Digital I/O.

SPI Data In.

I2C Data I/O.

RC5/SDO

RC5

SDO

24 26 43 43

I/O

—

Digital I/O.

SPI Data Out.

RC6/TX/CK

RC6

25 27 44 44

I/O

—

Digital I/O.

USART Asynchronous Transmit.

USART Synchronous Clock

(see related RX/DT).

RC7/RX/DT

RC7

26 29 11

I/O

Digital I/O.

USART Asynchronous Receive.

USART Synchronous Data

(see related TX/CK).

TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

DIP PLCC QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

OD = Open-Drain (no P diode to VDD)

PIC18FXX2

PORTD is a bidirectional I/O port, or a Parallel Slave

Port (PSP) for interfacing to a microprocessor port.

These pins have TTL input buffers when the PSP

module is enabled.

RD0/PSP0 19 21 38 38 I/O ST

TTL

Digital I/O.

Parallel Slave Port Data.

RD1/PSP1 20 22 39 39 I/O ST

TTL

Digital I/O.

Parallel Slave Port Data.

RD2/PSP2 21 23 40 40 I/O ST

TTL

Digital I/O.

Parallel Slave Port Data.

RD3/PSP3 22 24 41 41 I/O ST

TTL

Digital I/O.

Parallel Slave Port Data.

RD4/PSP4 27 30 22 I/O ST

TTL

Digital I/O.

Parallel Slave Port Data.

RD5/PSP5 28 31 33 I/O ST

TTL

Digital I/O.

Parallel Slave Port Data.

RD6/PSP6 29 32 44 I/O ST

TTL

Digital I/O.

Parallel Slave Port Data.

RD7/PSP7 30 33 55 I/O ST

TTL

Digital I/O.

Parallel Slave Port Data.

PORTE is a bidirectional I/O port.

RE0/RD/AN5

RE0

AN5

8925 25 I/O

TTL

Analog

Digital I/O.

Read control for parallel slave port

(see also WR and CS pins).

Analog input 5.

RE1/WR/AN6

RE1

AN6

91026 26 I/O

TTL

Analog

Digital I/O.

Write control for parallel slave port

(see CS and RD pins).

Analog input 6.

RE2/CS/AN7

RE2

AN7

10 11 27 27 I/O

TTL

Analog

Digital I/O.

Chip Select control for parallel slave port

(see related RD and WR).

Analog input 7.

VSS 12,

13, 34 6, 30,

6, 29 P — Ground reference for logic and I/O pins.

VDD 11,

12, 35 7, 8,

28, 29

7, 28 P — Positive supply for logic and I/O pins.

NC — 1, 17,

13 12, 13,

33, 34

— — These pins are not internally connected. They

should be left unconnected.

TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

DIP PLCC QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

OD = Open-Drain (no P diode to VDD)

PIC18FXX2

FIGURE 3: 44-PIN QFN PACKAGE

TOP VIEW

BOTTOM VIEW

PAD

METAL

EXPOSED

PIN 1

INDEX ON

EXPOSED PAD

TOP MARKING

INDEX ON

OPTIONAL PIN 1

DETAIL: CONTACT VARIANTS

(PROFILE MAY VARY)

2. REF: Reference Dimension, usually without tolerance, for information purposes only.

1. BSC: Basic Dimension. Theoretically exact value shown without tolerances.

A3Base Thickness .010 REF

JEDEC equivalent: M0-220

Exposed Pad Length

Exposed Pad Width

Contact Length

Overall Length

Overall Width

Notes:

Drawing No. C04-103, Revised 05-05-05

*Controlling Parameter

Contact Width

See ASME Y14.5M

.008

.014

.236

.309

.258

.016

.013

.315

.258

.315

Overall Height

Standoff

Number of Contacts

Pitch

Dimension Limits

Units

.000

.031

MIN

.026 BSC

.001

.035

NOM

INCHES

0.25 REF

8.00

6.55

0.40

8.00

0.33

.260

.019

.013

.321

.260

0.20

0.35

5.99

7.85

0.35

0.48

6.60

8.15

0.02

0.90

0.65 BSC

MILLIMETERS*

MIN

.039

.002

MAX

0.80

NOM

0.05

1.00

MAX

Exposed pad varies according to die attach paddle size.

44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)

PIC18FXX2

REVISION HISTORY

Rev A Document (08/2005)

First revision of this document. Listed silicon issues

1 (Core – Program Memory Space), 2 (Data

EEPROM), 3 (MSSP), 4 (Core – Instruction Set), 5

(Reset) and 6 (Program Memory), and data sheet

clarification issues 1 (DC Characteristics),

2 (Low-Voltage Detect Characteristics) and

3 (Packaging – Pinout and Product Identification).

PIC18FXX2

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. Use of Microchip’s products as critical components in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,

Smart Serial, SmartTel, Total Endurance and WiperLock are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro

8-bit MCUs, KEELOQ

code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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08/24/05