1. General description
The 74HC373; 74HCT373 is an octal D-type transparent latch with 3-state outputs. The
device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data
at the inputs enter the latches. In this condition the latches are transparent, a la tch output
will change each time its corresponding D-input changes. When LE is LOW the latches
store the information that was present at the inputs a set-up time preceding the
HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches. Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inp uts to voltages in excess of VCC.
2. Features and benefits
Input levels:
For 74HC373: CMOS level
For 74HCT373: TTL level
3-state non-inverting outputs for bus oriented applications
Common 3-state output enable input
Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573
Complies with JEDEC standard no. 7 A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce ed s 20 0 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 6 — 26 February 2016 Product data sheet
Table 1. Ordering information
Type number Package
Temperatur e ra nge Name Description Version
74HC373D 40 C to +125 C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74HCT373D
74HC373DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HCT373DB
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 2 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
4. Functional diagram
74HC373PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74HCT373PW
74HC373BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
74HCT373BQ
Table 1. Ordering information …continued
Type number Package
Temperatur e ra nge Name Description Version
Fig 1. Functional di agram
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Fig 2. Logic symbol Fig 3. IEC logic symbol
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74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 3 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 4. Logic diagra m (one latch)
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Fig 5. Logic diag ram
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74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 4 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration SO20, SSOP20 and
TSSOP20 Fig 7. Pin configuration DHVQFN20
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Table 2. Pin description
Symbol Pin Description
OE 1 3-state output enable input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 3-state latch output
D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input
GND 10 ground (0 V)
LE 11 latch enable input (active HIGH)
VCC 20 supply voltage
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 5 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
6. Functional description
6.1 Function table
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
[1] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
[2] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[3] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table[1]
Operating mode Control Input Internal latches Output
OE LE Dn Qn
Enable and read register
(transparent mode) LHLL L
HH H
Latch and read register L L l L L
hH H
Latch register and disable
outputs HXXX Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput curren t VO = 0.5 V to (VCC +0.5V) - 35 mA
ICC supply current - +70 mA
IGND ground current - 70 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation SO20 package [1] -500mW
SSOP20 package [2] -500mW
TSSOP20 package [2] -500mW
DHVQFN20 package [3] -500mW
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 6 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC373 74HCT373 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics 74HC373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL ---
IO=20 A; VCC =2.0V 1.9 2.0 - V
IO=20 A; VCC =4.5V 4.4 4.5 - V
IO=20 A; VCC =6.0V 5.9 6.0 - V
IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - V
IO = 7.8 mA; VCC = 6.0 V 5.48 5.81 - V
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 V
IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 V
IIinput leakage curren t VI=V
CC or GND; VCC = 6.0 V - - 0.1 A
IOZ OFF-st ate output curr en t VI=V
IH or VIL; VCC =6.0V;
VO=V
CC or GND --0.5 A
ICC supply current VCC = 6.0 V ; IO = 0 A;
VI=V
CC or GND --8.0A
CIinput capacitance - 3.5 - pF
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 7 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Tamb =40 Cto+85C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO=20 A; VCC =2.0V 1.9 - - V
IO=20 A; VCC =4.5V 4.4 - - V
IO=20 A; VCC =6.0V 5.9 - - V
IO = 6.0 mA; VCC = 4.5 V 3.84 - - V
IO = 7.8 mA; VCC = 6.0 V 5.34 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.33 V
IO = 7.8 mA; VCC = 6.0 V - - 0.33 V
IIinput leakage curren t VI=V
CC or GND; VCC = 6.0 V - - 1.0 A
IOZ OFF-st ate output curr en t VI=V
IH or VIL; VCC =6.0V;
VO=V
CC or GND --5.0 A
ICC supply current VCC = 6.0 V ; IO =0 A;
VI=V
CC or GND --80A
Tamb =40 C to +125 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO=20 A; VCC =2.0V 1.9 - - V
IO=20 A; VCC =4.5V 4.4 - - V
IO=20 A; VCC =6.0V 5.9 - - V
IO = 6.0 mA; VCC = 4.5 V 3.7 - - V
IO = 7.8 mA; VCC = 6.0 V 5.2 - - V
Table 6. Static characteristics 74HC373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 8 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - - 0.4 V
IIinput leakage curren t VI=V
CC or GND; VCC = 6.0 V - - 1.0 A
IOZ OFF-st ate output curr en t VI=V
IH or VIL; VCC =6.0V;
VO=V
CC or GND --10.0 A
ICC supply current VCC = 6.0 V ; IO = 0 A;
VI=V
CC or GND - - 160 A
Table 6. Static characteristics 74HC373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 7. Static characteristics 74HCT373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 4.5 - V
IO=6.0 mA; VCC = 4.5 V 3.98 4.32 - V
VOL LOW-level output voltage VI=V
IH or VIL
IO=20A; VCC = 4.5 V - 0.0 0.1 V
IO=6.0mA; V
CC = 4.5 V - 0.16 0.26 V
IIinput leakage curren t VI=V
CC or GND; VCC =5.5V - - 0.1 A
IOZ OFF-st ate output curr en t VI=V
IH or VIL; VCC =5.5V;
VO=V
CC or GND --0.5 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V --8.0A
ICC additional supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO=0A
Dn - 30 108 A
LE - 150 540 A
OE - 100 360 A
CIinput capacitance - 3.5 - pF
Tamb =40 C to +85 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 - - V
IO=6.0 A; VCC =4.5V 3.84 - - V
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 9 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
VOL LOW-level output voltage VI=V
IH or VIL
IO=20A; VCC = 4.5 V - - 0.1 V
IO=6.0mA; V
CC =4.5V - - 0.33 V
IIinput leakage curren t VI=V
CC or GND; VCC =5.5V - - 1.0 A
IOZ OFF-st ate output curr en t VI=V
IH or VIL; VCC =5.5V;
VO=V
CC or GND --5.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V --80A
ICC additional supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO=0A
Dn - - 135 A
LE - - 675 A
OE - - 450 A
Tamb =40 C to +125 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 - - V
IO=6.0 mA; VCC =4.5V 3.7 - - V
VOL LOW-level output voltage VI=V
IH or VIL
IO=20A; VCC = 4.5 V - - 0.1 V
IO=6.0mA; V
CC =4.5V - - 0.4 V
IIinput leakage curren t VI=V
CC or GND; VCC =5.5V - - 1.0 A
IOZ OFF-st ate output curr en t VI=V
IH or VIL; VCC =5.5V;
VO=V
CC or GND --10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 160 A
ICC additional supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO=0A
Dn - - 147 A
LE - - 735 A
OE - - 490 A
Table 7. Static characteristics 74HCT373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 10 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 8. Dynamic characteristics 74HC373
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
tpd propagation delay Dn to Qn; see Figure 8 [1]
VCC = 2.0 V - 41 150 ns
VCC = 4.5 V - 15 30 ns
VCC =5V; C
L=15pF - 12 - ns
VCC = 6.0 V - 12 26 ns
LE to Qn; see Figure 9
VCC = 2.0 V - 50 175 ns
VCC = 4.5 V - 18 35 ns
VCC =5V; C
L=15pF - 15 - ns
VCC = 6.0 V - 14 30 ns
ten enable time OE to Qn; see Figure 10 [2]
VCC = 2.0 V - 44 150 ns
VCC = 4.5 V - 16 30 ns
VCC = 6.0 V - 13 2 6 ns
tdis disable time OE to Qn; see Figure 10 [3]
VCC = 2.0 V - 47 150 ns
VCC = 4.5 V - 17 30 ns
VCC = 6.0 V - 14 2 6 ns
tttransition time Qn; see Figure 8 and Figure 9 [4]
VCC = 2.0 V - 14 60 ns
VCC = 4.5 V - 5 12 ns
VCC = 6.0 V - 4 10 ns
tWpulse width LE HIGH; see Figure 9
VCC = 2.0 V 80 17 - ns
VCC = 4.5 V 16 6 - ns
VCC = 6.0 V 14 5 - ns
tsu set-up time Dn to LE; see Figure 11
VCC = 2.0 V 50 14 - ns
VCC = 4.5 V 10 5 - ns
VCC = 6.0 V 9 4 - ns
thhold time Dn to LE; see Figure 11
VCC = 2.0 V +5 8-ns
VCC = 4.5 V +5 3-ns
VCC = 6.0 V +5 2-ns
CPD power dissipation capacitance per latch; VI=GNDtoV
CC [5] -45-pF
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 11 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Tamb =40 Cto+85C
tpd propagation delay Dn to Qn; see Figure 8 [1]
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
LE to Qn; see Figure 9
VCC = 2.0 V - - 220 ns
VCC = 4.5 V - - 44 ns
VCC = 6.0 V - - 37 ns
ten enable time OE to Qn; see Figure 10 [2]
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
tdis disable time OE to Qn; see Figure 10 [3]
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
tttransition time Qn; see Figure 8 and Figure 9 [4]
VCC = 2.0 V - - 75 ns
VCC = 4.5 V - - 15 ns
VCC = 6.0 V - - 13 ns
tWpulse width LE HIGH; see Figure 9
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
tsu set-up time Dn to LE; see Figure 11
VCC = 2.0 V 65 - - ns
VCC = 4.5 V 13 - - ns
VCC = 6.0 V 11 - - ns
thhold time Dn to LE; see Figure 11
VCC = 2.0 V 5 - - ns
VCC = 4.5 V 5 - - ns
VCC = 6.0 V 5 - - ns
Table 8. Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 12 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Tamb =40 C to +125 C
tpd propagation delay Dn to Qn; see Figure 8 [1]
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
LE to Qn; see Figure 9
VCC = 2.0 V - - 265 ns
VCC = 4.5 V - - 53 ns
VCC = 6.0 V - - 45 ns
ten enable time OE to Qn; see Figure 10 [2]
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
tdis disable time OE to Qn; see Figure 10 [3]
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
tttransition time Qn; see Figure 8 and Figure 9 [4]
VCC = 2.0 V - - 90 ns
VCC = 4.5 V - - 18 ns
VCC = 6.0 V - - 15 ns
tWpulse width LE HIGH; see Figure 9
VCC = 2.0 V 120 - - ns
VCC = 4.5 V 24 - - ns
VCC = 6.0 V 20 - - ns
tsu set-up time Dn to LE; see Figure 11
VCC = 2.0 V 75 - - ns
VCC = 4.5 V 15 - - ns
VCC = 6.0 V 13 - - ns
Table 8. Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 13 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
[1] tpd is the same as tPLH and tPHL.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
thhold time Dn to LE; see Figure 11
VCC = 2.0 V 5 - - ns
VCC = 4.5 V 5 - - ns
VCC = 6.0 V 5 - - ns
Table 8. Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
Table 9. Dynamic characteristics 74HCT373
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25C
tpd propagation delay Dn to Qn; see Figure 8 [1]
VCC = 4.5 V - 17 30 ns
VCC =5V; C
L=15pF - 14 - ns
LE to Qn; see Figure 9
VCC = 4.5 V - 16 32 ns
VCC =5V; C
L=15pF - 13 - ns
ten enable time OE to Qn; see Figure 10 [2]
VCC = 4.5 V - 19 32 ns
tdis disable time OE to Qn; see Figure 10 [3]
VCC = 4.5 V - 18 30 ns
tttransition time Qn; see Figure 8 and Figure 9 [4]
VCC = 4.5 V - 5 12 ns
tWpulse width LE HIGH; see Figure 9
VCC = 4.5 V 16 4 - ns
tsu set-up time Dn to LE; see Figure 11
VCC = 4.5 V 12 6 - ns
thhold time Dn to LE; see Figure 11
VCC = 4.5 V 4 1-ns
CPD power dissipation capacitance per latch;
VI=GNDto(V
CC 1.5 V) [5] -41-pF
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 14 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Tamb =40 Cto+85C
tpd propagation delay Dn to Qn; see Figure 8 [1]
VCC = 4.5 V - - 38 ns
LE to Qn; see Figure 9
VCC = 4.5 V - - 40 ns
ten enable time OE to Qn; see Figure 10 [2]
VCC = 4.5 V - - 40 ns
tdis disable time OE to Qn; see Figure 10 [3]
VCC = 4.5 V - - 38 ns
tttransition time Qn; see Figure 8 and Figure 9 [4]
VCC = 4.5 V - - 15 ns
tWpulse width LE HIGH; see Figure 9
VCC = 4.5 V 20 - - ns
tsu set-up time Dn to LE; see Figure 11
VCC = 4.5 V 15 - - ns
thhold time Dn to LE; see Figure 11
VCC = 4.5 V 4 - - ns
Tamb =40 C to +125 C
tpd propagation delay Dn to Qn; see Figure 8 [1]
VCC = 4.5 V - - 45 ns
LE to Qn; see Figure 9
VCC = 4.5 V - - 48 ns
ten enable time OE to Qn; see Figure 10 [2]
VCC = 4.5 V - - 48 ns
tdis disable time OE to Qn; see Figure 10 [3]
VCC = 4.5 V - - 45 ns
tttransition time Qn; see Figure 8 and Figure 9 [4]
VCC = 4.5 V - - 18 ns
tWpulse width LE HIGH; see Figure 9
VCC = 4.5 V 24 - - ns
tsu set-up time Dn to LE; see Figure 11
VCC = 4.5 V 18 - - ns
Table 9. Dynamic characteristics 74HCT373 …co n tinue d
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 15 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
[1] tpd is the same as tPLH and tPHL.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
thhold time Dn to LE; see Figure 11
VCC = 4.5 V 4 - - ns
Table 9. Dynamic characteristics 74HCT373 …co n tinue d
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
Measurement points are given in Table 10.
Fig 8. Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
DDH
'QLQSXW
4QRXWSXW
90
W3/+ W3+/
W7+/
W7/+
90
Measurement points are given in Table 10.
Fig 9. Pulse width latch enabl e i np ut (L E), pro pagati on de la y (L E) to output (Qn) and transition time out put (Qn)
90
90
W3/+
W3+/
W:
/(LQSXW
4QRXWSXW
DDH
W7/+
W7+/
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 16 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Measurement points are given in Table 10.
Fig 10. 3-state enable and disable time
DDH
W3/=
W3+=
RXWSXWV
GLVDEOHG
RXWSXWV
HQDEOHG
RXWSXWV
HQDEOHG
RXWSXW
/2:WR2))
2))WR/2:
RXWSXW
+,*+WR2))
2))WR+,*+
2(LQSXW
9,
92/
92+
9&&
90
*1'
*1'
W3=/
W3=+
90
90
Measurement points are given in Table 10.
Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE)
DDH
90
/(LQSXW
'QLQSXW 90
WK
WVX
WK
WVX
Table 10 . Measurement points
Type Input Output
VMVM
74HC373 0.5VCC 0.5VCC
74HCT373 1.3 V 1.3 V
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 17 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
9
0
9
0
W
:
W
:
9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0
W
I
W
U
W
U
W
I
DDG
'87
9
&&
9
&&
9,92
57
5/6
&/
RSHQ
*
Table 11. Test da ta
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC373 VCC 6ns 15pF, 50 pF 1kopen GND VCC
74HCT373 3 V 6 ns 15 pF, 50 pF 1 kopen GND VCC
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 18 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
12. Package outline
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74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 19 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 14. Package outline SOT339-1 (SSOP20)
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74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 20 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 15. Package outline SOT360-1 (TSSOP20)
81,7 $
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74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 21 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Fig 16. Package outline SOT764-1 (DHVQFN20)
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74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 22 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
13. Abbreviations
14. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT373 v.6 20160226 Product data sheet - 74HC_HCT373 v.5
Modifications: •Type numbers 74HC373N and 74HCT373N (SOT146-1) removed.
74HC_HCT373 v.5 20111213 Product data sheet - 74HC_HCT373 v.4
Modifications: •Legal pages updated.
74HC_HCT373 v.4 20100903 Product data sheet - 74HC_HCT373 v.3
74HC_HCT373 v.3 20060120 Product data sheet - 74HC_HCT373_CNV v.2
74HC_HCT373_CNV v.2 19970827 Product specification - -
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 23 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the applica tion or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data fro m the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
74HC_HCT373 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 6 — 26 February 2016 24 of 25
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qual ified,
the product is not suitable for automotive use. It is neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC373; 74HCT373
Octal D-type transparent latch; 3-state
© NXP Semiconductors N.V. 2016. All rig hts reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 February 2016
Document identifier: 74HC_HCT373
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16 Contact information. . . . . . . . . . . . . . . . . . . . . 24
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
