WwW WHITE MICROELECTRONICS WE128K32-XXX 128Kx32 EEPROM MODULE @ Automatic Page Write Operation M@ Page Write Cycle Time: 10 mS Max. FEATURES M@ Data Polling for End of Write Detection M@ Hardware and Software Data Protection @ Access Times of 150nS, 200nS, 250nS and 300nS @ Packaging: . . . . . @ TTL Compatible Inputs and Outputs 66-pin, PGA Type, 1.185 inch square HIP, Hermetic Ceramic Package, SMD Number 5962-94585 Mi 5 Volt Power Supply 68 lead. 40mm COFP @ Built in Decoupling Caps and Multiple Ground Pins for Low _ Noise Operation @ Organized as 128Kx32; User Configurable as 256Kx16 or 512Kx8 m Weight Mi Data Retention Ten Years Minimum WE128K32-XHX - 13 grams typical H Commercial, Industrial and Military Temperature Ranges WE128K32-XG4xX - 20 grams typical Mi Low Power CMOS, 5mA Standby FIG. 1 PIN CONFIGURATION FOR WE128K32-XHX, SMD5962-94585 PIN DESCRIPTION 1 12 23 a4 45 56 V/Oo-31 | Data Inputs/Outputs Ovoe Owe: Ovois WOx% OQ) Veo) WOO) Ao-16 Address Inputs Olos OC& Ovou vO C) C&O) vox WE1-4 Write Enables Ovo Oond OQvor WOO) WEA) WOat) CS1-4 Chip Selects Can Cron Ovo AsO vO2O) von BLOCK DIAGRAM OE Output Enable Oaw Oaw Ode aC AO oO WE: CS WE2CS WE3CS WE.CS Oa 10 7 a Ae WE: CS WE2 CS2 WE3CSa WE. CS. OE : t | ? { TI Vcc Power Supply _ a - Cas Oan One NCO OQ AO Ao-A1s. SP oI oe 1 | GND Ground Oas Can Owe: A> ASO) Ae Ne a A NY _ 128K xB 128K x 8 128K x8 128K x 8 NC Not Connected Cne Ovee Oor AsO WE) vont) Ciao OCS: Oids VOsQ C&O) vox ! 8 Cver One Cos vOrO GNOO vOerO +h toe ti te : gd ut wp) lay {Cu Ovos Ovos WOo8O) Ww) HOC 00-7 \oa-15 1016-28 vOz4-a1 Nn RB 8 4 B88 1D0401/1D0501 FIG. 2 PIN CONFIGURATION FOR WE128K32-XG4X PIN DESCRIPTION (/O0-31| Data Inputs/Outputs A0-16 Address Inputs WE Write Enable BLOCK DIAGRAM & Te ag & CS1-4 Chip Selects T T qT | | { j | I | oo vor oe vos I va vos | vos | | vor J i GND vos | vos vO: 4 | von cy Wore | vora vou oo vos OE Output Enable TT T TTI TT T Tt vec Power Supply 128K x B 128K x 8 128K x 8 128K x8 GND Ground NC Not Connected VOo-7 VWOs-15 016-23 1024-31 August 1994 3-27 White Microelectronics * Phoenix, AZ * (602) 437-1520 SJINGOW WO0dds4 cI("4 WHITE MICROELECTRONICS WE128K32-XXX ABSOLUTE MAXIMUM RATINGS TRUTH TABLE SJINGOIW WOddI4 Parameter Symbol Unit cs OE WE Mode Data 1/0 Operating Temperature TA ~55 to +125 C H x x Standby High Z Storage Temperature Tst -65 to +150 C L L H Read Data Qut Signal Voltage Relative to GND Ve -0.6 to +6.25 Vv L , ; F oT Hi ee | X ut Disable ig a-Ou Voltage an OE and Ag 0.6 to +13.5 X X 1 Write NOTE: a Stresses above those listed under Absolute Maximum Ratings" may cause x L x inhibit permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAPACITANCE RECOMMENDED OPERATING CONDITIONS {TA = 25 C) Parameter Symbol Min Max Unit Parameter Symbol Condition Max | Unit Supply Voltage Vee 45 5.5 Vv Ao-A1a Cap Vin = OV, f = 1.0MHz 50 pF Input High Voltage VK 2.0 Veo+03 | V OE Capacitance Coe Input Low Voltage VIL -0.5 40.8 V CS Capacitance Ccs Vin = OV, f = 1.0MHz 15 pF Operating Temp. (Mil.) TA 55 +125 C WE Capacitance Cwe | Vin-OV,f=1.0MHz | 15 | pF Operating Temp. (Ind.) Ta -40 +85 C \/Oo-1/031 Capacitance Cio Vin = OV, f = 1.0MHz 15 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (Vcc = SV, Vss = OV, TA = -55C ta +125C} Parameter Symbol Conditions Min Max | Unit Input Leakage Current HL Vcc = 5.5, VIN = GND to Vcc 10 pA Output Leakage Current ILox32 CS = Vin, OE = Vin, Vout = GND to Vec 10 pA Operating Supply Current x 32 Mode Iocx32. | CS = Vi, OE = Vin, f = 5MHz 250 | mA Standby Current ISB CS = Vcc, OE = Vin, f = 5MHz 2.5 mA Output Low Voltage VoL lol = 2.1mA, Vcc = 4.5V 0.45 Vv Qutput High Voltage VOH low = -400pA, VCC = 4.5V 2.4 Vv FIG. 3 AC TEST CONDITIONS AC TEST CIRCUIT 2 Parameter Typ Unit Current Source Input Pulse Levels ViL=0, Vin=3.0] V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 Vv D.U.T. Vz = 1.5V Output Timing Reference Level 50 V Coy = 50 pf (Bipolar Supply) NOTES: Vz is programmable from -2V to +7V lot & lon programmable from C to 16mA Tester Impedance Zo = 75 Q. \ Vz is typically the midpoint of Vor and Vo. OH lot & lon are adjusted to simulate a typical resistive load circuit. Current Source ATE tester includes jig capacitance. White Microelectronics * Phoenix, AZ * (602) 437-1520 3-28"4 WHITE MICROELECTRONICS iTS 2:1 720.84 WRITE A write cycle is initiated when OE is high and a low pulse is on WE or CS with CS or WE tow. The address is latched on the falling edge of CS or WE whichever occurs last. The data is latched by the rising edge of CS or WE, whichever occurs first. A byte write operation will automatically continue to completion. WRITE CYCLE TIMING Figures 4 and 5 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS tine low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low. The WE line transition from high to low also initiates an internal 150 pSec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150 uSec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. AC WRITE CHARACTERISTICS (Vcc = 5V, Vss= OV, TA= -55C to +125C) Write Cycle Parameter Symbol | Min | Max | Unit Write Cycle Time, TYP = 6 mS twe 10 ms Address Set-up Time tas 10 ns Write Pulse Width (WE or CS) twe | 150 ns Chip Select Set-up Time tes 0 ns Address Hold Time tAH 100 ns Data Hold Time tou 10 ns Chip Select Hold Time tcsH 0 ns Data Set-up Time tbs 100 ns Output Enable Set-up Time toes 10 ns Qutput Enable Hold Time tOEH 10 ns Write Pulse Width High tWPH 50 ns 3-29 White Microelectronics * Phoenix, AZ * (602) 437-1520 SJTNGOIW WOddI4 coSJINGOW WOddI3 ey a Witte eteteiten tee rape cree FIG. 4 WRITE WAVEFORMS WE CONTROLLED DATA IN FIG. 5 WRITE WAVEFORMS CS CONTROLLED DATA IN tos | White Microelectronics * Phoenix, AZ * (602) 437-1520 3-30("4 WHITE MICROELECTRONICS SPE ye oo The WE128K32-XXX stores data at the memory location determined by the address pins. When CS and OE are low and WE is high, this data is present on the outputs. When CS and OE are high, the outputs are in a high impedance state. This 2 line control prevents bus contention. AC READ CHARACTERISTICS (Vec= 5V, Vss= OV, Ta= -55C to +125C)} Read Cycle Parameter Symbol -150 -200 -250 -300 Unit Min Max Min Max Min Max Min Max Read Cycle Time tRC 150 200 250 300 ns Address Access Time tacc 150 200 250 300 ns Chip Select Access Time tacs 150 200 250 300 ns Output Hold from Add. Change, OE or CS tow 0 0 0 0 ns Output Enabie to Gutput Valid toe 0 85 0 85 0 100 0 125 ns Chip Select or OE to High Z Output tor 70 70 70 70 ns FIG. 6 READ WAVEFORMS ~_~ tac ADDRESS ADDRESS VALID cs i tacs >| OE 5 toe *| | tor t NOTES: Ace ton OE may be delayed up to tacs - toc after the HIGH Z q OUTPUT falling edge of CS without impact on toe or by OUTPUT 4 VALID 7 tacc - toe after an address change without impact on tacc. 3-31 White Microelectronics * Phoenix, AZ (602) 437-1520 STINGOW WOdd3d4 cISJINGOW WOYd34 o | "4 WHITE MICROELECTRONICS WE128K32-XXX DATA POLLING The WE128K32-XXxX offers a data polling feature which allows a faster method of writing to the device. Figure 7 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on 1/07. Once the write cycle has been completed, true data Is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. DATA POLLING CHARACTERISTICS (Vec= 5V, Vss= OV, TA= -55C to +125C) Parameter Symbol | Min | Max | Unit Data Hold Time {DH 10 ns OE Hold Time toeH 10 ns GE To Output Valid tOE 100 | ns Write RecoveryTime twR 0 ns FIG. 7 DATA POLLING WAVEFORMS WE1.4 A AG-A14 x x White Microelectronics * Phoenix, AZ * (602) 437-1520 3-32"4 WHITE MICROELECTRONICS WE128K32-XXX PAGE WRITE OPERATION PAGE WRITE CHARACTERISTICS (Vec = 5V, Vss= OV, TA= -55C to +125C} The WE128K32-XXX has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively Page Mode Write Characteristics Symbol Unit loads during the internal programming period. Successive bytes Parameter Min | Max may be loaded in the same manner after the first data byte has Write Cycle Time, TYP = 6 mS we 10 | ms been loaded. An internal timer begins a time out operation at each - write cycle. If another write cycle is completed within 150uS or Address Set-up Time as | 10 ns less, a new time out period begins. Each write cycle restarts the Address Hold Time (1) tan | 100 ns delay period. The write cycles can be continued as long as the Data Set-up Time tos | 100 ns interval is less than the time out period. Data Hold Time toy 10 ns The usual! procedure is to increment the least significant Write Pulse Width tw | 150 ns address lines from AQ through A6 at each write cycle. In this Byte Load Cycle Time taic 150 | us manner a page of up to 128 bytes can be loaded in to the Write Pulse Width High twer | 50 ns EEPROM ina burst mode before beginning the relatively long 1, Page address must remain valid for duration of write cycle. interval programming cycle. After the 150uS time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. FIG. 8 PAGE MODE WRITE WAVEFORMS OA twe twen tauc _ |, WEx AO-AG ADORESS: x x tos >| DATA YXensooarat BYTE Cc x ave? @YTE 127 3-33 White Microelectronics * Phoenix, AZ (602) 437-1520 SJTINGOW WOdd34 rySJINGOIN WOdds3 WwW) WHITE MICROELECTRONICS WE128K32-XXX FIG. 9 SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM LOAD DATA AA 0 T ADDRESS 5555 J LOAD DATA 55 T ADDRESS 2AAA J LOAD DATA AO WRITES ENABLED T ADDRESS 5555 I LOAD DATA XX TO ANY AppREss* AD LAST BYTE to te ENTER DATA LAST ADDRESS PROTECT STATE NOTES: 1. Data Format: D7 - Do (Hex): Address Format: A14 - Ao (Hex). 2, Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. White Microelectronics * Phoenix, AZ * (602) 437-1520 3-34a Miia laterite lee WE128K32-XXX FIG. 10 SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM LOAD DATAAA TO ADDRESS 5555 1 LOAD DATA 55 T ADDRESS 2AAA JI LOAD DATA 80 TO ADDRESS 5555 JI LOAD DATA AA TO ADDRESS 5555 J LOAD DATA 55 TO ADDRESS 2AAA J LOAD DATA 20 TO EXIT DATA (3) | ADDRESS 5555 PROTECT STATE q LOAD DATA Xx T ANY ADDRESS I LOAD LAST BYTE TO LAST ADDRESS SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WE- 128K32-XXX has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. The write protection feature can be disabled by a six byte write sequence of specific data to specific lacations. Power transitions will not reset the software write protection. Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. HARDWARE DATA PROTECTION These features protect against inadvertent writes to the WE128K32-XXX. These are included to improve reliability during normal operation: a) Vcc power on delay As Vcc climbs past 3.8V typical the device will wait 5mSec typical before allowing write cycles. b) Vcc sense While below 3.8V typical write cycles are inhibited. c) Write inhibiting Holding OE low and either CS or WE high inhibits write cycles. d) Noise filter LL Pulses of <15nS (typ) an WE or CS will not initiate a write cycle. White Microelectronics * Phoenix, AZ * (602) 437-1520 SJINGOW WOdd34 cySJINGOW WOddI3 EJ 4 WHITE MICROELECTRONICS 2:1 720.84 FIG. 11 PACKAGE DIMENSIONS (16406) A 4 * Pint This package is also available without shoulders on the corner pins. 25.4mm (1.0) = LP 30.1mm (1.185") + .38mm 0.015") SQ - 3.55mm (0.140") + y 0.127mm (0,005") (SR) 6.22mm (0.245") [ } MAX. | 44 = 3.93mm oe) i | | iL at 1.27mm (0.050") + .127mm (0.005") . 0.76mm (0.030") + 0.127mm (0.005") 2.54mm (0-100) 45.24mm (0600) 1.27mm (0.050') TYP. DIA. e 0.46mm (0.018") TYP. DIA. 25.4mm (1.0") FIG. 12 40mm (1.56") + 0.38mm (0.015") SQ | [-<t 5.1mm (0.205") MAX. PACKAGE DIMENSIONS (14A15) ({] ANC l ah eli | 1.27mm (0.050") 0.38mm (0.015') _ @ 0.25mm (0.010) TYP REF. + 0.08mm (0.003) 68 PLACES [38mm 1.50") REF 4 PLACES White Microelectronics * Phoenix, AZ (602) 437-1520 3-364 WHITE MICROELECTRONICS WE128K32-XXX ORDERING INFORMATION WE 128K32 X - XXX XX DEVICE GRADE: Q = MIL-STD-883 Compliant M = Military Screened -65C to +125C | = Industrial -40C to +85C Cc = Commercial 0 to +70C PACKAGE TYPE: H = Ceramic Hex in line package HS = Ceramic Hex in line package without shoulders G4 = 40mm Ceramic Quad Flat Pack ACCESS TIME in nS IMPROVEMENT MARK N = No Connect at pins 8, 21, 28, and 39 Blank = GND at pins 8,21, 28, and 39 ORGANIZATION 128K x 32 User Configurable as 256K x 16 or 512K x 8 EEPROM WHITE MICROELECTRONICS De > es peed << age ey: 128K x 32 EEPROM 300nS 66 pin HIP 5962 94585-01HXX 128K x 32 EEPROM 250nS 66 pin HIP 5962 94585-02HXX 128K x 32 EEPROM 200nS 66 pin HIP 5962 94585-03HXX 128K x 32 EEPROM 150nS 66 pin HIP 5962 94585-04HXX 3-37 White Microelectronics * Phoenix, AZ * (602) 437-1520 SJINGOW INOUd34 ca