For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX146/MAX147 12-bit data-acquisition systems
combine an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. The MAX146 oper-
ates from a single +2.7V to +3.6V supply; the MAX147
operates from a single +2.7V to +5.25V supply. Both
devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The
MAX146/MAX147 use either the internal clock or an exter-
nal serial-interface clock to perform successive-approxi-
mation analog-to-digital conversions.
The MAX146 has an internal 2.5V reference, while the
MAX147 requires an external reference. Both parts have
a reference-buffer amplifier with a ±1.5% voltage-
adjustment range.
These devices provide a hard-wired SHDN pin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a con-
version. Accessing the serial interface automatically
powers up the MAX146/MAX147, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60µA at reduced sampling rates.
The MAX146/MAX147 are available in 20-pin DIP and
SSOP packages.
For 4-channel versions of these devices, see the
MAX1246/MAX1247 data sheet.
________________________Applications
Portable Data Logging Data Acquisition
Medical Instruments Battery-Powered Instruments
Pen Digitizers Process Control
____________________________Features
♦8-Channel Single-Ended or 4-Channel
Differential Inputs
♦Single-Supply Operation
+2.7V to +3.6V (MAX146)
+2.7V to +5.25V (MAX147)
♦Internal 2.5V Reference (MAX146)
♦Low Power
1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
1µA (power-down mode)
♦SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
♦Software-Configurable Unipolar or Bipolar Inputs
♦20-Pin DIP/SSOP Packages
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
________________________________________________________________ Maxim Integrated Products 1
VDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
SHDN
SSTRB
DOUT
DIN
SCLK
CS
COM
AGND
DGND
VDD
CH7
4.7µF
0.1µF
CH0
0V TO
+2.5V
ANALOG
INPUTS MAX146
CPU
+3V
VREF
0.047µF
REFADJ
Typical Operating Circuit
19-0465; Rev 2; 10/01
PART
MAX146ACPP
MAX146BCPP
MAX146ACAP 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP RANGE PIN-PACKAGE
20 Plastic DIP
20 Plastic DIP
20 SSOP
EVALUATION KIT
AVAILABLE
Ordering Information
Ordering Information continued at end of data sheet.
*Dice are specified at TA= +25°C, DC parameters only.
MAX146BCAP 0°C to +70°C 20 SSOP
INL
(LSB)
±1/2
±1
±1/2
±1
SPI and QSPI are registered trademarks of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor
Corp.
Pin Configuration appears at end of data sheet.
MAX146BC/D 0°C to +70°C Dice* ±1
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX146); VDD = +2.7V to +5.25V (MAX147); COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMIN to TMAX; unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND, DGND................................................. -0.3V to 6V
AGND to DGND ...................................................... -0.3V to 0.3V
CH0–CH7, COM to AGND, DGND ............ -0.3V to (VDD + 0.3V)
VREF, REFADJ to AGND ........................... -0.3V to (VDD + 0.3V)
Digital Inputs to DGND .............................................. -0.3V to 6V
Digital Outputs to DGND ........................... -0.3V to (VDD + 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW
SSOP (derate 8.00mW/°C above +70°C) ................... 640mW
CERDIP (derate 11.11mW/°C above +70°C).............. 889mW
Operating Temperature Ranges
MAX146_C_P/MAX147_C_P .............................. 0°C to +70°C
MAX146_E_P/MAX147_E_P............................ -40°C to +85°C
MAX146_MJP/MAX147_MJP ........................ -55°C to +125°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
Relative Accuracy (Note 2)
6
µs
35 65
tCONV
Conversion Time (Note 5)
5.5 7.5
MHz1.0Full-Power Bandwidth
MHz2.25Small-Signal Bandwidth
dB-85Channel-to-Channel Crosstalk
80 90
-88 -80
70 73
LSB±0.25
Channel-to-Channel Offset
Matching
ppm/°C±0.25Gain Temperature Coefficient
±0.5
Bits12Resolution
LSBGain Error (Note 3) ±0.5 ±4
Offset Error
±1.0 LSB
±2.0
INL
±0.5 ±3 LSB
±0.5 ±4
UNITSMIN TYP MAXSYMBOLPARAMETER
External clock = 2MHz, 12 clocks/conversion
Internal clock, SHDN = VDD
Internal clock, SHDN = FLOAT
MAX14_A
-3dB rolloff
65kHz, 2.500Vp-p (Note 4)
MAX14_A/MAX14_B
MAX14_A/MAX14_B
MAX14_B
MAX147C
MAX14_A
MAX14_B/MAX147C
CONDITIONS
±1.0MAX14_A/MAX14_B
Differential Nonlinearity LSB
±0.8
DNL MAX147C
No Missing Codes Bits12NMC
dB
73
SINADSignal-to-Noise + Distortion Ratio MAX147C
dB
-88
THDTotal Harmonic Distortion Up to the 5th
harmonic
MAX14_A/MAX14_B
MAX147C
dB
90
SFDRSpurious-Free Dynamic Range MAX147C
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
CONVERSION RATE
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX146); VDD = +2.7V to +5.25V (MAX147); COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMIN to TMAX; unless otherwise noted.)
CONDITIONSPARAMETER SYMBOL MIN TYP MAX UNITS
µs1.5tACQ
Track/Hold Acquisition Time
0.1 2.0
1.8
ns
MHz
SHDN = FLOAT MHz
30
0.225
Aperture Delay
Internal Clock Frequency SHDN = VDD
0 2.0
External Clock Frequency Data transfer only
ps<50Aperture Jitter
On/off leakage current, VCH_ = 0V or VDD
Bipolar, COM = VREF / 2
Unipolar, COM = 0V
±0.01 ±1 µA
Input Voltage Range, Single-
Ended and Differential (Note 6) ±VREF / 2
V
0 to VREF
Multiplexer Leakage Current
REFADJ Adjustment Range ±1.5 %
Capacitive Bypass at REFADJ 0.047 µF
External compensation mode
Capacitive Bypass at VREF 4.7 µF
Internal compensation mode 0
0 to 0.2mA output loadLoad Regulation (Note 7) 0.35 mV
MAX146_M
VREF Temperature Coefficient
±30 ±80
ppm/°CMAX146_E ±30 ±60
MAX146_C ±30 ±50
VREF Short-Circuit Current 30 mA
TA= +25°CVREF Output Voltage 2.480 2.500 2.520 V
Input Capacitance 16 pF
VREF Input Voltage Range
(Note 8) 1.0 VDD +
50mV V
External compensation mode
MAX146
4.7
Reference Buffer Gain 2.06 V/V
Internal compensation mode
Capacitive Bypass at VREF 0µF
REFADJ Buffer Disable Threshold VDD -
0.5 V
VREF = 2.5VVREF Input Current 100 150 µA
VREF Input Resistance 18 25 kΩ
Shutdown VREF Input Current 0.01 10 µA
MAX147
MAX146
MAX147
REFADJ Input Current
2.00
±50
±10 µA
ANALOG/COM INPUTS
INTERNAL REFERENCE (MAX146 only, reference buffer enabled)
EXTERNAL REFERENCE AT VREF (Buffer disabled)
EXTERNAL REFERENCE AT REFADJ
µA
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX146); VDD = +2.7V to +5.25V (MAX147); COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMIN to TMAX; unless otherwise noted.)
V
3.0
VIH
VDD = 3.6V
DIN, SCLK, CS Input High Voltage VDD > 3.6V, MAX147 only
mV±0.3PSRSupply Rejection (Note 10) Full-scale input, external reference = 2.5V,
VDD = 2.7V to VDD(MAX)
pF15CIN
DIN, SCLK, CS Input Capacitance
µA±0.01 ±1IIN
DIN, SCLK, CS Input Leakage
V0.2VHYST
DIN, SCLK, CS Input Hysteresis
V0.8VIL
DIN, SCLK, CS Input Low Voltage
2.0
µA±4.0IS
SHDN Input Current
V0.4VSL
SHDN Input Low Voltage
VVDD - 0.4VSH
SHDN Input High Voltage
SHDN = 0V or VDD
nA±100
SHDN Maximum Allowed
Leakage, Mid Input
VVDD / 2VFLT
SHDN Voltage, Floating
SHDN = FLOAT
SHDN = FLOAT
UNITSMIN TYP MAXSYMBOLPARAMETER
(Note 9)
VIN = 0V or VDD
VDD ≤3.6V
IDD
CONDITIONS
Positive Supply Current, MAX146 µA
1.2 2.0
µA±0.01 ±10IL
Three-State Leakage Current
VVDD - 0.5VOH
Output Voltage High
V
0.8
VOL
Output Voltage Low 0.4
2.70 3.60
pF15COUT
Three-State Output Capacitance
MAX146
CS = VDD (Note 9)
CS = VDD
ISOURCE = 0.5mA
ISINK = 16mA
ISINK = 5mA
V
2.70 5.25
VDD
Positive Supply Voltage MAX147
0.9 1.5
Operating mode,
full-scale input
VDD = 5.25V
VDD = 3.6V
2.1 15VDD = 5.25V
VDD = 3.6V 1.2 10
Full power-down
mA
1.8 2.5
30 70
1.2 10
Operating mode, full-scale input
Fast power-down
Full power-down
mA
V1.1 VDD - 1.1VSM
SHDN Input Mid Voltage
IDD
Positive Supply Current, MAX147
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
IDD
Positive Supply Current, MAX147 µA
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 5
Figure 1
Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.5V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
0.5
0 1024 2048 3072 4096
INTEGRAL NONLINEARITY
vs. CODE
0.3
-0.3
-0.5
-0.1
0.1
0.4
0.2
-0.4
-0.2
0
MAX146/47-01
CODE
INL (LSB)
0.50
0
2.25 2.75 4.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
VDD (V)
INL (LSB)
3.75 5.253.25 4.75
MAX146/47-02
MAX146
MAX147
0
0.10
0.20
0.30
0.40
0.50
0.05
0.15
0.25
0.35
0.45
-60 -20 20 60 100 140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (°C)
INL (LSB)
MAX146/47-03
MAX147
MAX146
VDD = 2.7V
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX146); VDD = +2.7V to +5.25V (MAX147); TA= TMIN to TMAX; unless otherwise noted.)
Note 1: Tested at VDD = 2.7V; COM = 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX146—internal reference, offset nulled; MAX147—external reference (VREF = +2.5V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9: Guaranteed by design. Not subject to production testing.
Note
10:
Measured as
|
VFS(2.7V) - VFS(VDD, MAX)
|
.
Internal clock mode only (Note 9)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
Figure 1
Figure 2
Figure 1
MAX14_ _C/E
CONDITIONS
MAX14_ _M ns
20 240
Figure 1
ns
tCSH
ns240tSTR
CS Rise to SSTRB Output Disable
ns240tSDV
CS Fall to SSTRB Output Enable
240tSSTRB
SCLK Fall to SSTRB ns
200tCL
SCLK Pulse Width Low
ns200SCLK Pulse Width High
ns0
CS to SCLK Rise Hold
ns100tCSS
CS to SCLK Rise Setup
ns240tTR
CS Rise to Output Disable
ns240tDV
CS Fall to Output Enable
tCH
20 200
tDO
SCLK Fall to Output Data Valid
ns0tDH
DIN to SCLK Hold
ns
µs1.5tACQ
Acquisition Time
0tSCK
SSTRB Rise to SCLK Rise
ns100tDS
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
6 _______________________________________________________________________________________
2.00
0.50
2.25 2.75
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.75
1.25
1.50
1.00
0.75
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.75 5.253.25 4.25 4.75
MAX146/47-04
RL = ∞
CODE = 101010100000 CLOAD = 50pF
MAX147
MAX146
CLOAD = 20pF
3.5
3.0
0
2.25 2.75
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.5
2.0
1.5
1.0
0.5
VDD (V)
SHUTDOWN SUPPLY CURRENT (µA)
3.75 5.253.25 4.25 4.75
MAX146/47-05
FULL POWER-DOWN
2.5020
2.4990
2.25 2.75
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.5015
2.5005
2.5010
2.5000
2.4995
VDD (V)
VREF (V)
3.75 5.253.25 4.25 4.75
MAX146/47-06
0.8
0.9
1.0
1.1
1.2
1.3
-60 -20 20 60 100 140
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX146/47-07
MAX147
MAX146
RLOAD = ∞
CODE = 101010100000
0 10203040506070
FFT PLOT
FREQUENCY (kHz)
AMPLITUDE (dB)
-120
-100
-80
-60
-40
-20
0
20
MAX146/47-10
VDD = 2.7V
fIN = 10kHz
fSAMPLE = 133kHz
0
0.4
0.8
1.2
1.6
2.0
-60 -20 20 60 100 140
SHUTDOWN CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
MAX1247-08
2.494
2.495
2.496
2.497
2.498
2.499
2.500
2.501
-60 -20 20 60 100 140
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
VREF (V)
MAX146/47-09
VDD = 2.7V
VDD = 3.6V
11.0
11.2
11.4
11.6
11.8
12.0
1 10 100
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
MAX146/47-11
FREQUENCY (kHz)
ENOB
VDD = 2.7V
Typical Operating Characteristics (continued)
(VDD = 3.0V, VREF = 2.5V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 7
0.50
0
2.25 2.75 4.25
OFFSET vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
VDD (V)
OFFSET (LSB)
3.753.25 4.75 5.25
MAX146/47-12
0.50
0
2.25 2.75 3.75
GAIN ERROR
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
VDD (V)
GAIN ERROR (LSB)
3.25 4.25 5.254.75
MAX146/47-13
0.50
0
2.25 2.75 3.75
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
VDD (V)
GAIN MATCHING (LSB)
3.25 4.25 5.254.75
MAX146/47-14
0.50
0
-55 -30 45
OFFSET vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
OFFSET (LSB)
20-5 70 14512095
MAX146/47-15
0.50
0
2.25 2.75 4.25
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
VDD (V)
OFFSET MATCHING (LSB)
3.753.25 5.254.75
MAX146/47-18
0.50
0
-55 -30 20
GAIN ERROR
vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
GAIN ERROR (LSB)
-5 45 120 1459570
MAX146/47-16
0.50
0
-55 -30 20
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
GAIN MATCHING (LSB)
-5 45 1451209570
MAX146/47-17
0.50
0
-55 -30 45
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
OFFSET MATCHING (LSB)
20
-5 70 14512095
MAX146/47-19
Typical Operating Characteristics (continued)
(VDD = 3.0V, VREF = 2.5V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
8 _______________________________________________________________________________________
NAME FUNCTION
1–8 CH0–CH7 Sampling Analog Inputs
PIN
9COM Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
10 SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX146/MAX147 down; otherwise, they are
fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode.
Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
15 DOUT Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
14 DGND Digital Ground
13 AGND Analog Ground
11 VREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX146 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.
19 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
18 CS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
17 DIN Serial Data Input. Data is clocked in at SCLK’s rising edge.
16 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX146/MAX147 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external clock
mode).
______________________________________________________________Pin Description
VDD
6kΩ
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6kΩ
DOUT
a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL
VDD
6kΩ
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6kΩ
DOUT
a) VOH to High-Z b) VOL to High-Z
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time
12 REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.
20 VDD Positive Supply Voltage
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 9
_______________Detailed Description
The MAX146/MAX147 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX146/
MAX147.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from the fol-
lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a 16pF x [(VIN+) -
(VIN-)] charge from CHOLD to the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLD charges to the input signal.
INPUT
SHIFT
REGISTER CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+1.21V
REFERENCE
(MAX146)
T/H
ANALOG
INPUT
MUX
12-BIT
SAR
ADC
IN
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
COM
REFADJ
VREF
OUT
REF
CLOCK
+2.500V
20kΩ
*A ≈ 2.00 (MAX147)
10
11
12
9
15
16
17
18
19
CH6 7
CH7 8
CH4 5
CH5 6
CH1 2
CH2 3
CH3 4
CH0 1
MAX146
MAX147
CS
SHDN
20
14
13
≈ 2.06*
A
Figure 3. Block Diagram
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
9kΩ
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR
–+
16pF
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
10 ______________________________________________________________________________________
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
tACQ = 9 x (RS+ RIN) x 16pF
where RIN = 9kΩ, RS= the source impedance of the
input signal, and tACQ is never less than 1.5µs. Note
that source impedances below 1kΩdo not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to VDD and AGND, allow the channel input pins to swing
from AGND - 0.3V to VDD + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD by more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
Quick Look
To quickly evaluate the MAX146/MAX147’s analog per-
formance, use the circuit of Figure 5. The MAX146/
MAX147 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in con-
trol bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In exter-
nal clock mode, the SSTRB output pulses high for one
clock period before the most significant bit of the 12-bit
conversion result is shifted out of DOUT. Varying the
analog input to CH7 will alter the sequence of bits from
DOUT. A total of 15 clock cycles is required per con-
version. All transitions of the SSTRB and DOUT outputs
occur on the falling edge of SCLK.
0.1µF
2.5V
+3V
VDD
DGND
AGND
COM
CS
SCLK
DIN
DOUT
SSTRB
SHDN
+3V
N.C.
0.01µF
CH7
REFADJ
VREF
C1
0.1µF
0V TO
2.500V
ANALOG
INPUT
OSCILLOSCOPE
CH1 CH2 CH3 CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
MAX146
MAX147
+3V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
COMP
1000pF
VOUT
+3V
MAX872
OPTIONAL FOR MAX146,
REQUIRED FOR MAX147
Figure 5. Quick-Look Circuit
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 11
BIT NAME DESCRIPTION
7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.
6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
5 SEL1
4 SEL0
3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.
2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1 PD1 Selects clock and power-down modes.
0(LSB) PD0 PD1 PD0 Mode
0 0 Full power-down
0 1 Fast power-down (MAX146 only)
1 0 Internal clock mode
1 1 External clock mode
Table 1. Control-Byte Format
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
00 0 + –
10 0 + –
00 1 +–
10 1 +–
01 0 +–
11 0 +–
01 1 +–
11 1 + –
Table 3. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
00 0 +–
00 1 +–
01 0 +–
01 1 +–
10 0 –+
10 1 –+
11 0 –+
11 1 –+
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
12 ______________________________________________________________________________________
SSTRB
CS
SCLK
DIN
DOUT
14 8 12 16 20 24
START
SEL2 SEL1 SEL0 UNI/
BIP SGL/
DIF PD1 PD0
B11
MSB B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
LSB
ACQUISITION
(fSCLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
tACQ
A/D STATE
RB1 RB2 RB3
1.5µs
Figure 6. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with fSCLK ≤2MHz)
How to Start a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX146/MAX147’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX146/MAX147 are compatible with SPI™/
QSPI™ and Microwire™ devices. For SPI, select the
correct clock polarity and sampling edge in the SPI
control registers: set CPOL = 0 and CPHA = 0. Micro-
wire, SPI, and QSPI all transmit a byte and receive a
byte at the same time. Using the Typical Operating
Circuit, the simplest software interface requires only
three 8-bit transfers to perform a conversion (one 8-bit
transfer to configure the ADC, and two more 8-bit trans-
fers to clock out the 12-bit conversion result). See Figure
20 for MAX146/MAX147 QSPI connections.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero and three trailing zeros. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is two’s
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
Clock Modes
The MAX146/MAX147 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX146/MAX147. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 13
• • •
• • • • • •
• • •
tSDV
tSSTRB
PD0 CLOCKED IN
tSTR
SSTRB
SCLK
CS
tSSTRB
• • • • • • •
•
Figure 8. External Clock Mode SSTRB Detailed Timing
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). SSTRB and DOUT go into a high-impedance
state when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 8 shows the SSTRB
timing in external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial clock interruptions could cause the conversion
interval to exceed 120µs.
Internal Clock
In internal clock mode, the MAX146/MAX147 generate
their own conversion clocks internally. This frees the µP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
tCSH
tCSS tCL
tDS
tDH
tDV
tCH
tDO tTR
tCSH
Figure 7. Detailed Serial-Interface Timing
PD0 CLOCK IN
tSSTRB
tCSH
tCONV
tSCK
SSTRB
SCLK
DOUT
tCSS
tDO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 10. Internal Clock Mode SSTRB Detailed Timing
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
14 ______________________________________________________________________________________
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX146/MAX147 and three-states DOUT, but it
does not adversely affect an internal clock mode
conversion already in progress. When internal clock
mode is selected, SSTRB does not go into a high-
impedance state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX146/MAX147 at clock rates exceeding 2.0MHz
if the minimum acquisition time (tACQ) is kept above
1.5µs.
SSTRB
CS
SCLK
DIN
DOUT
14 8 12 18 20 24
START
SEL2 SEL1 SEL0 UNI/
BIP
SGL/
DIF PD1 PD0
B11
MSB B10 B9 B2 B1 B0
LSB
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5µs MAX
(SHDN = FLOAT)
2 3 5 6 7 9 10 11 19 21 22 23
tCONV
ACQUISITION
(fSCLK = 2MHz)
IDLE
A/D STATE 1.5µs
Figure 9. Internal Clock Mode Timing
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 15
SCLK
DIN
DOUT
CS
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
SSTRB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONTROL BYTE 2S
18115 1581
CS
SCLK
DIN
DOUT
S
18 16
18 16
CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8
CONVERSION RESULT 1
• • •
• • •
• • •
• • •
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Data Framing
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after VDD is applied.
OR
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized as
a start bit; the current conversion is terminated, and a
new one is started.
The fastest the MAX146/MAX147 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 11a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
clock mode. If CS is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (µCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a µC can drive the
MAX146/MAX147. Figure 11b shows the serial-
interface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX146/MAX147 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies stabi-
lize, the internal reset time is 10µs, and no conversions
should be performed during this phase. SSTRB is high
on power-up and, if CS is low, the first logical 1 on DIN
is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. (Also see Table 4.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
16 ______________________________________________________________________________________
Reference-Buffer Compensation
In addition to its shutdown function, SHDN selects inter-
nal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. The100kHz minimum clock rate is limited by
droop on the sample-and-hold and is independent of
the compensation used.
Float SHDN to select external compensation. The
Typical Operating Circuit uses a 4.7µF capacitor at
VREF. A 4.7µF value ensures reference-buffer stability
and allows converter operation at the 2MHz full clock
speed. External compensation increases power-up
time (see the Choosing Power-Down Mode section and
Table 4).
Pull SHDN high to select internal compensation.
Internal compensation requires no external capacitor at
VREF and allows for the shortest power-up times. The
maximum clock rate is 2MHz in internal clock mode
and 400kHz in external clock mode.
Choosing Power-Down Mode
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down mode or fast power-down mode via bits 1
and 0 of the DIN control byte with SHDN high or floating
(Tables 1 and 5). In both software power-down modes,
the serial interface remains operational, but the ADC
does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current to 2µA
(typ). Fast power-down mode turns off all circuitry
except the bandgap reference. With fast power-down
mode, the supply current is 30µA. Power-up time can be
shortened to 5µs in internal compensation mode.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7µF compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 5, PD1 and PD0
also specify the clock mode. When software shutdown is
asserted, the ADC operates in the last specified clock
mode until the conversion is complete. Then the ADC
powers down into a low quiescent-current state. In internal
clock mode, the interface remains active and conversion
results may be clocked out after the MAX146/MAX147
enter a software power-down.
The first logical 1 on DIN is interpreted as a start bit
and powers up the MAX146/MAX147. Following
the start bit, the data input word or control byte also
determines clock mode and power-down states. For
example, if the DIN word contains PD1 = 1, then the
chip remains powered up. If PD0 = PD1 = 0, a
power-down resumes after one conversion.
Table 4. Typical Power-Up Delay Times
1332Full——Disabled
1332Fast——Disabled
133See Figure 14cFull4.7ExternalEnabled
133See Figure 14cFast4.7ExternalEnabled
26300Full—InternalEnabled
265Fast—InternalEnabled
MAXIMUM
SAMPLING RATE
(ksps)
POWER-UP
DELAY
(µs)
POWER-DOWN
MODE
VREF
CAPACITOR
(µF)
REFERENCE-
BUFFER
COMPENSATION
MODE
REFERENCE
BUFFER
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 17
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down (Table 6). Unlike software power-down
mode, the conversion is not completed; it stops coin-
cidentally with SHDN being brought low. SHDN also
controls the clock frequency in internal clock mode.
Letting SHDN float sets the internal clock frequency to
1.8MHz. When returning to normal operation with SHDN
floating, there is a tRC delay of approximately 2MΩx CL,
where CLis the capacitive loading on the SHDN pin.
Pulling SHDN high sets internal clock frequency to
225kHz. This feature eases the settling-time requirement
for the reference voltage. With an external reference, the
MAX146/MAX147 can be considered fully powered up
within 2µs of actively pulling SHDN high.
POWERED UP
HARDWARE
POWER-
DOWN POWERED UP
POWERED UP
12 DATA BITS 12 DATA BITS INVALID
DATA
VALID
DATA
EXTERNAL
EXTERNAL
SXXXXX11 S 00
XXXXX XX XXX
S11
SOFTWARE
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS SOFTWARE
POWER-DOWN
POWER-DOWN
POWERED UP
POWERED UP
DATA VALID DATA VALID
INTERNAL
SXXXXX10 S 00
XXXXX S
MODE
DOUT
DIN
CLOCK
MODE SETS INTERNAL
CLOCK MODE
SETS
POWER-DOWN
CONVERSION
CONVERSION
SSTRB
Figure 12a. Timing Diagram Power-Down Modes, External Clock
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
18 ______________________________________________________________________________________
Figure 13. Average Supply Current vs. Conversion Rate with
External Reference
1000
10,000
0.1
0.1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
WITH EXTERNAL REFERENCE
100
10
1
CONVERSION RATE (Hz)
AVERAGE SUPPLY CURRENT (µA)
1 10010 1k 10k 1M100k
MAX146/47-13
VREF = VDD = 3.0V
RLOAD = ∞
CODE = 101010100000
1 CHANNEL
8 CHANNELS
Figure 14b. MAX146 Supply Current vs. Conversion Rate,
FASTPD
10,000
1
0.1 1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FASTPD)
1000
100
10
CONVERSION RATE (Hz)
AVERAGE SUPPLY CURRENT (µA)
100 1M10 1k 10k 100k
MAX146/47-Fig14b
RLOAD = ∞
CODE = 101010100000
8 CHANNELS
1 CHANNEL
Figure 14a. MAX146 Supply Current vs. Conversion Rate,
FULLPD
100
1
0.01 0.1 1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
(USING FULLPD)
10
CONVERSION RATE (Hz)
AVERAGE SUPPLY CURRENT (µA)
10010 1k
MAX146/47-Fig14a
RLOAD = ∞
CODE = 101010100000
8 CHANNELS
1 CHANNEL
Figure 14c. Typical Reference-Buffer Power-Up Delay vs. Time
in Shutdown
2.0
0
0.001 0.01 0.1 1 10
TYPICAL REFERENCE-BUFFER POWER-UP
DELAY vs. TIME IN SHUTDOWN
1.5
1.0
0.5
TIME IN SHUTDOWN (s)
POWER-UP DELAY (ms)
MAX146/47-Fig14c
Power-Down Sequencing
The MAX146/MAX147 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 13, 14a, and 14b show
the average supply current as a function of the sam-
pling rate. The following discussion illustrates the vari-
ous power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples show two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
Figure 14a depicts the MAX146 power consumption for
one or eight channel conversions utilizing full power-
down mode and internal-reference compensation. A
0.047µF bypass capacitor at REFADJ forms an RC filter
with the internal 20kΩreference resistor with a 0.9ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 9ms are required after power-up. Waiting
this 9ms in FASTPD mode instead of in full power-up
can reduce power consumption by a factor of 10 or
more. This is achieved by using the sequence shown in
Figure 15.
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 19
Lowest Power at Higher Throughputs
Figure 14b shows the power consumption with
external-reference compensation in fast power-down,
with one and eight channels converted. The external
4.7µF compensation requires a 200µs wait after
power-up with one dummy conversion. This graph
shows fast multi-channel conversion with the lowest
power consumption possible. Full power-down mode
may provide increased power savings in applications
where the MAX146/MAX147 are inactive for long peri-
ods of time, but where intermittent bursts of high-speed
conversions are required.
Internal and External References
The MAX146 can be used with an internal or external
reference voltage, whereas an external reference is
required for the MAX147. An external reference can be
connected directly at VREF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at
VREF for both the MAX146 and the MAX147. The
MAX146’s internally trimmed 1.21V reference is buf-
fered with a 2.06 gain. The MAX147’s REFADJ pin is
also buffered with a 2.00 gain to scale an external 1.25V
reference at REFADJ to 2.5V at VREF.
Internal Reference (MAX146)
The MAX146’s full-scale range with the internal refer-
ence is 2.5V with unipolar inputs and ±1.25V with bipo-
lar inputs. The internal reference voltage is adjustable
to ±1.5% with the circuit in Figure 16.
External Reference
With both the MAX146 and MAX147, an external refer-
ence can be placed at either the input (REFADJ) or the
output (VREF) of the internal reference-buffer amplifier.
The REFADJ input impedance is typically 20kΩfor the
MAX146, and higher than 100kΩfor the MAX147. At
100
DIN
REFADJ
VREF
1.21V
0V
2.50V
0V
101 1 11100 101
FULLPD FASTPD NOPD FULLPD FASTPD
9ms WAIT
COMPLETE CONVERSION SEQUENCE
tBUFFER ≈ 200µs
τ = RC = 20kΩ x CREFADJ
(ZEROS) CH1 CH7 (ZEROS)
Figure 15. MAX146 FULLPD/FASTPD Power-Up Sequence
+3.3V
510kΩ
24kΩ
100kΩ
0.047µF
12 REFADJ
MAX146
Figure 16. MAX146 Reference-Adjust Circuit
PD1 PD0 DEVICE MODE
0 0 Full Power-Down
0 1 Fast Power-Down
1 0 Internal Clock
1 1 External Clock
Table 5. Software Power-Down and
Clock Mode
Table 6. Hard-Wired Power-Down and
Internal Clock Frequency
SHDN
STATE
DEVICE
MODE
REFERENCE
BUFFER
COMPENSATION
INTERNAL
CLOCK
FREQUENCY
1Enabled Internal 225kHz
Floating Enabled External 1.8MHz
0Power-Down N/A N/A
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
20 ______________________________________________________________________________________
VREF, the DC input resistance is a minimum of 18kΩ.
During conversion, an external reference at VREF must
deliver up to 350µA DC load current and have 10Ωor
less output impedance. If the reference has a higher
output impedance or is noisy, bypass it close to the
VREF pin with a 4.7µF capacitor.
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct VREF input,
disable the internal buffer by tying REFADJ to VDD. In
power-down, the input bias current to REFADJ is typi-
cally 25µA (MAX146) with REFADJ tied to VDD. Pull
REFADJ to AGND to minimize the input bias current in
power-down.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
The external reference must have a temperature coeffi-
cient of 4ppm/°C or less to achieve accuracy to within
1LSB over the 0°C to +70°C commercial temperature
range.
Figure 17 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 18 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = 610µV (2.500V /
4096) for unipolar operation, and 1LSB = 610µV
[(2.500V / 2 - -2.500V / 2) / 4096] for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 19 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to the star ground. No other digital system ground
should be connected to this ground. For lowest-noise
operation, the ground return to the star ground’s power
supply should be low impedance and as short as
possible.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 1µF
capacitors close to pin 20 of the MAX146/MAX147.
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10Ωresis-
tor can be connected as a lowpass filter (Figure 19).
High-Speed Digital Interfacing with QSPI
The MAX146/MAX147 can interface with QSPI using
the circuit in Figure 20 (fSCLK = 2.0MHz, CPOL = 0,
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the eight channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
The MAX146/MAX147 are QSPI compatible up to the
maximum external clock frequency of 2MHz.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0
(COM)
FS
FS - 3/2LSB
FS = VREF + COM
ZS = COM
INPUT VOLTAGE (LSB)
1LSB = VREF
4096
Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
UNIPOLAR MODE BIPOLAR MODE
Full Scale Zero Scale Positive Zero Negative
Full Scale Scale Full Scale
VREF + COM COM VREF / 2 COM -VREF / 2
+ COM + COM
Table 7. Full Scale and Zero Scale
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 21
TMS320LC3x Interface
Figure 21 shows an application circuit to interface the
MAX146/MAX147 to the TMS320 in external clock mode.
The timing diagram for this interface circuit is shown in
Figure 22.
Use the following steps to initiate a conversion in the
MAX146/MAX147 and to read the results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
tied together with the MAX146/MAX147’s SCLK
input.
2) The MAX146/MAX147’s CS pin is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX146/MAX147’s DIN.
3) An 8-bit word (1XXXXX11) should be written to the
MAX146/MAX147 to initiate a conversion and place
the device into external clock mode. Refer to Table
1 to select the proper XXXXX bit values for your
specific application.
4) The MAX146/MAX147’s SSTRB output is monitored
via the TMS320’s FSR input. A falling edge on the
SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX146/MAX147.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
6) Pull CS high to disable the MAX146/MAX147 until
the next conversion is initiated.
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS COM*
INPUT VOLTAGE (LSB)
OUTPUT CODE
ZS = COM
+FS - 1LSB
*COM VREF / 2
+ COM
FS = VREF
2
-FS = + COM
-VREF
2
1LSB = VREF
4096
≤
Figure 18. Bipolar Transfer Function, Full Scale (FS) =
VREF / 2 + COM, Zero Scale (ZS) = COM
+3V +3V GND
SUPPLIES
DGND+3VDGNDCOM
AGNDVDD
DIGITAL
CIRCUITRY
MAX146
MAX147
R* = 10Ω
*OPTIONAL
Figure 19. Power-Supply Grounding Connection
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
22 ______________________________________________________________________________________
XF
CLKX
CLKR
DX
DR
FSR
CS
SCLK
DIN
DOUT
SSTRB
TMS320LC3x
MAX146
MAX147
Figure 21. MAX146/MAX147-to-TMS320 Serial Interface
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MAX146
MAX147
MC683XX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
VDD
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VREF
(POWER SUPPLIES)
SCK
PCS0
MOSI
MISO
0.1µF1µF
(GND)
0.1µF
ANALOG
INPUTS
+3V
+3V
+2.5V
Figure 20. MAX146/MAX147 QSPI Connections, External Reference
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 23
Ordering Information (continued)
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability of CERDIP package, and for
processing to MIL-STD-883B.
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
TOP VIEW
DIP/SSOP
VDD
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VREFSHDN
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX146
MAX147
Pin Configuration
___________________Chip Information
TRANSISTOR COUNT: 2554
CS
SCLK
DIN
SSTRB
DOUT
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
MSB B10 B1 LSB HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 22. TMS320 Serial-Interface Timing Diagram
PART
MAX146AEPP
MAX146BEPP
MAX146AEAP -40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP RANGE PIN-PACKAGE
20 Plastic DIP
20 Plastic DIP
20 SSOP
MAX146BEAP
INL
(LSB)
±1/2
±1
-40°C to +85°C 20 SSOP
±1/2
±1
MAX146AMJP
MAX146BMJP
MAX147ACPP 0°C to +70°C
-55°C to +125°C
-55°C to +125°C 20 CERDIP**
20 CERDIP**
20 Plastic DIP
MAX147BCPP
±1/2
±1
0°C to +70°C 20 Plastic DIP
±1/2
±1
MAX147ACAP
MAX147BCAP
MAX147AEPP -40°C to +85°C
0°C to +70°C
0°C to +70°C 20 SSOP
20 SSOP
20 Plastic DIP
MAX147BEPP
MAX147AEAP
±1/2
±1
-40°C to +85°C 20 Plastic DIP
±1/2
MAX147BEAP
±1
-40°C to +85°C
-40°C to +85°C 20 SSOP
20 SSOP
MAX147BMJP
±1/2
-55°C to +125°C 20 CERDIP**
±1
±1
MAX147BC/D 0°C to +70°C Dice* ±1
MAX147CCAP 0°C to +70°C 20 SSOP ±2.0
MAX147AMJP -55°C to +125°C 20 CERDIP** ±1/2
MAX147CEAP -40°C to +85°C 20 SSOP ±2.0
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SSOP.EPS
PACKAGE OUTLINE, SSOP, 5.3 MM
1
1
21-0056 C
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
7.90
H
L
0∞
0.301
0.025
8∞
0.311
0.037
0∞
7.65
0.63
8∞
0.95
MAX
5.38
MILLIMETERS
B
C
D
E
e
A1
DIM
A
SEE VARIATIONS
0.0256 BSC
0.010
0.004
0.205
0.002
0.015
0.008
0.212
0.008
INCHES
MIN MAX
0.078
0.65 BSC
0.25
0.09
5.20
0.05
0.38
0.20
0.21
MIN
1.73 1.99
MILLIMETERS
6.07
6.07
10.07
8.07
7.07
INCHES
D
D
D
D
D
0.239
0.239
0.397
0.317
0.278
MIN
0.249
0.249
0.407
0.328
0.289
MAX MIN
6.33
6.33
10.33
8.33
7.33
14L
16L
28L
24L
20L
MAX N
A
D
eA1 L
C
HE
N
12
B
0.068
