IR2184(4)(S) & (PbF)
Typical Connection
HALF-BRIDGE DRIVER
Features
•Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
•Gate drive supply range from 10 to 20V
•Undervoltage lockout for both channels
•3.3V and 5V input logic compatible
•Matched propagation delay for both channels
•Logic and power ground +/- 5V offset.
•Lower di/dt gate driver for better noise immunity
•Output source/sink current capability 1.4A/1.8A
•Also available LEAD-FREE (PbF)
IR21844
IR2184
www.irf.com 1
Data Sheet No. PD60174 revG
(Refer to Lead Assignments for correct
configuration). This/These diagram(s) show
electrical connections only. Please refer to
our Application Notes and DesignTips for
proper circuit board layout.
Packages
14-Lead PDIP
IR21844
8-Lead SOIC
IR2184S 14-Lead SOIC
IR21844S
8-Lead PDIP
IR2184
Description
The IR2184(4)(S) are high voltage,
high speed power MOSFET and IGBT
drivers with dependent high and low
side referenced output channels. Pro-
prietary HVIC and latch immune
CMOS technologies enable rugge-
dized monolithic construction. The
logic input is compatible with standard
CMOS or LSTTL output, down to 3.3V
logic. The output drivers feature a
high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be
used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600
volts.
IR2181/IR2183/IR2184 Feature Comparison
IR2184(4)(S) & (PbF)
2www.irf.com
Symbol Definition Min. Max. Units
VBHigh side floating absolute voltage -0.3 625
VSHigh side floating supply offset voltage VB - 25 VB + 0.3
VHO High side floating output voltage VS - 0.3 VB + 0.3
VCC Low side and logic fixed supply voltage -0.3 25
VLO Low side output voltage -0.3 VCC + 0.3
DT Programmable dead-time pin voltage (IR21844 only) VSS - 0.3 VCC + 0.3
VIN Logic input voltage (IN & SD) VSS - 0.3 VSS + 10
VSS Logic ground (IR21844 only) VCC - 25 VCC + 0.3
dVS/dt Allowable offset supply voltage transient — 50 V/ns
PDPackage power dissipation @ TA ≤ +25°C (8-lead PDIP) — 1.0
(8-lead SOIC) — 0.625
(14-lead PDIP) — 1.6
(14-lead SOIC) — 1.0
RthJA Thermal resistance, junction to ambient (8-lead PDIP) — 125
(8-lead SOIC) — 200
(14-lead PDIP) — 75
(14-lead SOIC) — 120
TJJunction temperature — 150
TSStorage temperature -50 150
TLLead temperature (soldering, 10 seconds) — 300
V
°C
°C/W
W
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential.
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: IN and SD are internally clamped with a 5.2V zener diode.
VB High side floating supply absolute voltage VS + 10 VS + 20
VSHigh side floating supply offset voltage Note 1 600
VHO High side floating output voltage VSVB
VCC Low side and logic fixed supply voltage 10 20
VLO Low side output voltage 0 VCC
VIN Logic input voltage (IN & SD) VSS VSS + 5
DT Programmable dead-time pin voltage (IR21844 only) VSS VCC
VSS Logic ground (IR21844 only) -5 5
TAAmbient temperature -40 125 °C
V
Symbol Definition Min. Max. Units
IR2184(4)(S) & (PbF)
www.irf.com 3
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, VSS = COM, CL = 1000 pF, TA = 25°C, DT = VSS unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn-on propagation delay — 680 900 VS = 0V
toff Turn-off propagation delay — 270 400 VS = 0V or 600V
tsd Shut-down propagation delay — 180 270
MTon Delay matching, HS & LS turn-on — 0 90
MToff Delay matching, HS & LS turn-off — 0 40
trTurn-on rise time — 40 60 VS = 0V
tfTurn-off fall time — 20 35 VS = 0V
DT Deadtime: LO turn-off to HO turn-on(DTLO-HO) & 280 400 520 RDT= 0
HO turn-off to LO turn-on (DTHO-LO) 456µsec RDT = 200k
MDT Deadtime matching = DTLO - HO - DTHO-LO — 0 50 RDT=0
— 0 600 RDT = 200k
nsec
nsec
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V, VSS = COM, DT= VSS and TA = 25°C unless otherwise specified. The VIL, VIH and IIN
parameters are referenced to VSS /COM and are applicable to the respective input leads: IN and SD. The VO, IO and Ron
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic “1” input voltage for HO & logic “0” for LO 2.7 — — VCC = 10V to 20V
VIL Logic “0” input voltage for HO & logic “1” for LO — — 0.8 VCC = 10V to 20V
VSD,TH+ SD input positive going threshold 2.7 —— V
CC = 10V to 20V
VSD,TH- SD input negative going threshold ——
0.8 VCC = 10V to 20V
VOH High level output voltage, VBIAS - VO— — 1.2 IO = 0A
VOL Low level output voltage, VO— — 0.1 IO = 0A
ILK Offset supply leakage current — — 50 VB = VS = 600V
IQBS Quiescent VBS supply current 20 60 150 VIN = 0V or 5V
IQCC Quiescent VCC supply current 0.4 1.0 1.6 mA VIN = 0V or 5V
IIN+ Logic “1” input bias current — 25 60 IN = 5V, SD = 0V
IIN- Logic “0” input bias current — — 1.0 IN = 0V, SD = 5V
VCCUV+ VCC and VBS supply undervoltage positive going 8.0 8.9 9.8
VBSUV+ threshold
VCCUV- VCC and VBS supply undervoltage negative going 7.4 8.2 9.0
VBSUV- threshold
VCCUVH Hysteresis 0.3 0.7 —
VBSUVH
IO+ Output high short circuit pulsed current 1.4 1.9 — VO = 0V,
PW ≤ 10 µs
IO- Output low short circuit pulsed current 1.8 2.3 — VO = 15V,
PW ≤ 10 µs
V
µA
µA
V
A
IR2184(4)(S) & (PbF)
4www.irf.com
Functional Block Diagrams
2184
SD
UV
DETECT
DELAY
IN VS
HO
VB
PULSE
FILTER
HV
LEVEL
SHIFTER
R
R
S
Q
UV
DETECT
PULSE
GENERATOR
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
+5V
DEADTIME
COM
LO
VCC
21844
SD
UV
DETECT
DELAY
IN
DT
VSS
VS
HO
VB
PULSE
FILTER
HV
LEVEL
SHIFTER
R
R
S
Q
UV
DETECT
PULSE
GENERATOR
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
+5V
DEADTIME
COM
LO
VCC
IR2184(4)(S) & (PbF)
www.irf.com 5
14-Lead PDIP 14-Lead SOIC
IR21844 IR21844S
Lead Assignments
8-Lead PDIP 8-Lead SOIC
Lead Definitions
Symbol Description
IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM
for IR2184 and VSS for IR21844)
SD Logic input for shutdown (referenced to COM for IR2184 and VSS for IR21844)
DT Programmable dead-time lead, referenced to VSS. (IR21844 only)
VSS Logic Ground (21844 only)
VBHigh side floating supply
HO High side gate drive output
VSHigh side floating supply return
VCC Low side and logic fixed supply
LO Low side gate drive output
COM Low side return
IR2184 IR2184S
1
2
3
4
8
7
6
5
IN
SD
COM
LO
VB
HO
VS
VCC
1
2
3
4
8
7
6
5
IN
SD
COM
LO
VB
HO
VS
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN
SD
VSS
DT
COM
LO
VCC
VB
HO
VS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN
SD
VSS
DT
COM
LO
VCC
VB
HO
VS
IR2184(4)(S) & (PbF)
6www.irf.com
Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions
Figure 5. Delay Matching Waveform Definitions
Figure 3. Shutdown Waveform Definitions
Figure 4. Deadtime Waveform Definitions
IR2184(4)(S) & (PbF)
www.irf.com 7
400
600
800
1000
1200
1400
-50 -25 0 25 50 75 100 125
T emperature (oC)
Turn-on P ropagation Delay (ns)
Typ.
Max.
F igure 4A. Turn-on Propagation Delay
vs. Temperature
400
600
800
1000
1200
1400
10 12 14 16 18 20
Su pply Voltage (V)
Turn-on P ropagation Delay (ns)
F igure4B. Turn-on Propagation Delay
vs. S upply Voltag e
Typ.
Max.
100
200
300
400
500
600
700
-50 -25 0 25 50 75 100 125
T emperature (oC)
Turn-off Propagation Delay (ns)
Typ.
Max.
F igure 5A. Turn-off P ropagation Delay
vs. Temperature
100
200
300
400
500
600
700
10 12 14 16 18 20
Su pply Voltage (V)
Turn-off Propagation Delay (ns)
F igure 5B. Turn-off Propagation Delay
vs. Supply Voltage
Typ.
Max.
IR2184(4)(S) & (PbF)
8www.irf.com
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
T emperature (oC)
SD Propagation Delay (ns)
Typ.
Max.
Figure 6A. S D Propag a tion Delay
vs. Temperature
0
100
200
300
400
500
10 12 14 16 18 20
Su pply Voltage (V)
SD P ropagation Delay (ns)
Figure 6B. S D Propag a tion Delay
v s. S u pply Voltage
Max.
Typ.
0
20
40
60
80
100
120
-50-250 255075100125
T emperature (oC)
Tu rn-o n Rise Tim e (n s)
Typ.
Max.
Figure 7 A . Turn-on Rise Time vs. Temperature
0
20
40
60
80
100
120
10 12 14 16 18 20
Su pply Voltage (V)
Turn -on Ri se T ime (ns)
Figure 7B. Turn-on Rise Time vs. Supply Voltag e
Typ.
Max.
IR2184(4)(S) & (PbF)
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0
20
40
60
80
-50 -25 0 25 50 75 100 125
T emperature (oC)
Tu rn-o ff Fall Tim e (n s)
Typ
Max.
Figure 8A. Turn-off Fall T ime v s. Temperature
0
20
40
60
80
10 12 14 16 18 20
Su pply Voltage (V)
Tu rn-o ff Fall Tim e (n s)
Figure 8B. Turn-off Fall T ime vs. S upply Voltage
Typ.
Max.
100
300
500
700
900
1100
-50 -25 0 25 50 75 100 125
T emperature (oC)
D e a d ti me (ns)
Min.
F igure 9A. Deadtime vs. Temperature
Typ.
Max.
100
300
500
700
900
1100
10 12 14 16 18 20
Su pply Voltage (v)
Deaduime (ns)
Figure 9B. Deadtime vs. Supply Voltag e
Typ.
Max.
Min.
IR2184(4)(S) & (PbF)
10 www.irf.com
0
1
2
3
4
5
6
7
0 50 100 150 200
RDT (KΗ)
Deadtime ( Ηs)
Figure 9C. Deadtime v s. RDT
Typ.
Max.
Min.
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
T emperature (oC)
Logic "1" Input V oltage (V)
Min.
Figure 10 A. Logic " 1 " I nput Voltage
vs. Temperature
0
1
2
3
4
5
6
10 12 14 16 18 20
Su pply Voltage (V)
Logic "1" Input Voltage (V )
Figure 10B. Logic " 1" Input Voltage
v s. S u pply Voltage
Min.
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
T emperature (oC)
Logic "0" Input V oltage (V)
Max.
Figure 11A . Logic "0 " Input Voltage
vs. Temperature
IR2184(4)(S) & (PbF)
www.irf.com 11
0
1
2
3
4
5
6
10 12 14 16 18 20
Su pply Voltage (V)
Logic "0" Input Voltage (V)
Figure 11B. Logic " 0" Input Voltage
v s. S u pply Voltage
Max.
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
T emperature (oC)
S D In put Positi ve Go i n g T h resho l d (V )
Min.
Figure 12 A. S D Input P ositive Going Threshold
v s. Temperature
0
1
2
3
4
5
6
10 12 14 16 18 20
Sup ply Voltage (V)
SD Input Positive Going Threshold (V)
Figure 1 2 B. SD Input Positiv e Going Threshold
vs. Supply Volta ge
Min.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
T emperature (oC)
SD Input Negative Going Threshold (V)
Max.
Figure 13 A. S D Input Nega tive Going Threshold
v s. Temperature
IR2184(4)(S) & (PbF)
12 www.irf.com
0
1
2
3
4
5
10 12 14 16 18 20
Su pply Voltage (V)
SD Input Negative Going Threshold (V)
Figure 13 B. S D Inp ut Nega tive Going Threshold
v s. S up ply Volta ge
Max.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
T emperature (oC)
High Level Output (V)
Max.
Figure 14 A. High Lev el Output vs. Temperature
0
1
2
3
4
5
10 12 14 16 18 20
Su pply Voltage (V)
High Level Output (V)
Figure 1 4 B. High Level Output vs. S upply Voltage
Max.
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
T emperature (oC)
Low Level Output (V)
Max.
Fig ure 15A . Lo w Lev el Ou tpu t v s. T emp erature
IR2184(4)(S) & (PbF)
www.irf.com 13
0.0
0.1
0.2
0.3
0.4
0.5
10 12 14 16 18 20
Su pply Voltage (V)
Low Level Output (V)
F igure 15B. Low Level O utput vs. Supply Voltage
Max.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
T emperature (oC)
Offset S upply Leakage Current ( ΗA)
Max.
Figure 16 A. Offset S upply Leakage C urrent vs.
Temperature
0
100
200
300
400
500
100 200 300 400 500 600
VB B oost Voltage (V)
Offset Sup p l y Leakage Current ( ΗA)
F igure 16B. O ffset Supply Leakage Current vs.
VB Boost Voltage
Max.
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
T emperature (oC)
VBS Su pply Current ( ΗA)
Min.
Figure 17A. VBS Supp ly C urrent
vs. Temperature
Typ.
Max.
IR2184(4)(S) & (PbF)
14 www.irf.com
0
50
100
150
200
250
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
VBS Supply Current ( ΗA)
Figure 17B. VBS S upply C urrent
vs. VBS F loa ting S upply Voltage
Typ.
Max.
Min.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
T emperature (oC)
VCC Su pp ly C urre nt (mA)
Min.
Figure 18A. VCC Supply C urrent
v s. Temperature
Typ.
Max.
0
1
2
3
4
5
10 12 14 16 18 20
VCC Supply Voltage (V)
VCC S u p p l y Cu rre n t (m A)
F igure 18B. VCC Su pply C urrent
vs. VCC S u pply Voltage
Typ.
Max.
Min.
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
T emperature (oC)
Logic "1" Input Bias Current ( ΗA)
Figure 1 9 A. Logic " 1 " Input Bia s Cu rrent
v s. Temperature
Typ.
Max.
IR2184(4)(S) & (PbF)
www.irf.com 15
0
20
40
60
80
100
120
10 12 14 16 18 20
Sup ply Voltage (V)
Logic "1" Input Bias Current ( ΗA)
F igure 19B. Logic "1" Input Bias Current
vs. Supply Volta ge
Typ.
Max.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
T emperature (oC)
Logic "0" Input Bi as Current ( ΗA)
Max.
Figure 20 A. Logic " 0 " Input Bias Cu rrent
vs. Temperature
0
1
2
3
4
5
10 12 14 16 18 20
Su pply Voltage (V)
Logic "0" Input Bias Current ( ΗA)
F igure 20B. Logic "0" Input Bias Current
vs. Supply Voltage
Max.
6
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
T emperature (oC)
VCC and V BS UV Thre s ho ld (+) (V)
Min.
F igure 21. VCC and VBS Undervoltage Threshold (+ )
vs. Temperature
Typ.
Max.
IR2184(4)(S) & (PbF)
16 www.irf.com
6
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
T emperature (oC)
VCC and V BS U VThre sho ld (- ) (V)
Min.
Figure 2 2 . VCC and VBS Undervolta ge Threshold (-)
vs. Temperature
Typ.
Max.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
T emperature (oC)
Outp u t Sou rce Curren t (A )
Min.
Figure 23A . Output Source Current
v s. Temperature
Typ.
0
1
2
3
4
5
10 12 14 16 18 20
Su pply Voltage (V)
Outp ut S o u rce Curren t (A )
Figure 23 B. O utput S ource Current
vs. S upply Voltage
Typ.
Min. 1.0
2.0
3.0
4.0
5.0
-50 -25 0 25 50 75 100 125
T emperature (oC)
Output Sink Current (A)
Min.
Figure 24 A. Output Sink C urrent
v s. Temperature
Typ.
IR2184(4)(S) & (PbF)
www.irf.com 17
0
1
2
3
4
5
10 12 14 16 18 20
Sup ply Voltage (V)
Output Sink Current (A)
Figure 24 B. Output S ink Current
v s. S up ply Volta ge
Typ.
Min.
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temprature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
Figure 21. IR2181 vs. Frequency (IRFBC20),
R
gate
=33
Ω
, V
CC
=15V
Figure 22. IR2181 vs . Frequency (IRFBC30),
R
gate
=22
Ω
, V
CC
=15V Figure 23. IR2181 vs . Frequency (IRFBC40),
R
gate
=15
Ω
, V
CC
=15V
IR2184(4)(S) & (PbF)
18 www.irf.com
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
70v
0v
140v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
Figure 24. IR2181 vs. Frequency (IRFPE50),
R
gate
=10
Ω
, V
CC
=15V Figure 25. IR21814 vs . Frequency (IRFBC20),
R
gate
=33
Ω
, V
CC
=15V
Figure 26. IR21814 vs. Frequency (IRFBC30),
R
gate
=22
Ω
, V
CC
=15V Figure 27. IR21814 vs . Frequency (IRFBC40),
R
gate
=15
Ω
, V
CC
=15V
IR2184(4)(S) & (PbF)
www.irf.com 19
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
70v
0v
140v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
0v
140v 70v
Figure 28. IR21814 vs . Frequency (IRFPE50),
R
g
ate
=10
Ω
, V
CC
=15V Figure 29. IR2181s vs. Frequency (IRFBC20),
R
gate
=33
Ω
, V
CC
=15V
Figure 30. IR2181s vs. Frequency (IRFBC30),
R
gate
=22
Ω
, V
CC
=15V Figure 31. IR2181s vs. Frequency (IRFBC40),
R
gate
=15
Ω
, V
CC
=15V
IR2184(4)(S) & (PbF)
20 www.irf.com
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Tempreture (
oC)
140V 70V 0V
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Fr equency (KHz)
Temperature (
oC)
140v
70v
0v
20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v
70v
0v
Figure 35. IR21814s vs. Frequency (IRF BC40),
Rgate=15Ω, VCC=15V
Figure 34. IR21814s vs. Frequency (IRF BC30),
Rgate=22Ω, VCC=15V
Figure 33. I R21 814 s vs. Frequency (IRFBC20),
Rgate=33Ω, VCC=15V
F igure 32. IR2181s vs. F requency (IRF P E50),
Rgate=10Ω, VCC=15V
IR2184(4)(S) & (PbF)
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20
40
60
80
100
120
140
1 10 100 1000
Frequency (KHz)
Temperature (
oC)
140v 70v
0v
Figure 36. IR21814s vs. Frequency (IRF P E50),
Rgate=10Ω, VCC=15V
IR2184(4)(S) & (PbF)
22 www.irf.com
01-6014
01-3003 01 (MS-001AB)
8-Lead PDIP
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
87
5
65
D B
E
A
e
6X
H
0. 25 [.010 ] A
6
4312
4 . OUT LINE CONFORMS TO JEDEC OUTLINE MS- 012AA.
NOTES:
1. DI MENSI ONING & TOLERANCI NG PER ASME Y14.5M-1994.
2 . CONT ROLLING DIMENSION: MIL LIMETER
3 . D IMENSIONS ARE SHOW N IN MILLIMETERS [ INCHES] .
7
K x 4 5 °
8X L 8X c
y
FOOTPRINT
8X 0.72 [ . 02 8]
6. 46 [ . 2 55]
3X 1.27 [ . 05 0] 8X 1. 78 [ .070]
5 D IMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 D IMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSI ONS NOT TO EXCEED 0.25 [.010].
7 D IMENSION IS THE LENGTH OF LEA D FOR SOL DERING TO
A SUBSTRATE.
MOLD PROTRUSI ONS NOT TO EXCEED 0.15 [.006].
0. 25 [.010 ] CAB
e1 A
A1
8X b
C
0. 10 [.004 ]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASI C
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINC HE S MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASI C 0.635 BASI C
IR2184(4)(S) & (PbF)
www.irf.com 23
01-6019
01-3063 00 (MS-012AB)
14-Lead SOIC (narrow body)
01-6010
01-3002 03 (MS-001AC)
14-Lead PDIP
IR2184(4)(S) & (PbF)
24 www.irf.com
Basic Part (Non-Lead Free)
8-Lead PDIP IR2184 order IR2184
8-Lead SOIC IR2184S order IR2184S
14-Lead PDIP IR21844 order IR21844
14-Lead SOIC IR21844 order IR21844S
Leadfree Part
8-Lead PDIP IR2184 order IR2184PbF
8-Lead SOIC IR2184S order IR2184SPbF
14-Lead PDIP IR21844 order IR21844PbF
14-Lead SOIC IR21844 order IR21844SPbF
ORDER INFORMATION
LEADFREE PART MARKING INFORMATION
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRxxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
P
?MARKING CODE
Thisproduct has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web Site http://www.irf.com
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
4/4/2006
