PIC16F631/677/685/687/689/690 PIC16F631/677/685/687/689/690 Family Silicon Errata and Data Sheet Clarification The PIC16F631/677/685/687/689/690 family devices that you have received conform functionally to the current Device Data Sheet (DS41262E), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2, MPLAB ICD 3, PICkitTM 2 or PICkitTM 3: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2 through Table 6. 2. The errata described in this document will be addressed in future revisions of the PIC16F631/677/685/687/689/ 690 silicon. Note: 3. 4. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 through Table 6 apply to the current silicon revision. Note: Data Sheet clarifications and corrections start on page 12, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger, PICkitTM 2 or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Programmer>Select Tool). Perform a "Connect" operation to the device (Programmer>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The Device ID values for the various devices and silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number PIC16F631 Device ID(1) Revision ID for Silicon Revision(2) A1 A3 A4 A5 A6 142x 1 PIC16F677 132x 1 PIC16F685 04Ax 3 4 5 6 PIC16F687 132x 3 4 5 6 PIC16F689 134x 3 4 5 6 PIC16F690 134x 3 4 5 6 Note 1: 2: The device and revision data is stored in the Device ID located at 2006h in program memory. Refer to the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for detailed information. 2010 Microchip Technology Inc. DS80243M-page 1 PIC16F631/677/685/687/689/690 TABLE 2: SILICON ISSUE SUMMARY (PIC16F631) Affected Revisions(1) Feature Item Number Ext. Crystal 5.1 Overflow may take additional count. Timer1 Ext. Crystal 5.2 Oscillator may stop running at low temps. X Timer1 Ext. Crystal 5.3 Sleep in LP mode disables T1OSC. X Prescaler 6. Spurious Reset may occur. X Module Timer1 WDT/Timer0 Note 1: Issue Summary A1 X Only those issues indicated in the last column apply to the current silicon revision. TABLE 3: SILICON ISSUE SUMMARY (PIC16F677) Affected Revisions(1) Feature Item Number SSP Start Bit 2.1 SSP SSPIF Flag 2.2 SSPIF flag set on first reception only. X 4. Oscillator may stop running at low temps. X Module ADC/INTOSC Freq. Disturbance Issue Summary A1 Fail to recognize Start bit. Timer1 Ext. Crystal 5.1 Overflow may take additional count. X Timer1 Ext. Crystal 5.2 Oscillator may stop running at low temps. X Timer1 Ext. Crystal 5.3 Sleep in LP mode disables T1OSC. X Prescaler 6. Spurious Reset may occur. X WDT/Timer0 Note 1: Only those issues indicated in the last column apply to the current silicon revision. TABLE 4: SILICON ISSUE SUMMARY (PIC16F685) Module ECCP Feature Item Number Affected Revisions(1) Issue Summary A3 A4 A5 A6 Auto-Shutdown 3. Overflow may take additional count. X X Freq. Disturbance 4. Oscillator may stop running at low temps. X X X X Timer1 Ext. Crystal 5.1 Overflow may take additional count. X X X X Timer1 Ext. Crystal 5.2 Oscillator may stop running at low temps. X X X X Timer1 Ext. Crystal 5.3 Sleep in LP mode disables T1OSC. X X X X Prescaler 6. Spurious Reset may occur. X X X X ADC/INTOSC WDT/Timer0 Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80243M-page 2 2010 Microchip Technology Inc. PIC16F631/677/685/687/689/690 TABLE 5: SILICON ISSUE SUMMARY (PIC16F687/PIC16F689) Affected Revisions(1) Feature Item Number EUSART Wake-up 1.1 WUE bit not clearing. EUSART Auto-Baud 1.2 Incorrect baud rate after a break. X X EUSART Auto-Baud 1.3 Baud rate value +2. X X EUSART Auto-Baud 1.4 Delay after auto-baud before transmit. X X EUSART Auto-Baud 1.5 R/W bit on ACK. X X EUSART Reset 1.6 Clock-stretching handling. X X EUSART Extra Character 1.7 Multi-byte transmission. X X SSP Start Bit 2.1 Fail to recognize Start bit. X X X SSP SSPIF Flag 2.2 SSPIF flag set on first reception only. X X X X Module ADC/INTOSC Issue Summary A3 A4 X X A5 A6 Freq. Disturbance 4. Oscillator may stop running at low temps. X X X X Timer1 Ext. Crystal 5.1 Overflow may take additional count. X X X X Timer1 Ext. Crystal 5.2 Oscillator may stop running at low temps. X X X X Timer1 Ext. Crystal 5.3 Sleep in LP mode disables T1OSC. X X X X Prescaler 6. Spurious Reset may occur. X X X X WDT/Timer0 Note 1: Only those issues indicated in the last column apply to the current silicon revision. TABLE 6: SILICON ISSUE SUMMARY (PIC16F690) Affected Revisions(1) Feature Item Number EUSART Wake-up 1.1 WUE bit not clearing. EUSART Auto-Baud 1.2 Incorrect baud rate after a break. X X EUSART Auto-Baud 1.3 Baud rate value +2. X X EUSART Auto-Baud 1.4 Delay after auto-baud before transmit. X X EUSART Auto-Baud 1.5 R/W bit on ACK. X X EUSART Reset 1.6 Clock-stretching handling. X X EUSART Extra Character 1.7 Multi-byte transmission. X X SSP Start Bit 2.1 Fail to recognize Start bit. X X X SSP SSPIF Flag 2.2 SSPIF flag set on first reception only. X X X X Module ECCP Issue Summary A3 A4 X X A5 A6 Auto-Shutdown 3. Overflow may take additional count. X X X X Freq. Disturbance 4. Oscillator may stop running at low temps. X X X X Timer1 Ext. Crystal 5.1 Overflow may take additional count. X X X X Timer1 Ext. Crystal 5.2 Oscillator may stop running at low temps. X X X X Timer1 Ext. Crystal 5.3 Sleep in LP mode disables T1OSC. X X X X Prescaler 6. Spurious Reset may occur. X X X X ADC/INTOSC WDT/Timer0 Note 1: Only those issues indicated in the last column apply to the current silicon revision. 2010 Microchip Technology Inc. DS80243M-page 3 PIC16F631/677/685/687/689/690 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision. 1. Module: EUSART (PIC16F687/689/690 only) 1.1 WUE Bit is not clearing. After a wake-up due to a Break character, the WUE bit is not automatically cleared. Work around Clear the WUE bit after waking up. 1.3 Auto-baud calculates a baud rate value that is +2. The SPBRGH:SPBRG are not initialized correctly when ABDEN is set. This causes the measured baud rate to be high by two counts. Work around Clearing the SPBRGH:SPBRG registers will correctly initialize the baud rate counter. After the auto-baud has been completed, the baud rate will now be +1. The firmware should now subtract 1 from the Baud Rate Generator to produce the correct baud rate. Fix Rev. A5 Silicon and later revisions. Affected Silicon Revisions PIC16F687/PIC16F689/PIC16F690 Fix Rev. A5 Silicon and later revisions. Affected Silicon Revisions PIC16F687/PIC16F689/PIC16F690 A3 A4 X X A5 A6 1.2 Auto-baud captures the incorrect baud rate after a break. The SPBRGH:SPBRG registers are not being initialized correctly. If WUE and ABDEN are set at the same time and a Break character followed by a Sync character are received, then the calculated baud rate will be random. Work around Set WUE and wait for the wake-up to occur. Clear SPBRGH:SPBRG after waking up with the break. Set ABDEN to begin the auto-baud process. Fix Rev. A5 Silicon and later revisions. Affected Silicon Revisions A3 A4 X X A5 A6 1.4. Delay after auto-baud before transmit is allowed. After the auto-baud Sync character has been received and the RCIF flag is set, there is approximately 17 ms of delay before the transmitter is enabled. Work around After the RCIF flag is set indicating the baud rate has been measured, read the SPBRG register and write the value back to SPBRG. This will terminate the delay, and enable the transmitter module. Fix Rev. A5 Silicon and later revisions. Affected Silicon Revisions PIC16F687/PIC16F689/PIC16F690 A3 A4 X X A5 A6 PIC16F687/PIC16F689/PIC16F690 A3 A4 X X DS80243M-page 4 A5 A6 2010 Microchip Technology Inc. PIC16F631/677/685/687/689/690 1.5 Auto-baud sequence cannot be aborted in some cases. If an auto-baud is started but no edges are received, there is no way to leave Auto-Baud mode. Work around Use the Watchdog Timer to reset the entire device. Fix Rev. A5 Silicon and later revisions. Affected Silicon Revisions PIC16F687/PIC16F689/PIC16F690 A3 A4 X X A5 A6 1.7 Extra character transmitted after auto-baud. If TXEN is high when ABDEN is set, it will be cleared as soon as the auto-baud process begins, and reset as soon as the auto-baud process completes. When TXEN is reset, the character in the transmit queue will be transmitted. Work around Before starting auto-baud, clear TXEN. This will reset the transmit state machine correctly. After the auto-baud is complete and the firmware has brought TXEN high, no character will be transmitted. Fix Rev. A5 Silicon and later revisions. Affected Silicon Revisions 1.6 Clearing SPEN does not reset EUSART state machine correctly. When SPEN is cleared, the entire EUSART is frozen. When SPEN is set, the EUSART resumes where it left off. This can cause some unexpected behavior. PIC16F687/PIC16F689/PIC16F690 A3 A4 X X A5 A6 Work around To reset the EUSART, toggle TXEN and CREN after clearing SPEN. This will reset the transmit and receive state machines. Fix Rev. A5 Silicon and later revisions. Affected Silicon Revisions PIC16F687/PIC16F689/PIC16F690 A3 A4 X X A5 A6 2010 Microchip Technology Inc. DS80243M-page 5 PIC16F631/677/685/687/689/690 2. Module: SSP (PIC16F687/689/690 only) 2.1 SSP module does not recognize first Start bit received. 2.2 Under certain conditions, the SSPIF flag sets on reception of the first byte. When all of the following conditions are met: In any of the I CTM modes, the SSP module will fail to recognize the first Start bit received after a transition from module disable to module enable. Subsequent Stop bits and Start bits are detected properly. * * * * Work around The SSPIF flag will only be set on reception of the first byte and the following bytes will not be correctly received. 2 Enable the SSP module in SSPMSK Access mode before changing the mode to the desired I2C operation. EXAMPLE 1: CODE EXAMPLE MOVLW MOVWF B'00111001' SSPCON MOVLW MOVWF B'00110110' SSPCON ;Module enable, clock ;enable, SSPMSK access. ;Optionally load ;address mask value ;into SSPMSK register. ;Module enable, clock ;enable, 7-bit address ;I2C slave. The module is configured as a SPI slave CKP = 1 CKE = 1 Multiple bytes are sent with the SS line remaining low between bytes Work around * Toggle the SS line between bytes or * On reception of the first byte modify the SSPM bits in the SSPCON register to configure the module as a SPI slave with SS pin disabled. Then restore the SSPM bits to the configuration for SPI slave with SS pin enabled. The module is then ready for reception of the following byte. Fix None. Fix Rev. A6 Silicon and later revisions. Affected Silicon Revisions Affected Silicon Revisions PIC16F677 A1 PIC16F677 X A1 PIC16F687/PIC16F689/PIC16F690 PIC16F687/PIC16F689/PIC16F690 A3 A4 A5 X X X DS80243M-page 6 A6 A3 A4 A5 A6 X X X X 2010 Microchip Technology Inc. PIC16F631/677/685/687/689/690 3. Module: ECCP with Auto-Shutdown (Silicon Rev. A4 and previous revisions) (PIC16F685 and PIC16F690 only) Fix Rev. A5 Silicon and later revisions. The PIC16F631/677/685/687/689/690 Rev. A4 silicon for the ECCP auto-shutdown is connected to the C1IF and C2IF flags. See Figures 8-2 and 8-3 on the following page. The auto-shutdown connection (Rev. A4 and previous) to C1IF and C2IF causes the autoshutdown to incorrectly operate synchronously. Additionally, reads of CMxCON0 will incorrectly clear an auto-shutdown event. The Silicon Rev. A5 (now shipping) and later revision devices have moved the auto-shutdown connection from CxIF to CxOUT. This will eliminate the synchronous shutdown and simplify the use of the comparator for a shutdown event. Figure 1 shows the function of auto-shutdown before and after the device revision. Affected Silicon Revisions PIC16F685 Work around Rev. A4 Silicon and previous revisions. A4 X X Poll the CxOUT bit until it is low. 2) Read CMxCON0 to precondition CxIF. 3) If CMxCON0 is read while CxOUT is changing, repeat steps 1 and 2. A4 A5 A6 X X X X COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1POL 2 C12IN0- 0 C12IN1C12IN2- 1 MUX 2 C12IN3- 3 D Q1 Q EN D C1VREN 0 MUX 1 0 MUX 1 (1) 2010 Microchip Technology Inc. Set C1IF EN CL NRESET Rev. A4 and previous: To ECCP Auto-Shutdown To other peripherals C1VIN- C1 C1VIN+ + C1OUT C1POL Note 1: 2: 3: Q Q3*RD_CM1CON0 C1ON C1IN+ To Data Bus RD_CM1CON0 C1R CVREF A6 A3 C1CH<1:0> FixedRef A5 PIC16F690 1) FIGURE 8-2: A3 C1OUT (to SR latch) Rev. A5: To ECCP Auto-Shutdown When C1ON = 0, the C1 comparator will produce a `0' output to the XOR Gate. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode. DS80243M-page 7 PIC16F631/677/685/687/689/690 FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM C2POL D Q1 To Data Bus Q EN RD_CM2CON0 C2CH<1:0> 2 D Q3*RD_CM2CON0 EN CL NRESET C2ON(1) C12IN0- 0 C12IN1C2IN2- 1 MUX 2 C2IN3- 3 C2VINC2VIN+ C2SYNC C2POL D C2IN+ FixedRef CVREF 0 MUX 1 0 MUX 1 Note 1: 2: 3: C2VREN FIGURE 1: Rev. A4 and previous: To ECCP Auto-Shutdown C2OUT C2 C2R Set C2IF Q Q Rev. A5: To ECCP Auto-Shutdown 0 MUX 1 SYNCC2OUT to Timer1 Gate, SR latch and other peripherals From TMR1 Clock When C2ON = 0, the C2 comparator will produce a `0' output to the XOR Gate. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode. SILICON REVISION A4 AND PREVIOUS VS. REVISION A5 A4 and previous revisions CCP Output Rev. A5 CCP Output CxOUT CxIF Uncertainty due to Q1 cycle delay DS80243M-page 8 Read CMxCON0 Uncertainty due to Q1 cycle delay Read CMxCON0 2010 Microchip Technology Inc. PIC16F631/677/685/687/689/690 4. Module: Analog-To-Digital Converter (ADC) Module (PIC16F685/687/689/690 Only) Selecting the VP6 reference as the analog input source (CHS<3:0> = 1101) for the ADC conversion after sampling another analog channel with input voltages approximately greater than 1.2V can temporarily disturb the HFINTOSC oscillator. Note: This only occurs when selecting the VP6 reference ADC channel using the CHS<3:0> bits in the ADCON0 register and NOT during the start of an actual ADC conversion using the GO/ DONE bit in the ADCON0 register. Work around Select an ADC channel with input voltages lower than 1.2V prior to selecting the VP6 reference voltage input. Any analog channel can be used, even if that channel is configured as a digital I/O (configured as an output) that is driving the output pin low. An alternative is to configure the CVREF module to output a voltage less than 1.2V and then selecting that analog channel CHS<3:0> = 1100 as the analog input source. EXAMPLE 2: BANKSEL MOVLW MOVWF MOVLW MOVWF AVOID DISTURBING THE HFINTOSC OSCILLATOR ADCON0 B'XX110001' ADCON0 B'XX110101' ADCON0 ; ;Select ADC ;Channel CVREF ;Select ADC ;Channel VP6 Silicon Fix 5. Module: Timer1 5.1 Asynchronous Timer1 This Errata supersedes Errata DS80233 and DS80329. When TImer1 is started or updated, the timer needs to see a falling edge from the external clock source before a rising edge can increment the counter. If writes to TMR1H and TMR1L are not completed while the external clock pulse is still high, Timer1 will not count the first clock pulse after the update. When using an external crystal, the pulse width from rising to falling edge is temperature dependent and may decrease with temperature. As a result, the timer may require an additional oscillation to overflow. Work around Switching to the HFINTOSC after reloading, the timer ensures the Timer1 will see a falling edge before switching back to the external clock source. Due to the time from Timer1 overflow to the reload being application specific, wait for the timer to increment before beginning the reload sequence. This ensures the timer does not miss a rising edge during reload. Affected Silicon Revisions PIC16F631/PIC16F677 A1 X PIC16F685/PIC16F687/PIC16F689/ PIC16F690 None. Affected Silicon Revisions PIC16F677 A3 A4 A5 A6 X X X X A1 X PIC16F685/PIC16F687/PIC16F689/ PIC16F690 A3 A4 A5 A6 X X X X 2010 Microchip Technology Inc. DS80243M-page 9 PIC16F631/677/685/687/689/690 EXAMPLE 3: BTFSC GOTO BTFSS GOTO TMR1L,0 $-1 TMR1L,0 $-1 ;Timer has just incremented, 31 s before next rising edge to ;complete reload Update: BCF BSF BCF BSF BCF T1CON,TMR1CS TMR1H,7 T1CON,TMR1ON T1CON,TMR1CS T1CON,TMR1ON ;Select ;Timer1 ;Timer1 ;Select ;Timer1 HFINTOSC for Timer1 high byte 0x80 off external crystal on Critical Timing of code sequence for instructions following last write to TMR1L or TMR1H. 5.2 LP/Timer1 Oscillator Operation Below 25C 1-2% of devices experience reduced drive as temperatures approach -40C. This will result in a loss of Timer1 counts or stopped Timer1 oscillation. 5.3 LP/Timer1 Oscillator Shared Operation This can also prevent Timer1 oscillator start-up under cold conditions. When using LP oscillator as the system clock and enabling Timer1 external oscillator, the shared crystal will clock both the core and Timer1. On execution of the SLEEP instruction, the oscillator amplifier will be disabled and Timer1 will not be clocked while the device is in Sleep. Work around Work around Use of low-power crystals properly matched to the device will reduce the likelihood of failure. A 1M resistor between OSC2 and VDD will further improve the drive strength of the circuit. None. Affected Silicon Revisions PIC16F631/PIC16F677 Affected Silicon Revisions PIC16F631/PIC16F677 A1 X PIC16F685/PIC16F687/PIC16F689/ PIC16F690 A1 X PIC16F685/PIC16F687/PIC16F689/ PIC16F690 A3 A4 A5 A6 X X X X DS80243M-page 10 A3 A4 A5 A6 X X X X 2010 Microchip Technology Inc. PIC16F631/677/685/687/689/690 6. Module: Timer0 and WDT Prescaler Assignment Spurious Reset A spurious Reset may occur if the Timer0/Watchdog Timer (WDT) prescaler is assigned from the WDT to Timer0 and then back to the WDT. Work around 1. Disable the Timer0 external clock input by clearing the TOCKI bit in the OPTION register. 2. Modify the TOSE bit in the OPTION register to the opposite configuration for the logic level on the T0CKI pin. 3. Select a prescaler rate other than 1:1 and issue a CLRWDT instruction before switching to the final prescaler rate. Summary The issue only arises when all of the below conditions are met: * Timer0 external clock input (TOCKI) is enabled. * The Prescaler is assigned to the WDT, then to the Timer0 and back to the WDT. * During the assignments, the T0CKI pin is high when bit TOSE is set, or low when TOSE is clear. * The 1:1 Prescaler option is chosen. Description On a POR, the Timer0/WDT prescaler is assigned to the WDT. If the prescaler is reassigned to Timer0 and Timer0 external clock input (TOCKI) is enabled then the prescaler would be clocked by a transition on the TOCKI pin. Affected Silicon Revisions PIC16F631/PIC16F677 A1 X PIC16F685/PIC16F687/PIC16F689/ PIC16F690 A3 A4 A5 A6 X X X X On power-up, the TOCKI pin is (by default) enabled for Timer0 in the OPTION register. If the T0CKI pin is: * High and Timer0 is configured to transition on a falling edge (TOSE set), or * Low and Timer0 is configured to transition on a rising edge (TOSE clear) Then, if the prescaler is reassigned to the WDT, a clock pulse to the prescaler will be generated on the reassignment. If the prescaler is configured for the 1:1 option, the clock pulse will incorrectly cause a WDT Time-out Reset of the device. 2010 Microchip Technology Inc. DS80243M-page 11 PIC16F631/677/685/687/689/690 Data Sheet Clarifications The following typographical corrections and clarifications are to be noted for the latest version of the device data sheet (DS41262E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Peripheral Features Corrections Summary. TABLE 1: to Table 1: PIC16F631 Pin PIC16F631 PIN SUMMARY I/O Pin Analog Comparators Timers Interrupt Pull-up Basic RA0 19 AN0/ULPWU C1IN+ -- IOC Y ICSPDAT RA1 18 -- C12IN0- -- IOC Y ICSPCLK RA2 17 -- C1OUT T0CKI IOC/INT Y -- MCLR/VPP RA3 4 -- -- -- IOC Y(1) RA4 3 -- -- T1G IOC Y OSC2/CLKOUT RA5 2 -- -- T1CKI IOC Y OSC1/CLKIN RB4 13 -- -- -- IOC Y -- RB5 12 -- -- -- IOC Y -- RB6 11 -- -- -- IOC Y -- RB7 10 -- -- -- IOC Y -- RC0 16 -- C2IN+ -- -- -- -- RC1 15 -- C12IN1- -- -- -- -- RC2 14 -- C12IN2- -- -- -- -- RC3 7 -- C12IN3- -- -- -- -- RC4 6 -- C2OUT -- -- -- -- RC5 5 -- -- -- -- -- -- RC6 8 -- -- -- -- -- -- RC7 9 -- -- -- -- -- -- -- 1 -- -- -- -- -- VDD -- 20 -- -- -- -- -- VSS Note 1: Pull-up enabled only with external MCLR configuration. DS80243M-page 12 2010 Microchip Technology Inc. PIC16F631/677/685/687/689/690 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (7/2005) Original release of this document. Clarifications/Corrections to the Data Sheet: Added Modules 1 through 7: Module 1: Device VDD Range Module 2: 4x4 QFN Package Marking Module 3: Table 1-1: Pinout Description - PIC16F685 Module 4: Register 10-5: EECON1 Module 5: Table11-2: Registers Associated with Capture, Compare and Timer1 Module 6: Section 12.0 EUSART Module 7: Section 14.2.2 MCLR Rev B Document (8/2005) Silicon Section: Added Module 1: EUSART (PIC16F687/689/690 only). Clarifications/Corrections to the Data Sheet: Added Modules 8 and 9: Module 8: SSP Module Overview Module 9: Electrical Specifications. Rev J Document (09/2008) Added Module 2.2: Under certain conditions, the SSPIF flag sets on reception of the first byte (under new 2. SSP (PIC16F687/689/690 only)), while changing Module 2. to 2.1. Revised Module 5: LP/ Timer1 Oscillator Operations Below 25C. Added Module 6: SSP. Clarifications/Corrections to the Data Sheet: Removed Modules 1 through 4, which have been included in the latest data sheet revision. Rev K Document (04/2009) Updated Errata to new format. Deleted Module 6: SSP (PIC16F687/689/690). Added Module 5: Timer1; Added Module 6: Timer0 and WDT Prescaler Assignment Spurious Reset. Rev L Document (07/2009) Data Sheet Clarifications: Added Module 1: Peripheral Features (Table 1: PIC16F631 Pin Summary). Rev M Document (05/2010) Added Module 5.3. Rev C Document (11/2005) Silicon Section: Added Module 2: SSP (PIC16F687/689/690 only) Rev D Document (01/2006) Clarifications/Corrections to the Data Sheet: Replaced the 20-Lead QFN package diagram in Module 2: 4x4 QFN Package Marking. Rev E Document (7/2006) Data Sheet Clarifications/Corrections Section: Removed Items 1 through 9, which have been incorporated into the data sheet. Added Item 1, 20-pin QFN Pin Diagram Title change. Rev F Document (11/2006) Data Sheet Clarifications/Corrections Section: Added Item 2, Product Identification System, Examples change. Added Module 3: ECCP with Auto-Shutdown (Silicon Rev. B2). Updated Module1: EUSART (PIC16F687/ 689/690 only) and Module2: SSP (PIC16F687/689/690 only) with Fix information. Rev G Document (01/2007) Removed Rev. A6 reference from Module 2 (SSP). Data Sheet Clarifications/Corrections Section: Added Module 3, Comparator and Voltage Reference Modules Associated Registers, removed REFCON register reference. Added Module 4: DC Characteristics, Table 17.3, revised Max values. Rev H Document (07/2007) Added Module 4: Analog-to-Digital Converter (ADC) Module. Module 2: Added Fix. 2010 Microchip Technology Inc. DS80243M-page 13 PIC16F631/677/685/687/689/690 NOTES: . DS80243M-page 14 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." 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Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-223-6 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. DS80243M-page 15 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/05/10 DS80243M-page 16 2010 Microchip Technology Inc.