NB6L11 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator. The device has the same pinout and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the device is optimized for the systems that require LOW skew, LOW jitter and LOW power consumption. Differential input can be configured to accept single-ended signal by applying an external reference voltage to unused complementary input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS, CML, or LVDS. The outputs are 800 mV ECL signals. http://onsemi.com MARKING DIAGRAMS* 8 8 1 SO-8 D SUFFIX CASE 751 1 6L11 ALYW G G Features * * * * * * * * * * * * Input Clock Frequency w 6 GHz Input Data Rate w 6 Gb/s Low 14 mA Typical Power Supply Current 150 ps Typical Propagation Delay 5 ps Typical Within Device Skew 75 ps Typical Rise/Fall Times PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V NECL Mode Op rating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V Open Input Default State Q Outputs Will Default LOW with Inputs Open or at VEE LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input Compatible Pb-Free Packages are Available (c) Semiconductor Components Industries, LLC, 2009 April, 2009 - Rev. 8 1 8 1 TSSOP-8 DT SUFFIX CASE 948R 8 1 6L11 ALYW G G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Publication Order Number: NB6L11/D NB6L11 Q0 1 Q0 2 R2 8 VCC 7 D 6 D 5 VEE R1 Q1 R1 3 R2 Q1 4 Figure 1. Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION AAA AAAA AAAAAAAAA AAA AAAA AAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA Pin Name I/O Default State Description 1 Q0 ECL Output - 2 Q0 ECL Output - 3 Q1 ECL Output - Non-inverted differential clock/data output 1. Typically terminated with 50 W resistor to VTT = VCC - 2 V. 4 Q1 ECL Output - Inverted differential clock/data output 1. Typically terminated with 50 W resistor to VTT = VCC - 2 V. 5 VEE - - Negative power supply voltage 6 D LVDS, CML, LVPECL, LVNECL, LVCMOS, LVTTL Input HIGH Inverted differential clock/data input. Internal 37.5 kW to VCC and 75 kW to VEE. 7 D LVDS, CML, LVPECL, LVNECL, LVCMOS, LVTTL Input LOW Non-inverted differential clock/data input. Internal 75 kW to VCC and 37.5 kW to VEE. 8 VCC - - Non-inverted differential clock/data output 0. Typically terminated with 50 W Resistor to VTT = VCC - 2 V. Inverted differential clock/data output 0. Typically terminated with 50 W resistor to VTT = VCC - 2 V. Positive power supply voltage Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 37.5 kW Internal Input Pullup Resistor ESD Protection 75 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC-8 TSSOP-8 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 100 V > 1 kV Pb Pkg Pb-Free Pkg Level 1 Level 1 Level 1 Level 3 UL 94 V-0 @ 0.125 in 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 NB6L11 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Power Supply Parameter VEE = 0 V Condition 1 3.6 V VEE Negative Power Supply VCC = 0 V -3.6 V VI Positive Input Voltage Negative Input Voltage VEE = 0 V VCC = 0 V 3.6 -3.6 V V VINPP Differential Input Voltage 2.8 |VCC - VEE| V Iout Output Current 25 50 mA mA TA Operating Temperature Range -40 to +85 C Tstg Storage Temperature Range -65 to +150 C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC-8 SOIC-8 190 130 C/W C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC-8 41 to 44 C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP-8 TSSOP-8 185 140 C/W C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP-8 41 to 44 C/W Tsol Wave Solder v 3 sec @ 248C v 3 sec @ 260C 265 265 C |D - D| Condition 2 VI v VCC VI w VEE VCC - VEE w 2.8 V VCC - VEE t 2.8 V Continuous Surge Standard Pb-Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 NB6L11 Table 4. DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 4) -40C Symbol Characteristic 25C 85C Min Typ Max Min Typ Max Min Typ Max Unit 5 14 20 5 14 20 5 14 20 mA IEE Negative Power Supply Current (Note 5) VOH Output HIGH Voltage (Note 6) 1350 1450 1550 1400 1500 1600 1450 1550 1650 mV VOL Output LOW Voltage (Note 6) 565 725 870 630 765 920 690 825 970 mV DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 14, 16) (Note 7) Vth Input Threshold Reference Voltage Range (Note 2) 1125 VCC -75 1125 VCC -75 1125 VCC -75 mV VIH Single-Ended Input HIGH Voltage Vth +75 VCC Vth +75 VCC Vth +75 VCC mV VIL Single-Ended Input LOW Voltage VEE Vth -75 VEE Vth -75 VEE Vth -75 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15, 17) (Note 8) VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VILD Differential Input LOW Voltage VEE VCC -75 VEE VCC -75 VEE VCC -75 mV VCMR Input Common Mode Range (Differential Cross-Point Voltage) (Note 3) 950 VCC -38 950 VCC -38 950 VCC -38 mV VID Differential Input Voltage (VIHD - VILD) 75 2500 75 2500 75 2500 mV IIH Input HIGH Current D D 150 150 mA IIL Input LOW Current D D 50 10 -150 -150 150 150 -5 -30 50 10 -150 -150 -5 -30 150 150 50 10 -150 -150 -5 -30 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Vth is applied to the complementary input when operating in single-ended mode. 3. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. 4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V. 5. All input and output pins left open. 6. All loading with 50 W to VCC - 2.0 V. 7. Vth, VIH, and VIL parameters must be complied with simultaneously. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. http://onsemi.com 4 NB6L11 Table 5. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11) -40C 25C 85C Characteristic Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current (Note 12) 5 14 20 5 14 20 5 14 20 mA VOH Output HIGH Voltage (Note 13) 2150 2250 2350 2200 2300 2400 2250 2350 2450 mV VOL Output LOW Voltage (Note 13) 1365 1525 1670 1430 1565 1720 1490 1625 1770 mV Symbol DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 14, 16) (Note 14) Vth Input Threshold Reference Voltage Range (Note 9) 1125 VCC -75 1125 VCC -75 1125 VCC -75 mV VIH Single-Ended Input HIGH Voltage Vth +75 VCC Vth +75 VCC Vth +75 VCC mV VIL Single-Ended Input LOW Voltage VEE Vth -75 VEE Vth -75 VEE Vth -75 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15, 17) (Note 15) VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VILD Differential Input LOW Voltage VEE VCC -75 VEE VCC -75 VEE VCC -75 mV VCMR Input Common Mode Range (Differential Cross-Point Voltage) (Note 10) 950 VCC -38 950 VCC -38 950 VCC -38 mV VID Differential Input Voltage (VIHD - VILD) 2500 75 2500 75 2500 mV IIH Input HIGH Current D D 150 150 mA IIL Input LOW Current D D 75 50 10 -150 -150 150 150 -5 -30 50 10 -150 -150 -5 -30 150 150 50 10 -150 -150 -5 -30 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Vth is applied to the complementary input when operating in single-ended mode. 10. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 12. All input and output pins left open. 13. All loading with 50 W to VCC - 2.0 V. 14. Vth, VIH, and VIL parameters must be complied with simultaneously. 15. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. http://onsemi.com 5 NB6L11 Table 6. DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 18) -40C Symbol Characteristic 25C 85C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current (Note 19) 5 14 20 5 14 20 5 14 20 mA VOH Output HIGH Voltage (Note 20) -1150 -1050 -950 -1100 -1000 -900 -1050 -950 -850 mV VOL Output LOW Voltage (Note 20) -1935 -1775 -1630 -1870 -1735 -1580 -1810 -1675 -1530 mV DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 14, 16) (Note 21) Vth Input Threshold Reference Voltage Range (Note 16) VEE +1125 VCC -75 VEE +1125 VCC -75 VEE +1125 VCC -75 mV VIH Single-Ended Input HIGH Voltage Vth +75 VCC Vth +75 VCC Vth +75 VCC mV VIL Single-Ended Input LOW Voltage VEE Vth -75 VEE Vth -75 VEE Vth -75 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15, 17) (Note 22) VIHD Differential Input HIGH Voltage VEE +1200 VCC VEE +1200 VCC VEE +1200 VCC mV VILD Differential Input LOW Voltage VEE VCC -75 VEE VCC -75 VEE VCC -75 mV VCMR Input Common Mode Range (Differential Cross-Point Voltage) (Note 17) VEE +950 VCC -38 VEE +950 VCC -38 VEE +950 VCC -38 mV VID Differential Input Voltage (VIHD - VILD) 75 2500 75 2500 75 2500 mV IIH Input HIGH Current D D 150 150 mA IIL Input LOW Current D D 50 10 -150 -150 150 150 -5 -30 50 10 -150 -150 -5 -30 150 150 50 10 -150 -150 -5 -30 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. Vth is applied to the complementary input when operating in single-ended mode. 17. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC 18. Input and output parameters vary 1:1 with VCC. 19. Input and output pins left open. 20. All loading with 50 W to VCC - 2.0 V. 21. Vth, VIH, and VIL parameters must be complied with simultaneously. 22. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. http://onsemi.com 6 NB6L11 Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 23) -40C Characteristic Symbol VOUTPP Output Voltage Amplitude (See Figures 2 & 3) fin v 3 GHz fin v 6 GHz fDATA Maximum Operating Data Rate tPLH, tPHL Propagation Delay to Output Differential @ 1 GHz tSKEW Duty Cycle Skew Within Device Skew Device-to-Device Skew tJITTER RMS Random Clock Jitter (Note 25) fin v 6 GHz Peak-to-Peak Data Dependent Jitter (Note 26) fin v 6 Gb/s VINPP Input Voltage Swing / Sensitivity (Differential Configuration) (Note 27) tr tf Output Rise/Fall Times @ 1 GHz (20% - 80%) Min Typ 480 270 700 300 25C Max Min Typ 480 270 700 300 85C Max Min Typ 480 270 700 300 Max mV 6 D to Q, Q Gb/s 110 (Note 24) Q, Q Unit 150 190 2 5 15 0.2 110 150 200 10 15 60 2 5 15 1 0.2 120 160 220 10 15 60 2 5 15 10 15 60 1 0.2 1 ps ps ps 2 12 2 12 2 12 75 700 2500 75 700 2500 75 700 2500 mV 30 75 120 30 75 120 30 75 120 ps 0.8 OUTPUT VOLTAGE AMPLITUDE (V) OUTPUT VOLTAGE AMPLITUDE (V) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 23. Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 24. See Figure 13 tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical transitions and conditions @ 1 GHz. 25. Additive RMS jitter with 50% duty cycle clock signal at 6 GHz. 26. Additive Peak-to-Peak data dependent jitter with NRZ PRBS 223-1 data rate at 6 Gb/s. 27. VINPP(max) cannot exceed VCC - VEE (applicable only when VCC - VEE < 2500 mV). Input voltage swing is a single-ended measurement operating in differential mode 0.7 0.6 0.5 -40C 0.4 25C 0.3 0.2 85C 0.1 0.0 1 2 3 4 5 6 INPUT CLOCK FREQUENCY (GHz) 7 0.8 0.7 0.6 0.4 25C 0.3 0.2 85C 0.1 0.0 8 -40C 0.5 Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) and Temperature at VCC - VEE = 3.3 V 1 2 3 4 5 6 INPUT CLOCK FREQUENCY (GHz) 7 Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) and Temperature at VCC - VEE = 2.5 V http://onsemi.com 7 8 NB6L11 Figure 4. Typical Phase Noise Plot at fcarrier = 156.25 MHz Figure 5. Typical Phase Noise Plot at fcarrier = 622.08 MHz Figure 6. Typical Phase Noise Plot at fcarrier = 1.5 GHz Figure 7. Typical Phase Noise Plot at fcarrier = 2 GHz device (integrated between 12 kHz and 20 MHz; as shown in the shaded region of the plot) at each of the frequencies is 75 fs, 12 fs, 6 fs and 4 fs respectively. The input source used for the phase noise measurements is Agilent E8663B. The above phase noise plots captured using Agilent E5052A show additive phase noise of the NB6L11 device at frequencies 156.25 MHz, 622.08 MHz, 1.5 GHz and 2 GHz respectively at an operating voltage of 3.3 V in room temperature. The RMS Phase Jitter contributed by the http://onsemi.com 8 OUTPUT VOLTAGE AMPLITUDE (100 mV/div) OUTPUT VOLTAGE AMPLITUDE (100 mV/div) NB6L11 TIME (64 ps/div) TIME (32 ps/div) Figure 8. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 (Total System Pk-Pk Jitter is 17 ps. Device Pk-Pk Jitter Contribution is 4 ps) Figure 9. Typical Output Waveform at 6.125 Gb/s with PRBS 223-1 (Total System Pk-Pk Jitter is 20 ps. Device Pk-Pk Jitter Contribution is 5 ps) NOTE: VCC - VEE = 3.3 V; VIN = 700 mV; TA = 25C. 210 120 RISE/FALL TIME (ps) 190 85C 170 150 -40C 25C 130 100 90 85C 80 70 60 25C -40C 50 40 110 30 2.375 2.5 3.3 3.465 2.375 2.5 3.3 3.465 POWER SUPPLY VOLTAGE (V) POWER SUPPLY VOLTAGE (V) Figure 10. Propagation Delay versus Power Supply Voltage and Temperature Figure 11. Rise/Fall Time versus Power Supply Voltage and Temperature 20 17 IEE CURRENT (mA) PROPAGATION DELAY (ps) 110 VCC - VEE = -3.465 V 14 11 VCC - VEE = -2.375 V 8 5 -40 25 85 TEMPERATURE (C) Figure 12. IEE Current versus Temperature and Power Supply Voltage http://onsemi.com 9 NB6L11 D VINPP(D) = VIH(D) - VIL(D) VINPP(D) = VIH(D) - VIL(D) D Q VOUTPP(Q) = VOH(Q) - VOL(Q) VOUTPP(Q) = VOH(Q) - VOL(Q) Q tPHL tPLH Figure 13. AC Reference Measurement Vth D D D D Vth Figure 14. Differential Input Driven Single-Ended VCC Vthmax Figure 15. Differential Inputs Driven Differentially VCC VCMmax VIHmax VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILmax VIH Vth VIL Vth VCMR VILDtyp VIHmin Vthmin GND GND Figure 16. Vth Diagram Q VIHDmin VILDmin VCMmax VILmin Figure 17. VCMR Diagram Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC - 2.0 V Figure 18. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) http://onsemi.com 10 NB6L11 ORDERING INFORMATION Package Shipping SOIC-8 98 Units / Rail NB6L11DG SOIC-8 (Pb-Free) 98 Units / Rail NB6L11DR2 SOIC-8 2500 / Tape & Reel NB6L11DR2G SOIC-8 (Pb-Free) 2500 / Tape & Reel NB6L11DT TSSOP-8 100 Units / Rail NB6L11DTG TSSOP-8 (Pb-Free) 100 Units / Rail NB6L11DTR2 TSSOP-8 2500 / Tape & Reel NB6L11DTR2G TSSOP-8 (Pb-Free) 2500 / Tape & Reel Device NB6L11D For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V) AN1503/D - ECLinPSt I/O SPiCE Modeling Kit AN1504/D - Metastability and the ECLinPS Family AN1568/D - Interfacing Between LVDS and ECL AN1672/D - The ECL Translator Guide AND8001/D - Odd Number Counters Design AND8002/D - Marking and Date Codes AND8020/D - Termination of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC Characteristics of ECL Devices http://onsemi.com 11 NB6L11 PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AH -X- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. A 8 5 S B 0.25 (0.010) M Y M 1 4 -Y- K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE -Z- 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NB6L11 PACKAGE DIMENSIONS TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF M T U V S 0.25 (0.010) B -U- 4 M A -V- S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S F DETAIL E C 0.10 (0.004) -T- SEATING PLANE D -W- G DETAIL E DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ ECLinPS is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB6L11/D