© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 8
1Publication Order Number:
NB6L11/D
NB6L11
2.5 V/3.3 V Multilevel Input to
Differential LVPECL/LVNECL
1:2 Clock or Data
Fanout Buffer/Translator
The NB6L11 is an enhanced differential 1:2 clock or data fanout
buffer/translator. The device has the same pinout and is functionally
equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW
jitter and LOW power consumption.
Differential input can be configured to accept single−ended signal
by applying an external reference voltage to unused complementary
input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS,
CML, or LVDS. The outputs are 800 mV ECL signals.
Features
•Input Clock Frequency w 6 GHz
•Input Data Rate w 6 Gb/s
•Low 14 mA Typical Power Supply Current
•150 ps Typical Propagation Delay
•5 ps Typical Within Device Skew
•75 ps Typical Rise/Fall Times
•PECL Mode Operating Range:
VCC = 2.375 V to 3.465 V with VEE = 0 V
•NECL Mode Op rating Range:
VCC = 0 V with VEE = −2.375 V to −3.465 V
•Open Input Default State
•Q Outputs Will Default LOW with Inputs Open or at VEE
•LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input
Compatible
•Pb−Free Packages are Available
6L11
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SO−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R
6L11
ALYW G
G
1
8
1
8
1
8
1
8
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See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
NB6L11
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2
1
2
3
45
6
7
8
D
VEE
VCC
Figure 1. Pinout (Top View) and Logic Diagram
Q0
D
Q1
Q1
Q0
R2
R2
R1
R1
Table 1. PIN DESCRIPTION
Pin Name I/O Default State Description
ÁÁÁ
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Q0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ECL Output −
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Non−inverted differential clock/data output 0. Typically termin-
ated with 50 W Resistor to VTT = VCC − 2 V.
2 Q0 ECL Output −Inverted differential clock/data output 0. Typically terminated with
50 W resistor to VTT = VCC − 2 V.
3 Q1 ECL Output −Non−inverted differential clock/data output 1. Typically termin-
ated with 50 W resistor to VTT = VCC − 2 V.
4 Q1 ECL Output −Inverted differential clock/data output 1. Typically terminated with
50 W resistor to VTT = VCC − 2 V.
5 VEE − − Negative power supply voltage
6 D LVDS, CML, LVPECL, LVNECL,
LVCMOS, LVTTL Input
HIGH Inverted differential clock/data input. Internal 37.5 kW to VCC and
75 kW to VEE.
7 D LVDS, CML, LVPECL, LVNECL,
LVCMOS, LVTTL Input
LOW Non−inverted differential clock/data input. Internal 75 kW to VCC
and 37.5 kW to VEE.
8 VCC − − Positive power supply voltage
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 37.5 kW
Internal Input Pullup Resistor 75 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg
SOIC−8
TSSOP−8
Level 1
Level 1
Level 1
Level 3
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
NB6L11
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3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply VEE = 0 V 3.6 V
VEE Negative Power Supply VCC = 0 V −3.6 V
VIPositive Input Voltage
Negative Input Voltage
VEE = 0 V
VCC = 0 V
VI v VCC
VI w VEE
3.6
−3.6
V
V
VINPP Differential Input Voltage |D − D| VCC − VEE w 2.8 V
VCC − VEE t 2.8 V
2.8
|VCC − VEE|
V
Iout Output Current Continuous
Surge
25
50
mA
mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−841 to 44 °C/W
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−841 to 44 °C/W
Tsol Wave Solder Standard
Pb−Free
v 3 sec @ 248°C
v 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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4
Table 4. DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 4)
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Negative Power Supply Current (Note 5) 5 14 20 5 14 20 5 14 20 mA
VOH Output HIGH Voltage (Note 6) 1350 1450 1550 1400 1500 1600 1450 1550 1650 mV
VOL Output LOW Voltage (Note 6) 565 725 870 630 765 920 690 825 970 mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 14, 16) (Note 7)
Vth Input Threshold Reference Voltage Range
(Note 2)
1125 VCC
−75
1125 VCC
−75
1125 VCC
−75
mV
VIH Single−Ended Input HIGH Voltage Vth
+75
VCC Vth
+75
VCC Vth
+75
VCC mV
VIL Single−Ended Input LOW Voltage VEE Vth
−75
VEE Vth
−75
VEE Vth
−75
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15, 17) (Note 8)
VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV
VILD Differential Input LOW Voltage VEE VCC
−75
VEE VCC
−75
VEE VCC
−75
mV
VCMR Input Common Mode Range
(Differential Cross−Point Voltage) (Note 3)
950 VCC
−38
950 VCC
−38
950 VCC
−38
mV
VID Differential Input Voltage (VIHD − VILD) 75 2500 75 2500 75 2500 mV
IIH Input HIGH Current D
D
50
10
150
150
50
10
150
150
50
10
150
150
mA
IIL Input LOW Current D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
2. Vth is applied to the complementary input when operating in single−ended mode.
3. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V.
5. All input and output pins left open.
6. All loading with 50 W to VCC − 2.0 V.
7. Vth, VIH, and VIL parameters must be complied with simultaneously.
8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
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5
Table 5. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Negative Power Supply Current (Note 12) 5 14 20 5 14 20 5 14 20 mA
VOH Output HIGH Voltage (Note 13) 2150 2250 2350 2200 2300 2400 2250 2350 2450 mV
VOL Output LOW Voltage (Note 13) 1365 1525 1670 1430 1565 1720 1490 1625 1770 mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 14, 16) (Note 14)
Vth Input Threshold Reference Voltage Range
(Note 9)
1125 VCC
−75
1125 VCC
−75
1125 VCC
−75
mV
VIH Single−Ended Input HIGH Voltage Vth
+75
VCC Vth
+75
VCC Vth
+75
VCC mV
VIL Single−Ended Input LOW Voltage VEE Vth
−75
VEE Vth
−75
VEE Vth
−75
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15, 17) (Note 15)
VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV
VILD Differential Input LOW Voltage VEE VCC
−75
VEE VCC
−75
VEE VCC
−75
mV
VCMR Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 10)
950 VCC
−38
950 VCC
−38
950 VCC
−38
mV
VID Differential Input Voltage (VIHD − VILD) 75 2500 75 2500 75 2500 mV
IIH Input HIGH Current D
D
50
10
150
150
50
10
150
150
50
10
150
150
mA
IIL Input LOW Current D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
9. Vth is applied to the complementary input when operating in single−ended mode.
10.VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
12.All input and output pins left open.
13.All loading with 50 W to VCC − 2.0 V.
14.Vth, VIH, and VIL parameters must be complied with simultaneously.
15.VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
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6
Table 6. DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 18)
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Negative Power Supply Current
(Note 19)
5 14 20 5 14 20 5 14 20 mA
VOH Output HIGH Voltage (Note 20) −1150 −1050 −950 −1100 −1000 −900 −1050 −950 −850 mV
VOL Output LOW Voltage (Note 20) −1935 −1775 −1630 −1870 −1735 −1580 −1810 −1675 −1530 mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 14, 16) (Note 21)
Vth Input Threshold Reference Voltage
Range (Note 16)
VEE
+1125
VCC
−75
VEE
+1125
VCC
−75
VEE
+1125
VCC
−75
mV
VIH Single−Ended Input HIGH Voltage Vth
+75
VCC Vth
+75
VCC Vth
+75
VCC mV
VIL Single−Ended Input LOW Voltage VEE Vth
−75
VEE Vth
−75
VEE Vth
−75
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15, 17) (Note 22)
VIHD Differential Input HIGH Voltage VEE
+1200
VCC VEE
+1200
VCC VEE
+1200
VCC mV
VILD Differential Input LOW Voltage VEE VCC
−75
VEE VCC
−75
VEE VCC
−75
mV
VCMR Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 17)
VEE
+950
VCC
−38
VEE
+950
VCC
−38
VEE
+950
VCC
−38
mV
VID Differential Input Voltage (VIHD − VILD) 75 2500 75 2500 75 2500 mV
IIH Input HIGH Current D
D
50
10
150
150
50
10
150
150
50
10
150
150
mA
IIL Input LOW Current D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
16.Vth is applied to the complementary input when operating in single−ended mode.
17.VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC
18.Input and output parameters vary 1:1 with VCC.
19.Input and output pins left open.
20.All loading with 50 W to VCC − 2.0 V.
21.Vth, VIH, and VIL parameters must be complied with simultaneously.
22.VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
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7
Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 23)
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
VOUTPP Output Voltage Amplitude fin v 3 GHz
(See Figures 2 & 3)fin v 6 GHz
480
270
700
300
480
270
700
300
480
270
700
300
mV
fDATA Maximum Operating Data Rate 6 Gb/s
tPLH,
tPHL
Propagation Delay to
Output Differential @ 1 GHz D to Q, Q 110 150 190 110 150 200 120 160 220
ps
tSKEW Duty Cycle Skew
Within Device Skew (Note 24)
Device−to−Device Skew
2
5
15
10
15
60
2
5
15
10
15
60
2
5
15
10
15
60
ps
tJITTER RMS Random Clock Jitter
(Note 25) fin v 6 GHz
Peak−to−Peak Data Dependent Jitter
(Note 26) fin v 6 Gb/s
0.2
2
1
12
0.2
2
1
12
0.2
2
1
12
ps
VINPP Input Voltage Swing / Sensitivity
(Differential Configuration) (Note 27)
75 700 2500 75 700 2500 75 700 2500 mV
tr
tf
Output Rise/Fall Times @ 1 GHz Q, Q
(20% − 80%)
30 75 120 30 75 120 30 75 120 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
23.Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).
24. See Figure 13 tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical
transitions and conditions @ 1 GHz.
25.Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
26.Additive Peak−to−Peak data dependent jitter with NRZ PRBS 223−1 data rate at 6 Gb/s.
27.VINPP(max) cannot exceed VCC − VEE (applicable only when VCC − VEE < 2500 mV). Input voltage swing is a single−ended measurement
operating in differential mode
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
12 456783
OUTPUT VOLTAGE AMPLITUDE (V)
Figure 2. Output Voltage Amplitude (VOUTPP)
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 3.3 V
INPUT CLOCK FREQUENCY (GHz)
85°C
−40°C
25°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
12345678
OUTPUT VOLTAGE AMPLITUDE (V)
−40°C
85°C
25°C
Figure 3. Output Voltage Amplitude (VOUTPP)
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 2.5 V
INPUT CLOCK FREQUENCY (GHz)
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Figure 4. Typical Phase Noise Plot at
fcarrier = 156.25 MHz
Figure 5. Typical Phase Noise Plot at
fcarrier = 622.08 MHz
Figure 6. Typical Phase Noise Plot at
fcarrier = 1.5 GHz
Figure 7. Typical Phase Noise Plot at
fcarrier = 2 GHz
The above phase noise plots captured using Agilent
E5052A show additive phase noise of the NB6L11 device at
frequencies 156.25 MHz, 622.08 MHz, 1.5 GHz and 2 GHz
respectively at an operating voltage of 3.3 V in room
temperature. The RMS Phase Jitter contributed by the
device (integrated between 12 kHz and 20 MHz; as shown
in the shaded region of the plot) at each of the frequencies
is 75 fs, 12 fs, 6 fs and 4 fs respectively. The input source
used for the phase noise measurements is Agilent E8663B.
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9
Figure 8. Typical Output Waveform at
2.488 Gb/s with PRBS 223−1 (Total System
Pk−Pk Jitter is 17 ps. Device Pk−Pk Jitter
Contribution is 4 ps)
TIME (64 ps/div)
OUTPUT VOLTAGE AMPLITUDE
(100 mV/div)
Figure 9. Typical Output Waveform at
6.125 Gb/s with PRBS 223−1 (Total System
Pk−Pk Jitter is 20 ps. Device Pk−Pk Jitter
Contribution is 5 ps)
TIME (32 ps/div)
OUTPUT VOLTAGE AMPLITUDE
(100 mV/div)
NOTE: VCC − VEE = 3.3 V; VIN = 700 mV; TA = 25°C.
110
130
150
170
190
210
2.375 2.5 3.3 3.465
85°C
−40°C25°C
PROPAGATION DELAY (ps)
Figure 10. Propagation Delay versus Power
Supply Voltage and Temperature
POWER SUPPLY VOLTAGE (V)
30
40
50
60
70
80
90
100
110
120
2.375 2.5 3.3 3.465
85°C
−40°C
25°C
Figure 11. Rise/Fall Time versus Power Supply
Voltage and Temperature
POWER SUPPLY VOLTAGE (V)
RISE/FALL TIME (ps)
5
8
11
14
17
20
−40 25 85
VCC − VEE = −3.465 V
VCC − VEE = −2.375 V
Figure 12. IEE Current versus Temperature and
Power Supply Voltage
TEMPERATURE (°C)
IEE CURRENT (mA)
NB6L11
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10
Figure 13. AC Reference Measurement
D
D
Q
Q
tPHL
tPLH
VINPP(D) = VIH(D) − VIL(D)
VINPP(D) = VIH(D) − VIL(D)
VOUTPP(Q) = VOH(Q) − VOL(Q)
VOUTPP(Q) = VOH(Q) − VOL(Q)
D
Vth
D
Vth
Figure 14. Differential Input Driven
Single−Ended
D
D
Figure 15. Differential Inputs Driven
Differentially
VIHmax
VILmax
VIH
Vth
VIL
VIHmin
VILmin
VCC
Vthmax
Vthmin
GND
Vth
VIHDmax
VILDmax
VIHDmin
VILDmin
VIHDtyp
VILDtyp
VID = VIHD − VILD
VCMR
VCC
VCMmax
VCMmax
GND
Figure 16. Vth Diagram Figure 17. VCMR Diagram
Figure 18. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
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11
ORDERING INFORMATION
Device Package Shipping†
NB6L11D SOIC−898 Units / Rail
NB6L11DG SOIC−8
(Pb−Free)
98 Units / Rail
NB6L11DR2 SOIC−82500 / Tape & Reel
NB6L11DR2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
NB6L11DT TSSOP−8100 Units / Rail
NB6L11DTG TSSOP−8
(Pb−Free)
100 Units / Rail
NB6L11DTR2 TSSOP−82500 / Tape & Reel
NB6L11DTR2G TSSOP−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D −ECL Clock Distribution Techniques
AN1406/D −Designing with PECL (ECL at +5.0 V)
AN1503/D −ECLinPSt I/O SPiCE Modeling Kit
AN1504/D −Metastability and the ECLinPS Family
AN1568/D −Interfacing Between LVDS and ECL
AN1672/D −The ECL Translator Guide
AND8001/D −Odd Number Counters Design
AND8002/D −Marking and Date Codes
AND8020/D −Termination of ECL Logic Devices
AND8066/D −Interfacing with ECLinPS
AND8090/D −AC Characteristics of ECL Devices
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12
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
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