_______________General Description
The MAX154/MAX158 and MX7824/MX7828 are high-
speed, multi-channel analog-to-digital converters
(ADCs). The MAX154 and MX7824 have four analog
input channels, while the MAX158 and MX7828 have
eight channels. Conversion time for all devices is 2.5µs.
The MAX154/MAX158 also feature a 2.5V on-chip refer-
ence, forming a complete high-speed data acquisition
system.
All four converters include a built-in track/hold, eliminat-
ing the need for an external track/hold with many input
signals. The analog input range is 0V to +5V, although
the ADC operates from a single +5V supply.
Microprocessor interfaces are simplified by the ADC’s
ability to appear as a memory location or I/O port without
the need for external logic. The data outputs use latched,
three-state buffer circuitry to allow direct connection to a
microprocessor data bus or system input port.
The MX7824 and MX7828 are pin compatible with
Analog Devices’ AD7824 and AD7828. The MAX154
and MAX158, which feature internal references, are also
compatible with these products.
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
High-Speed Servo Control
Audio Instrumentation
____________________________Features
♦One-Chip Data Acquisition System
♦Four or Eight Analog Input Channels
♦2.5µs per Channel Conversion Time
♦Internal 2.5V Reference (MAX154/MAX158 only)
♦Built-In Track/Hold Function
♦1/2LSB Error Specification
♦Single +5V Supply Operation
♦No External Clock
♦New Space-Saving SSOP Package
______________Ordering Information
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
________________________________________________________________
Maxim Integrated Products
1
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
VDD
NC
A0
A1
AIN1
AIN2
AIN3
AIN4
TOP VIEW
DB7
( ) ARE FOR MAX154/MAX158 ONLY.
DB6
DB5
DB4
DB2
DB1
DB0
TP (REF OUT)
16
15
14
13
9
10
11
12
CS
RDY
VREF+
VREF-
GND
INT
RD
DB3
DIP/SO/SSOP
MAX154
MX7824
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
AIN7
AIN8
VDD
A0
AIN3
AIN4
AIN5
AIN6
A1
A2
DB7
DB6
DB0
TP (REF OUT)
AIN1
AIN2
20
19
18
17
9
10
11
12
DB5
DB4
CS
RDY
RD
DB3
DB2
DB1
DIP/SO/SSOP
MAX158
MX7828
16
15
13
14
VREF+
VREF-
GND
INT
__________________________________________________________Pin Configurations
Call toll free 1-800-998-8800 for free samples or literature.
19-0255; Rev 2; 4/94
PART
MX7824LN
MX7824KN
MX7824LCWG 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
24 Narrow
Plastic DIP
24 Narrow
Plastic DIP
24 Wide SO
MX7824KCWG
MX7824LCAG
MX7824KCAG 0°C to +70°C
0°C to +70°C
0°C to +70°C 24 Wide SO
24 SSOP
24 SSOP
Ordering Information continued on last page.
ERROR
(LSB)
±1/2
±1
±1/2
±1
±1/2
±1
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VDD to GND........................................0V, +10V
Voltage at Any Other Pins......................GND - 0.3V, VDD + 0.3V
Output Current (REF OUT)..................................................30mA
Power Dissipation (any package) to +75°C ....................450mW
Derate above +25°C by..............................................6mW/°C
Operating Temperature Ranges
MX7824, MX7828
KN/LN/KCW_/LCW_............................................0°C to +70°C
BQ/CQ .............................................................-40°C to +85°C
TQ/UQ............................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
Input Capacitance (Note 4) CIN 58pF
Input Low Voltage VINL 0.8 V
Input High Current IINH 1µA
Input Low Current IINL -1 µA
Analog Input Current IAIN ±3 µA
Slew Rate, Tracking SR 0.7 0.157 V/µs
Input High Voltage VINH 2.4 V
Any channel, AIN = 0V to 5V
Output Noise eN200 µV/rms
Capacitive Load 0.01 µF
Analog Input Voltage Range AINR VREF-V
REF+ V
Analog Input Capacitance CAIN 45 pF
±1MAX15_B, MX782_K/B/T
PARAMETER SYMBOL MIN TYP MAX UNITS
Channel to Channel Mismatch ±1/4 LSB
No Missing Codes Resolution 8 Bits
Total Unadjusted Error (Note 1) ±1/2 LSB
Reference Resistance 14kΩ
V
REF+ Input Voltage Range VREF-V
DD V
VREF- Input Voltage Range GND VREF+ V
Resolution 8 Bits
Output Voltage REF OUT 2.47 2.50 2.53 V
Load Regulation -6 -10 mV
Power-Supply Sensitivity ±1 ±3 mV
40 70
40 70Temperature Drift (Note 3) 60 100 ppm/°C
CONDITIONS
TA= +25°C
IL= 0mA to 10mA, TA= +25°C
MAX15_A, MX782_L/C/U
VDD ±5%, TA= +25°C
MAX15_C
MAX15_E
MAX15_M
ACCURACY
REFERENCE INPUT
REFERENCE OUTPUT—MAX154/MAX158 Only (Note 2)
ANALOG INPUT
LOGIC INPUTS (–
R
—
D
–, –
C
—
S
–, A0, A1, A2)
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA= TMIN to TMAX, unless otherwise noted.)
TIMING CHARACTERISTICS (Note 5)
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA= TMIN to TMAX, unless otherwise noted.)
Note 1: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 2: Specified with no external load unless otherwise noted.
Note 3: Temperature drift is defined as change in output voltage from +25°C to TMIN or TMAX divided by (25 - TMIN) or (TMAX - 25).
Note 4: Guaranteed by design.
Note 5: All input control signals are specified with tR= tF= 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level.
Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________________________________________________________________________________ 3
(Note 6)
(Note 6)
CL= 50pF, RL= 5kΩ
(Note 7)
CL= 50pF
CONDITIONS
ns
60
tDH
Data Hold Time ns
40 75
tINTH
–
R
—
D
–to –
I
—
N
—
T
–Delay (Mode 1)
ns
0
tCSH
ns
0
tCSS
–
C
—
S
–to –
R
—
D
–Setup Time
–
C
—
S
–to –
R
—
D
–Hold Time
ns
20 50
tACC2
Data Access Time
After –
I
—
N
—
T
–, Mode 0
ns
85
tACC1
Data Access Time After –
R
—
D
–µs
1.6 2.0
tCRD
Conversion Time (Mode 0) ns
30 40
tRDY
–
C
—
S
–to RDY Delay
ns
0
tAS
Multiplexer Address
Setup Time
ns
30
tAH
Multiplexer Address
Hold Time
UNITS
TA= +25°C
SYMBOLPARAMETER
ns
500
tP
Delay Time
Between Conversions 500
70
100
0
0
60
110
2.4
60
0
35
MAX15_ _C/E
MX782_K/L/B/C
600
70
100
0
0
70
120
2.8
60
0
40
MAX15_ _M
MX782_T/U
MIN MAX MIN MAXMIN TYP MAX
ns
60 600
tRD
–
R
—
D
–Pulse Width (Mode 1) 80 500 80 400
DB0–DB7, –
I
—
N
—
T
–; IOUT = -360µA
–
C
—
S
–= –
R
—
D
–= 2.4V
5V ±5% for specified performance
DB0–DB7, RDY; VOUT = 0V to VDD
VDD = ±5%
CONDITIONS
LSB±1/16 ±1/4PSSPower-Supply Sensitivity
V4.0VOH
Output High Voltage
mW25 75Power Dissipation mA15IDD
Supply Current V4.75 5.25VDD
Supply Voltage
µA±3Three-State Output Current pF58C
OUT
Output Capacitance (Note 4)
UNITSMIN TYP MAXSYMBOLPARAMETER
DB0–DB7, –
I
—
N
—
T
–; RDY 0.4 V
0.4
VOL
Output Low Voltage IOUT = 1.6mA
IOUT = 2.6mA
LOGIC OUTPUTS
POWER SUPPLY
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
4 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
2.520
2.480 -50 150
REFERENCE TEMPERATURE
DRIFT (MAX154/MAX158 ONLY)
2.490
2.510
MX7824/28-1
AMBIENT TEMPERATURE (°C)
REF OUT VOLTAGE (V)
2.500
100
050
20
0-100 150
OUTPUT CURRENT
vs. TEMPERATURE
4
12
16
MX7824/28-2
AMBIENT TEMPERATURE (°C)
OUTPUT CURRENT (mA)
8
100
-50 0 50
VDD = 5V
ISOURCE VOUT = 2.4V
ISINK VOUT = 0.4V
2.0
0300 900
ACCURACY vs. DELAY BETWEEN
CONVERSIONS (tp)
0.5
1.0
1.5
MX7824/28-3
tp (ns)
LINEARITY ERROR (LSB)
700 800400 500 600
VDD = 5V
VREF = 5V
2.0
005
ACCURACY vs. VREF
(VREF = VREF+ - VREF-)
0.5
1.0
1.5
MX7824/28-4
VREF (V)
LINEARITY ERROR (LSB)
3412
V
DD = 5V
3k
3k
100pF
DGND
DBN
a. High-Z to V
OH
b. High-Z to V
OL
DBN
+5V
DGND
100pF 3k
3k
10pF
DGND
DBN
a. V
OH
to
High-Z b. V
OL
to
High-Z
DBN
+5V
DGND
10pF
8
2-100 150
POWER-SUPPLY CURRENT vs. TEMPERATURE
(NOT INCLUDING REFERENCE LADDER)
3
4
5
6
7
MX7824/28-5
AMBIENT TEMPERATURE (°C)
IDD – SUPPLY CURRENT (mA)
50 100-50 0
VDD = 5.25V
VDD = 5V
VDD = 4.75V
Figure 1. Load Circuits for Data-Access Time Test Figure 2. Load Circuits for Data-Hold Time Test
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________________________________________________________________________________ 5
Reference Output (2.5V) for MAX154.
Test point for MX7824. Do not connect.
REF OUT
TP
5
Three-State Data Output, bit 0 (LSB)DBO6 Three-State Data Output, bit 1DB17
Analog Input Channel 1AIN14 Analog Input Channel 2AIN23
PIN
Analog Input Channel 3AIN32 Analog Input Channel 4AIN41
FUNCTIONNAME
_____________________________________________________________Pin Descriptions
Three-State Data Output, bit 2DB28 Three-State Data Output, bit 3DB39 Read Input. –
R
—
D
–controls conversions
and data access. See
Digital Interface
section.
–
R
—
D
–
10
Three-State Data Output, bit 7 (MSB)DB720
GroundGND12 Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to VREF+.
VREF-13
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See
Digital Interface
section.
INT11
Chip-Select Input. –
C
—
S
–must be low for
the device to be selected.
–
C
—
S
–
16
Three-State Data Output, bit 4DB417 Three-State Data Output, bit 5DB518 Three-State Data Output, bit 6DB619
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See
Digital Interface
section.
INT13
GroundGND14
Analog Input Channel 2AIN25 Analog Input Channel 1AIN16 Reference Output (2.5V) for MAX158.
Test point for MX7828. Do not connect.
REF OUT
TP
7
Analog Input Channel 3AIN34 Analog Input Channel 4AIN43
PIN
Analog Input Channel 5AIN52 Analog Input Channel 6AIN61
FUNCTIONNAME
Three-State Data Output, bit 0 (LSB)DB08 Three-State Data Output, bit 1DB19 Three-State Data Output, bit 2DB210 Three-State Data Output, bit 3DB311
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to VREF+.
VREF-15
Read Input. –
R
—
D
–controls conversions
and data access. See
Digital Interface
section.
–
R
—
D
–
12
Ready Output. Open-drain output with
no active pull-up device. Goes low
when –
C
—
S
–goes low and high imped-
ance at the end of a conversion.
RDY17
Power-Supply Voltage, +5VVDD
26
Channel Address 2 InputA223 Channel Address 1 InputA124 Channel Address 0 InputA025
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: VREF- to VDD.
VREF+14
Ready Output. Open-drain output with
no active pull-up device. Goes low
when –
C
—
S
–goes low and high imped-
ance at the end of a conversion.
RDY15
Power-Supply Voltage, +5VVDD
24
Channel Address 1 InputA121 Channel Address 0 InputA022 No ConnectNC23
Three-State Data Output, bit 7 (MSB)DB722
Chip-Select Input. –
C
—
S
–must be low for
the device to be selected.
–
C
—
S
–
18
Three-State Data Output, bit 4DB419 Three-State Data Output, bit 5DB520 Three-State Data Output, bit 6DB621
Analog Input Channel 8AIN827 Analog Input Channel 7AIN728
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: VREF- to VDD.
VREF+16
MAX154
MX7824 MAX158
MX7828
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
6 _______________________________________________________________________________________
_______________Detailed Description
Converter Operation
The MAX154/MAX158 and MX7824/MX7828 use what is
commonly called a “half-flash” conversion technique
(Figure 3). Two 4-bit flash ADC sections are used to
achieve an 8-bit result. Using 15 comparators, the
upper 4-bit MS (most significant) flash ADC compares
the unknown input voltage to the reference ladder and
provides the upper four data bits.
An internal DAC uses the MS bits to generate an analog
signal from the first flash conversion. A residue voltage
representing the difference between the unknown input
and the DAC voltage is then compared to the reference
ladder by 15 LS (least significant) flash comparators to
obtain the lower four output bits.
Operating Sequence
The operating sequence is shown in Figure 4. A con-
version is initiated by a falling edge of RD and CS. The
comparator inputs track the analog input voltage for
approximately 1µs. After this first cycle, the MS flash
result is latched into the output buffers and the LS con-
version begins. INT goes low approximately 600ns
later, indicating the end of the conversion, and that the
lower four bits are latched into the output buffers. The
data can then be accessed using the CS and RD
inputs.
___________________Digital Interface
The MAX154/MAX158 and MX7824/MX7828 use only
Chip Select (CS) and Read (RD) as control inputs. A
READ operation, taking CS and RD low, latches the mul-
tiplexer address inputs and starts a conversion (Table 1).
There are two interface modes, which are determined
by the length of the RD input. Mode 0, implemented by
keeping RD low until the conversion ends, is designed
for microprocessors that can be forced into a WAIT
state. In this mode, a conversion is started with a READ
operation (taking CS and RD low), and data is read
when the conversion ends. Mode 1, on the other hand,
4-BIT
DAC
THREE-
STATE
DRIVERS
ADDRESS
LATCH
DECODE
4-BIT
FLASH
ADC
(4LSB)
4-BIT
FLASH
ADC
(4MSB)
2.5V
REF TIMING AND CONTROL
CIRCUITRY
MUX*
VREF+
VREF+
16
A0
*MAX154/MX7824 – 4-Channel Mux
MAX158/MX7828 – 8-Channel Mux
** REF OUT on MAX154/MAX158 only
A1 A2 RDY CS RD
AIN1
AIN4
AIN8
REF OUT**
VREF-
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
INT
MAX154/MX7824
A1 A0 MAX158/MX7828
A2 A1 A0 SELECTED
CHANNEL
00
01
10
11
000
001
010
011
AIN1
AIN2
AIN3
AIN4
Figure 3. Functional Diagram
Table 1. Truth Table for Input Channel
Selection
100
101
110
111
AIN5
AIN6
AIN7
AIN8
does not require microprocessor WAIT states. A READ
operation simultaneously initiates a conversion and
reads the previous conversion result.
Interface Mode 0
Figure 5 shows the timing diagram for Mode 0 opera-
tion. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extend-
ed to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
There are two status outputs: Interrupt (INT) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
device), is connected to the processor’s READY/WAIT
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
conversion result appears on the data outputs. If the RDY
output is not required, its external pull-up resistor can be
omitted. INT goes low when the conversion is complete
and returns high on the rising edge of CSor RD.
Interface Mode 1
Mode 1 is designed for applications where the micro-
processor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a conversion (Figure 6). Data from the previous conver-
sion is immediately read from the outputs (DB0–DB7).
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ oper-
ation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________________________________________________________________________________ 7
500ns
VIN IS TRACKED
BY INTERNAL
COMPARATORS
VIN IS SAMPLED
AND THE FOUR MSBs
ARE LATCHED
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
600ns
RD INT GOING LOW
INDICATES THAT
CONVERSION IS
COMPLETE AND
THAT DATA CAN
BE READ
1000ns
Figure 4. Operating Sequence
DATA DATA
VALID
ADDR
VALID
ADDR
VALID
INT
RDY
RD
ANALOG
CHANNEL
ADDRESS
CS
tAS
tAH
tRDY
tCRD
HIGH IMPEDANCE
tCSS tCSS
tINTH
tDH
tACC2
tAS
tP
tCSH
Figure 5. Mode 0 Timing Diagram
MX7824/MX7828
_____________Analog Considerations
Reference and Input
The VREF+ and VREF- inputs of the converter define the
zero and the full-scale of the ADC. In other words, the
voltage at VREF- is equal to the input voltage that pro-
duces an output code of all zeros, and the voltage at
VREF+ is equal to input voltage that produces an output
code of all ones (Figure 7).
Figure 8 shows some possible reference configura-
tions. For the MAX154/MAX158, a 0.01µF bypass
capacitor to GND should be used to reduce the high-
frequency output impedance of the internal reference.
Larger capacitors should not be used, as this degrades
the stability of the reference buffer. The 2.5V reference
output is with respect to the GND pin.
Bypassing
A 47µF electrolytic and 0.1µF ceramic capacitor should
be used to bypass the VDD pin to GND. These capaci-
tors must have minimum lead length, since excess lead
length may contribute to conversion errors and instability.
If the reference inputs are driven by long lines, they
should be bypassed to GND with 0.1µF capacitors at
the reference input pins.
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
8 _______________________________________________________________________________________
DATA NEW
DATA
ADDR
VALID
INT
RDY
RD
ANALOG
CHANNEL
ADDRESS
CS
tAS
tAH
tRDY
tACCI
tCRD
tRD
tCSS tRD
tRDY
tINTH
tDH
tAH
tINTH
tAS
tP
tCSS
tCSH
ADDR
VALID
OLD
DATA
tDH
tCSH
tACCI
Figure 6. Mode 1 Timing Diagram
11111111
11111110
11111101
00000011
00000010
00000001
00000000 1
VREF-23 FS
VREF+
FS–1LSB
OUTPUT
CODE FULL-SCALE
TRANSITION
1LSB = F8 = VREF+ - VREF-
256 256
AIN INPUT VOLTAGE
(IN TERMS OF LSBs)
Figure 7. Transfer Function
Input Current
The converters’ analog inputs behave somewhat differ-
ently from conventional ADCs. The sampled data com-
parators take varying amounts of current from the input,
depending on the cycle they are in. The equivalent cir-
cuit of the converter is shown in Figure 9a. When the
conversion starts, AIN(n) is connected to the MS and
LS comparators. Thus, AIN(n) is connected to thirty-one
1pF capacitors.
To acquire the input signal in approximately 1µs, the
input capacitors must charge to the input voltage
through the on-resistance of the multiplexer (about
600Ω) and the comparator’s analog switches (2kΩto
5kΩper comparator). In addition, about 12pF of stray
capacitance must be charged. The input can be mod-
eled as an equivalent RC network shown in Figure 9b.
As RS(source impedance) increases, the capacitors
take longer to charge.
Since the length of the input acquisition time is internal-
ly set, large source resistances (greater than 100Ω) will
cause settling errors. The output impedance of an op-
amp is its open-loop output impedance divided by the
loop gain at the frequency of interest. It is important
that the amplifier driving the converter input have suffi-
cient loop gain at approximately 1MHz to maintain low
output impedance.
Input Filtering
The transients in the analog input caused by the sam-
pled data comparators do not degrade the converter’s
performance, since the ADC does not “look” at the
input when these transients occur. The comparator’s
outputs track the input during the first 1µs of the con-
version, and are then latched. Therefore, at least 1µs
will be provided to charge the ADC’s input capaci-
tance. It is not necessary to filter these transients with
an external capacitor on the AIN terminals.
Sinusoidal Inputs
The MAX154/MAX158 and MX7824/MX7828 can mea-
sure input signals with slew rates as high as 157mV/µs
to the rated specifications. This means that the analog
input frequency can be as high as 10kHz without the
aid of an external track/hold. The maximum sampling
rate is limited by the conversion time (typical tCRD =
2µs) plus the time required between conversions (tp=
500ns). It is calculated as:
fMAX =1 =1 =400kHz
tCRD + tp(2.0 + 0.5) µs
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________________________________________________________________________________ 9
MAX154
MAX158
VIN
GND
VDD
REF OUT
VREF+
AINx(+)
AINx(-)
+5V
0.1µF47µF
0.01µFVREF-
MX7824
MX7828
MX584
VIN
GND
VDD
VREF+
AINx(+)
AINx(-)
+5V
2.5V
0.1µF47µF
VREF-
MAX154
MAX158
MX7824
MX7828
VIN
GND
VDD
VREF+
AINx(+)
AINx(-)
+5V
0.1µF47µF
VREF-
MAX154
MAX158
MX7824
MX7828
VIN
GND
* Current path must
still exist from
VIN(-) to Ground
VDD
VREF+
AINx(+)
AINx(-)
+5V
2.5V
0.1µF47µF
V
REF-
*
Figure 8a. Internal Reference (MAX154/MAX158 only)
Figure 8b. External Reference +2.5V Full-Scale
Figure 8c. Power Supply as Reference
Figure 8d. Inputs Not Referenced to GND
MX7824/MX7828
fMAX permits a maximum sampling rate of 50kHz per
channel when using the MAX158/MX7828 and 100kHz
per channel when using the MAX154/MX7824. These
rates are well above the Nyquist requirement of 20kHz
sampling rate for a 10kHz input bandwidth.
Bipolar Input Operation
The circuit in Figure 10a can be used for bipolar input
operation. The input voltage is scaled by an amplifier so
that only positive voltages appear at the ADC’s inputs.
An external reference should be used for the MX7824/
MX7828, but is not needed with the MAX154/MAX158.
The analog input range is ±4V and the output code is
complementary offset binary. The ideal input/output
characteristic is shown in Figure 10b.
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
10 ______________________________________________________________________________________
1pFCS
12pF
CS
2pF
1pF
•
•
•
15 LSB COMPARATORS
TO LS
LADDER
RON
1pF
1pF
•
•
•
16 MSB COMPARATORS
TO MS
LADDER
RON
RMUX
RS
VIN
AIN1
11111111
11111110
10000010
10000001
01111111
01111110
10000000
00000001
00000000
00000010
0V
AIN INPUT VOLTAGE (LSBs)
FS = 8V
1LSB = FS / 256
11111101
+FS
2
-FS + 1LSB
2
RS
VIN
AIN1
CS1
2pF CS2
2pF 32pF
B MUX
600ΩRON
350Ω
MAX154
MAX158
AIN1
ONLY CHANNEL 1 SHOWN
VREF+
REF OUT
VDD
VREF-
GND
11.5Ω3.57k
10.0k
0.01µF
0.01µF
0.1µF47µF
16.2k
VIN
+5V
CS
RDY
INT
DB0–DB7
RD
Figure 9a. Equivalent Input Circuit
Figure 10b. Transfer Function for ±4V Input Operation
Figure 9b. RC Network Model
Figure 10a. Bipolar ±4V Input Operation
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
______________________________________________________________________________________ 11
MAX154
MAX158
MX7824
MX7828
RD
RDY
*A2 ON MAX158/MX7828 ONLY.
CS
A1 A2*A0
5V
DATA BUS
A15
A0
ZBO
MREQ
WAIT
RD
DB0–DB7
D0–D7
ADDRESS
DECODE
EN
5k
ADDRESS BUS
MAX158
MX7828
AIN2
18
26
+5V
12
23
24
25
15 14
AIN8
VREF+
AIN1 CS
6
5
28
+5V
27
16
RD
A1
DB0–DB7
SPEECH
INPUT
A0
DATA
VDD
AIN7
BANDPASS
FILTER 1
BANDPASS
FILTER 2
AMP
VREF- GND
BANDPASS
FILTER 7
BANDPASS
FILTER 8
A2
MAX154
MX7824
AIN2 11
24 16 10
+5V
21
22
VREF-
VREF+
AIN1
INT
4
3
2
13
A0
DB0–DB7
VDD VDD
SAMPLE
PULSE
VSS
CS RD
AIN3
1AIN4
14
GND
12
A1
A0
A1
15
16
17
MX7226
4
18
3
+15V
6
5
A1
VREF
AGND
DB0–DB7
2
VOUT A
1
20
19
VOUT B
VOUT C
VOUT D
A0
DGND
WR
Figure 12. Speech Analysis Using Real-Time Filtering
Figure 13. 4-Channel Fast Sample and Infinite Hold
Figure 11. Simple Mode 0 Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
___________________Chip Topography_Ordering Information (continued)
±1/2
24 SSOP-40°C to +85°CMX7824LEAG ±124 SSOP-40°C to +85°CMX7824KEAG
±128 CERDIP-55°C to +125°CMX7828TQ ±1/2
28 CERDIP-55°C to +125°CMX7828UQ ±128 CERDIP-40°C to +85°CMX7828BQ ±1/2
28 CERDIP-40°C to +85°CMX7828CQ ±128 SSOP-40°C to +85°CMX7828KEAI ±1/2
28 SSOP-40°C to +85°CMX7828LEAI ±128 PLCC0°C to +70°CMX7828KP ±1/2
28 PLCC0°C to +70°CMX7828LP ±128 SSOP0°C to +70°CMX7828KCAI ±1/2
28 SSOP0°C to +70°CMX7828LCAI ±1
±1/2
±1
±1/2
±1
±1/2
±1
28 Wide SO
28 Wide SO0°C to +70°C
0°C to +70°C
±1/2
ERROR
(LSB)
MX7828KCWI
MX7828LCWI 28 Plastic DIP
28 Plastic DIP
24 CERDIP-55°C to +125°C
0°C to +70°C
0°C to +70°CMX7828KN
MX7828LN
MX7824TQ 24 CERDIP
24 CERDIP
24 CERDIP
PIN-PACKAGETEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-55°C to +125°CMX7824UQ
MX7824BQ
MX7824CQ
PART
A1
DB3
AIN3
(N.C.)
AIN4
(N.C.)
AIN5
(AIN1)
AIN6
(AIN2)
AIN7
(AIN3)
AIN8
(AIN4)
A0 INT
GND
0.127"
(3.228mm)
0.124"
(3.150mm)
VREF-
VREF+ ADY
A2 (N.C.)
DB7
DB6
DB5
DB4
CS
VDD A0
DB2
DB1
AIN2 (N.C.)
AIN1 (N.C.)
TP (REF OUT)
DB0
( ) ARE FOR MAX154/MX7824
