2010 Microchip Technology Inc. DS22248A-page 1
MCP4901/4911/4921
Features
• MCP4901: 8-Bit Voltage Output DAC
• MCP4911: 10-Bit Voltage Output DAC
• MCP4921: 12-Bit Voltage Output DAC
• Rail-to-Rail Output
• SPI Interface with 20 MHz Cloc k Supp ort
• Simultaneous Latching of the DAC Output
with LDAC Pin
• Fast Settling Ti me of 4.5 µs
• Selectable Unity or 2x Gain Out put
• External Voltage Reference Input
• Extern al Mu lti pli er Mod e
• 2.7V to 5.5V Single-Supply Operation
• Extended Temperature Range: -40°C to +125°C
Applications
• Set Point or Offset Trimming
• Precision Selectable Voltage Reference
• Motor Control Feedback Loop
• Digitally-Controlled Multiplier/Divider
• Calibration of Optical Communication Devices
Related Products
Description
The MCP4901/4911/4921 devices are single channel
8-bit, 10-bit and 12-bit buffered voltage output
Digita l-to-Ana log C onverters (DACs), respectiv ely. The
device s operate from a si ngl e 2.7V to 5.5 V supp ly with
an SPI compatible Serial Peripheral In terface. The user
can configure the full-scale range of the device to be
VREF or 2 *V REF by setting the gain selection option bit
(gain of 1 of 2).
The user can shut down the device by setting the Con-
figuration Register bit. In Shutdown mode, most of the
internal circuits are turned off for power savings, and
the output amplifier is configured to present a known
high resis t an ce out put load (500 ktypical.
The devices include double-buffered registers,
allow ing synchron ous update s of the DA C output usin g
the LDAC pin. These devices also incorporate a
Power-on Reset (POR) circuit to ensure reliable power-
up.
The devices utilize a resistive string architecture, with
its in herent advan tages of low Di fferen tial N on-Li near-
ity (DNL) error and fa st settling ti me. These de vices are
specified over the extended temperature range
(+125°C).
The devices provide high accuracy and low noise
performance for consumer and industrial applications
where calibration or compensation of signals (such as
temperature, pressure and humidity) are required.
The MCP4901/4911/4921 devices are available in the
PDIP, SOIC, MSOP and DFN packages.
Package Types
P/N DAC
Resolution No. of
Channels
Voltage
Reference
(VREF)
MCP4801 8 1
Internal
(2.048V)
MCP4811 10 1
MCP4821 12 1
MCP4802 8 2
MCP4812 10 2
MCP4822 12 2
MCP4901 8 1
External
MCP4911 10 1
MCP4921 12 1
MCP4902 8 2
MCP4912 10 2
MCP4922 12 2
Note: The products listed here have similar AC/DC
performances.
DFN-8 (2x3)*
1
2
3
4
8
7
6
5
CS
SCK
SDI
VDD VSS
VOUT
LDAC
MCP4901: 8-bit single DAC
MCP4911: 10-bit single D AC
MCP4921: 12-bit single DAC
MCP49x1
8-Pin PDIP, SOIC, MSOP
1
2
3
4
8
7
6
5
CS
SCK
SDI
VDD
VSS
VOUT
LDAC
VREF VREF
EP
9
* Includes Exposed Thermal Pad (EP); see Table 3-1.
8/10/12-Bit Voltage Output Digital-to-Analog Converter
with SP I In terface
MCP4901/4911/4921
DS22248A-page 2 2010 Microchip Technology Inc.
Block Diagram
Op Amp
VDD
VSS
CS SDI SCK
Interface Logic
Input
Register
DAC
Register
String
DAC
Power-on
Reset
VOUT
LDAC
Output Gain
Logic
Output
Logic
VREF
Buffer
2010 Microchip Technology Inc. DS22248A-page 3
MCP4901/4911/4921
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD............................................................................................................. 6.5V
All inputs and outputs w.r.t ................VSS –0.3V to VDD+0.3V
Current at Input Pins ....................................................±2 mA
Current at Supply Pins ...............................................±50 mA
Curren t at Output Pi n s ...................... .......... ........... ....±25 mA
Storage temperature ................. .. .. ....... .. .. .... .-65°C to +150°C
Ambient temp. with power applied................-55°C to +125°C
ESD protection on all pins 4 kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ)..........................+150°C
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to m aximum rating conditions for extended pe riods
may affect device reliability.
ELECTR ICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Power Requireme nts
Operati ng Volt age VDD 2.7 — 5.5
Supply Current IDD — 175 350 µA VDD = 5V
VDD = 3V
VREF input is unbuffered, all digital
inputs are grounded, all analog
outputs (VOUT) are unloaded.
Code = 0x00 0h
— 125 250 µA
Software Shutdown Current ISHDN_SW — 3.3 6 µA Power-on Reset circuit remains on
Power-On-Reset Threshold VPOR —2.0 — V
DC Accuracy
MCP4901
Resolution n 8 — — Bits
INL Error INL -1 ±0.125 1 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4911
Resolution n 10 — — Bits
INL Error INL -3.5 ±0.5 3.5 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4921
Resolution n 12 — — Bits
INL Error INL -12 ±2 12 LSb
DNL DNL -0.75 ±0.2 +0.75 LSb Note 1
Note 1: Guaranteed monotonic by des ig n over all codes.
2: This parameter is ensured by design, and not 100% tested.
MCP4901/4911/4921
DS22248A-page 4 2010 Microchip Technology Inc.
Offset Error VOS — ±0.02 1 % of
FSR Code = 0x00 0h
Offset Error Temperature
Coefficient VOS/°C — 0.16 — ppm/°C -45°C to 25°C
— -0.44 — ppm/°C +25°C to 85°C
Gain Error gE— -0.10 1 % of
FSR Code = 0xFFFh, not including
offset error
Gain Error Temperature
Coefficient G/°C — -3 — ppm/°C
Input Amplifier (VREF Input)
Input Range – Buffered
Mode VREF 0.040 — VDD –
0.040 VNote 2
Code = 2048
VREF = 0.2 Vp-p, f = 100 Hz and
1kHz
Input Range – Unbuffered
Mode VREF 0—V
DD V
Input Impedance RVREF —165 — kUnbuffered Mode
Input Capacitance –
Unbuffered Mode CVREF —7 — pF
Multiplier Mode
-3 dB Bandwidth fVREF —450 — kHzV
REF = 2.5V ±0.2Vp -p,
Unbuffe red, G = 1
fVREF —400 — kHzV
REF = 2.5V ±0.2 Vp-p,
Unbuffe red, G = 2
Multiplier Mode –
Total Harmonic Distortion THDVREF —-73 — dBV
REF = 2.5V ±0.2Vp -p,
Frequency = 1 kHz
Output Amplifier
Output Swing VOUT — 0.01 to
VDD –
0.04
— V Accuracy is better than 1 LSb for
VOUT = 10 mV to (VDD – 40 mV)
Phase Margin m — 66 — Degrees
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC —15 24 mA
Settling Time tsettling — 4.5 — µs Within 1/2 LSB of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — 10 — nV-s
Major Code Transition
Glitch — 45 — nV-s 1 LSB change around major carry
(0111...1111 to 1000...0000)
Digital Feedthrough — 10 — nV-s
Analog Crosstalk — 10 — nV-s
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by des ig n over all codes.
2: This parameter is ensured by design, and not 100% tested.
2010 Microchip Technology Inc. DS22248A-page 5
MCP4901/4911/4921
ELECTR ICAL CHARACTERISTIC WITH EX TENDED TEMPERATURE
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Power Requireme nts
Input Voltage VDD 2.7 — 5.5
Input Current IDD —200— µAV
REF input is unbuffered, all digi-
tal input s are grounde d, all analog
outputs (VOUT) are unloaded.
Code = 0x000h
Software Shutdown Current ISHDN_SW —5— µA
Power-on Reset Threshold VPOR —1.85— V
DC Accuracy
MCP4901
Resolution n 8 — — Bits
INL Error INL ±0.25 LSb
DNL DNL ±0.2 LSb Note 1
MCP4911
Resolution n 10 — — Bits
INL Error INL ±1 LSb
DNL DNL ±0.2 LSb Note 1
MCP4921
Resolution n12 — — Bits
INL Error INL ±4 LSb
DNL DNL ±0.25 LSb Note 1
Offset Error VOS — ±0.02 — % of FSR Code = 0x000h
Offset Error Temperature
Coefficient VOS/°C — -5 — ppm/°C +25°C to +125°C
Gain Error gE— -0.10 — % of FSR Code = 0xFFFh, not including
offset error
Gain Error Temperature
Coefficient G/°C — -3 — ppm/°C
Input Amplifier (VREF Input)
Input Range – Buffered
Mode VREF — 0.040 to
VDD-
0.040
—VNote 1
Code = 2048,
VREF = 0.2 Vp-p, f = 100 Hz and
1kHz
Input Range – Unbuffered
Mode VREF 0—V
DD V
Input Impedance RVREF —174— kUnbuffe red Mo de
Input Capacitance –
Unbuffered Mode CVREF —7— pF
Multiplying Mo de
-3 dB Bandwidth fVREF —450— kHzV
REF = 2.5V ±0.1 Vp-p,
Unbuffered, G = 1x
fVREF —400— kHzV
REF = 2.5V ±0.1 Vp-p,
Unbuffered, G = 2x
Note 1: Guaranteed monotonic by des ig n over all codes.
2: This parameter is ensured by design, and not 100% tested.
MCP4901/4911/4921
DS22248A-page 6 2010 Microchip Technology Inc.
Multiplying Mode - Total
Harmonic Distortion THDVREF ——— dBV
REF = 2.5V ±0.1Vp-p,
Frequency = 1 kHz
Output Amplifier
Output Swing VOUT — 0.01 to
VDD –
0.04
— V Accuracy is better than 1 LSb for
VOUT = 10 mV to (VDD – 40 mV)
Phase Margin m — 66 — Degrees
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC —17— mA
Settling Time tsettling — 4.5 — µs Within 1/2 LSB of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
Major Code Transition
Glitch — 45 — nV -s 1 LSB chang e around major c arry
(0111...1111 to 1000...0000)
Digital Feedthrough — 10 — nV-s
ELECTR IC AL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by des ig n over all codes.
2: This parameter is ensured by design, and not 100% tested.
2010 Microchip Technology Inc. DS22248A-page 7
MCP4901/4911/4921
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
FIGURE 1-1: SPI Input Timing Data.
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125 °C .
Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Schmitt Trigger High Level
Input Voltage (All digital input
pins)
VIH 0.7 VDD ——V
Schmitt T rigger Low Level Input
Voltage (All digital inpu t pins) VIL ——0.2V
DD V
Hysteresis of Schmitt Trigger
Inputs VHYS —0.05V
DD —
Input Leakage Current ILEAKAGE -1 — 1 ALDAC = CS = SDI =
SCK = VREF = VDD or VSS
Digital Pin Capacitance
(All inputs/outputs) CIN,
COUT
—10—pFV
DD = 5.0V, TA = +25°C,
fCLK = 1 MHz (Note 1)
Clock Frequency FCLK ——20MHzT
A = +25°C (Note 1)
Clock High Time tHI 15 — — ns Note 1
Clock Low Time tLO 15 — — ns Note 1
CS Fall to First Rising CLK
Edge tCSSR 40 — — ns Applies only when CS falls with
CLK high (Note 1)
Data Input Setup Time tSU 15 — — ns Note 1
Data Input Hold Time tHD 10 — — ns Note 1
SCK Rise to CS Rise Hold
Time tCHS 15 — — ns Note 1
CS High Time tCSH 15 — — ns Note 1
LDAC Pulse Wid th tLD 100 — — ns Note 1
LDAC Setup T ime tLS 40 — — ns Note 1
SCK Idle Ti me before CS Fal l tIDLE 40 — — ns Note 1
Note 1: This parameter is ensured by design and not 100% tested.
CS
SCK
SI
LDAC
tCSSR
tHD
tSU
tLO
tCSH
tCHS
LSB in
MSB in
tIDLE
Mode 1,1
Mode 0,0
tHI
tLD
tLS
MCP4901/4911/4921
DS22248A-page 8 2010 Microchip Technology Inc.
TE MPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Tem perature R ange TA-40 — +125 °C
Operati ng Temper atu re Ra nge TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Therm al Resi stanc e, 8L-DFN (2 x 3) JA —68—°C/W
Thermal Resistance, 8L-PDIP JA —90—°C/W
Thermal Resistance, 8L-SOIC JA —150—°C/W
Thermal Resistance, 8L-MSOP JA —211—°C/W
Note 1: The MCP4901/4911/4921 devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the maximum junction temperature of
150°C.
2010 Microchip Technology Inc. DS22248A-page 9
MCP4901/4911/4921
2.0 TYPICAL PERFORMANCE CURVES
Note: Unles s o the rwise in dic ate d, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-1: DNL vs. Code (MCP4921).
FIGURE 2-2: DNL vs. Code and
Temperature (MCP4921).
FIGURE 2-3: DNL vs. Code and VREF,
Gain=1 (MCP4921).
FIGURE 2-4: Absolute DNL vs.
Temperature (MCP4921).
FIGURE 2-5: Absolute DNL vs. Voltage
Reference (MCP4921).
FIGURE 2-6: INL vs. Code and
Temperature (MCP4921).
Note: The g r ap hs and t ables prov id ed following this n ote are a sta tis tic al s umm ary bas ed on a lim ite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 1024 2048 3072 4096
Code (Decimal)
DNL (LSB)
-0.2
-0.1
0
0.1
0.2
0 1024 2048 3072 4096
Code (Decimal)
DNL (LSB)
125C 85C 25C
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0 1024 2048 3072 4096
Code (Decimal)
DNL (LSB)
1 2 3 4 5.5
0.075
0.0752
0.0754
0.0756
0.0758
0.076
0.0762
0.0764
0.0766
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Absolute DNL (LSB)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
12345
Voltage Reference (V)
Absolute DNL (LSB)
-5
-4
-3
-2
-1
0
1
2
3
4
5
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
125C 85 25
Ambient Temperature
MCP4901/4911/4921
DS22248A-page 10 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-7: Absolute INL vs.
Temperature (MCP4921).
FIGURE 2-8: Absolute INL vs. VREF
(MCP4921).
FIGURE 2-9: INL vs. Code and VREF
(MCP4921).
FIGURE 2-10: INL vs. Code (MCP4921).
FIGURE 2-11: DNL vs. Code and
Temperature (MCP4911).
FIGURE 2-12: INL vs. Code and
Temperature (MCP4911).
0
0.5
1
1.5
2
2.5
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Absolute INL (LSB)
0
0.5
1
1.5
2
2.5
3
12345
Voltage Reference (V)
Absolute INL (LSB)
-4
-3
-2
-1
0
1
2
3
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
12345.5
VREF
Note: Single device graph (Figure 2-10) for
illustration of 64 code effect.
-6
-4
-2
0
2
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
-0.2
-0.1
0
0.1
0.2
0 128 256 384 512 640 768 896 1024
Code
DNL (L SB)
Temp = - 40oC to +125oC
-3.5
-2.5
-1.5
-0.5
0.5
1.5
0 128 256 384 512 640 768 896 1024
Code
INL (LS B )
125oC
85oC
25
oC
- 40oC
2010 Microchip Technology Inc. DS22248A-page 11
MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-13: DNL vs. Code and
Temperature (MCP4901).
FIGURE 2-14: INL vs. Code and
Temperature (MCP4901).
FIGURE 2-15: IDD vs. Temperature and
VDD.
FIGURE 2-16: IDD Histogram (VDD =
2.7V).
FIGURE 2-17: IDD Histogram (VDD =
5.0V).
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0 32 64 96 128 160 192 224 256
Code
DNL (LSB)
Temp = -40oC to +125oC
-0.5
-0.25
0
0.25
0.5
0 326496128160192224256
Code
INL (LSB)
125
oC
-40oC to +85oC
110
130
150
170
190
210
-40-200 20406080100120
Ambient Temperature (°C)
IDD (µA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0
2
4
6
8
10
12
14
16
18
143
145
147
149
151
153
155
157
159
161
163
165
167
IDD (μA)
Occurrence
0
1
2
3
4
5
6
7
8
9
151 156 161 166 171 176 181 186 191 196 201
IDD (μA)
Occurrence
MCP4901/4911/4921
DS22248A-page 12 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-18: Shutdown Current vs.
Temperature and VDD.
FIGURE 2-19: Offset Error vs.Temperature
and VDD.
FIGURE 2-20: Gain Error vs. Temperature
and VDD.
FIGURE 2-21: VIN High Threshold vs.
Temperature and VDD.
FIGURE 2-22: VIN Low Threshold vs.
Temperature and VDD.
0
1
2
3
4
5
6
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
ISHDN_SW (μA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Offset Error (%)
VDD
5.5V
4.0
V
5.0V
3.0V
2.7V
-0.16
-0.14
-0.12
-0.1
-0.08
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Gain Error (%)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
1
1.5
2
2.5
3
3.5
4
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VIN Hi Threshold (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VIN Low Threshold (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
2010 Microchip Technology Inc. DS22248A-page 13
MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-23: Input Hysteresis vs.
Temperature and VDD.
FIGURE 2-24: VREF Input Impedance vs.
Temperature and VDD.
FIGURE 2-25: VOUT High Limit vs.
Temperature and VDD.
FIGURE 2-26: VOUT Low Limit vs.
Temperature and VDD.
FIGURE 2-27: IOUT High Short vs.
Temperature and VDD.
FIGURE 2-28: IOUT vs. VOUT. Gain = 1.
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VIN_SPI Hysteresis (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
155
160
165
170
175
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VREF_UNBUFFERED Impedance
(kOhm)
VDD
5.5V -
2.7V
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VOUT_HI Limit (VDD-Y)(V)
VDD
5.5V
4.0
V
5.0V
3.0V
2.7V
0.0015
0.002
0.0025
0.003
0.0035
0.004
0.0045
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VOUT_LOW Limit (Y-AVSS)(V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
10
11
12
13
14
15
16
17
18
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
IOUT_HI_SHORTED (mA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0246810121416
IOUT (mA)
VOUT (V)
VREF=4.0
Output Shorted to VSS
Output Shorted to VDD
MCP4901/4911/4921
DS22248A-page 14 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-29: VOUT Rise Time
FIGURE 2-30: VOUT Fall Time.
FIGURE 2-31: VOUT Rise Time
FIGURE 2-32: VOUT Rise Time
FIGURE 2-33: VOUT Rise Time Exit
Shutdown.
FIGURE 2-34: PSRR vs. Frequency.
VOUT
SCK
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
Time (1 µs/div)
VOUT
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Ripple Rejection (dB)
Frequency (Hz)
2010 Microchip Technology Inc. DS22248A-page 15
MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.50V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-35: Multiplier Mode Bandwidth.
FIGURE 2-36: -3 db Bandwidth vs. Worst
Codes.
FIGURE 2-37: Phase Shift.
-12
-10
-8
-6
-4
-2
0
100 1,000
Frequency (kHz)
Attenuation (dB)
D = 160
D = 416
D = 672
D = 928
D = 1184
D = 1440
D = 1696
D = 1952
D = 2208
D = 2464
D = 2720
D = 2976
D = 3232
D = 3488
D = 3744
Figure 2-35 calculation:
Attenuation (dB) = 20 log (VOUT/VREF) – 20 log (G(D/4096))
400
420
440
460
480
500
520
540
560
580
600
160
416
672
928
1184
1440
1696
1952
2208
2464
2720
2976
3232
3488
3744
Worst Case Codes (decimal)
Bandwidth (kHz)
G = 1
G = 2
-180
-135
-90
-45
0
100 1,000
Frequency (kHz)
qVREF – q
VOUT
D = 160
D = 416
D = 672
D = 928
D = 1184
D = 1440
D = 1696
D = 1952
D = 2208
D = 2464
D = 2720
D = 2976
D = 3232
D = 3488
D = 3744
MCP4901/4911/4921
DS22248A-page 16 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22248A-page 17
MCP4901/4911/4921
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.1 Supply Voltage Pins (VDD, VSS)
VDD is the po siti ve sup ply v oltage input pin. The i nput
supply voltage is relative to VSS and can range from
2.7V to 5.5V. The power supply at the VDD pin should
be as clean as possible for good DAC performance. It
is recommended to use an appropriate bypass capaci-
tor of about 0.1 µF (ceramic) to ground. An additional
10 µF capacitor (tantalum) in parallel is also recom-
mended to further attenuate high-frequency noise
present in applicati on boards .
VSS is the analog ground pin and the current return path
of the device. The user must connect the VSS pin to a
ground plane through a low-impedance connection. If
an analog ground path is available in the application
Printed Circuit Board (PCB), it is highly recommended
that the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
3.2 Chip Select (CS)
CS is the chip sele ct input, which req uires an active-low
signal to enable serial clock and data functions.
3.3 Serial Clock Input (SCK)
SCK is the SP I compatible serial clock i nput.
3.4 Serial Data Input (SDI)
SDI is the SPI compatible serial data input.
3.5 Latch DAC Input (LDAC)
The LDAC (latch DAC synchronization input) pin is
used to t ransfe r the inp ut latc h regist er to th e DAC re g-
ister (outp ut latches , VOUT). Wh en this pin is low, VOUT
is u pdated with input regist er c ontent . Thi s pin can be
tied to low (VSS) if the VOUT update is desired at the
rising edge of the CS pin. This pin can be driven by an
external control device such as an MCU I/O pin.
3.6 Analog Output (VOUT)
VOUT is the DAC analog output pin. The DAC output
has an outp ut amplifier . The full-scale range of the DAC
output is from VSS to G*VREF, where G is the gain
selection option (1x or 2x). The DAC analog output
cannot go higher than the supply voltage (VDD).
3.7 Voltage Reference Input (VREF)
VREF is the voltage reference input for the device. The
reference on this pin is utilized to set the reference
volt age on the string DAC. The inp ut volta ge can range
from VSS to VDD. This pin can be tied to VDD.
3.8 Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin. They must
be connected to the same potential on the PCB.
TABLE 3-1: PIN FUNCTION TABLE
PDIP, MSOP, SOIC DFN Symbol Description
11V
DD Supply Voltage Input (2.7V to 5.5V)
22CSChip Select Input
3 3 SCK Se rial Clock I nput
4 4 SDI Serial Data Input
55LDAC
DAC Output Synchronization Input. This pin is used to transfer
the input register (DAC settings) to the output register (VOUT)
66V
REF Voltage Reference Input
77V
SS Ground reference point for all circuitry on the device
88V
OUT DAC Analog Output
—9 EP Exposed Thermal Pad. This pad must be connected to VSS in
application
MCP4901/4911/4921
DS22248A-page 18 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22248A-page 19
MCP4901/4911/4921
4.0 GENERAL OVERVIEW
The MCP4901, MCP4911 and MCP4921 are single
channel voltage output 8-bit, 10-bit and 12-bit DAC
devices, respectively. These devices include a VREF
input buf fer, a rail-to -rail outpu t amplifi er , shu tdow n and
reset management circuitry. The devices use an SPI
serial communication interface and operate with a
single-supply voltage from 2.7V to 5.5V.
The DAC input coding of these devices is straight
binary. Equation 4-1 shows the DAC analog output
voltage calculation.
EQUATION 4-1: ANALOG OUTPUT
VOLTAGE (VOUT)
The ideal output range of each device is:
• MCP4901 (n = 8)
(a) 0V to 255/256*VREF when gain setting = 1x.
(b) 0V to 255/256*2*VREF when gain setting = 2x.
•MCP4911 (n = 10)
(a) 0V to 1023/1024*VREF when gain setting = 1x.
(b) 0V to 1023/1024*2*VREF when gain setting = 2x.
• MCP4921 (n = 12)
(a) 0V to 4095/4096*VREF when gain set tin g = 1x.
(b) 0V to 4095/4096*2*VREF when gain setting = 2x.
1 LSb is the ideal voltage difference between two
successive codes. Table 4-1 illustrates the LSb
calculation of ea ch devic e.
4.1 DC Accuracy
4.1.1 INL ACCU RACY
Integral Non-Linearity (INL) error is the maximum
deviation between an actual code transition point and
its corresponding ideal transition point, after offset and
gain errors have been removed. The two endpoints
(from 0x000 and 0xFFF) method is used for the calcu-
lation. Figure 4-1 shows t he details.
A positive INL error represents transition(s) later than
ideal. A negativ e INL error repres ent s transitio n(s) ear-
lier than ideal.
FIGURE 4-1: Example for INL Error.
4.1.2 DNL ACCU RACY
A Dif fere nti al No n-Li nea rity (DN L) err or is the measu re
of variations in code widths from the ideal code width.
A DNL error of zero indicate s that every code is exac tly
1 LSB wide.
Note: See the output s win g volt age s pecif icatio n
in Section 1.0 “Electrical Characteris-
tics”.
VOUT VREF Dn
2n
-------------------------------G=
Where:
VREF =EXternal voltag e refere nce
Dn= D AC input code
G=
=
=
Gain Sele ction
2 for <GA> bit = 0
1 for <GA> bit = 1
n=
=
=
=
DAC Resolution
8 for MCP4901
10 for MCP4911
12 for MCP4912
TABLE 4-1: LSb OF EACH DEVICE
Device Gain
Selection LSb Size
MCP4901
(n = 8) 1x VREF/256
2x (2*VREF)/256
MCP4911
(n = 10) 1x VREF/1024
2x (2*VREF)/1024
MCP4921
(n = 12) 1x VREF/4096
2x (2*VREF)/4096
where VREF is the external voltage reference.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
INL < 0
Ideal Transfer
Function
INL < 0
DAC Output
MCP4901/4911/4921
DS22248A-page 20 2010 Microchip Technology Inc.
FIGURE 4-2: Example for DNL Accuracy.
4.1.3 OFFSET ERROR
An of fset error i s the devi ation from z ero vol tag e outp ut
when the digital input code is zero.
4.1.4 GAIN ERROR
A gain error is the deviation from the ideal output,
VREF– 1 LS B, excluding the effects of offset error.
4.2 Circui t Descriptions
4.2. 1 OUTPUT AMPLIFIER
The DAC’s output is buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
of fset volt age and l ow n ois e. T he outp ut s tage e na ble s
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for the analog output voltage range
and load conditions.
In addition to resistive load driving capability, the
amplifier will also drive high capacitive loads without
oscill ation. The amp lifier’s strong output allo ws VOUT to
be used as a programmable voltage reference in a
system.
Selecting a gain of 2 reduces the bandwidth of the
amplifier in Multiplying mode. Refer to Section 1.0
“Ele ctric al Char acter istics ” for the Multiplying mode
bandwidth for given load conditions.
4.2.1.1 Programmable Gain Block
The rail-to-rail output amplifier has two configurable
gain options: a gain of 1x (<GA> = 1) or a gain of 2x
(<GA> = 0). The default value is a gain of 2x
(<GA>=0).
4.2.2 VOLTAGE REFERENCE AMPLIFIER
The input buffer amplifier for the MCP4901/4911/4921
devices provides low offset voltage and low noise. A
Config uration bi t for each DA C allow s the VREF input to
bypass the VREF input buffer amplifier, achieving
Buffered or Unbuffered mode. Buffered mode provides
a very hi gh input impe dance, with onl y minor limit ations
on the input range and frequency response. Unbuf-
fered mode provides a wide input range (0V to VDD),
with a typical input impedance of 165 k with 7 pF.
Unbuffered mode (<BUF> = 0) is the default
configuration.
4.2.3 POWER-ON RESET CIRCUIT
The internal Power-on Reset (POR) circuit monitors the
power supply voltage (VDD) during device operation.
The circ uit al so en sures that th e dev ice pow ers up wi th
high output impedance (<SHDN> = 0, typically
500 k. The devices will continue to have a high-
impedance output until a valid write command is
receive d, and the LDAC pin me ets the in put low thresh-
old.
If the power supply voltage is less than the POR
threshol d (VPOR = 2.0V, ty pical ), the d evic e will be hel d
in its Reset state. It will remain in that state until
VDD >V
POR and a subsequent write command is
received.
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the VDD pin, can
provide additional transient immunity.
FIGURE 4-3: Typical Transient Response.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
Ideal Transfer
Function
Narrow Code, < 1 LSb
DAC Outpu t
Wide Code, > 1 LSb
Transients above the
Transients below the
5V
Time
Supply V oltages
Transient Duration
V
POR
V
DD
- V
POR
TA =
Transient Duration (µs)
10
8
6
4
2
012345
V
DD
– V
POR
(V)
2010 Microchip Technology Inc. DS22248A-page 21
MCP4901/4911/4921
4.2.4 SHUTDOWN MODE
The user c an shut down the devi ce by using a s oftwa re
comma nd. During Shu tdown mode, most o f the interna l
circuit s, inclu ding t he outp ut am plifie r, are turned of f for
power savings. The serial interface remains active,
thus allowing a write command to bring the device out
of Shutdown mode. There will be no analog output at
the VOUT pin, and the VOUT pin is internall y switched to
a known resistive load (500 k typical. Figure 4-4
shows the analog output s tage during Shutdown m ode.
The device will remain in Shutdown mode until it
receive s a write comman d with <SHDN> bit = 1 and the
bit is latched into the device. When the device is
changed from Shutdown to Active mode, the output
settling time takes less than 10 µs, but more than the
standard active mode settling time (4.5 µs).
FIGURE 4-4: Output Stage for Shutdown
Mode.
500 k
Power-Down
Control Circuit
Resistive
Load
VOUT
OP
Amp
Resistive String DAC
MCP4901/4911/4921
DS22248A-page 22 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22248A-page 23
MCP4901/4911/4921
5.0 SERIAL INTERFACE
5.1 Overview
The MCP4901/4911/4921 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, which is available on many microcontrollers
and supp orts Mode 0,0 and M ode 1, 1. Com mand s and
data are sent to the device via the SDI pin, with data
being clocked-in on the rising edge of SCK. The
communications are unidirectional, thus the data
cannot be read out of the MCP4901/4911/4921. The
CS pin must be held low for the duration of a write
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches.
Regis ter 5-1 throug h Register 5-3 det ail the i nput regis-
ter that is used to configure and load the DAC register
for each device. Figure 5-1 through Figure 5-3 show
the write command for each device.
Refer to Figure 1-1 and the SPI Timing Specifications
Table for det ailed in put and outpu t timing sp ecificat ions
for both Mode 0,0 and Mode 1,1 operation.
5.2 Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin i s then ra is ed, causing th e data t o be
latched into the DAC’s input register.
The MCP4901/4911/4921 utilizes a double-buffered
latch structure to allow the analog output to be
synchronized with the LDAC pin, if desired.
By bring ing th e LD AC p in dow n to a low state, the co n-
tent stored in the DAC’ s input register is transferred into
the DAC’s output register (VOUT), and VOUT is updated.
All writes to the MCP4901/4911/4921 devices are
16-bit words. Any clocks past the 16th clock will be
ignored. The Most Significant 4 bits are Configuration
bits. The remaining 12 bits are data bits. No data can
be transferred into the device with CS high. This
transfer will only occur if 16 clocks have been
transferred into the device. If the rising edge of CS
occurs prior to that, shifting of data into the input
register will be aborted.
MCP4901/4911/4921
DS22248A-page 24 2010 Microchip Technology Inc.
REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4921 (12-BIT DAC)
REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4911 (10-BIT DAC)
REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4901 (8-BIT DAC)
Where:
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
0BUFGA
SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 0
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
0BUFGA
SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x
bit 15 bit 0
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
0BUFGA
SHDN D7 D6 D5 D4 D3 D2 D1 D0 xxxx
bit 15 bit 0
bit 15 0 = Write to DAC register
1 = Ignore this command
bit 14 BUF: VREF Input Buffer Control bit
1 = Buffered
0 = Unbuffered
bit 13 GA: Output Gain Selection bit
1 =1x (V
OUT = VREF * D /4096)
0 =2x (V
OUT = 2 * VREF * D/4096)
bit 12 SHDN: Output Shutdown Control bit
1 = Active mode operation. VOUT is availabl e.
0 = Shutdown the device. Analog output is not available. VOUT pin is connected to 500 ktypical)
bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored.
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
2010 Microchip Technology Inc. DS22248A-page 25
MCP4901/4911/4921
FIGURE 5-1: Write Command for MCP4921 (12-bit DAC).
FIGURE 5-2: Write Command for MCP4911 (10-bit DAC). Note: X are don’t care bits.
FIGURE 5-3: Write Command for MCP4901(8-bit DAC). Note: X are don’t care bits.
SDI
SCK
CS
021
GA SHDN D11 D10
config bits 12 data bits
LDAC
3 4
D9
567
D8 D7 D6
8 9 10 12
D5 D4 D3 D2 D1 D0
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
BUF
0
SDI
SCK
CS
021
GA SHDN D9 D8
config bits 12 data bits
LDAC
3 4
D7
5 6 7
D6 D5 D4
8910 12
D3 D2 D1 D0 X X
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
BUF
0
SDI
SCK
CS
021
GA SHDN
config bits 12 data bits
LDAC
3 4 567
X
D7 D6
8 9 10 12
D5 D4 D3 D2 D1 D0
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
XX
X
BUF0
MCP4901/4911/4921
DS22248A-page 26 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22248A-page 27
MCP4901/4911/4921
6.0 TYPICAL APPLICATIONS
The MCP4901/4911/4921 family devices are general
purpose DACs intended to be used in applications
where precision with low-power and moderate
bandwidth is required.
Applications generally suited for the devices are:
• Set Point or Offset Trimming
• Sensor C alibration
• Digitally-Controlled Multiplier/Divider
• Port ab le Instrum en t ati on (Battery Powered)
• Motor Control Feedback Loop
6.1 Digital Interface
The MCP4901/4911/4921 devices utilize a 3-wire
synchronous serial protocol to tran sfer the DAC’s setup
and output values from the digital source. The serial
protocol can be interfaced to SPI or Microwire periph-
erals that are common on many microcontrollers,
including Microchip’s PIC® MCUs and dsPIC® DSCs.
In addition to the three serial connections (CS, SCK
and SDI), the LDAC pin synchronizes the analog outp ut
(VOUT) with the pin event. By bringing the LDAC pin
down “low”, the DAC input code and settings in the
input register are latched into the output register, and
the analog output is updated. Figure 6-1 shows an
example of the pin connections. Note that the LDAC pin
can be tied low (VSS) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16-clock transmission has been received and CS pin
has been rais ed.
6.2 Power Supply Considerations
The typical application will require a bypass capacitor
in order to fil ter high-frequ ency noise. The no ise can be
induced onto the power supply's traces from various
events such as digital switching or as a result of
changes on the DAC's output. The bypass capacitor
helps to minimize the effect of these noise sources.
Figure 6-1 illustrates an appropriate bypass strategy . In
this example, two bypass capacitors are used in
parallel: (a) 0.1 µF (ceramic) and (b) 10 µF (tantalum).
These capacitors should be placed as close to the
device power pin (VDD) as possible (within 4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 6-1: Typical Connection
Diagram.
6.3 Layout Considerations
Inductively-coupled AC transients and digital switching
noises can degrade the input and output signal
integrity , potentially reducing the device’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench test-
ing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, and
isolated outputs with proper decoupling, is critical for
best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
VDD
VDD VDD
AVSS
AVSS VSS
VREF
VOUT
PIC® Microcontroller
VREF
VOUT
SDI
SDI
CS1
SDO
SCK
LDAC
CS0
C1 C1 C2
C2
MCP49X1
MCP49X1
C1
C1 = 10 µF
C2 = 0.1 µF
MCP4901/4911/4921
DS22248A-page 28 2010 Microchip Technology Inc.
6.4 Single-Supply Operation
The MCP4901/4911/4921 devices are rail-to-rail volt-
age output DAC devices designed to operate with a
VDD range of 2.7V to 5.5V. Its out put ampl ifier is robus t
enough to dri ve small signa l load s directly. Therefo re, it
does not require an external output buffer for most
applications.
6.4.1 DC SET POINT OR CALIBRATION
A common application for DAC devices is
digitally-controlled set points and/or calibration of
variable parameters, such as sensor offset or slope.
For example, the MCP4921 and MCP4922 provide
4096 output steps. If the external voltage reference
(VREF) is 4.096V, the LSb size is 1 mV. If a smaller
output step size is desired, a lower external voltage
reference is needed.
6.4.1.1 Decreasing Output Step Size
If the application is calibrating the bias voltage of a
diode or tran sistor , a bia s voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common methods to achieve a 0.8V range is to either
reduce VREF to 0.82V or use a voltage divider on the
DAC’s output.
Using a VREF is an option if the VREF is avai lable with
the desired output voltage range. However,
occas ionall y, when us ing a low-v olt ag e VREF, the noise
floor causes an SNR error that is intolerable. Using a
voltage divider method is another option and provides
some advantages when VREF needs to be very low or
when t he des ired ou tput v olt age is not av ailab le. In this
case, a larger value VREF is used while two resistors
scale the output range down to the precise desired
level.
Example 6-1 illustrates this concept. Note that the
bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the
environment.
EXAMPLE 6-1: EX AMP LE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION.
VDD
SPI 3-wire
VTRIP
R1
R20.1 uF
Comparator
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUT VREF GDn
2N
------
=
VCC+
VCC–
VOUT
Vtrip VOUT
R2
R1R2
+
--------------------
=
VDD
RSENSE
DAC
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
VREF VO
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
2010 Microchip Technology Inc. DS22248A-page 29
MCP4901/4911/4921
6.4.1.2 Building a “Window” DAC
When calibrating a set point or threshold of a sensor,
typica lly only a sma ll portion of the DAC output ran ge is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increa se the resolution around the desired threshold.
If the threshold is not near VREF or VSS, then creating
a “window” around the threshold has several
advantages. One simple method to create this
“window” is to use a voltage divider network with a
pull-up and pull-down resistor. Example 6-2 and
Example 6-4 illustrate this concept.
EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC.
VREF VDD
SPI 3
Vtrip
R1
R20.1 µF
Comparator
R3
VCC-
VCC+ VCC+
VCC-
VOUT
R23 R2R3
R2R3
+
------------------
=
V23 VCC+R2
VCC-R3
+
R2R3
+
-----------------------------------------------------
=
Vtrip VOUTR23 V23R1
+
R2R23
+
--------------------------------------------
=
R1
R23
V23
VOUT VO
Thevenin
Equivalent
Rsense
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUT VREF GDn
2N
------
=
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
DAC
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
MCP4901/4911/4921
DS22248A-page 30 2010 Microchip Technology Inc.
6.5 Bipolar Operation
Bipolar operation is achievable using the MCP4901/
4911/4921 family devices by using an external
operational amplifier (op amp). This configuration is
desirable due to the wide variety and availability of op
amps. This allows a general purpose DAC, with its cost
and availability advantages, to meet almost any
desired output voltage range, power and noise
performance.
Example 6-3 ill ustrate s a simple bipola r volt age so urce
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC's output to a selected
offset. Note that R4 can be tied to VREF instead of VSS
if a higher offset is desired. Note that a pull-up to VREF
could be used, instead of R4, if a higher offset is
desired.
EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE.
6.5.1 DESIGN EXAMPLE: DESIGN A BIPOLAR
DAC USING EXAMPLE 6-3 WITH 12-BIT
MCP4912 OR MCP4922
An output st ep magnitude of 1 mV with an output range
of ±2.05V is desired for a particular application.
The following steps show the details:
1. Calculate the range: +2.05V – (-2.05V) = 4.1V.
2. Calculate the resolution needed:
4.1V/1 mV = 4100
Since 212 = 4096, 12-bit resolution is desired.
3. The amplifier gain (R2/R1), multiplied by VREF,
must be equ al to th e desired m in im um ou tput to
achieve bipolar operation. Since any gain can
be realized by choosing resistor values
(R1+R
2), the VREF source needs to be deter-
mined first. If a VREF of 4.1V is used, solve for
the gain by setting the DAC to 0, knowing that
the output nee ds to be -2.05V. The equati on can
be simplified to:
4. Next, solve for R3 and R4 by setting the DAC to
4096, knowing that the output needs to be
+2.05V.
VREF
VREF
VDD
SPI 3
VOUT R3
R4
R1
VIN+
0.1 µF
VCC+
VCC–
VO
VIN+ VOUTR4
R3R4
+
--------------------
=
VOVIN+ 1R2
R1
------
+
VDD R2
R1
------
–=
G = Gain selection ( 1x or 2x)
Dn = Digital value of DAC (0 – 255) for MCP4901/MCP4902
VOUT VREF GDn
2N
------
=
= Digital value of DAC (0 – 1023) for MCP4911/MCP4912
= Digital value of DAC (0 – 4095) for MCP4921/MCP4922
N = DAC Bit Resolution
DAC
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
R2
–
R1
---------2.05–
VREF
------------- 2.05–
4.1
-------------
==
If R1 = 20 k and R2 = 10 k, the gain will be 0.5
R2
R1
------1
2
---
=
R4
R3R4
+
----------------------- 2.05V0.5VREF
+
1.5VREF
----------------------------------------- 2
3
---
==
If R4 = 20 k, then R3 = 10 k
2010 Microchip Technology Inc. DS22248A-page 31
MCP4901/4911/4921
6.6 Select able Gain and Offset Bipolar
Voltage Output Using DAC
Devices
In some applications, precision digital control of the
output range is desirable. Example 6-4 illustr ates how
to use the DAC devices to achieve this in a bipolar or
single-supply application.
This circuit is typically used in Multiplier mode and is
ideal for linearizing a sensor whose slope and offset
varies. Refer to Section 6.9 “Using Multiplier Mode”
for more information on Multiplier mode.
The eq uat ion to desi gn a b ipo lar “w indo w” D AC wo uld
be utilized if R3, R4 and R5 are populated.
EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET.
VREFA
DACB
VDD
R3
R4
R2
DACA
VDD
R1
DACA (Gain Adjust)
DACB (Offset Adjust)
SPI 3
R5
VCC+
Thevenin
Bipolar “Window” DAC using R4 and R5
0.1uF
VCC–
VCC+
VCC–
VOUTB VREFBGB
DB
2N
-------=
VOUTA
VOUTB
VOUTA VREFAGA
DA
2N
-------=
VIN+ VOUTBR4VCC-R3
+
R3R4
+
------------------------------------------------
=
VOVIN+ 1R2
R1
------
+
VOUTA R2
R1
------
–=
Equivalent V45 VCC+R4VCC-R5
+
R4R5
+
--------------------------------------------
=R45 R4R5
R4R5
+
------------------
=
VIN+ VOUTBR45 V45R3
+
R3R45
+
-----------------------------------------------
=VOVIN+ 1R2
R1
------
+
VOUTA R2
R1
------
–=
Offset Adju st Gain Adjust
Offset Adjust Gain Adjust
VREFB
GX = Gain selection (1x or 2x)
DA, DB = Digital value of DAC (0-255) for MCP4901/MCP4902
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4912/MCP4922
N = DAC Bit Resolution
VO
MCP4901/4911/4921
DS22248A-page 32 2010 Microchip Technology Inc.
6.7 Designing a Double-Precision
DAC
Example 6-5 illustrates how to design a single-supply
voltage output capable of up to 24-bit resolution by
using 12-bit DACs. This design is simply a voltage
divider with a buffered output.
As an example, if a similar application to the one
developed in Section 6.5.1 “Design Example:
Design a bipolar dac using example 6-3 with 12-bit
MCP4912 or MCP4922” required a resolution of 1 µV
inste ad of 1 m V and a r ang e of 0V to 4.1V, th en 12 -bit
resolution would not be adequate.
1. Calculate the resolution needed:
4.1V/1 µV = 4.1x 106. Since 222 = 4.2 x 106,
22-b it resolu tion is desired. Since DNL = ±0. 75
LSB, thi s design can be done with th e MCP4921
or MCP4922.
2. Since the DACB‘s VOUTB has a resolution of
1 mV, its ou tput only needs to be “p ulled” 1/1000
to meet t he 1 µV tar get. Dividi ng VOUTA by 100 0
would allow the application to compensate for
DACB’s DNL error.
3. If R2 is 100, then R1 needs to be 100 k.
4. The resulting transfer function is not perfectly
linear, as shown in the equa tion of Example 6-5.
EXAMPLE 6-5: SIMPLE, DOUBLE PRECISION DAC WITH MCP4921 OR MCP4922.
VREF
DACB
VDD
R2
DACA
VDD
R1
DACA (Fine Adjust)
DACB (Course Adjust)
SPI 3
R1 >> R2
VOVOUTAR2VOUTBR1
+
R1R2
+
-----------------------------------------------------
=
G = Gain selection (1x or 2x)
D = Digital value of DAC (0-4096)
0.1 µF
VCC+
VCC–
VOUTA VREFAGADA
212
-------=
VOUTB VREFBGBDB
212
-------=
VOUTA
VOUTB
VO
2010 Microchip Technology Inc. DS22248A-page 33
MCP4901/4911/4921
6.8 Buildi ng Programmable Current
Source
Example 6-6 shows an example for building a
program mable current so urce usin g a voltage follow er.
The current sensor (sensor resistor) is used to convert
the DAC voltage output into a digitally-selectable
current source.
Adding the resistor network from Example 6-2 would
be advantageous i n this application. The smaller Rsense
is, the less power is dissipated acros s it. Howev er, this
also reduces the resolution that the current can be
controlled with. The voltage divider, or “window”, DAC
configu ration would allow the range to be reduced, thus
increasing the resolution around the range of interest.
When w orkin g with ver y small sens or vo lta ges, p lan o n
eliminating the amplifier’s offset error by storing the
DAC's setting under known sensor conditions.
EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE.
DAC
RSENSE
Ib
Load
IL
VDD
SPI 3-wire
VCC+
VCC–
VOUT
ILVOUT
Rsense
---------------
1+
------------=
IbIL
----
=
G = Gain sele ct (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUT VREF GDn
2N
------
=
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
Common-Emitter Current Gainwhere
VREF
VDD or VREF
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
MCP4901/4911/4921
DS22248A-page 34 2010 Microchip Technology Inc.
6.9 Using Multiplier Mode
The MCP4901/4911/4921 and MCP4902/MCP4912/
MCP4922 family devices use external reference, and
these devices are ideally suited for use as a multiplier/
divider in a signal chain. Common applications are: (a)
precision p rogram mable gai n/atten uator am plifie rs an d
(b) motor cont rol feedb ack l oop s. T he wi de inpu t range
(0V – VDD) is in Unbuffered mode, and near rail-to-rail
range in Buffered mode. Its bandwidth (> 400 kHz),
selectabl e 1x /2 x ga in and low power cons um pti on give
maximum flexibility to meet the application’s needs.
To configure the device for multiplier applications,
connect the input signal to VREF and serially configure
the DAC’s input buffer, gain and output value. The
DAC’s output can utilize any of the examples from 6-1
to 6-6, depending on the application requirements.
Example 6-7 is an illustration of how the DAC can
operate in a motor control feedback loop.
If the gain selection bit is configured for 1x mode
(<GA>=1), the resul ting input s ignal will be attenuated
by D/2n. With the 12-bit DAC (MCP49 21 or MCP4922),
if the gain is config ured for 2x m ode (<GA>=0), codes
less than 2048 attenuate the signal, while codes
greater than 2048 gain the signal.
A DAC provides significantly more gain/attenuation
resolution when compared to typical programmable
gai n amplifiers. Adding an op amp to buffer t he output ,
as illustrated in Examples 6-2 through 6-6, extends the
output range and power to meet the precise needs of
the application.
EXAMPLE 6-7: MULTIPLIER MODE USING VREF INPUT.
VCC+
VCC–
VREF DAC
VRPM
+
–
VDD
SPI 3
VOUT
Rsense
VRPM_SET
ZFB
MCP4901
MCP4911
MCP4921
(a) Single Output DAC:
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
VOUT VREF GDn
2N
------
=
2010 Microchip Technology Inc. DS22248A-page 35
MCP4901/4911/4921
7.0 DEVELOPMENT SU PPORT
7.1 Evaluation & Demonstration
Boards
The Mixed Signal PICtail™ Board supports the
MCP49 01/4 911/ 492 1 fa mi ly of device s. Pl ease refer to
www.microchip.com for further information on this
product’s capabilit ies and availabil i ty.
MCP4901/4911/4921
DS22248A-page 36 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22248A-page 37
MCP4901/4911/4921
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for customer-specific information.
3
e
3
e
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Le ad SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP4901
E/P 256
1010
MCP4901E
SN 1010
256
8-Le ad MSOP Example:
XXXXXX
YWWNNN 4901E
010256
3
e
3
e
8-Lead DFN (2x3) Example:
XXX
YWW
NN 010
25
AHS
MCP4901/4911/4921
DS22248A-page 38 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS22248A-page 39
MCP4901/4911/4921
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DS22248A-page 40 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS22248A-page 41
MCP4901/4911/4921
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP4901/4911/4921
DS22248A-page 42 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS22248A-page 43
MCP4901/4911/4921
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DS22248A-page 44 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS22248A-page 45
MCP4901/4911/4921
APPENDIX A: REVISION HISTORY
Revision A (April 2010)
• Original Release of this Document.
MCP4901/4911/4921
DS22248A-page 46 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22248A-page 47
MCP4901/4911/4921
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device MCP4901: 8-Bit Volt age Output DAC
MCP4901T: 8-Bit Voltage Output DAC
(Tape and Reel)
MCP4911: 10-Bit Voltage Output DAC
MCP4911T: 10-Bit Voltage Output DAC
(Tape and Reel)
MCP4921: 12-Bit Volt age Output DAC
MCP4921T: 12-Bit Volt age Output DAC
(Tape and Reel)
Temp er atu re Rang e E = -40C to +125C (Extended)
Package MC = 8-Lead Plastic Dual Flat, No Lead Package -
2x3x0.9 mm Body (DFN)
MS = 8-Lead Plastic Micro Small Outline (MSOP)
SN = 8-Lead Plastic Small Outline - Narrow, 150 mil
(SOIC)
P = 8-Lead Plastic Dual In-Line (PDIP)
Examples:
a) MCP4901-E /P: Extended temperature,
PDIP package.
b) MCP4901-E /SN : Extended temperature,
SOIC package.
c) MCP 4901T-E/SN: Extended temperature,
SOIC pa cka ge
Tape and Reel.
d) MCP4901-E /M S: Extended temperature,
MSOP package.
e) MCP4901T-E/MS:Extended tem perat ure,
MSOP package
Tape and Reel.
f) MCP4901-E /MC: Extended temperature,
DFN package.
g) MCP4901T-E/MC:Extended temperature,
DFN package
Tape and Reel.
h) MCP4911-E/P: Extended temperature,
PDIP package.
i) MCP4911-E/SN: Extended temperature,
SOIC package.
j) MCP4911T-E/SN: Extended temperature,
SOIC pa cka ge
Tape and Reel.
k) MCP 4911-E/MS: Extended temperature,
MSOP package.
l) MCP 4911T-E /M S: Extended temperat ure,
MSOP package
Tape and Reel.
m) MCP 4911-E/MC: Extended temperature,
DFN package.
n) MCP4911T-E /M C:Extended temperature,
DFN package
Tape and Reel.
o) MCP4921-E/P: Extended temperature,
PDIP package.
p) MCP4921-E/SL: Extended temperature,
SOIC package.
q) MCP4921T-E/SL: Extended temperature,
SOIC pa cka ge
Tape and Reel.
r) MCP4921-E /M S: Extended temperature,
MSOP package.
s) MCP 4921T-E/MS:Extended tem perat ure,
MSOP package
Tape and Reel.
t) MCP4921-E /MC: Extended temperature,
DFN package.
u) MCP4921T-E/MC:Extended temperature,
DFN package
Tape and Reel.
MCP4901/4911/4921
DS22248A-page 48 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22248A-page 49
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI CSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI- TIDE, In-Circu it Se r i a l
Programming, ICSP, Mindi, MiWi, MPASM, MPLA B Cert ified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN:
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that i t s family of products is one of the most secure families of its kind on the market today, when used in t he
intended manner and under normal conditions.
• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Mill ennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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and manufacture of development systems is ISO 9001:2000 certified.
DS22248A-page 50 2010 Microchip Technology Inc.
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China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11- 4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Kaohsi ung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangko k
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madri d
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
01/05/10
