Freescale Semiconductor
Data Sheet: Document Number: MSC8122
Rev. 16, 12/2008
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
MSC8122
FC PBGA–431
20 mm ×20 mm
• Four StarCore™ SC140 DSP extended cores, each with an SC140
DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte
total), 16 way 16 Kbyte instruction cache (ICache), four-entry
write buffer, external cache support, programmable interrupt
controller (PIC), local interrupt controller (LIC), and low-power
Wai t and Stop processing modes.
• 475 Kbyte M2 memory for critical data and temporary data
buffering.
• 4 Kbyte boot ROM.
• M2-accessible multi-core MQBus con necting the M2 memory
with all four cores, operating at the core frequency, with data bus
access of up to 128-bit reads and up to 64-bit writes, central
efficient round-robin arbiter for core access to the bus, and atomic
operation control of M2 memory access by the cores and the local
bus.
• Internal PLL conf igured are reset by config uration signal values.
• 60x-compatible system bus with 64 or 32 bit data and 32-bit
address bus, support for multi-master designs, four-beat burst
transfers (eight- beat in 3 2-bit dat a mode), po rt size of 64/3 2/16 /8
bits cont rolled by the internal memory co ntroller,.access to
external memory or peripheral s, access by an extern al host to
internal resou rc es, slave support wi th direct access to internal
resources in cluding M1 and M2 memories, and on-device
arbitration for up to four master devices.
• Direct slave interface (DSI) using a 32/64-bit slave host interface
with 21 –25 bit add ressing and 32/ 64-bit data transf er s, direct
access by an ex ternal host to internal and exte rnal resources,
synchronous or asynchronous accesses with burst capability in
synchronous mode, dual or single s trobe mode, write and read
buffers to improve host bandwidth, byte enable signals for
1/2/4/8-byte write granularity, sliding window mode for access
using a re duced num ber of address pins, chip ID decoding to
allow one CS signal to contr ol multiple DS Ps, broad cast mod e to
write to multiple DSPs, and big-endian/little-endian/munged
support.
• Three mode signal multiplexing: 64-bit DSI and 32-bit system
bus, 32-bit DSI and 64-bit system bus, or 32-bit DSI and 32-bit
system bus .
• Flexible memory controller with three UPMs, a GPCM, a
page-mode SDRAM machine, glueless interface to a variety of
memo r ie s a nd de vices, b yte e na bles for 6 4- or 32-bit bus w idths,
8 memory banks for external memories, and 2 memory banks for
IPBus peripherals and internal memories.
• Multi-channel DMA controller with 16 time-multiplexed single
channels, up to four external peripherals, DONE or DRACK
protocol for two external peripherals,.service for up to 16 internal
requests from up to 8 internal FIFOs per channel, FIFO generated
watermarks and hungry requests, priority-based
time- multiplexing between chan nels using 16 in terna l priority
levels or round-robin time-multiplexing between channels,
flexible channel configuration with connection to local bus or
system bus, and flyby transfer support that bypasses the FIFO.
• Up to four independent TDM modules with programmable word
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,
up to 128 Mbps data rate for all channels, with glueless interface
to E1 or T1 framers, and can interface with H-MVIP/H.110
devices, TSI, and codecs such as AC-97.
• Ethernet controller with support for 10/100 Mbps MII/RMII/SMII
including full- and half-duplex operation, full-duplex flow
controls, out-of-sequence transmi t queues, program mable
maximu m frame length includi ng jumbo frame s and VLAN tags
and priority, retransmission after collision, CRC generation and
verification of inboun d/outbo un d pa c ke ts , address rec og nition
(including exact match, broadcast address, individual hash check,
group hash che ck, and promiscuous mode), pattern matching,
insertion with expansion or replacement for transmit frames,
VLAN tag insertion, RM ON statistics, local bus master DMA for
descriptor fetching and buffer access, and optional multiplexing
with GPIO (MII/RMII/SMII) or DSI/system bus signals lines
(MII/RMII).
• UART with full-duplex operation up to 6.2 5 Mbps.
• Up to 32 general-purpose input/output (GPIO) ports.
•I
2C interface that allows booting from EEPROM devices.
• Two timer modules, e a ch with sixte en c onfigurable 16-bit timers.
• Eight programmable hard war e semaphores.
• Global interrupt contro ller (GIC) with int errupt consolida tion and
routing to INT_OUT , NMI_OUT , and the cores; thirty-two virtual
maskable interrupts (8 per core) and four virtual NMI (one per
core) that can be generated by a simple write acce ss.
• Optional booting external memory, external ho st, UART, TDM,
or I2C.
Quad Digital Signal
Processor
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freesca le Sem ico nd uctor2
Table of Contents
1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ba ll La yout Diagrams. . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location . . . . . . . . . . . . . . . . . . . . . . .7
2 Ele c t r i c a l C h a ra c t e r i s t i c s . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Max imum Ra ting s . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .14
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .14
2.4 DC Electrical Chara c te ristics . . . . . . . . . . . . . . . . . . . .15
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .39
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .39
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .40
3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .41
3.4 External SDRAM Selection. . . . . . . . . . . . . . . . . . . . . .42
3.5 The rm a l C o n s i d e ra tion s . . . . . . . . . . . . . . . . . . . . . . . .4 3
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6 Pro duct D o c u menta ti o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
7 Revisio n History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
List of Figures
Figure 1. MSC8122 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC140 DS P Extended Core Block Diagram . . 3
Figure 3. MSC8122 Package, Top View . . . . . . . . . . . . . . . . . . . . 5
Figure 4. MSC8122 Package, Bottom View. . . . . . . . . . . . . . . . . . 6
Figure 5. Overshoot/Undersho ot Voltage for VIH and VIL. . . . . . . 1 6
Figure 6. Start-Up Sequence: VDD and VDDH Raised Together . . 17
Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN
Started with VDDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN . . . . . 18
Figure 9. Timing Diagram for a Reset Configuration Write . . . . . 21
Figure 10.Internal Tick Spacing for Memory Controller Signals. . . 22
Figure 11.SIU T iming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12.CLKOUT and CLKIN Signals. . . . . . . . . . . . . . . . . . . . . 26
Figure 13.DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14.Asynchronous Single- and Dual-Strobe Modes Read
Timing Diagr a m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15.Asynchr onous Single- and Dual-Strobe Modes Write
Timing Diagr a m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16.Asynchr onous Broadc ast Write Timing Diagram. . . . . . 30
Figure 17.DSI Synchronous Mode Signals Timing Diagram . . . . . 31
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21.UART Ou tp u t Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22.Timer Ti min g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23.MDIO Timing Rela tio n s h i p to MDC . . . . . . . . . . . . . . . . 34
Figure 24.MII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 25.RMII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 26.SMII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 29.Test Clock Input Timing Diagram. . . . . . . . . . . . . . . . . . 38
Figure 30.Boundary Scan (JTAG) T iming Diagram . . . . . . . . . . . . 38
Figure 31.Test Access Port Timing Dia gram . . . . . . . . . . . . . . . . . 39
Figure 32.TRST Timing Diag ram. . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 33.Core Power Supply Decoupling. . . . . . . . . . . . . . . . . . . 40
Figure 34.VCCSYN Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 35.MSC8122 Mechanical Information, 431-pin FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 3
Figure 1. MSC8122 Block Diagram
Figure 2. StarCore SC140 DSP Extended Core Block Diagram
MQBus SQBus
Local Bu s
128
128
Boot
ROM
64
PLL
JTAG
RS-232
Internal Local Bus
Interna l Sy stem Bus
IPBus
IP M as te r
64
64
UART
Memory
Controller
M2
RAM
GPIO P in s
Interrupts
Memory
Controller
System Bus
32/64
DSI Port
32
32/64
PLL/Clock
JTAG Port
SC140
Extended Core SC140
Extended Core SC140
Extended Core
System
Interface
32 Timers
4 TDMs
DMA
Bridge SIU
Registers
Direct
Slave
Interface
(DSI)
8 Ha rdware
Semaphores
GIC
GPIO
MII/RMII/SMII
Ethernet
SC140
Extende d Core
SC140
Power
Management
Core
Program
Sequencer Address
Register
File Data ALU
Register
File
Address
ALU
EOnCEJTAG
Xa
Xb
P
QBus
IRQs
IRQs
MQBus
SQBus
Local Bus
128 128
64
64 64
LIC
PIC
128
128
QBus
Interface
Instruction
Cache
M1
RAM
Notes: 1. The arrows show the data transfer direction.
QBus
Bank 1 QBus
Bank 3
2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines
four QBus banks. In addition, the QBC handles internal memory contentions.
QBC
SC140 Core
Data
ALU
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor4
1 Pin Assignments
This section includes diagrams of the MSC8122 package ball grid array layouts and pinout allocation tables.
1.1 FC-PBGA Ball Layout Diagrams
Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers.
Pin Assignments
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 5
Figure 3. MSC8122 Package, Top View
2345678910111213141516171819202122
BVDD GND GND NMI_
OUT GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GPIO0 VDD VDD GND
CGND VDD TDO S
RESET GPIO28 HCID1 GND VDD GND VDD GND VDD GND GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6
D TDI EE0 EE1 GND VDDH HCID2 HCID3 GND VDD GND VDD GND VDD VDD GPIO31 GPIO29 VDDH GPIO4 VDDH GND GPIO8
ETCK TRST TMS HRESET GPIO27 HCID0 GND VDD GND VDD GND VDD GND GND VDD GND GND GPIO9 GPIO13 GPIO10 GPIO1
2
FPO
RESET RST
CONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD ETHRX_
CLK ETHTX_
CLK GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO1
9
GHA24HA27HA25HA23HA17PWE0VDD VDD BADDR
31 BM0 ABB VDD INT_
OUT ETHCR
SVDD CS1 BCTL0 GPIO15 GND GPIO17 GPIO2
2
HHA20HA28 VDD HA19 TEST PSD
CAS PGTA VDD BM1 ARTRY AACK DBB HTA VDD TT4 CS4 GPIO24 GPIO21 VDD VDDH A31
JHA18HA26 VDD HA13 GND PSDA
MUX BADDR
27 VDD CLKIN BM2 DBG VDD GND VDD TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30
K HA15 HA21 HA16 PWE3 PWE1 POE BADDR
30 Res. GND GND GND GND CLKOUT VDD TT2 ALE CS2 GND A26 A29 A28
LHA12HA14HA11VDDH VDDH BADDR
28 BADDR
29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22
M HD28 HD31 VDDH GND GND GND VDD VDDH GND GND VDDH HB
RST VDDH VDDH GND VDDH A24 A21
N HD26 HD30 HD29 HD24 PWE2 VDDH HWBS
0HBCS GND GND HRDS BG HCS CS0 PSDWE GPIO26 A23 A20
P HD20 HD27 HD25 HD23 HWBS
3HWBS
2HWBS
1HCLKIN GND GNDSYN VCCSYN GND GND TA BR TEA PSD
VAL DP0 VDDH GND A19
R HD18 VDDH GND HD22 HWBS
6HWBS
4TSZ1 TSZ3 GBL VDD VDD VDD TT0 DP7 DP6 DP3 TS DP2 A17 A18 A16
T HD17 HD21 HD1 HD0 HWBS
7HWBS
5TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 DP5 DP4 DP1 D30 GND A15 A14
U HD16 HD19 HD2 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH A12 A13
V HD3 VDDH GNDD0D1D4D5D7D10D12D13D18D20GNDD24D27D29A8A9A10A11
W HD6 HD5 HD4 GND GND VDDH VDDH GND HDST1 HDST0 VDDH GND HD40 VDDH HD33 VDDH HD32 GND GND A7 A6
Y HD7 HD15 VDDH HD9 VDD HD60 HD58 GND VDDH HD51 GND VDDH HD43 GND VDDH GND HD37 HD34 VDDH A4 A5
AA VDD HD14 HD12 HD10 HD63 HD59 GND VDDH HD54 HD52 VDDH GND VDDH HD46 GND HD42 HD38 HD35 A0 A2 A3
AB GND HD13 HD11 HD8 HD62 HD61 HD57 HD56 HD55 HD53 HD50 HD49 HD48 HD47 HD45 HD44 HD41 HD39 HD36 A1 VDD
Top View
MSC8122
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor6
Figure 4. MSC8122 Package, Bottom View
2221201918171615141312111098765432
BGND VDD VDD GPIO0 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND NMI_
OUT GND GND VDD
C GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GND GND VDD GND VDD GND VDD GND HCID1 GPIO28 S
RESET TDO VDD GND
D GPIO8 GND VDDH GPIO4 VDDH GPIO29 GPIO31 VDD VDD GND VDD GND VDD GND HCID3 HCID2 VDDH GND EE1 EE0 TDI
EGPIO12 GPIO10 GPIO13 GPIO9 GND GND VDD GND GND VDD GND VDD GND VDD GND HCID0 GPIO27 HRESET TMS TRST TCK
F GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20 ETHTX_
CLK ETHRX_
CLK VDD GND VDD GND VDD VDD VDD GND HA22 HA29 NMI RST
CONF PO
RESET
G GPIO22 GPIO17 GND GPIO15 BCTL0 CS1 VDD ETHCR
SINT_
OUT VDD ABB BM0 BADDR
31 VDD VDD PWE0 HA17 HA23 HA25 HA27 HA24
HA31 VDDH VDD GPIO21 GPIO24 CS4 TT4 VDD HTA DBB AACK ARTRY BM1 VDD PGTA PSD
CAS TEST HA19 VDD HA28 HA20
J A30 GPIO25 GND GPIO23 BCTL1 PSDA10 TT3 VDD GND VDD DBG BM2 CLKIN VDD BADDR
27 PSDA
MUX GND HA13 VDD HA26 HA18
KA28 A29 A26 GND CS2 ALE TT2 VDD CLKOUT GND GND GND GND Res. BADDR
30 POE PWE1 PWE3 HA16 HA21 HA15
LA22 A25 A27VDDH CS3 GND GND VDDH GND GND GND BADDR
29 BADDR
28 VDDH VDDH HA11 HA14 HA12
MA21 A24 VDDH GND VDDH VDDH HB
RST VDDH GND GND VDDH VDD GND GND GND VDDH HD31 HD28
N A20 A23 GPIO26 PSDWE CS0 HCS BG HRDS GND GND HBCS HWBS
0VDDH PWE2 HD24 HD29 HD30 HD26
PA19 GNDVDDH DP0 PSD
VAL TEA BR TA GND GND VCCSYN GNDSYN GND HCLKIN HWBS
1HWBS
2HWBS
3HD23 HD25 HD27 HD20
RA16 A18 A17 DP2 TS DP3 DP6 DP7 TT0 VDD VDD VDD GBL TSZ3 TSZ1 HWBS
4HWBS
6HD22 GND VDDH HD18
T A14 A15 GND D30 DP1 DP4 DP5 D23 D21 TT1 D16 VDD TBST TSZ2 TSZ0 HWBS
5HWBS
7HD0 HD1 HD21 HD17
UA13 A12VDDH D31 D28 D26 D25 D22 D19 D17 D15 D14 D11 D9 D8 D6 D3 D2 HD2 HD19 HD16
V A11 A10 A9 A8 D29 D27 D24 GND D20 D18 D13 D12 D10 D7 D5 D4 D1 D0 GND VDDH HD3
WA6 A7 GNDGNDHD32
VDDH HD33 VDDH HD40 GND VDDH HDST0 HDST1 GND VDDH VDDH GND GND HD4 HD5 HD6
YA5 A4VDDH HD34 HD37 GND VDDH GND HD43 VDDH GND HD51 VDDH GND HD58 HD60 VDD HD9 VDDH HD15 HD7
AA A3 A2 A0 HD35 HD38 HD42 GND HD46 VDDH GND VDDH HD52 HD54 VDDH GND HD59 HD63 HD10 HD12 HD14 VDD
AB VDD A1 HD36 HD39 HD41 HD44 HD45 HD47 HD48 HD49 HD50 HD53 HD55 HD56 HD57 HD61 HD62 HD8 HD11 HD13 GND
Bottom View
MSC8122
Pin Assignments
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 7
1.2 Signal List By Ball Location
Table 1 presents signal list sorted by ball number. -
Table 1. MSC8122 Signal Listing by Ball Designator
Des. Signal Name Des. Signal Name
B3 VDD C18 GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1
B4 GND C19 GPIO7/TDM3RCLK/IRQ5/ETHTXD3
B5 GND C20 GPIO3/TDM3TSYN/IRQ1/ETHTXD2
B6 NMI_OUT C21 GPIO5/TDM3TDAT/IRQ3/ETHRXD3
B7 GND C22 GPIO6/TDM3RSYN/IRQ4/ETHRXD2
B8 VDD D2 TDI
B9 GND D3 EE0
B10 VDD D4 EE1
B11 GND D5 GND
B12 VDD D6 VDDH
B13 GND D7 HCID2
B14 VDD D8 HCID3/HA8
B15 GND D9 GND
B16 VDD D10 VDD
B17 GND D11 GND
B18 VDD D12 VDD
B19 GPIO0/CHIP_ID0/IRQ4/ETHTXD0 D13 GND
B20 VDD D14 VDD
B21 VDD D15 VDD
B22 GND D16 GPIO31/TIMER3/SCL
C2 GND D17 GPIO29/CHIP_ID3/ETHTX_EN
C3 VDD D18 VDDH
C4 TDO D19 GPIO4/TDM3TCLK/IRQ2/ETHTX_ER
C5 SRESET D20 VDDH
C6 GPIO28/UTXD/DREQ2 D21 GND
C7 HCID1 D22 GPIO8/TDM3RDAT/IRQ6/ETHCOL
C8 GND E2 TCK
C9 VDD E3 TRST
C10 GND E4 TMS
C11 VDD E5 HRESET
C12 GND E6 GPIO27/URXD/DREQ1
C13 VDD E7 HCID0
C14 GND E8 GND
C15 GND E9 VDD
C16 GPIO30/TIMER2/TMCLK/SDA E10 GND
C17 GPIO2/TIMER1/CHIP_ID2/IRQ6 E11 VDD
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor8
E12 GND G6 HA17
E13 VDD G7 PWE0/PSDDQM0/PBS0
E14 GND G8 VDD
E15 GND G9 VDD
E16 VDD G10 IRQ3/BADDR31
E17 GND G11 BM0/TC0/BNKSEL0
E18 GND G12 ABB/IRQ4
E19 GPIO9/TDM2TSYN/IRQ7/ETHMDIO G13 VDD
E20 GPIO13/TDM2RCLK/IRQ11/ETHMDC G14 IRQ7/INT_OUT
E21 GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC G15 ETHCRS/ETHRXD
E22 GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC G16 VDD
F2 PORESET G17 CS1
F3 RSTCONF G18 BCTL0
F4 NMI G19 GPIO15/TDM1TSYN/DREQ1
F5 HA29 G20 GND
F6 HA22 G21 GPIO17/TDM1TDAT/DACK1
F7 GND G22 GPIO22/TDM0TCLK/DONE2/DRACK2
F8 VDD H2 HA20
F9 VDD H3 HA28
F10 VDD H4 VDD
F11 GND H5 HA19
F12 VDD H6 TEST
F13 GND H7 PSDCAS/PGPL3
F14 VDD H8 PGTA/PUPMWAIT/PGPL4/PPBS
F15 ETHRX_CLK/ETHSYNC_IN H9 VDD
F16 ETHTX_CLK/ETHREF_CLK/ETHCLOCK H10 BM1/TC1/BNKSEL1
F17 GPIO20/TDM1RDAT H11 ARTRY
F18 GPIO18/TDM1RSYN/DREQ2 H12 AACK
F19 GPIO16/TDM1TCLK/DONE1/DRACK1 H13 DBB/IRQ5
F20 GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD H14 HTA
F21 GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC H15 VDD
F22 GPIO19/TDM1RCLK/DACK2 H16 TT4/CS7
G2 HA24 H17 CS4
G3 HA27 H18 GPIO24/TDM0RSYN/IRQ14
G4 HA25 H19 GPIO21/TDM0TSYN
G5 HA23 H20 VDD
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name
Pin Assignments
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 9
H21 VDDH K15 VDD
H22 A31 K16 TT2/CS5
J2 HA18 K17 ALE
J3 HA26 K18 CS2
J4 VDD K19 GND
J5 HA13 K20 A26
J6 GND K21 A29
J7 PSDAMUX/PGPL5 K22 A28
J8 BADDR27 L2 HA12
J9 VDD L3 HA14
J10 CLKIN L4 HA11
J11 BM2/TC2/BNKSEL2 L5 VDDH
J12 DBG L6 VDDH
J13 VDD L7 BADDR28
J14 GND L8 IRQ5/BADDR29
J15 VDD L9 GND
J16 TT3/CS6 L10 GND
J17 PSDA10/PGPL0 L14 GND
J18 BCTL1/CS5 L15 VDDH
J19 GPIO23/TDM0TDAT/IRQ13 L16 GND
J20 GND L17 GND
J21 GPIO25/TDM0RCLK/IRQ15 L18 CS3
J22 A30 L19 VDDH
K2 HA15 L20 A27
K3 HA21 L21 A25
K4 HA16 L22 A22
K5 PWE3/PSDDQM3/PBS3 M2 HD28
K6 PWE1/PSDDQM1/PBS1 M3 HD31
K7 POE/PSDRAS/PGPL2 M4 VDDH
K8 IRQ2/BADDR30 M5 GND
K9 Reserved M6 GND
K10 GND M7 GND
K11 GND M8 VDD
K12 GND M9 VDDH
K13 GND M10 GND
K14 CLKOUT M14 GND
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor10
M15 VDDH P12 VCCSYN
M16 HBRST P13 GND
M17 VDDH P14 GND
M18 VDDH P15 TA
M19 GND P16 BR
M20 VDDH P17 TEA
M21 A24 P18 PSDVAL
M22 A21 P19 DP0/DREQ1/EXT_BR2
N2 HD26 P20 VDDH
N3 HD30 P21 GND
N4 HD29 P22 A19
N5 HD24 R2 HD18
N6 PWE2/PSDDQM2/PBS2 R3 VDDH
N7 VDDH R4 GND
N8 HWBS0/HDBS0/HWBE0/HDBE0 R5 HD22
N9 HBCS R6 HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6
N10 GND R7 HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4
N14 GND R8 TSZ1
N15 HRDS/HRW/HRDE R9 TSZ3
N16 BG R10 IRQ1/GBL
N17 HCS R11 VDD
N18 CS0 R12 VDD
N19 PSDWE/PGPL1 R13 VDD
N20 GPIO26/TDM0RDAT R14 TT0/HA7
N21 A23 R15 IRQ7/DP7/DREQ4
N22 A20 R16 IRQ6/DP6/DREQ3
P2 HD20 R17 IRQ3/DP3/DREQ2/EXT_BR3
P3 HD27 R18 TS
P4 HD25 R19 IRQ2/DP2/DACK2/EXT_DBG2
P5 HD23 R20 A17
P6 HWBS3/HDBS3/HWBE3/HDBE3 R21 A18
P7 HWBS2/HDBS2/HWBE2/HDBE2 R22 A16
P8 HWBS1/HDBS1/HWBE1/HDBE1 T2 HD17
P9 HCLKIN T3 HD21
P10 GND T4 HD1/DSISYNC
P11 GNDSYN T5 HD0/SWTE
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name
Pin Assignments
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 11
T6 HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7 U21 A12
T7 HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5 U22 A13
T8 TSZ0 V2 HD3/MODCK1
T9 TSZ2 V3 VDDH
T10 TBST V4 GND
T11 VDD V5 D0
T12 D16 V6 D1
T13 TT1 V7 D4
T14 D21 V8 D5
T15 D23 V9 D7
T16 IRQ5/DP5/DACK4/EXT_BG3 V10 D10
T17 IRQ4/DP4/DACK3/EXT_DBG3 V11 D12
T18 IRQ1/DP1/DACK1/EXT_BG2 V12 D13
T19 D30 V13 D18
T20 GND V14 D20
T21 A15 V15 GND
T22 A14 V16 D24
U2 HD16 V17 D27
U3 HD19 V18 D29
U4 HD2/DSI64 V19 A8
U5 D2 V20 A9
U6 D3 V21 A10
U7 D6 V22 A11
U8 D8 W2 HD6
U9 D9 W3 HD5/CNFGS
U10 D11 W4 HD4/MODCK2
U11 D14 W5 GND
U12 D15 W6 GND
U13 D17 W7 VDDH
U14 D19 W8 VDDH
U15 D22 W9 GND
U16 D25 W10 HDST1/HA10
U17 D26 W11 HDST0/HA9
U18 D28 W12 VDDH
U19 D31 W13 GND
U20 VDDH W14 HD40/D40/ETHRXD0
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Pin Assignments
Freesca le Sem ico nd uctor12
W15 VDDH AA9 VDDH
W16 HD33/D33/reserved AA10 HD54/D54/ETHTX_EN
W17 VDDH AA11 HD52/D52
W18 HD32/D32/reserved AA12 VDDH
W19 GND AA13 GND
W20 GND AA14 VDDH
W21 A7 AA15 HD46/D46/ETHTXT0
W22 A6 AA16 GND
Y2 HD7 AA17 HD42/D42/ETHRXD2/reserved
Y3 HD15 AA18 HD38/D38/reserved
Y4 VDDH AA19 HD35/D35/reserved
Y5 HD9 AA20 A0
Y6 VDD AA21 A2
Y7 HD60/D60/ETHCOL/reserved AA22 A3
Y8 HD58/D58/ETHMDC AB2 GND
Y9 GND AB3 HD13
Y10 VDDH AB4 HD11
Y11 HD51/D51 AB5 HD8
Y12 GND AB6 HD62/D62
Y13 VDDH AB7 HD61/D61
Y14 HD43/D43/ETHRXD3/reserved AB8 HD57/D57/ETHRX_ER
Y15 GND AB9 HD56/D56/ETHRX_DV/ETHCRS_DV
Y16 VDDH AB10 HD55/D55/ETHTX_ER/reserved
Y17 GND AB11 HD53/D53
Y18 HD37/D37/reserved AB12 HD50/D50
Y19 HD34/D34/reserved AB13 HD49/D49/ETHTXD3/reserved
Y20 VDDH AB14 HD48/D48/ETHTXD2/reserved
Y21 A4 AB15 HD47/D47/ETHTXD1
Y22 A5 AB16 HD45/D45
AA2 VDD AB17 HD44/D44
AA3 HD14 AB18 HD41/D41/ETHRXD1
AA4 HD12 AB19 HD39/D39/reserved
AA5 HD10 AB20 HD36/D36/reserved
AA6 HD63/D63 AB21 A1
AA7 HD59/D59/ETHMDIO AB22 VDD
AA8 GND
Table 1. MSC8122 Signal Listing by Ball Designator (continued)
Des. Signal Name Des. Signal Name
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 13
2 Electrica l Characteristics
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications. For additional information, see the MSC8122 Reference Manual.
2.1 Maximum Ratings
In calculat ing timi ng requir ements, adding a maximu m value o f one specification to a minimu m value of anoth er specification
does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values
in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.
Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that can never exist.
Table 2 describes the maximum electrical ratings for the MSC8 122.
CAUTION
This device contains circuitry protecting against damage
due to high static voltage or electrical fields; however,
normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (for
example, either GND or VDD).
Table 2. Absolute Maximum Ratings
Rating Symbol Value Unit
Core and PLL supply voltage VDD –0.2 to 1 .6 V
I/O supply voltage VDDH –0 .2 to 4 .0 V
Input voltage VIN –0.2 to 4 .0 V
Maximum operat ing temperature:
• Standard range
• Extended range
TJ90
105 °C
°C
Minimum operating temperature
• Standard range
• Extended range
TJ0
–40 °C
°C
Storage temperature range TSTG –55 to +150 °C
Notes: 1. Functional operating conditions are given in Table 3.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permane nt damage.
3. Section 3.5, Thermal Considerations includes a formula for computing the chip junction temperature (TJ).
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor14
2.2 Recommended Operating Conditions
Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
2.3 Thermal Characteristics
Table 4 describes thermal characteristics of the MSC8122 for the FC-PBGA packages.
Section 3.5, Thermal Considerations provides a detailed explanation of these characteristics.
Table 3. Recommended Operating Conditions
Rating Symbol Value Unit
Core and PLL supply voltage:
• Standard
— 400 MHz
— 500 MHz
• Reduced (300 and 400 MHz)
VDD
VCCSYN 1.14 to 1.26
1.16 to 1.24
1.07 to 1.13
V
V
V
I/O supply voltage VDDH 3.135 to 3.465 V
Input voltage VIN –0.2 to VDDH+0.2 V
Operating temperature range:
• Standard
• Extended TJ
TJ
0 to 90
–40 to 105 °C
°C
Table 4. Thermal Characteristics for the MSC8122
Characteristic Symbol
FC-PBGA
20 × 20 mm5Unit
Natural
Convection 200 ft/min
(1 m/s) airflow
Junction-to-ambient1, 2 RθJA 26 21 °C/W
Junction-to-ambient , four-layer board1, 3 RθJA 19 15 °C/W
Junction-to-board (bottom)4RθJB 9°C/W
Junction-to-case5RθJC 0.9 °C/W
Junction-to-package-top6ΨJT 1°C/W
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package therma l resistance, mount ing site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDE C JESD51-2 with the single layer board horizontal.
3. Per JEDEC JES D 51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 15
2.4 DC Electrical Characteristics
This sec tion desc ribes the DC elec trical c haracte ristics for the MSC8122. The meas urements i n Table 5 assume th e
following system conditions:
•T
A = 25 °C
•VDD =
— 300/400 MHz 1.1 V nominal = 1.07–1.13 VDC
— 400 MHz 1.2 V nominal = 1.14–1.26 VDC
— 500 MHz 1.2 V nominal = 1.16–1.24 VDC
•VDDH = 3.3 V ± 5% VDC
•GND = 0 VDC
Note: The leakage current is measured for nominal VDDH and VDD.
Table 5. DC Electrical Characteristics
Characteristic Symbol Min Typical Max Unit
Input high voltage1, all inputs except CLKIN VIH 2.0 — 3.465 V
Input low voltage1VIL GND 0 0.8 V
CLKIN input high voltage VIHC 2.4 3.0 3.465 V
CLKIN input low voltage VILC GND 0 0.8 V
Input leakage current, VIN = VDDH IIN –1.0 0.09 1 µA
Tri-state (high impedance off state) leakage current, VIN = VDDH IOZ –1.0 0.09 1 µA
Signal low input current, VIL = 0.8 V2IL–1.0 0.09 1 µA
Signal high input current, VIH = 2.0 V2IH–1.0 0.09 1 µA
Output high voltage, IOH = –2 mA,
except open drain pins VOH 2.0 3.0 — V
Output low voltage, IOL= 3.2 mA VOL —00.4V
VCCSYN PLL supply current IVCCSYN —2 4mA
Internal supply current:
• W ait mode
• Stop mode IDDW
IDDS
—
—3753
2903—
—mA
mA
Typical power 400 MHz at 1.2 V4P — 1.15 — W
Notes: 1. See Figure 5 for undershoot and overshoot voltages.
2. Not tested. Guaranteed by design.
3. Measured for 1.2 V core at 25°C junction temperature.
4. The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No
peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and
all four cores. It was created using CodeWarrior® 2.5. These values are provided as examples only. Power consum ption is
application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining
proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of
this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor16
2.5 AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems s uch as DSP farms are develop ed using the DSI, us e a device loading of 4 pF per pi n. AC timings are base d on a 20 pF
load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF do wn
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1 Output Buffer Impedances
2.5.2 Sta rt-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3
describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8122 device:
•PORESET and TRST must be asserted extern ally for the dur ation of th e power-up sequence. See Table 11 for timing.
• If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD
levels and then the VDDH levels (see Figure 7).
•CLKIN should start toggling at least 16 cycles (starting after VDDH reaches its nom inal level) before PORESET
deassertion to guarantee correct device operation (see Figur e 6 and Figure 7).
•CLKIN must not be pul l ed high during VDDH power-up. CLKIN can toggle during thi s period.
Note: See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power suppl y des ign
recommendations.
The following figures show acceptable start-up sequence examples. Fi gure 6 shows a sequence in which VDD and VDDH are
ra is ed tog e t h e r. Figure 7 shows a sequence in which VDDH is raised af ter VDD and CLKIN begins to toggle as VDDH rises.
Figure 5. Overshoot/Undershoot Voltage for VIH and VIL
Table 6. Output Buffer Impedances
Output Buffers Typical Impedance (Ω)
System bus 50
Memory cont roller 50
Parallel I/O 50
Note: These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
GND
GND – 0.3 V
GND – 0.7 V
VIL
VIH
Must not exceed 10% of clock period
VDDH + 17%
VDDH + 8%
VDDH
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 17
Figure 6. Start-Up Sequence: VDD and VDDH Raised Together
Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH
Voltage
Time
o.5 V
3.3 V
1.2 V
VDDH Nominal Level
PORESET/TRST Asserted
VDD Nominal Level
CLKIN S tarts Toggling
VDD/VDDH Applied
PORESET/TRST Deasserted
1
2.2 V
VDDH = Nominal Value
VDD = Nominal Value
Voltage
Time
o.5 V
3.3 V
1.2 V
VDDH Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied PORESET/TRST deasserted
1
VDDH applied
V
DDH
= Nominal
VDD = Nominal
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor18
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
The following rules apply:
1. During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level.
The duration of interval A should be kept below 10 ms.
2. The duration of tim ing interval B should be kept as small as possible and less than 10 ms.
2.5.3 Clock and Timing Signals
The following sections includ e a des cription o f clock sign al ch aracteristics. Table 7 sh ows the maximu m frequ ency value s for
internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum
frequency values are not exceeded.
Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN
Table 7. Maximum Frequencies
Characteristic Maximum in MHz
Core frequency 300/400/500
Reference frequency (REFCLK) 100/133/166
Internal bus frequency (BLCK) 100/133/166
DSI clock frequency (HCLKIN)
• Core frequency = 300 MHz
• Core frequency = 400/500 MHz HCLKIN ≤ (min{70 MHz, CLKOUT})
HCLKIN ≤ (min{100 MHz, CLKOUT})
External clock frequency (CLK IN or CLKOUT ) 100/133/166
Table 8. Clock Frequencies
Characteristics Symbol 300 MHz Device 400 MHz Device 500 MHz Device
Min Max Min Max Min Max
CLKIN frequency FCLKIN 20 100 20 133.3 20 166.7
BCLK frequency FBCLK 40 100 40 133.3 40 166.7
Reference clock (REFCLK) frequency FREFCLK 40 100 40 133.3 40 166.7
Output clock (CLKOUT) frequency FCLKOUT 40 100 40 133.3 40 166.7
SC140 core clock frequency FCORE 200 300 200 400 200 500
Note: The rise and fall time of external clocks should be 3 ns maximum
3.3 V
1.2 V
A
B
VDD/VCCSYN
VDDH (IO)
t (time
)
V
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 19
2.5.4 Reset Timing
The MSC8122 has several inputs to the reset logic:
• Power-on reset (PORESET)
• Exter nal ha rd reset (HRESET)
• External soft reset (SRESET)
• Software watchdog reset
• Bus monitor reset
• Host reset command through JTAG
All MSC8122 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.
Table 9. System Clock Parameters
Characteristic Min Max Unit
Phase jitter between BCLK and CLKIN — 0.3 ns
CLKIN frequency 20 see Table 8 MHz
CLKIN slope —3ns
CLKIN period jitter1— 150 ps
CLKIN jitter spectrum 150 — KHz
PLL input clock (after predivider) 20 100 MHz
PLL output frequency (VCO output)
• 300 MHz core
• 400 MHz core
• 500 MHz core
800 1200
1600
2000
MHz
MHz
MHz
MHz
CLKOUT frequency jitter1— 200 ps
CLKOUT phase jitter1 with CLKIN phase jitter of ±100 ps. — 500 ps
Notes: 1. Peak-to-peak.
2. Not tested. Guaranteed by design.
Table 10. Reset Sources
Name Direction Description
Power-on reset
(PORESET)Input Initiates the power-on reset flow that resets the MSC8122 and configures various attributes of the
MSC8122. On PORESET, the entire MSC8122 device is reset. SPLL states is reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64
bits port or a System Bus 64 bits port are configured only when PORESET is asserted.
External hard
reset (HRESET)Input/ Output Initiates the hard reset flow that configures various attributes of the MSC8122. While HRESET is
asserted, S RES ET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The
most configurable features are reconfigured. These features are defined in the 32-bit hard reset
configuration word described in Hard Reset Configuration Word section of the Reset chapter in the
MSC8122 Reference Manual.
External soft reset
(SRESET)Input/ Output Initiates the soft reset flow. The MSC 8122 detects an external assertion of SRESET only if it occurs
while the MSC8122 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the SC140 extended cores are reset, and system conf iguration is maintained.
Software
watchdog reset Internal When the MSC8122 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor reset Internal When the MSC8122 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
Host reset
command through
the TAP
Internal When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor20
Table 11 summarizes the reset actions that occur as a result of the different reset sources.
2.5.4.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
VDD and VDDH are both at their nominal levels.
2.5.4.2 Reset Configuration
The MSC8122 has two mechanis ms for wri ting the reset configuration:
• Through the direct slave interface (DSI)
• Through the system bus. When the reset configuratio n is written through the system bus, the MSC8122 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configur ation word is applied.
Fourteen signal levels (s ee Chapter 1 f or signal description det ails ) are sampled on PORESET deassertion to define the Reset
Configuration Mode and boot and operating cond itions:
•RSTCONF
•CNFGS
•DSISYNC
•DSI64
•CHIP_ID[0–3]
•BM[0–2]
•SWTE
•MODCK[1–2]
Table 11. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On
Reset
(PORESET)Hard Reset (HRESET) Soft Reset (SRESET)
External only External or Internal
(Software Watchdog or
Bus Monitor) External JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Section 2.5.4.1 for details).Yes NoNoNo
SPLL state reset Yes No No No
System reset configuration write through
the DSI Yes NoNoNo
System reset configuration write though
the system bus Yes Yes No No
HRESET driven Yes Yes No No
SIU registers reset Yes Yes No No
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
Yes Yes Yes Yes
SRESET driven Yes Yes Yes Depends on command
SC140 extended cores reset Yes Yes Yes Yes
MQBS reset Yes Yes Yes Yes
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 21
2.5.4.3 Reset Timing Tables
Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or
through the system bus.
Table 12. Timing for a Reset Configuration Write through the DSI or System Bus
No. Characteristics Expression Min Max Unit
1 Required external PORESET duration minimum
• C LKIN = 20 MHz
• C LKIN = 100 MHz (300 MHz core)
• C LKIN = 133 MHz (400 MHz core)
• C LKIN = 166 MHz (500 MHz core)
16/CLKIN 800
160
120
96
—
—
—
—
ns
ns
ns
ns
2 Delay from deassertion of external PORESET to deassertion of internal
PORESET
• CLKI N = 20 MHz to 166 MHz
1024/CLKIN
6.17 51.2 µs
3 Delay from de-assertion of internal PORESET to SPLL lock
• CLKI N = 20 MHz (RDF = 1)
• CLKI N = 100 MHz (RDF = 1) (300 MHz core)
• CLKI N = 133 MHz (RDF = 2) (400 MHz core)
• CLKI N = 166 MHz (RDF = 2) (500 MHz core)
6400/(CLKIN/RDF)
(PLL reference
clock-division factor) 320
64
96
77
320
64
96
77
µs
µs
µs
µs
5 Delay from SPLL to HRESET deassertion
• REFC LK = 40 MHz to 166 MHz 512/REFCLK 3.08 12.8 µs
6 Delay from SPLL lock to SRESET deassertion
• REFC LK = 40 MHz to 166 MHz 515/REFCLK 3.10 12.88 µs
7 Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64,
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
3—ns
8 Hold time from deassertion of PORESET to deassertion of RSTCONF,
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
5—ns
Note: Timings are not tested, but are guaranteed by design.
Figure 9. Timing Diagram for a Reset Configuration Write
PORESET
Internal
HRESET
Input
Output (I/O)
SRESET
Output (I/O)
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]
Host programs
Word
SPLL is locked
(no external indication)
PORESET
Reset Configuration
pins are sampled
1
2
MODCK[3–5]
1 + 2
3
5
6
SPLL
locking period
Reset configuration write
sequence during this
period.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor22
2.5.5 System Bus Access Timing
2.5.5.1 Core Data Transfers
General ly, all MSC8122 bus and sy st em ou t put si g nals are driven from the ri sing edge of the reference clock (R EFC LK ). The
REFCLK is the CLKIN signal. Memory control ler sig nals, how ever, trigger on four p oints within a REFCLK cycle. Each cycle
is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling
edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 13 show s.
Figure 10 is a graphical representation of Table 13.
Table 13. Tick Spacing for Memory Controller Signals
BCLK/SC140 clock Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
T2 T3 T4
1:4, 1:6, 1:8, 1:10 1/4 REFCLK 1/2 REFCLK 3/4 REFCLK
1:3 1/6 REFCLK 1/2 REFCLK 4/6 REFCLK
1:5 2/10 REFCLK 1/2 REFCLK 7/10 REFCLK
Figure 10. Internal Tick Spacing for Memory Controller Signals
REFCLK
T1 T2 T3 T4
REFCLK
T1 T2 T3 T4
for 1:3
for 1:5
REFCLK
T1 T2 T3 T4
for 1:4, 1:6, 1:8, 1:10
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 23
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.
The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge.
Table 14. AC Timing for SIU Inputs
No. Characteristic
Value for Bus Speed in MHz
Units
Ref = CLKIN Ref = CLKOUT
1.1 V 1.2 V 1.2 V 1.2 V
100/
133 133 166 133
10 Hold time for all signals after the 50% level of the REFCLK rising edge 0.5 0.5 0.5 0.5 ns
11a ARTRY/ABB set-up time before the 50% level of the REFCLK rising
edge 3.1 3.0 3.0 3.0 ns
11b DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK
rising edge 3.6 3.3 3.3 3.3 ns
11c AACK set-up time before the 50% level of the REFCLK rising edge 3.0 2.9 2.9 2.9 ns
11d TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK
rising edge
• Data-pipeline mode
• Non-pipeline mode 3.5
4.4 3.4
4.0 3.4
4.0 3.4
4.0 ns
ns
12 Data bus set-up time before REFCLK rising edge in Normal mode
• Data-pipeline mode
• Non-pipeline mode 1.9
4.2 1.8
4.0 1.7
4.0 1.8
4.0 ns
ns
131Data bus set-up time before the 50% level of the REFCLK rising edge
in ECC and PARITY modes
• Data-pipeline mode
• Non-pipeline mode 2.0
8.2 2.0
7.3 2.0
7.3 2.0
7.3 ns
ns
141DP set-up time before the 50% level of the REFCLK rising edge
• Data-pipeline mode
• Non-pipeline mode 2.0
7.9 2.0
6.1 2.0
6.1 2.0
6.1 ns
ns
15a TS and Address bus set-up time before the 50% level of the REFCLK
rising edge
• E xt ra cycle mode (S IUBCR[E XDD ] = 0)
• No extra cycle mode (SIUBCR[EXDD] = 1) 4.2
5.5 3.8
5.0 3.8
5.0 3.8
5.0 ns
ns
15b Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%
level of the REFCLK rising edge
• E xt ra cycle mode (S IUBCR[E XDD ] = 0)
• No extra cycle mode (SIUBCR[EXDD] = 1) 3.7
4.8 3.5
4.4 3.5
4.4 3.5
4.4 ns
ns
16 PUPMWAIT signal set-up time before the 50% level of the REFCLK
rising edge 3.7 3.7 3.7 3.7 ns
17 IRQx setup time before the 50% level; of the REFCLK rising edge34.0 4.0 4.0 4.0 ns
18 IRQx minimum pulse width36.0 +
TREFCLK
6.0 +
TREFCLK
6.0 +
TREFCLK
6.0 + TREFCLK ns
Notes: 1. Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
2. Values are measured from the 50% TTL transition level r elative to the 50% level of the REFCLK rising edge.
3. Guaranteed by design.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor24
Table 15. AC Timing for SIU Outputs
No. Characteristic
Value for Bus Speed in MHz3
Units
Ref = CLKIN Ref = CLKOUT
1.1 V 1.2 V 1.2 V 1.2 V
100/
133 133 166 100/133
302Minimum delay from the 50% level of the REFCLK for all signals 0.9 0.8 0.8 1.0 ns
31 PSDVAL/TEA/TA max delay from the 50% level of the REFCLK
rising edge 6.0 4.9 4.9 5.8 ns
32a Address bus max delay from the 50% level of the REFCLK rising
edge
• Multi-master mode (SIUBCR[EBM] = 1)
• Single-master mode (SIUBCR[EBM] = 0) 6.4
5.3 5.5
4.2 5.5
3.9 6.4
5.1 ns
ns
32b Address attributes: TT[0–1]/T BST/TSZ/GBL max delay from the 50%
level of the REFCLK rising edge 6.4 5.1 5.1 6.0 ns
32c Address attributes: TT[2–4]/TC max delay from the 50% level of the
REFCLK rising edge 6.9 5.7 5.7 6.6 ns
32d BADDR max delay from the 50% level of the REFCLK rising edge 5.2 4.2 4.2 5.1 ns
33a Data bus max delay from the 50% level of the REFCLK rising edge
• Data-pipeline mode
• Non-pipeline mode 4.8
7.1 3.9
6.1 3.7
6.1 4.8
7.0 ns
ns
33b DP max delay from the 50% level of the REFCLK rising edge
• Data-pipeline mode
• Non-pipeline mode 6.0
7.5 5.3
6.5 5.3
6.5 6.2
7.4 ns
ns
34 Memory controller signals/ALE/CS[0–4] max delay from the 50%
level of the REFCLK rising edge 5.1 4.2 3.9 5.1 ns
35a DBG/BG/BR/DBB max delay from the 50% level of the REFCLK
rising edge 6.0 4.7 4.7 5.6 ns
35b AACK/ABB/TS/CS[5–7] max delay from the 50% level of the
REFCLK rising edge 5.5 4.5 4.5 5.4 ns
Notes: 1. Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
2. Except for specification 30, which is specified for a 10 pF load, all timings in this table are specified for a 20 pF load.
Decreasing the load results in a timing decrease at the rate of 0.3 ns per 5 pF decrease in load. Increasing the load results in
a timing increase at the rate of 0.15 ns per 5 pF increase in load.
3. The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8122 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8122.
• To achieve maximum perf orm ance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 25
Figure 11. SIU Timing Diagram
REFCLK
AACK/ARTRY/TA/TEA/DBG/BG/BR
Data bus inputs—normal mode
PUPMWAIT input
PSDVAL/TEA/TA outputs
Address bus/TT[ 0–4]/TC [0–2]/T BS T/TSZ[0–3]/GBL outputs
Data bus outputs
Min delay for all output pins
11 10
10
10
12
15
31
32a/b
33a
30
DP outputs 33b
Memory controller/ALE outputs 34
Data bus inputs—ECC and parity modes
10
13
AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs 35
BADDR outputs 32c
DP inputs 14
Address bus/TS /TT[0–4]/TC[0–2]/
16
PSDVAL/ABB/DBB inputs
TBST/TSZ[0–3]/GBL inputs
18
17
IRQx inputs
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor26
2.5.5.2 CLKIN to CLKOUT Skew
Table 17 describes the CLKOUT-to-CLKIN skew timing.
For designs that us e the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing
values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings.
Table 16. CLKOUT Skew
No. Characteristic Min1Max1Units
20 Rise-to-rise skew
•V
DD = 1.1 V
•V
DD = 1.2 V 0.0
0.0 0.95
0.85 ns
ns
21 Fall-to-fall skew
•V
DD = 1.1 V
•V
DD = 1.2 V –1.5
–0.8 1.0
1.0 ns
ns
22 CLKOUT phase (1.2 V, 133 MHz)
• P hase high
• P hase low 2.8
2.8 —
—ns
ns
23 CLKOUT phase (1.1 V, 133 MHz)
• P hase high
• P hase low 2.2
2.2 —
—ns
ns
24 CLKOUT phase (1.1 V, 100 MHz)
• P hase high
• P hase low 3.3
3.3 —
—ns
ns
Notes: 1. A positive number indicates that CLKOUT precedes CLKI N, A negative number indicates that CLKOUT follows CLKIN.
2. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.
3. CLKOUT skews are measured using a load of 10 pF.
4. CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.
Figure 12. CLKOUT and CLKIN Signals.
CLKIN
CLKOUT
20 21
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 27
2.5.5.3 DMA Data Transfers
Table 17 describes the DMA signal timing.
The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ
according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction.
Table 17. DMA Signals
No. Characteristic Ref = CLKIN Ref = CLKOUT
(1.2 V only) Units
Min Max Min Max
37 DREQ set-up time before the 50% level of the falling edge of REFCLK 5.0 — 5.0 — ns
38 DREQ hold time after the 50% level of the falling edge of REFCLK 0.5 — 0.5 — ns
39 DONE set-up time before the 50% level of the rising edge of REFCLK 5.0 — 5.0 — ns
40 DONE hold time after the 50% level of the rising edge of REFCLK 0.5 — 0.5 — ns
41 DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge 0.5 7.5 0.5 8.4 ns
Figure 13. DMA Signals
REFCLK
DREQ
DONE
DACK/DONE/DRACK
37
38
40
39
41
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor28
2.5.6 DSI Timing
The timings in the following sections are based on a 20 pF capacitive load.
2.5.6.1 DSI Asynchronous Mode
Table 18. DSI Asynchronous Mode Timing
No. Characteristics Min Max Unit
100 Attributes1 set-up time before strobe (HWBS[n]) assertion 1.5 — ns
101 Attributes1 hold time after data strobe deassertion 1.3 — ns
102 Read/Write data strobe deassertion width:
• DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
• DCR[HTAAD] = 0
1.8 + TREFCLK
5 + TREFCLK
5 + (1.5 × TREFCLK)
5 + (2.5 × TREFCLK)
1.8 + TREFCLK
—
ns
ns
ns
ns
ns
103 Read data strobe deassertion to output data high impedance — 8.5 ns
104 Read data strobe assertion to output data active from high impedance 2.0 — ns
105 Output data hold time after read data strobe deassertion 2.2 — ns
106 Read/Write data strobe assertion to HTA active from high impedance 2.2 — ns
107 Output data valid to HTA assertion 3.2 — ns
108 Read/Write data strobe assertion to HTA valid2
•1.1 V core
•1.2 V core —
—7.4
6.7 ns
ns
109 Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0) —6.5ns
110 Read/Write data strobe deassertion to output HTA deasse rtion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1) —6.5ns
111 Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
• DCR[HTADT] = 01
• DCR[HTADT] = 10
• DCR[HTADT] = 11
—
5 + TREFCLK
5 + (1.5 × TREFCLK)
5 + (2.5 × TREFCLK)
ns
ns
ns
112 Read/Write data strobe assertion width 1.8 + TREFCLK —ns
201 Host data input set-up time before write data strobe deassertion 1.0 — ns
202 Host data input hold time after write data strobe deassertion
•1.1 V core
•1.2 V core 1.7
1.5 —
—ns
ns
Notes: 1. Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
3. All values listed in this table are tested or guaranteed by design.
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 29
Figure 14 shows DSI asynchronous read signals timing.
Figure 14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram
HDBSn1
HA[11–29]
HCS
HD[0–63]
102
100
105
101
103
104
109
108
106
HTA4
HCID[0–4]
HDST
HTA3
107
110
111
112
HRW1
HWBSn2
HRDS2
Notes: 1. Us ed for single-strobe mode access.
2. Used for dual-strobe mode access.
3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with
pull-down implementation.
4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up
implementation.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor30
Figure 15 shows DSI asynchronous write signals timing.
Figure 16 shows DSI asynchronous broadcast write signals timing.
Figure 15. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram
Figure 16. Asynchronous Broadcast Write Timing Diagram
HD[0–63]
100 101
102
201 202
109
106
HWBSn2
108 110
111
112
HDBSn1
HTA4
HTA3
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.
4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
HA[11–29]
HCS
HCID[0–4]
HDST
HRW1
HRDS2
HD[0–63]
100 101
102
201 202
HWBSn2
112
HDBSn1
Notes: 1. Used for single-strobe mode access.
2. Used for dual-strobe mode access.
HA[11–29]
HCS
HCID[0–4]
HDST
HRW1
HRDS2
Electrical Characteri stics
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 31
2.5.6.2 DSI Synchronous Mode
Table 19. DSI Inputs in Synchronous Mode
No. Characteristic Expression 1.1 V Core 1.2 V Core Units
Min Max Min Max
120 HCLKIN cycle time1,2 HTC 10.0 55.6 10.0 55.6 ns
121 HCLKIN high pulse width (0.5 ± 0.1) × HTC 4.0 33.3 4.0 33.3 ns
122 HCLKIN low pulse width (0.5 ± 0.1) × HTC 4.0 33.3 4.0 33.3 ns
123 HA[11–29] inputs set-up time — 1.2 — 1.2 — ns
124 HD[0–63] inputs set-up time — 0. 6 — 0. 4 — ns
125 HCID[0–4] inputs set-up time — 1.3 — 1.3 — ns
126 All other inputs set-up time — 1. 2 — 1.2 — ns
127 All inputs hold time — 1.5 — 1.5 — ns
Notes: 1. Values are based on a frequency range of 18–100 MHz.
2. Refer to Table 7 for HCLKIN frequency limi ts.
Table 20. DSI Outputs in Synchronous Mode
No. Characteristic 1.1 V Core 1.2 V Core Units
Min Max Min Max
128 HCLKIN high to HD[0–63] output active 2.0 — 2.0 — ns
129 HCLKIN high to HD[0–63] output valid — 7.6 — 6.3 ns
130 HD[0–63] output hold time 1.7 — 1.7 — ns
131 HCLKIN high to HD[0–63] output high impedance — 8.3 — 7.6 ns
132 HCLKIN high to HTA output active 2.2 — 2.0 — ns
133 HCLKIN high to HTA output valid — 7. 4 — 5. 9 ns
134 HTA output hold time 1.7 — 1.7 — ns
135 HCLKIN high to HTA high impedance — 7.5 — 6.3 ns
Figure 17. DSI Synchronous Mode Signals Timing Diagram
HCLKIN
HA[11–29] input signals
All other input s i gnals
HD[0–63] output signals
HTA output signal
~
~
HD[0–63] input signals
120
127
123
126 127
122
121
131
130
129
128
133 135
134
132
~
~
~
~
HCID[0–4] input signals
125 127
127
124
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freesca le Sem ico nd uctor32
2.5.7 TDM Timing
Table 21. TDM Timing
No. Characteristic Expression 1.1 V Core 1.2 V Core Units
Min Max Min Max
300 TDMxRCLK/TDMxTCLK TC116 — 16 — ns
301 TDMxRCLK/TDMxTCLK high pulse width (0.5 ± 0.1) × TC7—7—ns
302 TDMxRCLK/TDMxTCLK low pulse width (0.5 ± 0.1) × TC7—7—ns
303 TDM receive all input set-up time 1.3 — 1.3 — ns
304 TDM receive all input hold time 1.0 — 1.0 — ns
305 TDMxTCLK high to TDMxTDAT/TDMxRCLK output
active2,3 2.8 — 2.8 — ns
306 TDMxTCLK high to TDMxTDAT/TDMxRCLK output — 10.0 — 8.8 ns
307 All output hold time42.5 — 2.5 — ns
308 TDMxTCLK high to TDmXTDAT/TDMxRCLK output high
impedance2,3 — 10.7 — 10.5 ns
309 TDMxTCLK high to TDMXTSYN output valid2—9.7—8.5ns
310 TDMxTSYN output hold time42.5 — 2.5 — ns
Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.
Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz.
2. Values are based on 20 pF capacitive load.
3. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8122 Reference Manual for details.
4. Values are based on 10 pF capacitive load.
Figure 18. TDM Inputs Signals
Figure 19. TDM Output Signals
TDMxRCLK
TDMxRDAT
TDMxRSYN
300
301 302
303
303 304
304
TDMxTCLK
TDMxTDAT
~
~
TDMxTSYN
~
~
305
306 308
307
300
301 302
310
309
TDMxRCLK
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 33
2.5.8 UART Timing
Table 22. UART Timing
No. Characteristics Expression Min Max Unit
400 URXD and UTXD inputs high/low duration 16 × TREFCLK 160.0 — ns
401 URXD and UTXD inputs rise/fall time 10 ns
402 UTXD output rise/fall time 10 ns
Figure 20. UART Input Timing
Figure 21. UART Output Timing
UTXD, URXD
400
inputs
400
401 401
UTXD output
402 402
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freesca le Sem ico nd uctor34
2.5.9 Timer Timing
2.5.10 Ethernet Timing
2.5.10.1 Management Interface Timing
Ta bl e 23. Ti mer Tim in g
No. Characteristics Ref = CLKIN Unit
Min Max
500 TIMERx frequen cy 10.0 — ns
501 TIMERx Input high period 4.0 — ns
502 TIMERx Output low period 4.0 — ns
503 TIMERx Propagations delay from its clock input
•1.1 V core
•1.2 V core 3.1
2.8 9.5
8.1 ns
ns
Figure 22. Timer Timing
Table 24. Ethernet Controller Management Interface Timing
No. Characteristics Min Max Unit
801 ETHMDIO to ETHMDC rising edge set-up time 10 — ns
802 ETHMDC rising edge to ETHMDIO hold time 10 — ns
Figure 23. MDIO Timing Relationship to MDC
500
502
501
TIMERx (Input)
TIMERx (Output)
503
Valid
ETHMDC
ETHMDIO
802
801
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 35
2.5.10.2 MII Mode Timing
2.5.10. 3 RMII Mode
Table 25. MII Mode Signal Timing
No. Characteristics Min Max Unit
803 ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time 3.5 — ns
804 ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3] , ETHRX_E R hold time 3.5 — ns
805 ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay
•1.1 V core
•1.2 V core 1
114.6
12.6 ns
ns
Figure 24. MII Mode Signal T iming
Table 26. RMII Mode Signal Timing
No. Characteristics 1.1 V Core 1.2 V Core Unit
Min Max Min Max
806 ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising
edge set-up time 1.6 — 2 — ns
807 ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold
time 1.6 — 1.6 — ns
811 ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay. 3 12. 5 3 11 ns
Figure 25. RMII Mode Signal T iming
Valid
ETHRX_CLK
ETHRX_DV
ETHRXD[0–3]
ETHTX_CLK
ETHRX_ER
ETHTX_EN
ETHTXD[0–3] Valid Valid
ETHTX_ER
803 804
805
Valid
ETHREF_CLK
ETHCRS_DV
ETHRXD[0–1]
ETHRX_ER
807
806
ETHTX_EN
ETHTXD[0–1] Valid Valid
811
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freesca le Sem ico nd uctor36
2.5.10.4 SMII Mode
2.5.11 GPIO Timing
Table 27. SMII Mode Signal Timing
No. Characteristics Min Max Unit
808 ETHSYNC_IN , ETHRXD to ETHCL OCK rising edge set-up time 1.0 — ns
809 ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time 1.0 — ns
810 ETHCLOCK rising edge to ETHSYN C, ETHT XD output delay
• 1.1 V core.
• 1.2 V core. 1.51
1.516.02
5.02ns
ns
Notes: 1. Measured using a 5 pF load.
2. Measured using a 15 pF load.
Figure 26. SMII Mode Signal Timing
Table 28. GPIO Timing
No. Characteristics Ref = CLKIN Ref = CLKOUT
(1.2 V only) Unit
Min Max Min Max
601 REFCLK edge to GPIO out valid (GPIO out delay time) — 6.1 — 6.9 ns
602 REFCLK edge to GPIO out not valid (GPIO out hold time) 1.1 — 1.3 — ns
603 REFCLK edge to high impedance on GPIO out — 5.4 — 6.2 ns
604 GPIO in valid to REFCLK edge (GPIO in set-up time) 3 .5 — 3.7 — ns
605 REFCLK edge to GPIO in not valid (GPIO in hold time) 0.5 — 0.5 — ns
Valid
ETHCLOCK
ETHSYNC_IN
ETHRXD
ETHSYNC
ETHTXD Valid Valid
810
809808
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 37
2.5.12 EE Signals
Figure 28 shows the signal behavior of the EE pins.
2.5.13 JTAG Signals
Figure 27. GPIO Timing
Table 29. EE Pin Timing
Number Characteristics Type Min
65 EE0 (input) Asynchronous 4 core clock periods
66 EE1 (output) Synchronous to Core clock 1 core clock period
Notes: 1. T he core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.
Figure 28. EE Pin Timing
Table 30. JTAG Timing
No. Characteristics All
frequencies Unit
Min Max
700 TCK frequency of operation (1/(TC × 4); maximum 25 MHz) 0.0 25 MHz
701 TCK cycle time 40.0 — ns
702 TCK clock pulse width measured at VM = 1.6 V
•High
•Low 20.0
16.0 —
—ns
ns
703 TCK rise and fall times 0.0 3.0 ns
REFCLK
GPIO
(Output)
GPIO
(Input) Valid
603
High Impedance
604 605
602
60
1
EE1 out
EE0 in 65
66
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freesca le Sem ico nd uctor38
704 Boundary scan input data set-up time 5.0 — ns
705 Boundary scan input data hold time 20.0 — ns
706 TCK low to output data valid 0.0 30.0 ns
707 TCK low to output high impedance 0.0 30.0 ns
708 TMS, TDI data set-up time 5.0 — ns
709 TMS, TDI data hold time 20.0 — ns
710 TCK low to TDO data valid 0.0 20.0 ns
711 TCK low to TDO high impedance 0.0 20.0 ns
712 TRST assert time 100.0 — ns
713 TRST set-up time to TCK low 30.0 — ns
Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
Figure 29. Test Clock Input Timing Diagram
Figure 30. Boundary Scan (JTAG) Timing Diagra m
Table 30. JTAG Timing (continued)
No. Characteristics All
frequencies Unit
Min Max
TCK
(Input)
VMVM
VIH VIL
701
702
703703
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
VIH
VIL
Input Data Valid
Output Data Valid
705704
706
707
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 39
3 Hardware Design Considerations
The following sections discuss areas to consider when the MSC8122 device is designed into a system.
3.1 Start-up Sequencing Recommendations
Use the following guidelines for start-up and power-down sequences:
•Assert
PORESET and TRST before applying power and keep the signals driven low until the power reaches the
required minimum power levels. This can be implemented via weak pull-down resistors.
•CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must
start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels.
• If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up
VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both
voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and
then VDD/VCCSYN.
Note: This recommended power sequencing for the MSC8122 is different from the MSC8102. See Section 2.5.2 for
start-up timing specifications.
External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during
power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes.
This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the
system during start-up.
During the power-up sequence, if VDD rises before VDDH (see Figure 6), current can pass from the VDD supply th rough the
device ESD protection circuits to the VDDH supply . The ESD pr otection diode can allow this to occur when VDD exceeds VDDH
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
Figure 31. Test Access Port Timing Diagram
Figure 32. TRST Timing Diagram
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
VIH
VIL
Input Data Valid
Output Data Valid
TMS
708 709
710
711
TCK
(Input)
TRST
(Input)
713
712
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Hardware Design Considerations
Freesca le Sem ico nd uctor40
• Never allow VDD to exceed VDDH + 0.8V.
• Design the VDDH supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the
current. Such a design yields an initial VDDH level of VDD – 0.8 V before i t is en able d.
After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V.
3.2 Power Supply Design Considerations
When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines
described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8122 Design Checklist (AN3374
for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937)
provides detailed design information. See Section 2.5.2 for start-up timing specifications.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupl ing capacitors sh ould suppl y the requi red device current without any drop in vol tage on the device pins. The voltage o n
the package pins should not drop below the minimum specifi ed voltage level even for a very short spikes. Th is can be achieved
by using the following guidelines:
• For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw , but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than su pplies with lower current ratings.
• Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number . If possible, mount
at least one of the capacitors directly below the MSC8122 device.
Each VCC and VDD pin on the MSC8122 device should have a low-impedance path to the board power supply. Similarly, each
GND pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the
chip. The VCC power sup ply s hou ld hav e at leas t fou r 0.1 µF by-pass capacitors to gro und located as closely as possible to the
four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should
be kept to less than half an inch per capacitor lead. A four- layer board is recommended , employing two inner lay ers as VCC and
GND planes.
All output pins on the MSC8122 have fast rise and fall times. PCB trace interconnection length should be minimized to
minimi ze undershoot and reflection s caused by thes e fast outpu t switch ing times. Thi s recomm endation particul arly applies to
the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in
synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.
Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to
proper PCB layout and bypassing becomes especially critical in systems with high er capacitive loads because thes e loads create
higher transient currents in the VCC, VDD, and GND circuits. Pu ll up all unused inp uts or signals that w ill be inputs dur ing reset.
Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:
VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input wi th a circui t similar to the one in
Figure 33. Core Power Supply Decoupling
+
-
Power supply
or
Voltage Regulator
High frequency capacitors
(very low ESR and ESL)
Bulk/Tantalum capacitors
with low ESR and ESL
MSC8122
Maximum IR drop
of 15 mV at 1 A
Note: Use at least three capacitors.
Lmax = 2 cm
One 0.01 µF capacitor
for every 3 core supply
(Imin = 3 A)
pads.
1.2 V
Each capacitor must be at least 150 μF.
Hardware Design Considerations
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 41
Figur e 34. For optimal noise filtering, pl ace the circuit as close as possible to VCCSYN. The 0.01-µF capacitor should be closest
to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be
kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN
by a 0.01-µF capacitor located as close as possible to the chip package. For best results, pl ace this capacitor on the backside of
the PCB aligned with the depopulated void on the MSC8122 located in the square defined by positions, L11, L12, L13, M11,
M12, M13, N11, N12, and N13.
3.3 Connectivity Guidelines
Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to
VDDH or GND, except for the following:
• If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be
disconnected.
• When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either
up or down, depending on design requirements.
•HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the
DCR[DSRFA] bit is set.
• When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/
HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].
• When the DSI is in 32 -bit d ata bu s mode and D CR[BEM] i s cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3]
must be pulled up.
• When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.
• When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be
connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the
DSI expects full address mode (DC R[SLDWA] = 0). The DCR ad dres s in t he DS I memo ry m ap i s 0x1 BE0 00, which
requires the following connections:
— HA11 must be pulled high (1)
— HA12 must be pulle d high (1)
— HA13 must be pulled low (0)
• The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.
• In single-maste r mod e (BCR[EBM] = 0) with internal arbitration (PPC_A CR[E ARB] = 0):
—BG, DBG, and TS can be left unconnected.
—EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus
functionality. For any other fu nctionality, connect the signa l lines based on the multiplexed func tionality.
—BR must be pulled up.
—EXT_BR[2–3] must be pulled up if multiplexed to the system bus funct ionality.
• If there is an external bus master (BCR[EBM] = 1):
—BR, BG, DBG, and TS must be pulled up.
—EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus
functionality.
• In si ng le -m as ter mo d e, ABB and DBB can be selected as IRQ input s and be connected to the non-acti ve valu e. In other
modes, they must be pulled up.
Figure 34. VCCSYN Bypass
V
DD
0.01 µF
10 µF
V
CCSYN
10Ω10nH
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Hardware Design Considerations
Freesca le Sem ico nd uctor42
Note: The MSC8122 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is
disabled (that is, the DLLD IS bit in the Hard Reset Configuration Word is set).
• If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the
available clock modes.
•In the CLKIN synchronization mode, use the following connections:
— Connect the oscillator output through a buffer to CLKIN.
— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path
between the clock buffer to the MSC8122 and the SDRAM is equal (that is, has a skew less than 100 ps).
— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.
•In
CLKOUT synchronization mode (for 1.2 V devices), CLKOUT is the main clock to SDRAM. Use the follo wing
connections:
— Connect the oscillator output through a buffer to CLKIN.
— Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the following
guidelines:
– The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.
– The maximum load on CLKOUT must not exceed 10 pF.
– Use a zero-delay buffer with a jitter less than 0.3 ns.
— All clock modes are valid in this clock scheme.
Note: See the Clock chapter in the MSC8122 Ref erence Manual fo r details.
• I f the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it
should be pulled up.
• The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are
used to configure the MSC8122 and are sampled on the deassertion of the PORESET signal. Therefore, they should
be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal.
• When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must
be pulled up.
• When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected
externally to any signal line.
Note: For details on configuration, s e e the MSC8122 User’s Guide and MSC8122 Reference Manual. For additional
information, refer to the MSC8122 Design Checklist (AN2787).
3.4 External SDRAM Selection
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of
differ ences in timing characteristics amo ng various SDRAM manufactur ers, you may have use a faster speed rated SDRAM to
assure efficient data transfer across the bus. For example, for 166 MHz operation, you may have to use 183 or 200 MHz
SDRAM. Always perform a detailed timing analysis using the MSC8122 bus timing values and the manufacturer specifications
for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is
usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by
the SDRAM manufacturer.
Ordering Information
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 43
3.5 Thermal Consid erations
An estimation of the chip-junctio n temp erat ure, TJ, in °C can be obtained from the f oll owing:
TJ = TA + (RθJA × PD)Eqn. 1
where
TA = ambient temperature near the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = PINT + PI/O = power dissipation in the package (W)
PINT = IDD × VDD = internal power dissip ation (W)
PI/O = power dissipated from device on output pins (W)
The power dissipation values for the MSC8 122 are listed in Table 2-3. The ambient temperature for the device is the air
temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC
standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the
value determined on a single layer board and the value obtained on a board with two planes. The value that more closely
approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB).
The value ob tained us ing a s ingle layer board is approp riate fo r tightly p acked PCB con figurations. Th e va lue obtai ned us ing a
board with internal planes is more approp ri ate for boards with low power dissipation (less th an 0.02 W/cm2 with natural
convection) and well separated components. Based on an estimation of junction temperature using this technique, determine
whether a more detailed thermal analysis is required. Standard thermal manageme nt techniques can be used to maintain th e
device thermal junction temperature below its maximum. If TJ appears to b e too high , either lower the ambient temperature or
the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small
diameter thermocouple (40 gauge is recommended) or an infr ared temperature sensor on a spot on the device c ase that is painted
black. The MSC8122 device case surfac e is too shiny (low emissivity) to yield an accurate infrared temp erature meas ur ement.
Use the following equation to determine TJ:
TJ = TT + (θJA × PD)Eqn. 2
where
TT = thermocouple (or infrared) temperature on top of the package (°C)
θJA = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D).
4 Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Part Package Type Core
Voltage Operating
Temperature
Core
Frequency
(MHz)
Order Number
Lead-Free Lead-Bearing
MSC8122 Flip Chip Plastic Ball Grid Array (FC-PBGA) 1.1 V –40° to 105°C 300 MSC8122TVT4800V MSC8122TMP4800V
400 MSC8122TVT6400V MSC8122TMP6400V
1.2 V –40° to 105°C 400 MSC8122TVT6400 MSC8122TMP6400
0° to 90°C 500 MSC8122VT8000 MSC8122MP8000
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Package Information
Freesca le Sem ico nd uctor44
5 Package Information
6 Product Documentation
•MSC8122 Tech nical Data S heet (MSC8122) . Details the signals, AC/DC characteristics, clock sign al characteristics,
package and pinout, and electrical design considerations of the MSC8122 device.
•MSC8122 Reference Manual (MSC8122RM). In cludes functional descriptions of the extended cores and all the
internal subsystems including configuration and programming information.
•Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8122 device.
•SC140 DSP Core Reference Manual. Covers the SC140 core architecture, control registers, clock registers, program
control, and in struction set.
Figure 35. MSC8122 Mechanical Information, 431-pin FC-PBGA Package
Notes:
1. All dimensions in mi llimete rs.
2. Dimensioning and tolerancing
per ASME Y14.5M–1994.
3. Features are symmetrical abou
t
the packa ge center li nes unless
dimensioned otherwise.
4. Maximum solder ball diameter
measured parallel to Datum A.
5. Datum A, the seating plane, is
determined by the spherical
crowns of the solder balls.
6. Parallelism measurement shall
exclude any effect of mark on
top surface of package.
7. Capacitors may not be present
on all devices.
8. Caution must be taken not to
short capacitors or exposed
metal capacitor pads on
package top.
9. FC CBGA (Ceramic) package
code: 5238.
FC PBGA (Plastic) package
code: 5263.
10.Pin 1 indicator can be in the
form of number 1 mar king or an
“L” shape marking.
Revision History
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 45
7 Revision History
Table 31 provides a revision history for this data sheet.
Table 31. Document Revision History
Revision Date Description
0 May 2004 • Initial release.
1 Jun. 2004 • Updated timing number 32b.
• Updated DSI timin g specifications.
2 Sep 2004 • New orderable parts added with other core voltage and temperature options.
• Updated thermal characteristics.
• In Table 2-14, removed ref erences to 30 pF.
• Des ign guideline s and la yout reco m mendations up da te d.
3 Nov. 2004 • Added 500 MHz core and 166 MHz bus speed options.
• Definitions of GPIO[27–28] updated.
• Bus, TDM, and GPIO timing updated. I2C timing changed to GPIO timing.
• GPIO[27–28] connections updated. MWBEn replaced with correct name HWBEn.
• Design guidelines update.
4 Jan. 2005 • Package type changed to FC-PBGA for all frequencies.
• Low-voltage 300 MHz power changed to 1.1 V.
•HRESET and SRESET definitions updated.
• Undershoot and overshoot values added for VDDH.
• RMII timing updated.
• Desig n guidelines upda ted and reorganized.
5 Apr. 2005 • Added 400 MHz, 1.1 V co re part.
• Temperature ran ge descriptions changed to standard and extended.
• CLKOUT timing specifications adde d.
• Device start-up guide lines added to desi gn considera tions and updated power supply guidelines.
• Ordering information updated.
6 May 2005 • Multiple AC timing specifications updated.
7 May 2005 • Multiple AC timing specifications updated.
8 Jul. 2005 • Multiple AC timing specifications updated.
9 Jul. 2005 • AC specification table layout modified.
10 Sep. 2005 • E THTX_EN type and TRST description updated.
• Package drawing updated.
• Clock specifications updated.
• Start-up sequ ence updated.
11 Oct 2005 •V
DDH + 10% chan g e d t o VDDH + 8% in Figure 2-1.
•V
DDH +20% changed to VDDH + 17% in Fi gure 2-1.
12 Apr 2006 • Reset timing updated to reflect actual values in Table 2-11.
13 Oct. 2006 • Added new timings 17 and 18 for IRQ set time and pu lse width in Table 2-13
14 Dec. 2007 • C onverted to new data sheet format.
• Added PLL supply curr e nt to Table 5 in Section 2.4.
• Modified Figure 5 in Section 2. 4 to make it clear that the time limits for undershoot referred to values
below –0.3 V and not GND.
• Added cross-references between Se ctions 2.5.2 and Section 3.1 and 3.2.
• Added power-seq uence guidelines to Sect ions 2.5.2.
• Added CLKIN jitter ch aract eri s t i c specifications to Table 9.
• Added additional guidelines to prevent reverse current to Section 3.1.
• Added connectivity guidelines for DSI in sliding windows mode to Section 3.3.
15 May 2008 •Changed V
IL maximum and ref e rence value to 0.8 V in Table 5.
16 Dec. 2008 • Clarified the wording of note 2 in Table 15 on p. 2 4.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Revision History
Freesca le Sem ico nd uctor46
Revision History
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Freescale Semicond uc tor 47
Document Number: MSC8122
Rev. 16
12/2008
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