PRELIMINARY IDT71V2576 IDT71V2578 IDT71V3576 IDT71V3578 128K X 36, 256K X 18, 3.3V SYNCHRONOUS SRAMS WITH 2.5V I/O OPTION, PIPELINED OUTPUTS, BURST COUNTER, SINGLE CYCLE DESELECT FEATURES: DESCRIPTION: * 128K x 36, 256K x 18 memory configurations * Supports high system speed: - 200MHz 3.1ns clock access time - 183MHz 3.3ns clock access time - 166MHz 3.5ns clock access time - 150MHz 3.8ns clock access time - 133MHz 4.2ns clock access time * LBO input selects interleaved or linear burst mode GW * Self-timed write cycle with global write control (GW GW), byte write BWE BW enable (BWE BWE), and byte writes (BW BWx) * 3.3V core power supply * Power down controlled by ZZ input * 2.5V or 3.3V I/O option * Packaged in a JEDEC Standard 100-lead plastic thin quad flatpack (TQFP) and 119-lead ball grid array (BGA) The IDT71Vx576/578 are high-speed SRAMs organized as 128K x 36/ 256K x 18. The IDT71Vx576/578 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71Vx576/578 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71Vx576/578 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-lead thin plastic quad flatpack (TQFP) as well as a 119-lead ball grid array (BGA). PIN DESCRIPTION SUMMARY A0-A17 Ad d re ss Inp uts Inp ut Synchro no us CE Chip Enab le Inp ut Synchro no us CS0, CS1 Chip Se le cts Inp ut Synchro no us OE Outp ut Enab le Inp ut Asynchro no us GW Glo b al Write Enab le Inp ut Synchro no us BWE Byte Write Enab le Inp ut Synchro no us BW1, BW2, BW3, BW4(1) Ind ivid ual Byte Write Se le cts Inp ut Synchro no us CLK Clo ck Inp ut N/A ADV Burst Ad d re ss Ad vance Inp ut Synchro no us ADSC Ad d re ss Status (Cache Co ntro lle r) Inp ut Synchro no us ADSP Ad d re ss Status (Pro ce sso r) Inp ut Synchro no us LBO Line ar / Inte rle ave d Burst Ord e r Inp ut DC ZZ S le e p Mo d e Inp ut Asynchro no us I/O0-I/O31, I/OP1-I/OP4 Data Inp ut / Outp ut I/O Synchro no us VDD, VDDQ Co re Po we r, I/O Po we r Sup p ly N/A VSS Gro und Sup p ly N/A 4876 tb l 01 NOTE: 1. BW3 and BW4 are not applicable for the IDT71Vx578. APRIL 1999 1 1998 Integrated Device Technology, Inc. DSC-4876/2 IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE PIN DEFINITIONS (1) Symbol Pin Function I/O Active Description A0-A17 Ad d re ss Inp uts I N/A Synchro no us Ad d re ss inp uts. The ad d re ss re g iste r is trig g e re d b y a co mb inatio n o f the rising e d g e o f CLK and ADSC Lo w o r ADSP Lo w and CE Lo w. ADSC Ad d re ss Status (Cache Co ntro lle r) I LOW Synchro no us Ad d re ss Status fro m Cache Co ntro lle r. ADSC is an active LOW inp ut that is use d to lo ad the ad d re ss re g iste rs with ne w ad d re sse s. ADSP Ad d re ss Status (Pro ce sso r) I LOW Synchro no us Ad d re ss Status fro m Pro ce sso r. ADSP is an active LOW inp ut that is use d to lo ad the ad d re ss re g iste rs with ne w ad d re sse s. ADSP is g ate d b y CE. ADV Burst Ad d re ss Ad vance I LOW Synchro no us Ad d re ss Ad vance . ADV is an active LOW inp ut that is use d to ad vance the inte rnal b urst co unte r, co ntro lling b urst acce ss afte r the initial ad d re ss is lo ad e d . Whe n the inp ut is HIGH the b urst co unte r is no t incre me nte d ; that is, the re is no ad d re ss ad vance . BWE Byte Write Enab le I LOW Synchro no us b yte write e nab le g ate s the b yte write inp uts BW1-BW4. If BWE is LOW at the rising e d g e o f CLK the n BWx inp uts are p asse d to the ne xt stag e in the circuit. If BWE is HIGH the n the b yte write inp uts are b lo cke d and o nly GW can initiate a write cycle . BW1-BW4 Ind ivid ual Byte Write Enab le s I LOW Synchro no us b yte write e nab le s. BW1 co ntro ls I/O0-7, I/OP1, BW2 co ntro ls I/O8-15, I/OP2, e tc. Any active b yte write cause s all o utp uts to b e d isab le d . CE Chip Enab le I LOW Synchro no us chip e nab le . CE is use d with CS0 and CS1 to e nab le the IDT71Vx576/578. CE also g ate s ADSP. CLK Clo ck I N/A This is the clo ck inp ut. All timing re fe re nce s fo r the d e vice are mad e with re sp e ct to this inp ut. CS0 Chip Se le ct 0 I HIGH Synchro no us active HIGH chip se le ct. CS0 is use d with CE and CS1 to e nab le the chip . CS1 Chip Se le ct 1 I LOW Synchro no us active LOW chip se le ct. CS1 is use d with CE and CS0 to e nab le the chip . GW Glo b al Write Enab le I LOW Synchro no us g lo b al write e nab le . This inp ut will write all fo ur 9-b it d ata b yte s whe n LOW o n the rising e d g e o f CLK. GW sup e rse d e s ind ivid ual b yte write e nab le s. I/O0-I/O31 I/OP1-I/OP4 Data Inp ut/Outp ut I/O N/A Synchro no us d ata inp ut/o utp ut (I/O) p ins. Bo th the d ata inp ut p ath and d ata o utp ut p ath are re g iste re d and trig g e re d b y the rising e d g e o f CLK. LBO Line ar Burst Ord e r I LOW Asynchro no us b urst o rd e r se le ctio n inp ut. Whe n LBO is HIGH, the inte rle ave d b urst se q ue nce is se le cte d . Whe n LBO is LOW the Line ar b urst se q ue nce is se le cte d . LBO is a static inp ut and must no t chang e state while the d e vice is o p e rating . OE Outp ut Enab le I LOW Asynchro no us o utp ut e nab le . Whe n OE is LOW the d ata o utp ut d rive rs are e nab le d o n the I/O p ins if the chip is also se le cte d . Whe n OE is HIGH the I/O p ins are in a hig himp e d ance state . VDD Po we r Sup p ly N/A N/A 3.3V co re p o we r sup p ly. VDDQ Po we r Sup p ly N/A N/A 3.3V o r 2.5V I/O Sup p ly. VSS Gro und N/A N/A Gro und . NC No Co nne ct N/A N/A NC p ins are no t e le ctrically co nne cte d to the d e vice . ZZ S le e p Mo d e I HIGH Asynchro no us sle e p mo d e inp ut. ZZ HIGH will g ate the CLK inte rnally and p o we r d o wn the IDT71Vx576/78 to its lo we st p o we r co nsump tio n le ve l. Data re te ntio n is g uarante e d in S le e p Mo d e . 4876 tb l 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 2 1998 Integrated Device Technology, Inc. DSC-4876/2 COMMERCIAL TEMPERATURE RANGE IDT71Vx576/IDTVx578 FUNCTIONAL BLOCK DIAGRAM LBO ADV CLK 2 Binary Counter ADSC Burst Logic Q0 CLR# ADSP Q1 A0A16/17 GW BWE 17/18 A0* A1* 128K x 36/ 256K x 18BIT MEMORY ARRAY 2 CE# ADDRESS REGISTER INTERNAL ADDRESS Burst Sequence CE# A0,A1 A2A17 36/18 17/18 Byte 1 Write Register 36/18 Byte 1 Write Driver BW1 9 Byte 2 Write Register Byte 2 Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Write Register Byte 4 Write Driver BW4 9 OUTPUT REGISTER CE CS0 CS1 D Q Enable Register DATA INPUT REGISTER CE# ZZ Powerdown D Q Enable Delay Register OE OE I/O0 -- I/O31 I/OP1 -- I/OP4 OUTPUT BUFFER 36/18 4876 drw 01 3 1998 Integrated Device Technology, Inc. DSC-4876/2 IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Commercial Unit Te rminal Vo ltag e with Re s p e c t to GND -0.5 to +4.6 V VTERM (2) VTERM (3,6) Te rminal Vo ltag e with Re s p e c t to GND -0.5 to VDD V VTERM(4,6) Te rminal Vo ltag e with Re s p e c t to GND -0.5 to VDD +0.5 V VTERM(5,6) Te rminal Vo ltag e with Re s p e c t to GND -0.5 to VDDQ +0.5 V TA -0 to +70 o Te mp e rature Und e r Bias -55 to +125 o -55 to +125 o Sto rag e Te mp e rature TSTG C W IOUT DC Outp ut Curre nt 50 mA 0V 3.3V 5% 2.5V 5% Co mme rc ial 0 C to +70 C 0V 3.3V 5% VDD Parameter Min. Typ. Max. Unit VDD Co re Sup p ly Vo ltag e 3.135 3.3 3.465 V VDDQ I/O Sup p ly Vo ltag e 2.375 2.5 2.625 V VSS Sup p ly Vo ltag e 0 0 0 V 1.7 ____ VIH Inp ut Hig h Vo ltag e - I/O VIL Inp ut Lo w Vo ltag e Symbol Parameter 1.7 ____ VDDQ +0.3(1) -0.3(2) ____ 0.7 Unit VIN = 3d V 5 pF VOUT = 3d V 7 pF V 4876 tb l 05 Min. Typ. Max. Unit Co re Sup p ly Vo ltag e 3.135 3.3 3.465 V VDDQ I/O Sup p ly Vo ltag e 3.135 3.3 3.465 V VSS Sup p ly Vo ltag e 0 0 0 V 2.0 ____ Inp ut Hig h Vo ltag e - Inp uts Max. V VDD VIH Conditions V VDD +0.3 RECOMMENDED DC OPERATING CONDITIONS WITH VDDQ AT 3.3V (TA = +25C, f = 1.0MHz) I/O Cap ac itanc e 0 C to +70 C NOTES: 1. VIH (max) = V DDQ + 1.0V for pulse width less than tCYC/2 , once per cycle. 2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle. CAPACITANCE CI/O Co mme rc ial Inp ut Hig h Vo ltag e - Inp uts 4876 tb l 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supplies have ramped up. Power supply sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up. Inp ut Cap ac itanc e VDDQ VIH 1.25 CIN VDD Symbol C Po we r Dis s ip atio n Parameter(1) V SS RECOMMENDED DC OPERATING CONDITIONS WITH VDDQ AT 2.5V C PT Symbol Temperature 4876 tb l 04 Op e rating Te mp e rature TBIAS Grade VIH Inp ut Hig h Vo ltag e - I/O VIL Inp ut Lo w Vo ltag e V VDD +0.3 2.0 ____ VDDQ +0.3(1) V -0.3(2) ____ 0.8 V NOTES: 1. VIH (max) = V DDQ + 1.0V for pulse width less than tCYC/2 , once per cycle. 2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle. 4876 tb l 07 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 4876 tb l 06 4 1998 Integrated Device Technology, Inc. DSC-4876/2 COMMERCIAL TEMPERATURE RANGE IDT71Vx576/IDTVx578 BW3 BW2 BW1 CS 1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 A6 A7 CE CS0 BW4 PIN CONFIGURATION 128K x 36 TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 V DDQ V SS I/O18 I/O19 I/O20 I/O21 V SS V DDQ I/O22 I/O23 V DD(1) VDD NC V SS I/O24 I/O25 V DDQ V SS I/O26 I/O27 I/O28 I/O29 V SS V DDQ I/O30 I/O31 I/OP4 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 I/OP2 I/O15 I/O 14 V DDQ V SS I/O 13 I/O 12 I/O 11 I/O 10 V SS V DDQ I/O 9 I/O 8 V SS NC VDD ZZ I/O 7 I/O 6 V DDQ V SS I/O 5 I/O 4 I/O 3 I/O 2 V SS VDDQ I/O 1 I/O 0 I/OP1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A16 A10 A11 A12 A13 A14 A15 NC(2) NC(2) V SS V DD NC NC LBO A5 A4 A3 A2 A1 A0 4876 drw 02 TOP VIEW NOTES: 1. Pins 14 does not have to be directly connected to VDD as long as the input voltage is V IH. 2. Pins 38 and 39 can be either NC or connected to VSS. 5 1998 Integrated Device Technology, Inc. DSC-4876/2 IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE A8 A9 CS 0 NC NC BW2 BW1 CS 1 V DD V SS CLK GW BWE OE ADSC ADSP ADV A6 A7 CE PIN CONFIGURATION 256K x 18 TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC 1 80 2 79 3 V DDQ VSS NC NC I/O8 I/O9 VSS V DDQ I/O10 I/O11 VDD(1) VDD NC VSS I/O12 I/O13 V DDQ VSS I/O14 I/O15 I/OP2 NC VSS V DDQ NC NC NC 4 78 77 5 6 76 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 64 17 18 19 63 62 20 61 21 60 22 59 23 24 58 57 25 56 26 55 27 54 53 28 29 52 51 30 A10 NC NC V DDQ V SS NC I/OP1 I/O7 I/O6 V SS V DDQ I/O5 I/O4 V SS NC VDD ZZ I/O 3 I/O 2 V DDQ V SS I/O1 I/O0 NC NC V SS V DDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A 17 NC(2) V SS V DD NC NC A 11 A 12 A 13 A 14 A 15 A 16 LBO A5 A4 A3 A2 A1 A0 NC(2) 4876 drw 03 TOP VIEW NOTES: 1. Pins 14 does not have to be directly connected to VDD as long as the input voltage is VIH. 2. Pins 38 and 39 can be either NC or connected to VSS. 6 1998 Integrated Device Technology, Inc. DSC-4876/2 COMMERCIAL TEMPERATURE RANGE IDT71Vx576/IDTVx578 PIN CONFIGURATION 128K x 36 BGA (1,2) 1 2 3 4 5 6 7 A VDDQ A6 A4 ADSP A8 A16 VDDQ B NC CS 0 A3 ADSC A9 CS1 NC C NC A7 A2 VDD A12 A15 NC D I/O16 I/OP3 VSS NC VSS I/OP2 I/O15 E I/O17 I/O18 VSS CE VSS I/O13 I/O14 F VDDQ I/O19 VSS OE VSS I/O12 VDDQ G I/O20 I/O21 BW3 ADV BW2 I/O11 I/O10 H I/O22 I/O23 VSS GW VSS I/O9 I/O8 J VDDQ VDD NC VDD NC VDD VDDQ K I/O24 I/O26 VSS CLK VSS I/O6 I/O7 L I/O25 I/O27 BW4 NC BW1 I/O4 I/O5 M VDDQ I/O28 VSS BWE VSS I/O3 VDDQ N I/O29 I/O30 VSS A1 VSS I/O2 I/O1 P I/O31 I/OP4 VSS A0 VSS I/O0 I/OP1 R NC A5 LBO VDD A13 NC T NC NC A10 A11 A14 NC ZZ U VDDQ NC NC NC NC NC VDDQ V DD 4876 drw 04 TOP VIEW PIN CONFIGURATION 256K x 18 BGA (1,2) A 1 2 3 4 5 6 7 VDDQ A6 A4 ADSP A8 A16 VDDQ B NC CS0 A3 ADSC A9 CS1 NC C NC A7 A2 VDD A13 A17 NC D I/O8 NC VSS NC VSS I/O7 NC E NC I/O9 VSS CE VSS NC I/O6 F VDDQ NC VSS OE VSS I/O5 VDDQ G NC I/O10 BW 2 ADV VSS NC I/O4 H I/O11 NC VSS GW VSS I/O3 NC J VDDQ VDD NC VDD NC VDD VDDQ K NC I/O12 VSS CLK VSS NC I/O2 L I/O13 NC VS S NC BW1 I/O1 NC M VDDQ I/O14 VSS BWE VSS NC VDDQ N I/O15 NC VSS A1 VSS I/O0 NC P NC I/OP2 VSS A0 VSS NC I/OP1 R NC A5 LBO VDD VDD A12 NC T NC A10 A15 NC A14 A11 ZZ U VDDQ NC NC NC NC NC VDDQ 4876 drw 05 TOP VIEW NOTES: 1. R5 does not have to be directly connected to VDD as long as the input voltage is VIH . 2. L4 and U4 can be either NC or connected to V SS. 7 1998 Integrated Device Technology, Inc. DSC-4876/2 IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VDD = 3.3V 5%) Symbol Parameter |ILI| Inp ut Le ak ag e Curre nt |ILZZ| ZZ and LBO Inp ut Le ak ag e Curre nt Test Conditions (1) |ILO| Outp ut Le ak ag e Curre nt Min. Max. Unit VDD = Max ., VIN = 0V to VDD ___ 5 A VDD = Max ., VIN = 0V to VDD ___ 30 A VOUT = 0V to VDDQ, De v ic e De s e le c te d ___ 5 A VOL(3.3V) Outp ut Lo w Vo ltag e IOL = +8mA, VDD = Min. ___ 0.4 V VOH(3.3V) Outp ut Hig h Vo ltag e IOH = -8mA, VDD = Min. 2.4 ___ V VOL(2.5V) Outp ut Lo w Vo ltag e IOL = +6mA, VDD = Min. ___ 0.4 V 2.0 ___ VOH(2.5V) Outp ut Hig h Vo ltag e IOH = -6mA, VDD = Min. V NOTE: 1. The LBO pin will be internally pulled to V DD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven. 4876 tb l 08 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) Symbol IDD Parameter Test Conditions 200MHz 183MHz 166MHz 150MHz 133MHz Unit De vice Se le cte d , Outp uts Op e n, VDD = Max., VIN > VIH o r < VIL, f = fMAX(2) 360 340 320 295 250 mA Op e rating Po we r Sup p ly Curre nt 20 CMOS Stand b y Po we r Sup p ly Curre nt De vice De se le cte d , Outp uts Op e n, VDD = Max., VIN > VHD o r < VLD, f = 0(2,3) 20 20 20 20 20 mA 130 Clo ck Running Po we r Sup p ly Curre nt De vice De se le cte d , Outp uts Op e n, VDD = Max., VIN > VHD o r < VLD, f = fMAX(2.3) 130 120 110 100 90 mA 20 Full Sle e p Mo d e Sup p ly Curre nt ZZ > VHD, VDD = Max. 20 20 20 20 20 mA NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V. AC TEST CONDITIONS 4876 tb l 09 AC TEST LOADS (VDDQ = 3.3V/2.5V) Inp ut Pulse Le ve ls VDDQ/2 0 to 3V / 0 to VDDQ 50 Inp ut Rise /Fall Time s 2ns I/O Inp ut Timing Re fe re nce Le ve ls 1.5V / (VDDQ/2) Outp ut Timing Re fe re nce Le ve ls 1.5V / (VDDQ/2) AC Te st Lo ad Z0 = 50 4876 drw 06 Figure 1. AC Test Load Se e Fig ure 1 6 4876 tb l 10 5 4 tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200 4876 drw 07 Figure 2. Lumped Capacitive Load, Typical Derating 8 1998 Integrated Device Technology, Inc. DSC-4876/2 COMMERCIAL TEMPERATURE RANGE IDT71Vx576/IDTVx578 SYNCHRONOUS TRUTH TABLE (1,3) Address Used CE CS0 CS1 ADSP ADSC ADV GW BWE BWx OE (2) CLK I/O De s e le c te d Cy c le , Po we r Do wn No ne H X X X L X X X X X - HI-Z De s e le c te d Cy c le , Po we r Do wn No ne L X H L X X X X X X - HI-Z De s e le c te d Cy c le , Po we r Do wn No ne L L X L X X X X X X - HI-Z De s e le c te d Cy c le , Po we r Do wn No ne L X H X L X X X X X - HI-Z De s e le c te d Cy c le , Po we r Do wn No ne L L X X L X X X X X - HI-Z Re ad Cy c le , Be g in Burs t Ex te rnal L H L L X X X X X L - DOUT Re ad Cy c le , Be g in Burs t Ex te rnal L H L L X X X X X H - HI-Z Re ad Cy c le , Be g in Burs t Ex te rnal L H L H L X H H X L - DOUT Re ad Cy c le , Be g in Burs t Ex te rnal L H L H L X H L H L - DOUT Re ad Cy c le , Be g in Burs t Ex te rnal L H L H L X H L H H - HI-Z Write Cy c le , Be g in Burs t Ex te rnal L H L H L X H L L X - DIN Write Cy c le , Be g in Burs t Ex te rnal L H L H L X L X X X - DIN Re ad Cy c le , Co ntinue Burs t Ne x t X X X H H L H H X L - DOUT Re ad Cy c le , Co ntinue Burs t Ne x t X X X H H L H H X H - HI-Z Re ad Cy c le , Co ntinue Burs t Ne x t X X X H H L H X H L - DOUT Re ad Cy c le , Co ntinue Burs t Ne x t X X X H H L H X H H - HI-Z Re ad Cy c le , Co ntinue Burs t Ne x t H X X X H L H H X L - DOUT Re ad Cy c le , Co ntinue Burs t Ne x t H X X X H L H H X H - HI-Z Re ad Cy c le , Co ntinue Burs t Ne x t H X X X H L H X H L - DOUT Re ad Cy c le , Co ntinue Burs t Ne x t H X X X H L H X H H - HI-Z Write Cy c le , Co ntinue Burs t Ne x t X X X H H L H L L X - DIN Write Cy c le , Co ntinue Burs t Ne x t X X X H H L L X X X - DIN Write Cy c le , Co ntinue Burs t Ne x t H X X X H L H L L X - DIN Write Cy c le , Co ntinue Burs t Ne x t H X X X H L L X X X - DIN Re ad Cy c le , Sus p e nd Burs t Curre nt X X X H H H H H X L - DOUT Re ad Cy c le , Sus p e nd Burs t Curre nt X X X H H H H H X H - HI-Z Re ad Cy c le , Sus p e nd Burs t Curre nt X X X H H H H X H L - DOUT Re ad Cy c le , Sus p e nd Burs t Curre nt X X X H H H H X H H - HI-Z Re ad Cy c le , Sus p e nd Burs t Curre nt H X X X H H H H X L - DOUT Re ad Cy c le , Sus p e nd Burs t Curre nt H X X X H H H H X H - HI-Z Re ad Cy c le , Sus p e nd Burs t Curre nt H X X X H H H X H L - DOUT Re ad Cy c le , Sus p e nd Burs t Curre nt H X X X H H H X H H - HI-Z Write Cy c le , Sus p e nd Burs t Curre nt X X X H H H H L L X - DIN Write Cy c le , Sus p e nd Burs t Curre nt X X X H H H L X X X - DIN Write Cy c le , Sus p e nd Burs t Curre nt H X X X H H H L L X - DIN Write Cy c le , Sus p e nd Burs t Curre nt H X X X H H L X X X - DIN Operation NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. OE is an asynchronous input. 3. ZZ = low for this table. 4876 tb l 11 9 1998 Integrated Device Technology, Inc. DSC-4876/2 IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE SYNCHRONOUS WRITE FUNCTION TRUTH TABLE(1, 2) Operation GW BWE BW1 BW2 BW3 BW4 Re ad H H X X X X Re ad H L H H H H Write all By te s L X X X X X Write all By te s H L L L L L (3) H L L H H H (3) H L H L H H (3) Write By te 3 H L H H L H Write By te 4(3) H L H H H L Write By te 1 Write By te 2 NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. BW3 and BW4 are not applicable for the IDT71Vx579. 3. Multiple bytes may be selected during the same cycle. 4876 tb l 12 ASYNCHRONOUS TRUTH TABLE(1) Operation(2) OE ZZ I/O Status Power Re ad L L Data Out Ac tiv e Re ad H L Hig h-Z Ac tiv e Write X L Hig h-Z - Data In Ac tiv e De s e le c te d X L Hig h-Z Stand b y S le e p Mo d e X H Hig h-Z S le e p NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements. 4876 tb l 13 INTERLEAVED BURST SEQUENCE TABLE (LBO LBO=VDD) LBO Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 Firs t Ad d re s s 0 0 0 1 1 0 1 1 Se c o nd Ad d re s s 0 1 0 0 1 1 1 0 Third Ad d re s s 1 0 1 1 0 0 0 1 Fo urth Ad d re s s (1) 1 1 1 0 0 1 0 0 4876 tb l 14 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. LINEAR BURST SEQUENCE TABLE (LBO LBO=V SS) LBO Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 Firs t Ad d re s s 0 0 0 1 1 0 1 1 Se c o nd Ad d re s s 0 1 1 0 1 1 0 0 Third Ad d re s s 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 Fo urth Ad d re s s (1) NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. 4876 tb l 15 10 1998 Integrated Device Technology, Inc. DSC-4876/2 COMMERCIAL TEMPERATURE RANGE IDT71Vx576/IDTVx578 AC ELECTRICAL CHARACTERISTICS (VDD = 3.3V 5%, TA = 0 to 70C) 200MHz Symbol Parameter Clo c k Cy c le Time tCYC (1) Clo c k Hig h Puls e Wid th tCH (1) Clo c k Lo w Puls e Wid th tCL 183MHz 166MHz 150MHz 133MHz M i n. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit 5 ____ 5.5 ____ 6 ____ 6.7 ____ 7.5 ____ ns 2 ____ 2.2 ____ 2.4 ____ 2.6 ____ 3 ____ ns 2 ____ 2.2 ____ 2.4 ____ 2.6 ____ 3 ____ ns ____ 3.1 ____ 3.3 ____ 3.5 ____ 3.8 ____ 4.2 ns 1.5 ____ 1.5 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns Output Parameters Clo c k Hig h to Valid Data tCD Clo c k Hig h to Data Chang e tCDC (2) Clo c k Hig h to Outp ut Ac tiv e (2) Clo c k Hig h to Data Hig h-Z 1.5 3.1 1.5 3.3 1.5 3.5 1.5 3.8 1.5 4.2 ns Outp ut Enab le Ac c e s s Time ____ 3.1 ____ 3.3 ____ 3.5 ____ 3.8 ____ 4.2 ns 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 3.1 ____ 3.3 ____ 3.5 ____ 3.8 ____ 4.2 ns tCLZ tCHZ tOE (2) Outp ut Enab le Lo w to Outp ut Ac tiv e tOLZ (2) Outp ut Enab le Hig h to Outp ut Hig h-Z tOHZ Set Up Times tSA Ad d re s s Se tup Time 1.2 ____ 1.5 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns tSS Ad d re s s Status Se tup Time 1.2 ____ 1.5 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns 1.2 ____ 1.5 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns 1.5 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns 1.5 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns 1.5 ____ 1.5 ____ 1.5 ____ ns 0.5 ____ 0.5 ____ 0.5 ____ ns ns Data In Se tup Time tSD tSW Write Se tup Time 1.2 ____ tSAV Ad d re s s Ad v anc e Se tup Time 1.2 ____ Chip Enab le /Se le c t Se tup Time 1.2 ____ 1.5 ____ Ad d re s s Ho ld Time 0.4 ____ 0.5 ____ 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns ns tSC Hold Times tHA Ad d re s s Status Ho ld Time tHS tHD Data In Ho ld Time 0.4 ____ tHW Write Ho ld Time 0.4 ____ 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ Chip Enab le /Se le c t Ho ld Time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns ZZ Puls e Wid th 100 ____ 100 ____ 100 ____ 100 ____ 100 ____ ns 100 ____ 100 ____ 100 ____ 100 ____ ns 22 ____ 24 ____ 27 ____ 30 ____ tHAV tHC Ad d re s s Ad v anc e Ho ld Time Sleep tZZPW (3) tZZR ZZ Re c o v e ry Time 100 ____ tCFG(4) Co nfig uratio n Se t-up Time 20 ____ NOTES: 1. Measured as HIGH above VIH and LOW below VIL. 2. Transition is measured 200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation. ns 4876tb l 16 11 1998 Integrated Device Technology, Inc. DSC-4876/2 1998 Integrated Device Technology, Inc. Output Disabled tSC tSA tSS tHS Ax Pipelined Read tOLZ tOE tHC tHA O1(Ax) Ay (1) tCH tCLZ tOHZ tSW tCL tCD O1(Ay) tCDC tSAV tHAV O2(Ay) tHW Burst Pipelined Read O3(Ay) O4(Ay) (Burst wraps around to its initial state) ADV HIGH suspends burst O1(Ay) tCHZ O2(Ay) NOTES: 1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. LBO is Don't Care for this cycle. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. DATAOUT OE ADV (Note 3) CE, CS 1 GW, BWE, BWx ADDRESS ADSC ADSP CLK tCYC 4876 d 08 IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF PIPELINED READ CYCLE(1,2) 12 DSC-4876/2 1998 Integrated Device Technology, Inc. tSA tHA tSS tHS tCLZ tCD Single Read Ax (2) tOE O1(Ax) tOHZ tSW Ay tCH Pipelined Write I1(Ay) tSD tHD tCL tHW Az tOLZ tCDC O2(Az) Pipelined Burst Read O1(Az) NOTES: 1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH. 2. LBO is Don't Care for this cycle. 3. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. DATAOUT DATAIN OE ADV GW ADDRESS ADSP CLK tCYC 4876 dr 09 O3(Az) IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF COMBINED PIPELINED READ AND WRITE CYCLES(1,2,3) 13 DSC-4876/2 1998 Integrated Device Technology, Inc. tHC O4(Aw) Ax Burst Read O3(Aw) tSC tSA tHA tSS tHS Ay tCL Single Write tOHZ I1(Ax) I1(Ay) I2(Ay) Burst Write I2(Ay) (ADV HIGH suspends burst) tSAV GW is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge tCH I3(Ay) tHAV I4(Ay) tSD I1(Az) tHW tSW Az NOTES: 1. BWE is HIGH and LBO is Don't Care for this cycle. 2. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. DATAOUT DATAIN OE ADV (Note 3) CE, CS1 GW ADDRESS ADSC ADSP CLK tCYC I3(Az) 4876 drw 10 Burst Write I2(Az) tHD IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 - GW CONTROLLED(1,2,3) 14 DSC-4876/2 1998 Integrated Device Technology, Inc. tHC Burst Read O3(Aw) tSC tSA tHA tSS tHS O4(Aw) Ax Ay tCL Single Write tOHZ I1(Ax) I1(Ay) Burst Write I2(Ay) (ADV suspends burst) BWx is ignored when ADSP initiates a cycle and is sampled on next clock rising edge BWE is ignored when ADSP initiates a cycle and is sampled on next clock rising edge tCH I2(Ay) I3(Ay) I4(Ay) tSD Extended Burst Write I1(Az) tSAV tHW tSW tHW tSW Az NOTES: 1. GW is HIGH and LBO is Don't Care for this cycle. 2. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. DATAOUT DATAIN OE ADV (Note 3) CE, CS 1 BWx BWE ADDRESS ADSC ADSP CLK tCYC I2(Az) tHD I3(Az) IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 2 - BYTE CONTROLLED(1,2,3) 15 DSC-4876/2 1998 Integrated Device Technology, Inc. tSS tSC tSA tHS Ax Single Read tOLZ tOE tHC tHA O1(Ax) tCH tCL tZZPW Snooze Mode tZZR NOTES: 1. Device must power up in deselected Mode (CE and CS1 are HIGH, CS0 is LOW.) 2. LBO is Don't Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. 4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH. ZZ DATA OUT OE ADV (Note 4) CE, CS1 GW ADDRESS ADSC ADSP CLK tCYC Az 4876 d 12 IDT71Vx576/IDTVx578 COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF SLEEP (ZZ) AND POWER-DOWN MODES (1,2,3) 16 DSC-4876/2 ORDERING INFORMATION IDT XXX S X XX Device Type Power Speed Package PF BG 100-lead Plastic Thin Quad Flatpack (TQFP) 119-lead Ball Grid Array (BGA) 200 183 166 150 133 Frequency in Megahertz 71V2576 71V2578 71V3576 71V3578 128K x 36 Pipelined Burst Synchronous SRAM with 2.5V I/O 256K x 18 Pipelined Burst Synchronous SRAM with 2.5V I/O 128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O 256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O 4876 drw 13 Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible products. 2975 Stender Way Santa Clara, CA 95054 fax: 831-754-4547 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 17 800-544-SRAM SRAMHELP@IDT.COM