1
1998 Integrated Device Technology, Inc. DSC-4876/2
APRIL 1999
128K X 36, 256K X 18, 3.3V
SYNCHRONOUS SRAMS WITH
2.5V I/O OPTION, PIPELINED OUTPUTS,
BURST COUNTER,
SINGLE CYCLE DESELECT
PRELIMINARY
IDT71V2576
IDT71V2578
IDT71V3576
IDT71V3578
FEATURES:
• 128K x 36, 256K x 18 memory configurations
• Supports high system speed:
– 200MHz 3.1ns clock access time
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
•LBOLBO
LBOLBO
LBO input selects interleaved or linear burst mode
• Self-timed write cycle with global write control (GWGW
GWGW
GW), byte write
enable (BWEBWE
BWEBWE
BWE), and byte writes (BWBW
BWBW
BWx)
• 3.3V core power supply
• Power down controlled by ZZ input
• 2.5V or 3.3V I/O option
• Packaged in a JEDEC Standard 100-lead plastic thin quad flatpack
(TQFP) and 119-lead ball grid array (BGA)
DESCRIPTION:
The IDT71Vx576/578 are high-speed SRAMs organized as 128K x 36/
256K x 18. The IDT71Vx576/578 SRAMs contain write, data, address and
control registers. Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the system
designer, as the IDT71Vx576/578 can provide four cycles of data for a single
address presented to the SRAM. An internal burst address counter accepts the
first cycle address from the processor, initiating the access sequence. The first
cycle of output data will be pipelined for one cycle before it is available on the
next rising clock edge. If burst mode operation is selected (ADV=LOW),
the subsequent three cycles of output data will be available to the user on
the next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71Vx576/578 SRAMs utilize IDT’s latest high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm 100-lead thin
plastic quad flatpack (TQFP) as well as a 119-lead ball grid array (BGA).
PIN DESCRIPTION SUMMARY
NOTE:
1. BW3 and BW4 are not applicable for the IDT71Vx578.
A
0
A-
71
stupnIsserddAtupnIsuonorhcnyS
EC elbanEpihCtupnIsuonorhcnyS
SC
0
,SC
1
stceleSpihCtupnIsuonorhcnyS
EO elbanEtuptuOtupnIsuonorhcnysA
WG elbanEetirWlabolGtupnIsuonorhcnyS
EWB elbanEetirWetyBtupnIsuonorhcnyS
WB
1
,WB
2
,WB
3
,WB
4
)1(
stceleSetirWetyBlaudividnItupnIsuonorhcnyS
KLCkcolCtupnIA/N
VDA ecnavdAsserddAtsruBtupnIsuonorhcnyS
CSDA )rellortnoCehcaC(sutatSsserddAtupnIsuonorhcnyS
PSDA )rossecorP(sutatSsserddAtupnIsuonorhcnyS
OBL redrOtsruBdevaelretnI/raeniLtupnICD
ZZedoMpeelStupnIsuonorhcnysA
O/I
0
O/I-
13
O/I,
1P
O/I-
4P
tuptuO/tupnIataDO/IsuonorhcnyS
V
DD
V,
QDD
rewoPO/I,rewoPeroCylppuSA/N
V
SS
dnuorGylppuSA/N
10lbt6784
2
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGEIDT71Vx576/IDTVx578
PIN DEFINITIONS(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
lobmySnoitcnuFniPO/IevitcAnoitpircseD
A
0
A-
71
stupnIsserddAIA/N ehtfonoitanibmocaybdereggirtsiretsigersserddaehT.stupnisserddAsuonorhcnyS dnaKLCfoegdegnisir CSDA rowoL PSDA dnawoL EC .woL
CSDA sutatSsserddA )rellortnoCehcaC( IWOL.rellortnoCehcaCmorfsutatSsserddAsuonorhcnyS CSDA sitahttupniWOLevitcanasi
.sesserddawenhtiwsretsigersserddaehtdaolotdesu
PSDA sutatSsserddA )rossecorP( IWOL.rossecorPmorfsutatSsserddAsuonorhcnyS PSDA otdesusitahttupniWOLevitcanasi
.sesserddawenhtiwsretsigersserddaehtdaol PSDA ybdetagsi EC .
VDA sserddAtsruB ecnavdA IWOL.ecnavdAsserddAsuonorhcnyS VDA ehtecnavdaotdesusitahttupniWOLevitcanasi ehtnehW.dedaolsisserddalaitiniehtretfasseccatsrubgnillortnoc,retnuoctsrublanretni .ecnavdasserddaonsiereht,sitaht;detnemercnitonsiretnuoctsrubehtHGIHsitupni
EWB elbanEetirWetyBIWOLstupnietirwetybehtsetagelbaneetirwetybsuonorhcnyS WB
1
-WB
4
fI. EWB ehttaWOLsi
nehtKLCfoegdegnisir WB fI.tiucricehtniegatstxenehtotdessaperastupnix EWB si
ylnodnadekcolberastupnietirwetybehtnehtHGIH WG .elcycetirwaetaitininac
WB
1
-WB
4
etyBlaudividnI selbanEetirW IWOL.selbaneetirwetybsuonorhcnyS WB
1
O/Islortnoc
7-0
O/I,
1P
,WB
2
O/Islortnoc
51-8
O/I,
2P
.cte,
.delbasidebotstuptuollasesuacetirwetybevitcaynA
EC elbanEpihCIWOL.elbanepihcsuonorhcnyS EC SChtiwdesusi
0
dna SC
1
.875/675xV17TDIehtelbaneot
EC setagosla PSDA .
KLCkcolCIA/N sihtottcepserhtiwedameraecivedehtrofsecnerefergnimitllA.tupnikcolcehtsisihT .tupni
SC
0
0tceleSpihCIHGIHSC.tcelespihcHGIHevitcasuonorhcnyS
0
htiwdesusi EC dna SC
1
.pihcehtelbaneot
SC
1
1tceleSpihCIWOL.tcelespihcWOLevitcasuonorhcnyS SC
1
htiwdesusi EC SCdna
0
.pihcehtelbaneot
WG etirWlabolG elbanE IWOL WOLnehwsetybatadtib-9ruofllaetirwlliwtupnisihT.elbaneetirwlabolgsuonorhcnyS .KLCfoegdegnisirehtno WG .selbaneetirwetyblaudividnisedesrepus
O/I
0
O/I-
13
O/I
1P
O/I-
4P
tuptuO/tupnIataDO/IA/N erahtaptuptuoataddnahtaptupniatadehthtoB.snip)O/I(tuptuo/tupniatadsuonorhcnyS .KLCfoegdegnisirehtybdereggirtdnaderetsiger
OBL redrOtsruBraeniLIWOLnehW.tupninoitcelesredrotsrubsuonorhcnysA OBL tsrubdevaelretnieht,HGIHsi
nehW.detcelessiecneuqes OBL .detcelessiecneuqestsrubraeniLehtWOLsi OBL asi
.gnitareposiecivedehtelihwetatsegnahctontsumdnatupnicitats
EO elbanEtuptuOIWOLnehW.elbanetuptuosuonorhcnysA EO ehtnodelbaneerasrevirdtuptuoatadehtWOLsinehW.detcelesoslasipihcehtfisnipO/I EO -hgihanierasnipO/IehtHGIHsi
.etatsecnadepmi
V
DD
ylppuSrewoPA/NA/N.ylppusrewoperocV3.3
V
QDD
ylppuSrewoPA/NA/N.ylppuSO/IV5.2roV3.3
V
SS
dnuorGA/NA/N.dnuorG
CNtcennoCoNA/NA/N.ecivedehtotdetcennocyllacirtceletonerasnipCN
ZZedoMpeelSIHGIH ehtnwodrewopdnayllanretniKLCehtetaglliwHGIHZZ.tupniedompeelssuonorhcnysA nideetnaraugsinoitneterataD.levelnoitpmusnocrewoptsewolstiot87/675xV17TDI .edoMpeelS
20lbt6784
3
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
FUNCTIONAL BLOCK DIAGRAM
A0ÐA16/17 ADDRESS
REGISTER
CLR# A1*
A0* 17/18
2
17/18 A2ÐA17
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A0,A1
BW4
BW3
BW2
BW1
Byte 1
Write Register
36/18 36/1
8
ADSP
ADV
CLK
ADSC
CS0
CS1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Writ e Regi ster
9
9
9
9
GW
CE
BWE
LBO
I/O0 — I/O31
I/OP1 — I/OP4
OE
DATA
INPUT
REGISTER
36/18
OUTPUT
BUFFER
OUTPUT
REGISTER
DQ
DQ
Enable
Register
Enable
Delay
Register
OE
Burst
Sequence
CE#
CE#
CE#
Q1
Q0
2Burst
Logic
Binary
Counter
4876 dr w 01
ZZ Powerdown
4
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGEIDT71Vx576/IDTVx578
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
RECOMMENDED DC OPERATING
CONDITIONS WITH VDDQ AT 2.5V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY
VOLTAGE
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have ramped up.
Power supply sequencing is not necessary; however, the voltage on any input or I/O pin
cannot exceed VDDQ during power supply ramp up.
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
RECOMMENDED DC OPERATING
CONDITIONS WITH VDDQ AT 3.3V
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
lobmySgnitaRlaicremmoCtinU
V
MRET
)2(
htiwegatloVlanimreT DNGottcepseR 6.4+ot5.0-V
V
MRET
)6,3(
htiwegatloVlanimreT DNGottcepseR Vot5.0-
DD
V
V
MRET
)6,4(
htiwegatloVlanimreT DNGottcepseR Vot5.0-
DD
5.0+V
V
MRET
)6,5(
htiwegatloVlanimreT DNGottcepseR Vot5.0-
QDD
5.0+V
T
A
erutarepmeTgnitarepO 07+ot0-
o
C
T
SAIB
erutarepmeT saiBrednU 521+ot55-
o
C
T
GTS
egarotS erutarepmeT 521+ot55-
o
C
P
T
noitapissiDrewoP52.1W
I
TUO
tnerruCtuptuOCD05Am
30lbt6784
edarGerutarepmeTV
SS
V
DD
V
QDD
laicremmoCC°07+otC°0V0%5±V3.3%5±V5.2
laicremmoCC°07+otC°0V0%5±V3.3V
DD
40lbt6784
lobmySretemaraP.niM.pyT.xaMtinU
V
DD
egatloVylppuSeroC531.33.3564.3V
V
QDD
egatloVylppuSO/I573.25.2526.2V
V
SS
egatloVylppuS 000V
V
HI
stupnI-egatloVhgiHtupnI 7.1
____
V
DD
3.0+ V
V
HI
egatloVhgiHtupnI-O/I 7.1
____
V
QDD
3.0+
)1(
V
V
LI
egatloVwoLtupnI3.0-
)2(
____
7.0V
50lbt6784
lobmySretemaraP.niM.pyT.xaMtinU
V
DD
egatloVylppuSeroC531.33.3564.3V
V
QDD
egatloVylppuSO/I531.33.3564.3V
V
SS
egatloVylppuS 000V
V
HI
stupnI-egatloVhgiHtupnI 0.2
____
V
DD
3.0+ V
V
HI
egatloVhgiHtupnI-O/I 0.2
____
V
QDD
3.0+
)1(
V
V
LI
egatloVwoLtupnI3.0-
)2(
____
8.0V
60lbt6784
lobmySretemaraP
)1(
snoitidnoC.xaMtinU
C
NI
ecnaticapaCtupnIV
NI
Vd3=5Fp
C
O/I
ecnaticapaCO/IV
TUO
Vd3=7Fp
70lbt6784
5
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
PIN CONFIGURATION 128K x 36 TQFP
TOP VIEW
NOTES:
1. Pins 14 does not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. Pins 38 and 39 can be either NC or connected to VSS.
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
(2)
NC
(2)
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O31
I/O30
VDDQ
VSS
I/O29
I/O28
I/O27
I/O26
VSS
VDDQ
I/O25
I/O24
VSS
VDD
I/O23
I/O22
VDDQ
VSS
I/O21
I/O20
I/O19
I/O18
VSS
VDDQ
I/O17
I/O16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
4876 dr w 02
VDD(1)
I/O15
I/OP3
NC
I/OP4
A
15
A
16
I/OP1
NC
I/OP2
ZZ
6
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGEIDT71Vx576/IDTVx578
PIN CONFIGURATION 256K x 18 TQFP
TOP VIEW
NOTES:
1. Pins 14 does not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. Pins 38 and 39 can be either NC or connected to VSS.
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
NC
NC
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
(2)
NC
(2)
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
VDDQ
VSS
NC
I/OP2
I/O15
I/O14
VSS
VDDQ
I/O13
I/O12
VSS
VDD
I/O11
I/O10
VDDQ
VSS
I/O9
I/O8
NC
NC
VSS
VDDQ
NC
NC 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
4876 drw 03
VDD(1)
NC
NC
NC
NC
A
16
A
17
NC
NC
A10
ZZ
7
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
PIN CONFIGURATION 256K x 18 BGA(1,2)
PIN CONFIGURATION 128K x 36 BGA(1,2)
TOP VIEW
TOP VIEW
NOTES:
1. R5 does not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. L4 and U4 can be either NC or connected to VSS.
1234567
A
V
DDQ
A
6
A
4
ADSP A
8
A
16
V
DDQ
B
NC CS
0
A
3
ADSC A
9
CS
1
NC
C
A
7
A
2
V
DD
A
12
A
15
NC
D
I/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
E
I/O
17
I/O
18
V
SS
CE V
SS
I/O
13
I/O
14
F
V
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
G
I/O
20
I/O
21
BW
3
ADV BW
2
I/O
11
I/O
10
H
I/O
22
I/O
23
V
SS
GW V
SS
I/O
9
I/O
8
J
V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K
I/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
L
I/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
M
V
DDQ
I/O
28
V
SS
BWE V
SS
I/O
3
V
DDQ
N
I/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
P
I/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
R
NC A
5
LBO V
DD
A
13
T
NC NC A
10
A
11
A
14
NC ZZ
U
V
DDQ
NC NC NC NC NC V
DDQ
4876 drw 04
VDD
NC
NC
1234567
A
V
DDQ
A
6
A
4
ADSP A
8
A
16
V
DDQ
B
NC CS0 A
3
ADSC A
9
CS
1
NC
C
A
7
A
2
V
DD
A
13
A
17
NC
D
I/O
8
NC V
SS
NC V
SS
I/O
7
NC
E
NC I/O
9
V
SS
CE V
SS
NC I/O
6
F
V
DDQ
NC V
SS
OE V
SS
I/O
5
V
DDQ
G
NC I/O
10
BW
2
ADV NC I/O
4
H
I/O
11
NC V
SS
GW V
SS
I/O
3
NC
J
V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K
NC I/O
12
V
SS
CLK V
SS
NC I/O
2
L
I/O
13
NC NC BW
1
I/O
1
NC
M
V
DDQ
I/O
14
V
SS
BWE V
SS
NC V
DDQ
N
I/O
15
NC V
SS
A
1
V
SS
I/O
0
NC
P
NC I/O
P2
V
SS
A
0
V
SS
NC I/O
P1
R
NC A
5
LBO V
DD
A
12
T
NC A
10
A
15
NC A
14
A
11
ZZ
U
V
DDQ
NC NC NC NC NC V
DDQ
4876 drw 05
NC
DD
VNC
V
SS
V
SS
8
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGEIDT71Vx576/IDTVx578
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC TEST LOADSAC TEST CONDITIONS
(VDDQ = 3.3V/2.5V)
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O
Z
0
= 50Ω
4876 drw 06
1
2
3
4
20 30 50 100 200
∆tCD
(T ypical, ns)
Ca pa ci ta n ce (pF)
80
5
6
4876 drw 07
lobmySretemaraPsnoitidnoCtseT.niM.xaMtinU
I|
LI
|tnerruCegakaeLtupnIV
DD
V,.xaM=
NI
VotV0=
DD
___
5Aµ
I|
ZZL
|dnaZZ OBL tnerruCegakaeLtupnI
)1(
V
DD
V,.xaM=
NI
VotV0=
DD
___
03Aµ
I|
OL
|tnerruCegakaeLtuptuOV
TUO
VotV0=
QDD
detceleseDeciveD,
___
5Aµ
V
LO
)V3.3(egatloVwoLtuptuOI
LO
V,Am8+=
DD
.niM=
___
4.0V
V
HO
)V3.3(egatloVhgiHtuptuOI
HO
V,Am8-=
DD
.niM=4.2
___
V
V
LO
)V5.2(egatloVwoLtuptuOI
LO
V,Am6+=
DD
.niM=
___
4.0V
V
HO
)V5.2(egatloVhgiHtuptuOI
HO
V,Am6-=
DD
.niM=0.2
___
V
80lbt6784
lobmySretemaraPsnoitidnoCtseTzHM002zHM381zHM661zHM051zHM331tinU
I
DD
tnerruCylppuSrewoPgnitarepO ,nepOstuptuO,detceleSeciveD
V
DD
V,.xaM=
NI
> V
HI
ro<V
LI
f=f,
XAM
)2(
063043023592052Am
02tnerruCylppuSrewoPybdnatSSOMC,nepOstuptuO,detceleseDeciveD
V
DD
V,.xaM=
NI
> V
DH
ro<V
DL
0=f,
)3,2(
0202020202Am
031tnerruCylppuSrewoPgninnuRkcolC,nepOstuptuO,detceleseDeciveD
V
DD
V,.xaM=
NI
> V
DH
ro<V
DL
,
f=f
XAM
)3.2(
03102101100109Am
02tnerruCylppuSedoMpeelSlluFZZ>
V
,DH
V
DD
.xaM=0202020202Am
90lbt6784
sleveLesluPtupnI
semiTllaF/esiRtupnI
sleveLecnerefeRgnimiTtupnI
sleveLecnerefeRgnimiTtuptuO
daoLtseTCA
ot0/V3ot0V
QDD
sn2
V(/V5.1
QDD
)2/
V(/V5.1
QDD
)2/
1erugiFeeS
01lbt6784
9
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
SYNCHRONOUS TRUTH TABLE(1,3)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
noitarepOsserddA desU
EC SC
0
SC
1
PSDACSDAVDAWGEWBWBxEO
)2( KLCO/I
nwoDrewoP,elcyCdetceleseDenoN HXXX LXXXXX- Z-IH
nwoDrewoP,elcyCdetceleseDenoN LXHL XXXXXX- Z-IH
nwoDrewoP,elcyCdetceleseDenoN LLX L XXXXXX- Z-IH
nwoDrewoP,elcyCdetceleseDenoN LXHX LXXXXX - Z-IH
nwoDrewoP,elcyCdetceleseDenoN LLXX LXXXXX- Z-IH
tsruBnigeB,elcyCdaeRlanretxE LHL L XXXXXL-D
TUO
tsruBnigeB,elcyCdaeRlanretxE LHL L XXXXXH- Z-IH
tsruBnigeB,elcyCdaeRlanretxELHLHLXHHXL-D
TUO
tsruBnigeB,elcyCdaeRlanretxELHLHLXHLHL-D
TUO
tsruBnigeB,elcyCdaeRlanretxELHLHLXHLHH-Z-IH
tsruBnigeB,elcyCetirWlanretxELHLHLXHLLX-D
NI
tsruBnigeB,elcyCetirWlanretxE LHL H LXLXXX-D
NI
tsruBeunitnoC,elcyCdaeRtxeN XXXH HLHHXL-D
TUO
tsruBeunitnoC,elcyCdaeRtxeN XXXH HLHHXH- Z-IH
tsruBeunitnoC,elcyCdaeRtxeN XXXH HLHXHL-D
TUO
tsruBeunitnoC,elcyCdaeRtxeN XXXH HLHXHH- Z-IH
tsruBeunitnoC,elcyCdaeRtxeNHXXXHLHHXL-D
TUO
tsruBeunitnoC,elcyCdaeRtxeNHXXXHLHHXH-Z-IH
tsruBeunitnoC,elcyCdaeRtxeNHXXXHLHXHL-D
TUO
tsruBeunitnoC,elcyCdaeRtxeNHXXXHLHXHH-Z-IH
tsruBeunitnoC,elcyCetirWtxeN XXXH HLHLLX-D
NI
tsruBeunitnoC,elcyCetirWtxeN XXXH HLLXXX-D
NI
tsruBeunitnoC,elcyCetirWtxeNHXXXHLHLLX-D
NI
tsruBeunitnoC,elcyCetirWtxeN HXXX HLLXXX-D
NI
tsruBdnepsuS,elcyCdaeRtnerruC XXXH HHHHXL-D
TUO
tsruBdnepsuS,elcyCdaeRtnerruC XXXH HHHHXH- Z-IH
tsruBdnepsuS,elcyCdaeRtnerruC XXXH HHHXHL-D
TUO
tsruBdnepsuS,elcyCdaeRtnerruC XXXH HHHXHH- Z-IH
tsruBdnepsuS,elcyCdaeRtnerruC HXXX HHHHXL-D
TUO
tsruBdnepsuS,elcyCdaeRtnerruC HXXX HHHHXH- Z-IH
tsruBdnepsuS,elcyCdaeRtnerruCHXXXHHHXHL-D
TUO
tsruBdnepsuS,elcyCdaeRtnerruCHXXXHHHXHH-Z-IH
tsruBdnepsuS,elcyCetirWtnerruC XXXH HHHLLX-D
NI
tsruBdnepsuS,elcyCetirWtnerruC XXXH HHLXXX-D
NI
tsruBdnepsuS,elcyCetirWtnerruCHXXXHHHLLX-D
NI
tsruBdnepsuS,elcyCetirWtnerruC HXXX HHLXXX-D
NI
11lbt6784
10
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGEIDT71Vx576/IDTVx578
LINEAR BURST SEQUENCE TABLE (LBOLBO
LBOLBO
LBO=VSS)
SYNCHRONOUS WRITE FUNCTION TRUTH TABLE(1, 2)
ASYNCHRONOUS TRUTH TABLE(1)
INTERLEAVED BURST SEQUENCE TABLE (LBOLBO
LBOLBO
LBO=VDD)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71Vx579.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
noitarepO WGEWBWB
1
WB
2
WB
3
WB
4
daeR HHXXXX
daeR HLHHHH
setyBllaetirW LXXXXX
setyBllaetirW HLLLLL
1etyBetirW
)3(
HLLHHH
2etyBetirW
)3(
HLHLHH
3etyBetirW
)3(
HLHHLH
4etyBetirW
)3(
HLHHHL
21lbt6784
1ecneuqeS2ecneuqeS3ecneuqeS4ecneuqeS
1A0A1A0A1A0A1A0A
sserddAtsriF 00011011
sserddAdnoceS01101100
sserddAdrihT 10110001
sserddAhtruoF
)1(
11000110
51lbt6784
1ecneuqeS2ecneuqeS3ecneuqeS4ecneuqeS
1A0A1A0A1A0A1A0A
sserddAtsriF 00011011
sserddAdnoceS 01001110
sserddAdrihT 10110001
sserddAhtruoF
)1(
11100100
41lbt6784
noitarepO
)2(
EO ZZsutatSO/IrewoP
daeRLL tuOataDevitcA
daeRHL Z-hgiHevitcA
etirWXL nIataD–Z-hgiHevitcA
detceleseDXLZ-hgiHybdnatS
edoMpeelSXHZ-hgiHpeelS
31lbt6784
11
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
AC ELECTRICAL CHARACTERISTICS
(VDD = 3.3V ±5%, TA = 0 to 70°C)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
zHM002zHM381zHM661zHM051zHM331
lobmySretemaraP.niM.xaM.niM.xaM.niM.xaM.niM.xaM.niM.xaMtinU
t
CYC
emiTelcyCkcolC5
____
5.5
____
6
____
7.6
____
5.7
____
sn
t
HC
)1(
htdiWesluPhgiHkcolC2
____
2.2
____
4.2
____
6.2
____
3
____
sn
t
LC
)1(
htdiWesluPwoLkcolC2
____
2.2
____
4.2
____
6.2
____
3
____
sn
sretemaraPtuptuO
t
DC
ataDdilaVothgiHkcolC
____
1.3
____
3.3
____
5.3
____
8.3
____
2.4sn
t
CDC
egnahCataDothgiHkcolC5.1
____
5.1
____
5.1
____
5.1
____
5.1
____
sn
t
ZLC
)2(
evitcAtuptuOothgiHkcolC0
____
0
____
0
____
0
____
0
____
sn
t
ZHC
)2(
Z-hgiHataDothgiHkcolC5.11.35.13.35.15.35.18.35.12.4sn
t
EO
emiTsseccAelbanEtuptuO
____
1.3
____
3.3
____
5.3
____
8.3
____
2.4sn
t
ZLO
)2(
evitcAtuptuOotwoLelbanEtuptuO0
____
0
____
0
____
0
____
0
____
sn
t
ZHO
)2(
Z-hgiHtuptuOothgiHelbanEtuptuO
____
1.3
____
3.3
____
5.3
____
8.3
____
2.4sn
semiTpUteS
t
AS
emiTputeSsserddA2.1
____
5.1
____
5.1
____
5.1
____
5.1
____
sn
t
SS
emiTputeSsutatSsserddA2.1
____
5.1
____
5.1
____
5.1
____
5.1
____
sn
t
DS
emiTputeSnIataD2.1
____
5.1
____
5.1
____
5.1
____
5.1
____
sn
t
WS
emiTputeSetirW2.1
____
5.1
____
5.1
____
5.1
____
5.1
____
sn
t
VAS
emiTputeSecnavdAsserddA2.1
____
5.1
____
5.1
____
5.1
____
5.1
____
sn
t
CS
emiTputeStceleS/elbanEpihC2.1
____
5.1
____
5.1
____
5.1
____
5.1
____
sn
semiTdloH
t
AH
emiTdloHsserddA4.0
____
5.0
____
5.0
____
5.0
____
5.0
____
sn
t
SH
emiTdloHsutatSsserddA4.0
____
5.0
____
5.0
____
5.0
____
5.0
____
sn
t
DH
emiTdloHnIataD4.0
____
5.0
____
5.0
____
5.0
____
5.0
____
sn
t
WH
emiTdloHetirW4.0
____
5.0
____
5.0
____
5.0
____
5.0
____
sn
t
VAH
emiTdloHecnavdAsserddA4.0
____
5.0
____
5.0
____
5.0
____
5.0
____
sn
t
CH
emiTdloHtceleS/elbanEpihC4.0
____
5.0
____
5.0
____
5.0
____
5.0
____
sn
peelS
t
WPZZ
htdiWesluPZZ001
____
001
____
001
____
001
____
001
____
sn
t
RZZ
)3(
emiTyrevoceRZZ001
____
001
____
001
____
001
____
001
____
sn
t
GFC
)4(
emiTpu-teSnoitarugifnoC02
____
22
____
42
____
72
____
03
____
sn
61lbt6784
12
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGEIDT71Vx576/IDTVx578
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
TIMING WAVEFORM OF PIPELINED READ CYCLE(1,2)
t
CHZ
t
SA
t
SC
t
HS
G
W, BWE, BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OE
t
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay) O3(Ay) O2(Ay)
O2(Ay)
t
CLZ
ADV
CE, CS
1
(Note 3)
Pipelined
ReadBurst Pipelined Read
Output
Disabled
Ax Ay
t
SS
O1(Ay)
(Burst wraps ar ound
to its initial state)
O4(Ay)
4876d08
ADSP
ADV HIGH sus pen ds
burst
13
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
TIMING WAVEFORM OF COMBINED PIPELINED READ AND WRITE CYCLES(1,2,3)
CLK
ADSP
ADDRESS
GW
ADV
OE
DATA
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
Ax Ay Az
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DATA
IN
(2)
t
OE
O1(Az)
O1(Az)
Single ReadPipelined Burst Read
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
4876dr 09
14
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGEIDT71Vx576/IDTVx578
NOTES:
1. BWE is HIGH and LBO is Don't Care for this cycle.
2. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 - GWGW
GWGW
GW CONTROLLED(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
Ax Ay Az
ADV
DATA
OUT
OE
t
HC
t
SD
I1(Ax) I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE, CS
1
t
HW
GWt
SW
(Note 3)
I2(Az)
Burst W rite
Burst Read Burst Write
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADV HIGH suspends burst)
I1(Ay)
GW is ignored when ADSP init iates a cycle and is s ampled on the next clock rising edge
t
SC
4876drw10
15
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGE
IDT71Vx576/IDTVx578
NOTES:
1. GW is HIGH and LBO is Don't Care for this cycle.
2. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 - BYTE CONTROLLED(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
Ax Ay
t
HW
BWx
ADV
DATA
OUT
OE
t
HC
t
SD
Single
Write Burst Write
I1(Ax) I2(Ay) I2(Ay)
(ADV suspe nds burst)
I2(Az)
tHD
Burst
Read Extended
Burst W rite
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE, CS
1
t
HW
BWE
t
SW
(Note 3)
I1(Az)
Az
I4(Ay)
I1(Ay)I4(Ay)
I3(Ay)
t
SC
BWE is ig nored when ADSP initiates a cycle and is sampled on next clock rising edge
BWx is ignored wh en ADSP initiates a cycle and is sampled on next clock rising edge
I3(Az)
O3(Aw)
16
1998 Integrated Device Technology, Inc. DSC-4876/2
COMMERCIAL TEMPERATURE RANGEIDT71Vx576/IDTVx578
TIMING WAVEFORM OF SLEEP (ZZ) AND POWER-DOWN MODES(1,2,3)
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
A
DDRESS
GW
CE, CS
1
ADV
DATA
OUT
OE
ZZ
Single ReadSnooze Mode
tZZPW
4876 d12
O1(Ax)
Ax
(Note 4)
tZZR
Az
NOTES:
1. Device must power up in deselected Mode (CE and CS1 are HIGH, CS0 is LOW.)
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
17
2975 Stender Way 800-544-SRAM
Santa Clara, CA 95054 fax: 831-754-4547 SRAMHELP@IDT.COM
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
100-lead Plastic Thin Quad Flatpack (TQFP)
119-lead Ball Grid Array (BGA)
S
Power
X
Speed
XX
Package
PF
BG
IDT XXX
200
183
166
150
133
Frequency in Megahertz
4876 dr w 13
Device
Type
71V2576
71V2578 128K x 36 Pipelined Burst Synchronous SRAM with 2.5V I/
O
256K x 18 Pipelined Burst Synchronous SRAM with 2.5V I/
O
71V3576
71V3578 128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/
O
256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/
O
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible products.
