This is information on a product in full production.
July 2012 Doc ID 12276 Rev 19 1/53
1
M95256-W M95256-R
M95256-DR M95256-DF
256-Kbit serial SPI bus EEPROM with high-speed clock
Datasheet − production data
Features
■Compatible with the Serial Peripheral Interface
(SPI) bus
■Memory array
– 256 Kb (32 Kbytes) of EEPROM
– Page size: 64 bytes
■Write
– Byte Write within 5 ms
– Page Write within 5 ms
■Additional Write lockable page (Identification
page)
■Write Protect: quarter, half or whole memory
array
■High-speed clock: 20 MHz
■Single supply voltage:
– 2.5 V to 5.5 V for M95256-W
– 1.8 V to 5.5 V for M95256-R and M95256-
DR
– 1.7 V to 5.5 V for M95256-DF
■Operating temperature range: from -40°C up to
+85°C
■Enhanced ESD protection
■More than 4 million Write cycles
■More than 200-year data retention
■Packages
– RoHS compliant and halogen-free
(ECOPACK®)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
WLCSP (CS)
UFDFPN8 (MC)
2 x 3 mm (MLP)
(preliminary data)
www.st.com
Contents M95256-W M95256-R M95256-DR M95256-DF
2/53 Doc ID 12276 Rev 19
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M95256-W M95256-R M95256-DR M95256-DF Contents
Doc ID 12276 Rev 19 3/53
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6.1 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . 25
6.7 Read Identification Page (available only in M95256-D devices) . . . . . . . . 26
6.8 Write Identification Page (available only in M95256-D devices) . . . . . . . . 27
6.9 Read Lock Status (available only in M95256-D devices) . . . . . . . . . . . . . 28
6.10 Lock ID (available only in M95256-D devices) . . . . . . . . . . . . . . . . . . . . . 29
7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
List of tables M95256-W M95256-R M95256-DR M95256-DF
4/53 Doc ID 12276 Rev 19
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. M95256-D instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Operating conditions (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Operating conditions (M95256-R and M95256-DR, device grade 6) . . . . . . . . . . . . . . . . . 32
Table 11. Operating conditions (M95256-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. DC characteristics (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. DC characteristics (M95256-R, M95256-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. DC characteristics (M95256-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. AC characteristics (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. AC characteristics (M95256-R, M95256-DR device grade 6). . . . . . . . . . . . . . . . . . . . . . . 38
Table 21. AC characteristics (M95256-DF device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 42
Table 23. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 44
Table 25. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data. 46
Table 26. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
M95256-W M95256-R M95256-DR M95256-DF List of figures
Doc ID 12276 Rev 19 5/53
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . . 7
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Write identification page sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 42
Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 43
Figure 25. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . 45
Description M95256-W M95256-R M95256-DR M95256-DF
6/53 Doc ID 12276 Rev 19
1 Description
The M95256 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 32768 x 8 bits, accessed through the SPI bus.
The M95256-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95256-R and
M95256-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M95256-DF can
operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of
-40 °C / +85 °C.
The M95256-Dx offers an additional page, named the Identification Page (64 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
The SPI bus signals are C, D and Q, as shown in Figure 1 and Ta bl e 1 . The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data Input Input
Q Serial Data Output Output
SChip Select Input
WWrite Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground
AI01789C
S
VCC
M95xxx
HOLD
VSS
W
Q
C
D
M95256-W M95256-R M95256-DR M95256-DF Description
Doc ID 12276 Rev 19 7/53
Figure 2. 8-pin package connections (top view)
1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.
Figure 3. WLCSP connections (top view, marking side, with balls on the underside)
Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
DVSS
C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
-36
1
3
7
6##
#
$
(/,$
633
Memory organization M95256-W M95256-R M95256-DR M95256-DF
8/53 Doc ID 12276 Rev 19
2 Memory organization
The memory is organized as shown in the following figure.
Figure 4. Block diagram
-36
(/,$
3
7#ONTROLLOGIC (IGHVOLTAGE
GENERATOR
)/SHIFTREGISTER
!DDRESSREGISTER
ANDCOUNTER
$ATA
REGISTER
PAGE
8DECODER
9DECODER
#
$
1
3IZEOFTHE
2EADONLY
%%02/-
AREA
3TATUS
REGISTER
)DENTIFICATIONPAGE


M95256-W M95256-R M95256-DR M95256-DF Signal description
Doc ID 12276 Rev 19 9/53
3 Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
described next.
3.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
3.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
Signal description M95256-W M95256-R M95256-DR M95256-DF
10/53 Doc ID 12276 Rev 19
3.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7 VCC supply voltage
VCC is the supply voltage.
3.8 VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
M95256-W M95256-R M95256-DR M95256-DF Connecting to the SPI bus
Doc ID 12276 Rev 19 11/53
4 Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 5. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 5 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
RR R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
Connecting to the SPI bus M95256-W M95256-R M95256-DR M95256-DF
12/53 Doc ID 12276 Rev 19
4.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
●CPOL=0, CPHA=0
●CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 6, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●C remains at 0 for (CPOL=0, CPHA=0)
●C remains at 1 for (CPOL=1, CPHA=1)
Figure 6. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M95256-W M95256-R M95256-DR M95256-DF Operating features
Doc ID 12276 Rev 19 13/53
5 Operating features
5.1 Supply voltage (VCC)
5.1.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS device pins.
5.1.2 Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC
and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the
following state:
●in Standby Power mode,
●deselected,
●Status Register values:
– The Write Enable Latch (WEL) bit is reset to 0.
– The Write In Progress (WIP) bit is reset to 0.
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and
stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating
conditions in Section 9: DC and AC parameters.
5.1.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 5).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
Operating features M95256-W M95256-R M95256-DR M95256-DF
14/53 Doc ID 12276 Rev 19
5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be:
●deselected (Chip Select S should be allowed to follow the voltage applied on VCC),
●in Standby Power mode (there should not be any internal write cycle in progress).
5.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).
5.3 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
been in progress.(a)(b)
Figure 7. Hold condition activation
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 7).
a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
ai02029E
c
HOLD
Hold
condition
Hold
condition
M95256-W M95256-R M95256-DR M95256-DF Operating features
Doc ID 12276 Rev 19 15/53
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 7 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
5.5 Data protection and protocol control
The device features the following data protection mechanisms:
●Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
●All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
●The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
●The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
●The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
Status Register bits
Protected block Protected array addresses
BP1 BP0
0 0 none none
0 1 Upper quarter 6000h - 7FFFh
1 0 Upper half 4000h - 7FFFh
1 1 Whole memory 0000h - 7FFFh
Instructions M95256-W M95256-R M95256-DR M95256-DF
16/53 Doc ID 12276 Rev 19
6 Instructions
Each instruction starts with a single-byte code, as summarized in Ta b l e 3 .
If an invalid instruction is sent (one not contained in Ta b le 3 ), the device automatically
deselects itself.
Table 3. Instruction set
Instruction Description Instruction format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
Table 4. M95256-D instruction set
Instruction Description Instruction
format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
Read Identification
Page Reads the page dedicated to identification. 1000 0011(1)
1. Address bit A10 must be 0, all other address bits are Don't Care.
Write Identification
Page Writes the page dedicated to identification. 1000 0010(1)
Read Lock Status Reads the lock status of the Identification Page. 1000 0011(2)
2. Address bit A10 must be 1, all other address bits are Don't Care.
Lock ID Locks the Identification page in read-only mode. 1000 0010(2)
Table 5. Address range bits
Address significant bits A14-A0(1)
1. Upper MSBs are Don’t Care.
M95256-W M95256-R M95256-DR M95256-DF Instructions
Doc ID 12276 Rev 19 17/53
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 8. Write Enable (WREN) sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
Instructions M95256-W M95256-R M95256-DR M95256-DF
18/53 Doc ID 12276 Rev 19
6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●Power-up
●WRDI instruction execution
●WRSR instruction completion
●WRITE instruction completion.
Figure 9. Write Disable (WRDI) sequence
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M95256-W M95256-R M95256-DR M95256-DF Instructions
Doc ID 12276 Rev 19 19/53
6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 10.
Figure 10. Read Status Register (RDSR) sequence
The status and control bits of the Status Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
●Power-up
●Write Disable (WRDI) instruction completion
●Write Status Register (WRSR) instruction completion
●Write (WRITE) instruction completion
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Ta b l e 2 ) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M95256-W M95256-R M95256-DR M95256-DF
20/53 Doc ID 12276 Rev 19
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11.
Figure 11. Write Status Register (WRSR) sequence
Table 6. Status Register format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M95256-W M95256-R M95256-DR M95256-DF Instructions
Doc ID 12276 Rev 19 21/53
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
also reset at the end of the Write cycle tW.
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
●The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Ta bl e 2 .
●The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Ta b l e 7 . When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
The protection features of the device are summarized in Ta bl e 7 .
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
Table 7. Protection modes
W
signal
SRWD
bit Mode Write protection of the
Status Register
Memory content
Protected area(1)
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
Unprotected area(1)
10
Software-
protected
(SPM)
Status Register is
writable (if the WREN
instruction has set the
WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Write-protected Ready to accept
Write instructions
00
11
01
Hardware-
protected
(HPM)
Status Register is
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
Write-protected Ready to accept
Write instructions
Instructions M95256-W M95256-R M95256-DR M95256-DF
22/53 Doc ID 12276 Rev 19
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
●If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
●If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●either setting the SRWD bit after driving the Write Protect (W) input pin low,
●or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
6.5 Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
Figure 12. Read from Memory Array (READ) sequence
M95256-W M95256-R M95256-DR M95256-DF Instructions
Doc ID 12276 Rev 19 23/53
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
6.6 Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
Figure 13. Byte Write (WRITE) sequence
C
D
AI01795D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
High Impedance
Instruction 16-Bit Address
0
765432 0
1
Data Byte
31
Instructions M95256-W M95256-R M95256-DR M95256-DF
24/53 Doc ID 12276 Rev 19
The instruction is not accepted, and is not executed, under the following conditions:
●if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
●if a Write cycle is already in progress,
●if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
●if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
Figure 14. Page Write (WRITE) sequence
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 345678910 2021222324252627
1413 3210
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
M95256-W M95256-R M95256-DR M95256-DF Instructions
Doc ID 12276 Rev 19 25/53
6.6.1 Cycling with Error Correction Code (ECC)
M95256 and M95256-D devices offer an Error Correction Code (ECC) logic. The ECC is an
internal logic function which is transparent for the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes(c). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(c). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the four bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Ta bl e 1 4 .
c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
Instructions M95256-W M95256-R M95256-DR M95256-DF
26/53 Doc ID 12276 Rev 19
6.7 Read Identification Page (available only in M95256-D
devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Reading this page is achieved with the Read Identification Page instruction (see Ta bl e 4 ).
The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data Input (D). Address bit A10 must be 0, upper
address bits are Don't Care, and the data byte pointed to by the lower address bits [A5:A0]
is shifted out on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the
internal address register is automatically incremented, and the byte of data at the new
address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the ID page from location 24d, the number of
bytes should be less than or equal to 40d, as the ID page boundary is 64 bytes).
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 15. Read Identification Page sequence
#
$
!I
3
1

        
 
  

(IGHIMPEDANCE $ATA/UT
)NSTRUCTION BITADDRESS
-3"
-3"

$ATA/UT
M95256-W M95256-R M95256-DR M95256-DF Instructions
Doc ID 12276 Rev 19 27/53
6.8 Write Identification Page (available only in M95256-D
devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Writing this page is achieved with the Write Identification Page instruction (see Tabl e 4 ). The
Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and
at least one data byte are then shifted in on Serial Data Input (D). Address bit A10 must be
0, upper address bits are Don't Care, the lower address bits [A5:A0] address bits define the
byte address inside the identification page. The instruction sequence is shown in Figure 16.
Figure 16. Write identification page sequence
#
$
!I
3
1

        
 
  
(IGHIMPEDANCE
)NSTRUCTION BITADDRESS

$ATABYTE

Instructions M95256-W M95256-R M95256-DR M95256-DF
28/53 Doc ID 12276 Rev 19
6.9 Read Lock Status (available only in M95256-D devices)
The Read Lock Status instruction (see Ta b l e 4 ) is used to check whether the Identification
Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with
the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are
then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are
Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data
Output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip
Select (S) continues to be driven low, the same data byte is shifted out. The read cycle is
terminated by driving Chip Select (S) high.
The instruction sequence is shown in Figure 17.
Figure 17. Read Lock Status sequence
#
$
!I
3
1

        
 
  

(IGHIMPEDANCE $ATA/UT
)NSTRUCTION BITADDRESS
-3"
-3"

$ATA/UT
M95256-W M95256-R M95256-DR M95256-DF Instructions
Doc ID 12276 Rev 19 29/53
6.10 Lock ID (available only in M95256-D devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed.
The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction
code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data
byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is tW (as specified in AC characteristics in Section 9: DC and AC
parameters). The instruction sequence is shown in Figure 18.
The instruction is discarded, and is not executed, under the following conditions:
●If a Write cycle is already in progress,
●If the Block Protect bits (BP1,BP0) = (1,1),
●If a rising edge on Chip Select (S) happens outside of a byte boundary.
Figure 18. Lock ID sequence
#
$
!I
3
1

        
 
  
(IGHIMPEDANCE
)NSTRUCTION BITADDRESS

$ATABYTE

Power-up and delivery state M95256-W M95256-R M95256-DR M95256-DF
30/53 Doc ID 12276 Rev 19
7 Power-up and delivery state
7.1 Power-up state
After power-up, the device is in the following state:
●Standby power mode,
●deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
●not in the Hold condition,
●the Write Enable Latch (WEL) is reset to 0,
●Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
M95256-W M95256-R M95256-DR M95256-DF Maximum rating
Doc ID 12276 Rev 19 31/53
8 Maximum rating
Stressing the device outside the ratings listed in Ta bl e 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 8. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering See note (1)
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
VOOutput voltage –0.50 VCC+0.6 V
VIInput voltage –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
IOL DC output current (Q = 0) 5 mA
IOH DC output current (Q = 1) 5 mA
VESD Electrostatic discharge voltage (human body model)(2)
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
4000(3)
3. VESD is 3000 V (max) for the M95256 identified by process letters KA.
V
DC and AC parameters M95256-W M95256-R M95256-DR M95256-DF
32/53 Doc ID 12276 Rev 19
9 DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Figure 19. AC measurement I/O waveform
Table 9. Operating conditions (M95256-W, device grade 6)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
TAAmbient operating temperature –40 85 °C
Table 10. Operating conditions (M95256-R and M95256-DR, device grade 6)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.8 5.5 V
TAAmbient operating temperature –40 85 °C
Table 11. Operating conditions (M95256-DF, device grade 6)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.7 5.5 V
TAAmbient operating temperature –40 85 °C
Table 12. AC measurement conditions
Symbol Parameter Min. Max. Unit
CLLoad capacitance 30 or 100(1)
1. 100 pF when the clock frequency fC is less than 10 MHz, 30 pF when the clock frequency fC is equal to or
greater than 10 MHz.
pF
Input rise and fall times 25 ns
Input pulse voltages 0.2 VCC to 0.8 VCC V
Input and output timing reference voltages 0.3 VCC to 0.7 VCC V
!)#
6
##
6
##
6
##
6
##
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
M95256-W M95256-R M95256-DR M95256-DF DC and AC parameters
Doc ID 12276 Rev 19 33/53
Table 13. Capacitance
Symbol Parameter Test conditions(1)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Min. Max. Unit
COUT Output capacitance (Q) VOUT = 0 V 8 pF
CIN
Input capacitance (D) VIN = 0 V 8 pF
Input capacitance (other pins) VIN = 0 V 6 pF
Table 14. Cycling performance by groups of four bytes
Symbol Parameter(1)
1. Cycling performance for products identified by process letters KB.
Test conditions Min. Max. Unit
Ncycle Write cycle endurance(2)
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1,
4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and
qualification.
TA ≤ 25 °C,
VCC(min) < VCC < VCC(max) 4,000,000
Write cycle(3)
3. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID instruction is
decoded. When using the Byte Write, the Page Write or the WRID instruction, refer also to Section 6.6.1:
Cycling with Error Correction Code (ECC).
TA = 85 °C,
VCC(min) < VCC < VCC(max) 1,200,000
Table 15. Memory cell data retention
Parameter Test conditions Min. Unit
Data retention(1)
1. For products identified by process letters KB. The data retention behavior is checked in production. The
200-year limit is defined from characterization and qualification results.
TA = 55 °C 200 Year
DC and AC parameters M95256-W M95256-R M95256-DR M95256-DF
34/53 Doc ID 12276 Rev 19
Table 16. DC characteristics (M95256-W, device grade 6)
Symbol Parameter Test conditions Min. Max. Unit
ILI
Input leakage
current VIN = VSS or VCC ± 2 µA
ILO
Output leakage
current S = VCC, VOUT = VSS or VCC ± 2 µA
ICC
Supply current
(Read)
VCC= 2.5 V, C = 0.1 VCC/0.9 VCC
at 5 MHz, Q = open 3(1)
1. For previous products identified with process letter A.
mA
VCC= 2.5 V, C = 0.1 VCC/0.9 VCC
at 10 MHz, Q = open 2(2)
2. 4 mA at 10 MHz and 3 mA at 5 MHz for M95256 previous devices identified by process letter A.
VCC= 5.5 V, C = 0.1 VCC/0.9 VCC
at 5 MHz, Q = open 5(1)
VCC= 5.5 V, C = 0.1 VCC/0.9 VCC
at 20 MHz, Q = open 5(3)
3. For the M95256 devices identified by process letter K.
ICC0(4)
4. Characterized only, not tested in production.
Supply current
(Write)
During tW, S = VCC,
2.5 V < VCC < 5.5 V 5mA
ICC1
Supply current
(Standby)
S = VCC, VCC = 5.5 V,
VIN = VSS or VCC,3(5)
5. 5 µA for M95256 previous devices identified by process letter A.
µA
S = VCC, VCC = 2.5 V,
VIN = VSS or VCC,2(5)
VIL Input low voltage –0.45 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC+1 V
VOL Output low voltage VCC = 2.5 V and IOL = 1.5 mA or
VCC = 5 V and IOL = 2 mA 0.4 V
VOH Output high voltage VCC = 2.5 V and IOH = –0.4 mA or
VCC = 5 V and IOH = –2 mA 0.8 VCC V
M95256-W M95256-R M95256-DR M95256-DF DC and AC parameters
Doc ID 12276 Rev 19 35/53
Table 17. DC characteristics (M95256-R, M95256-DR, device grade 6)
Symbol Parameter Test conditions(1) Min. Max. Unit
ILI
Input leakage
current VIN = VSS or VCC ± 2 µA
ILO
Output leakage
current S = VCC, voltage applied on Q = VSS or VCC ± 2 µA
ICC
Supply current
(Read)
VCC = 1.8V, C = 0.1V
CC or 0.9 VCC,
at 2 MHz, Q = open 1(2)
mA
VCC = 1.8V, C = 0.1V
CC or 0.9 VCC,
at 5 MHz, Q = open 2(3)
ICC0(4) Supply current
(Write) VCC = 1.8 V, during tW, S = VCC 3mA
ICC1
Supply current
(Standby) VCC = 1.8 V, S = VCC, VIN = VSS or VCC 1(5) µA
VIL Input low voltage 1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V
VIH Input high voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 V
VOL Output low voltage IOL = 0.15 mA, VCC = 1.8 V 0.3 V
VOH Output high voltage IOH = –0.1 mA, VCC = 1.8 V 0.8 VCC V
1. If the application uses the M95256-R and M95256-DR devices at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, please refer
to Table 16: DC characteristics (M95256-W, device grade 6), rather than to the above table.
2. Value tested only for previous M95256 devices identified by process letter A.
3. Only the M95256 devices identified by process letter K.
4. Characterized only, not tested in production.
5. 3 µA for previous M95256 devices identified by process letter A.
DC and AC parameters M95256-W M95256-R M95256-DR M95256-DF
36/53 Doc ID 12276 Rev 19
Table 18. DC characteristics (M95256-DF, device grade 6)
Symbol Parameter Test conditions(1) Min. Max. Unit
ILI
Input leakage
current VIN = VSS or VCC ± 2 µA
ILO
Output leakage
current S = VCC, voltage applied on Q = VSS or VCC ± 2 µA
ICC
Supply current
(Read)
VCC = 1.7V, C = 0.1V
CC or 0.9 VCC,
at 5 MHz, Q = open 2mA
ICC0(2) Supply current
(Write) VCC = 1.7 V, during tW, S = VCC 3mA
ICC1
Supply current
(Standby) VCC = 1.7 V, S = VCC, VIN = VSS or VCC 1µA
VIL Input low voltage 1.7 V ≤ VCC < 2.5 V –0.45 0.25 VCC V
VIH Input high voltage 1.7 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 V
VOL Output low voltage IOL = 0.15 mA, VCC = 1.7 V 0.3 V
VOH Output high voltage IOH = –0.1 mA, VCC = 1.7 V 0.8 VCC V
1. If the application uses the M95256-DF devices at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, please refer to Table 16: DC
characteristics (M95256-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.
M95256-W M95256-R M95256-DR M95256-DF DC and AC parameters
Doc ID 12276 Rev 19 37/53
Table 19. AC characteristics (M95256-W, device grade 6)
Test conditions specified in
Table 9 and Ta b l e 12
Previous(1)
and new
products CL =
100 pF
1. Previous products are identified by process letters AB.
New products(2)
CL = 30 pF
2. New products are M95256 devices identified by process letter K.
Unit
Vcc ≥ 2.5V Vcc ≥ 4.5V
Symbol Alt. Parameter Min. Max. Min. Max. Min. Max.
fCfSCK Clock frequency D.C. 5 D.C. 10 D.C. 20 MHz
tSLCH tCSS1 S active setup time 90 30 15 ns
tSHCH tCSS2 S not active setup time 90 30 15 ns
tSHSL tCS S deselect time 100 40 20 ns
tCHSH tCSH S active hold time 90 30 15 ns
tCHSL S not active hold time 90 30 15 ns
tCH (3)
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
tCLH Clock high time 90 40 20 ns
tCL (3) tCLL Clock low time 90 40 20 ns
tCLCH (3) tRC Clock rise time 1 2 2 µs
tCHCL (3) tFC Clock fall time 1 2 2 µs
tDVCH tDSU Data in setup time 20 10 5 ns
tCHDX tDH Data in hold time 30 10 10 ns
tHHCH
Clock low hold time after
HOLD not active 70 30 15 ns
tHLCH
Clock low hold time after
HOLD active 40 30 15 ns
tCLHL
Clock low setup time
before HOLD active 000ns
tCLHH
Clock low setup time
before HOLD not active 000ns
tSHQZ (4)
4. Characterized only, not tested in production.
tDIS Output disable time 100 40 20 ns
tCLQV tVClock low to output valid 60 40 20 ns
tCLQX tHO Output hold time 0 0 0 ns
tQLQH (4) tRO Output rise time 50 20 10 ns
tQHQL (4) tFO Output fall time 50 20 10 ns
tHHQV tLZ
HOLD high to output
valid 50 40 20 ns
tHLQZ (4) tHZ
HOLD low to output
High-Z 100 40 20 ns
tWtWC Write time 5 5 5 ms
DC and AC parameters M95256-W M95256-R M95256-DR M95256-DF
38/53 Doc ID 12276 Rev 19
Table 20. AC characteristics (M95256-R, M95256-DR device grade 6)
Test conditions specified in Table 10 and Ta ble 1 2
Symbol Alt. Parameter
Previous
products
(1)
New products (2)
UnitVcc ≥ 1.8V Vcc ≥ 2.5V Vcc ≥ 4.5V
Min. Max. Min. Max. Min. Max. Min. Max.
fCfSCK Clock frequency 2 5 10 20 MHz
tSLCH tCSS1 S active setup time 200 60 30 15 ns
tSHCH tCSS2 S not active setup time 200 60 30 15 ns
tSHSL tCS S deselect time 200 90 40 20 ns
tCHSH tCSH S active hold time 200 60 30 15 ns
tCHSL S not active hold time 200 60 30 15 ns
tCH (3) tCLH Clock high time 200 80 40 20 ns
tCL(3) tCLL Clock low time 200 80 40 20 ns
tCLCH(4) tRC Clock rise time 1 2 2 2 µs
tCHCL(4) tFC Clock fall time 1 2 2 2 µs
tDVCH tDSU Data in setup time 40 20 10 5 ns
tCHDX tDH Data in hold time 50 20 10 10 ns
tHHCH Clock low hold time after HOLD not active 140 60 30 15 ns
tHLCH Clock low hold time after HOLD active 90 60 30 15 ns
tCLHL Clock low setup time before HOLD active 0 0 0 0 ns
tCLHH Clock low setup time before HOLD not active 0 0 0 0 ns
tSHQZ(4) tDIS Output disable time 250 80 40 20 ns
tCLQV tVClock low to output valid 150 80 40 20 ns
tCLQX tHO Output hold time 0 0 0 0 ns
tQLQH(4) tRO Output rise time 100 20 20 10 ns
tQHQL(4) tFO Output fall time 100 20 20 10 ns
tHHQV tLZ HOLD high to output valid 100 80 40 20 ns
tHLQZ(4) tHZ HOLD low to output High-Z 250 80 40 20 ns
tWtWC Write time 5555ms
1. Previous products are identified by process letters AB.
2. New products are the M95256 devices identified by process letter K.
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
4. Characterized only, not tested in production.
M95256-W M95256-R M95256-DR M95256-DF DC and AC parameters
Doc ID 12276 Rev 19 39/53
Table 21. AC characteristics (M95256-DF device grade 6)
Test conditions specified in Tabl e 10 and Tabl e 12(1)
Parameter
Vcc ≥ 1.7 V Vcc ≥ 2.5 V Vcc ≥ 4.5 V
Unit
Min. Max. Min. Max. Min. Max.
fCfSCK Clock frequency 5 10 20 MHz
tSLCH tCSS1 S active setup time 60 30 15 ns
tSHCH tCSS2 S not active setup time 60 30 15 ns
tSHSL tCS S deselect time 90 40 20 ns
tCHSH tCSH S active hold time 60 30 15 ns
tCHSL S not active hold time 60 30 15 ns
tCH (2) tCLH Clock high time 80 40 20 ns
tCL(3) tCLL Clock low time 80 40 20 ns
tCLCH(3) tRC Clock rise time 2 2 2 µs
tCHCL(4) tFC Clock fall time 2 2 2 µs
tDVCH tDSU Data in setup time 20 10 5 ns
tCHDX tDH Data in hold time 20 10 10 ns
tHHCH Clock low hold time after HOLD not active 60 30 15 ns
tHLCH Clock low hold time after HOLD active 60 30 15 ns
tCLHL Clock low setup time before HOLD active 0 0 0 ns
tCLHH Clock low setup time before HOLD not active 0 0 0 ns
tSHQZ(4) tDIS Output disable time 80 40 20 ns
tCLQV tVClock low to output valid 80 40 20 ns
tCLQX tHO Output hold time 0 0 0 ns
tQLQH(4) tRO Output rise time 20 20 10 ns
tQHQL(4) tFO Output fall time 20 20 10 ns
tHHQV tLZ HOLD high to output valid 80 40 20 ns
tHLQZ(4) tHZ HOLD low to output High-Z 80 40 20 ns
tWtWC Write time 5 5 5 ms
1. Preliminary data.
2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
3. Characterized only, not tested in production.
DC and AC parameters M95256-W M95256-R M95256-DR M95256-DF
40/53 Doc ID 12276 Rev 19
Figure 20. Serial input timing
Figure 21. Hold timing
C
D
AI01447d
S
MSB IN
Q
tDVCH
High impedance
LSB IN
tSLCH
tCHDX
tCLCH
tSHCH
tSHSL
tCHSHtCHSL tCH
tCL
tCHCL
C
Q
AI01448c
S
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ
M95256-W M95256-R M95256-DR M95256-DF DC and AC parameters
Doc ID 12276 Rev 19 41/53
Figure 22. Serial output timing
C
Q
AI01449f
S
D
ADDR
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCHCL
tCLQX
tCLQV
tSHSL
tCLCH
Package mechanical data M95256-W M95256-R M95256-DR M95256-DF
42/53 Doc ID 12276 Rev 19
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
ccc 0.100 0.0039
D 4.900 4.800 5.000 0.1929 0.1890 0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 - - 0.0500 - -
h 0.250 0.500 0.0098 0.0197
k 0°8° 0°8°
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M95256-W M95256-R M95256-DR M95256-DF Package mechanical data
Doc ID 12276 Rev 19 43/53
Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package
outline
1. Drawing is not to scale.
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 23. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K (rev MC) 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
eee(2)
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 0.0031
$
%
:7?-%E6
!
!
EEE
,
E B
$
,
%
,
0IN
+
Package mechanical data M95256-W M95256-R M95256-DR M95256-DF
44/53 Doc ID 12276 Rev 19
Figure 25. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 24. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 - - 0.0256 - -
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
N8 8
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
M95256-W M95256-R M95256-DR M95256-DF Package mechanical data
Doc ID 12276 Rev 19 45/53
Figure 26. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline
1. Drawing is not to scale.
8
AAA
7AFERBACKSIDE
$
%
3IDEVIEW
$ETAIL!
!
!
E
E
E
'
&
"UMPSSIDE
&
$ETAIL!
2OTATED
"UMP
EEE !
3EATINGPLANE
#G?-%?6
E
B
BBB
:
:
8
CCC- 9
:
DDD-
89
:
:
2EFERENCE
/RIENTATION
(
Package mechanical data M95256-W M95256-R M95256-DR M95256-DF
46/53 Doc ID 12276 Rev 19
Table 25. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package
mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 0.540 0.500 0.580 0.0213 0.0197 0.0228
A1 0.190 0.0075
A2 0.350 0.0138
b 0.270 0.0106
D 1.271 1.291 0.0500 0.0508
E 1.358 1.378 0.0535 0.0543
e 0.800 0.0315
e1 0.693 0.0273
e2 0.400 0.0157
e3 0.400 0.0157
F 0.333 0.0131
G 0.235 0.0093
H 0.236 0.0093
N (number of terminals) 8 8
aaa 0.11 0.0043
bbb 0.11 0.0043
ccc 0.11 0.0043
ddd 0.06 0.0024
eee 0.06 0.0024
M95256-W M95256-R M95256-DR M95256-DF Part numbering
Doc ID 12276 Rev 19 47/53
11 Part numbering
Table 26. Ordering information scheme
Example: M95256-D W MN 6 T P /K
Device type
M95 = SPI serial access EEPROM
Device function
256 = 256 Kbit
Device family
Blank = without Identification page
D =With additional Identification page
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (MLP8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)
Process(1)
1. The process letters apply to WLCSP devices only. The process letters appear on the device package
(marking) and on the shipment box. Please contact your nearest ST Sales Office for further information.
/K= Manufacturing technology code
Revision history M95256-W M95256-R M95256-DR M95256-DF
48/53 Doc ID 12276 Rev 19
12 Revision history
Table 27. Document revision history
Date Revision Changes
17-Nov-1999 2.1 New -V voltage range added (including the tables for DC characteristics,
AC characteristics, and ordering information).
07-Feb-2000 2.2 New -V voltage range extended to M95256 (including AC characteristics,
and ordering information).
22-Feb-2000 2.3 tCLCH and tCHCL, for the M95xxx-V, changed from 1μs to 100ns
15-Mar-2000 2.4 -V voltage range changed to 2.7-3.6V
29-Jan-2001 2.5
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Illustrations and Package Mechanical data updated
12-Jun-2001 2.6
Correction to header of Table 12B
TSSOP14 Illustrations and Package Mechanical data updated
Document promoted from Preliminary Data to Full Data Sheet
08-Feb-2002 2.7 Announcement made of planned upgrade to 10 MHz clock for the 5V, –40
to 85°C, range.
09-Aug-2002 2.8 M95128 split off to its own datasheet. Data added for new and forthcoming
products, including availability of the SO8 narrow package.
24-Feb-2003 2.9 Omission of SO8 narrow package mechanical data remedied
26-Jun-2003 2.10 -V voltage range removed
21-Nov-2003 3.0 Table of contents, and Pb-free options added. -S voltage range extended
to -R. VIL(min) improved to –0.45V
17-Mar-2004 4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) changed.
Soldering temperature information clarified for RoHS compliant devices.
Device grade information clarified
21-Oct-2004 5.0
M95128 datasheet merged back in. Product List summary table added.
AEC-Q100-002 compliance. Device Grade information clarified. tHHQX
corrected to tHHQV. 10MHz product becomes standard
M95256-W M95256-R M95256-DR M95256-DF Revision history
Doc ID 12276 Rev 19 49/53
13-Apr-2006 6
M95128 part numbers removed from document. PDIP8 package removed.
Delivery state paragraph added.
Section 3.8: Operating supply voltage (VCC) added and information
removed below Section 4: Operating features.
Power up state removed below Section 6: Delivery state.
Figure 18: SPI modes supported modified and Note 2 added.
Note 1 added to Ta b l e 8 .
ICC1 specified over the whole VCC range and ICC0 added in Ta b l e 1 4 ,
Ta bl e 1 5 and Ta b le 1 6 . ICC specified over the whole VCC range in
Ta bl e 1 4 .
Table 17: AC Characteristics (M95256, Device Grade 6) added.
tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively.
Figure 21: Hold timing modified. Process added to Table 25: Ordering
information scheme. Note 1 added to Ta b l e 2 5 .
Note 1 removed from Table 20: AC characteristics (M95256-DR, M95256-
R device grade 6).
TA added to Table 7: Absolute maximum ratings.
Order of sections modified.
15-Oct-2007 7
M95256 with device grade 6 temperature range removed.
Section 3.7: VSS ground added, Section 3.8: Operating supply voltage
(VCC) modified. Small text changes.
Section 5.4: Write Status Register (WRSR), Section 5.5: Read from
Memory Array (READ) and Section 6: Delivery state updated.
Note 2 below Figure 17: Bus master and memory devices on the SPI bus
removed, replaced by explanatory paragraph.
TLEAD added to Table 7: Absolute maximum ratings.
Test conditions modified for ICC0 and ICC1, and VIH min modified in
Table 17: AC characteristics (M95256, device grade 3).
tW modified and “preliminary data” note removed in Tabl e 2 0 : AC
characteristics (M95256-DR, M95256-R device grade 6).
Blank option removed below Plating technology, process A modified and
process V removed in Table 25: Ordering information scheme.
Table 26: Available M95256x products (package, voltage range,
temperature grade) added.
SO8N and SO8W package specifications updated (see Section 10:
Package mechanical data). Package mechanical data: inches calculated
from mm and rounded to 3 decimal digits.
27-Mar-2008 8
Section 3.8: Operating supply voltage (VCC) modified. Small text
changes. Frequency corrected on page 1.
VIL and VIH modified in Table 16: DC characteristics (M95256-R, M95256-
DR, device grade 6).
AB Process added to Table 25: Ordering information scheme.
15-Jul-2008 9
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 10: Package
mechanical data).
Table 27. Document revision history (continued)
Date Revision Changes
Revision history M95256-W M95256-R M95256-DR M95256-DF
50/53 Doc ID 12276 Rev 19
24-Jun-2010 10
M95080 part number added.
Updated Section 3.8: Operating supply voltage (VCC)
Updated Section 4.3: Data protection and protocol control
Updated Section 5.4: Write Status Register (WRSR)
Added note in Section 5.6: Write to Memory Array (WRITE)
Updated Table 7: Absolute maximum ratings
Added Table 20: AC characteristics (M95256-DR, M95256-R device grade
6)
Updated Table 20: AC characteristics (M95256-DR, M95256-R device
grade 6)
07-Sep-2010 11
Updated Section 1: Description.
Updated Section 5.7: Read Identification Page (available only in M95256-
DR devices).
Updated Section 5.8: Write Identification Page.
Updated Section 5.9: Read Lock Status (available only in M95256-DR
devices).
12-Nov-2010 12
Updated Features.
Updated Section 5.8: Write Identification Page.
Added Figure 25: TSSOP8 – 8 lead thin shrink small outline, package
outline.
Added Table 23: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat
package no lead 2 × 3 mm, package mechanical data.
Updated Section 11: Part numbering.
Updated Table 26: Available M95256x products (package, voltage range,
temperature grade).
Updated Figure 25, Figure 26.
22-Mar-2011 13
Deleted:
– SO8 (MW) picture under Features
– SO8 (MW) mechanical dimensions
Updated:
– UFDFPN8 (MB) with UFDFPN8 (MB, MC) picture under Features
– Section 5.6.1: ECC (error correction code) and Write cycling
– Section 7: Connecting to the SPI bus
– Table 7: Absolute maximum ratings
Process letter K substituted with only concerned products (M95256-D and
M95256 in MLP8 package MC).9
(...)
Table 27. Document revision history (continued)
Date Revision Changes
M95256-W M95256-R M95256-DR M95256-DF Revision history
Doc ID 12276 Rev 19 51/53
22-Mar-2011 13
(...)
– Rephrased “test condition” text in:
Table 14: DC characteristics (M95256, device grade 3)
Table 20: DC characteristics (current M95080-W products)
Table 16: DC characteristics (M95256-W, device grade 3)
Table 23: DC characteristics (current and new M95080-R and M95080-
DR products)
Table 18: AC characteristics (M95256, device grade 3)
Table 31: AC characteristics, M95080-W, device grade 6
Table 20: AC characteristics (M95256-W, device grade 3)
Table 36: AC characteristics (M95080-R, M95080-DR device grade 6)
Added:
– Caution under Figure 3: WLCSP connections (top view, marking side,
with balls on the underside)
– MC = UFDFPN8 package in Section 11: Part numbering
20-May-2011 14
Updated:
– UFDFPN8 offered in only one package version
Added:
– Table 15: Memory cell characteristics
19-Jul-2011 15 MC package added (UFDFPN8)
23-Nov-2011 16
Updated:
– Footnote 3 below Table 7: Absolute maximum ratings
– Footnotes 1, 2, 4, 5 below Table 15: DC characteristics (M95256-W,
device grade 6)
– Footnotes 1, 2, 3, 5 below Table 17: DC characteristics (M95256-R,
M95256-DR, device grade 6)
–Table 19: AC characteristics, M95256-W, device grade 6 headings,
TQLQH and TQHQL values. One footnote removed and one added
–Table 21: AC characteristics (M95256-DR, M95256-R device grade 6),
new columns for new pairs of products. Footnote 2 edited.
17-Jan-2012 17 Updated Figure 25: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat
no lead, package outline.
Table 27. Document revision history (continued)
Date Revision Changes
Revision history M95256-W M95256-R M95256-DR M95256-DF
52/53 Doc ID 12276 Rev 19
21-Jun-2012 18
Datasheet split into:
– M95256-125 datasheet for automotive products (range 3),
– M95256-W, M95256-R, M95256-DR, M95256-DF (this datasheet) for
standard products (range 6).
Added:
– 1.7 V device (M95256-DF)
Updated:
–Figure 4: Block diagram
–Table 25: M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale
package mechanical data and Figure 26: M95256-DFCS6TP/K,
WLCSP 8-bump wafer-level chip scale package outline
– Cycling and data retention values (Ta bl e 1 4 and Ta bl e 1 5 )
Deleted:
– UFDFPN8 package rev MB
24-Jul-2012 19
Updated:
– WLCSP package reference from “CT” to “CS”
–Figure 3: WLCSP connections (top view, marking side, with balls on the
underside)
–Figure 26: M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale
package outline
Table 27. Document revision history (continued)
Date Revision Changes
M95256-W M95256-R M95256-DR M95256-DF
Doc ID 12276 Rev 19 53/53
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2012 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com