74AHCT08BQ,115 - NEXPERIA

74AHC08; 74AHCT08

Quad 2-input AND gate

Rev. 4 — 26 May 2020 Product data sheet

1. General description

The 74AHC08; 74AHCT08 are quad 2-input AND gates. Inputs are overvoltage tolerant. This

feature allows the use of these devices as translators in mixed voltage environments.

2. Features and benefits

•Wide supply voltage range from 2.0 V to 5.5 V

•Input levels:

•For 74AHC08: CMOS level

•For 74AHCT08: TTL level

•Balanced propagation delays

•All inputs have a Schmitt-trigger action

•Overvoltage tolerant inputs to 5.5 V

•High noise immunity

•CMOS low power dissipation

•ESD protection:

•HBM EIA/JESD22-A114E exceeds 2000 V

•MM EIA/JESD22-A115-A exceeds 200 V

•CDM EIA/JESD22-C101C exceeds 1000 V

•Latch-up performance exceeds 100 mA per JESD 78 Class II Level A

•Multiple package options

•Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74AHC08D

74AHCT08D

-40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74AHC08PW

74AHCT08PW

-40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74AHC08BQ

74AHCT08BQ

-40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal

enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 × 3 × 0.85 mm

SOT762-1

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

4. Functional diagram

mna222

1B 1Y

2B 2Y

3B 3Y

4B 4Y

12 11

Fig. 1. Logic symbol

mna223

Fig. 2. IEC logic symbol

mna221

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74AHC08

74AHCT08

1A VCC

1B 4B

1Y 4A

2A 4Y

2B 3B

2Y 3A

GND 3Y

aaa-031693

7 8

Fig. 4. Pin configuration SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

aaa-031694

74AHC08

74AHCT08

GND(1)

Transparent top view

2Y 3A

2B 3B

2A 4Y

1Y 4A

1B 4B

GND

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND

Fig. 5. Pin configuration SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol Pin Description

1A, 2A, 3A, 4A 1, 4, 9, 12 data inputs

1B, 2B, 3B, 4B 2, 5, 10, 13 data inputs

1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data outputs

GND 7 ground (0 V)

VCC 14 supply voltage

Product data sheet Rev. 4 — 26 May 2020 2 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

6. Functional description

Table 3. Function selection

H = HIGH voltage level; L = LOW voltage level; X = don’t care

Input Output

nA nB nY

L X L

X L L

HHH

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +7.0 V

VIinput voltage -0.5 +7.0 V

IIK input clamping current VI < -0.5 V [1] -20 - mA

IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA

IOoutput current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA

ICC supply current - 75 mA

IGND ground current -75 - mA

Tstg storage temperature -65 +150 °C

Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 500 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.

For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.

For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

74AHC08 74AHCT08Symbol Parameter Conditions

Min Typ Max Min Typ Max

Unit

VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V

VIinput voltage 0 - 5.5 0 - 5.5 V

VOoutput voltage 0 - VCC 0 - VCC V

Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C

VCC = 3.3 V ± 0.3 V - - 100 - - - ns/VΔt/ΔV input transition rise and

fall rate VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V

Product data sheet Rev. 4 — 26 May 2020 3 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

9. Static characteristics

Table 6. Static characteristics

Voltages are referenced to GND (ground = 0 V).

25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

74AHC08

VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V

VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V

VIH HIGH-level

input voltage

VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V

VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V

VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V

VIL LOW-level

input voltage

VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V

VI = VIH or VIL

IO = -50 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = -50 μA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V

IO = -50 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = -4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.4 - V

VOH HIGH-level

output voltage

IO = -8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.7 - V

VI = VIH or VIL

IO = 50 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 50 μA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 50 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V

VOL LOW-level

output voltage

IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current

VI = 5.5 V or GND;

VCC = 0 V to 5.5 V

- - 0.1 - 1.0 - 2.0 μA

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 5.5 V

- - 2.0 - 20 - 40 μA

CIinput

capacitance

- 3.0 10 - 10 - 10 pF

74AHCT08

VIH HIGH-level

input voltage

VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V

VIL LOW-level

input voltage

VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V

VI = VIH or VIL; VCC = 4.5 V

IO = -50 μA 4.4 4.5 - 4.4 - 4.4 - V

VOH HIGH-level

output voltage

IO = -8.0 mA 3.94 - - 3.8 - 3.7 - V

VI = VIH or VIL; VCC = 4.5 V

IO = 50 μA - 0 0.1 - 0.1 - 0.1 V

VOL LOW-level

output voltage

IO = 8.0 mA - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current

VI = 5.5 V or GND;

VCC = 0 V to 5.5 V

- - 0.1 - 1.0 - 2.0 μA

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 5.5 V

- - 2.0 - 20 - 40 μA

Product data sheet Rev. 4 — 26 May 2020 4 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

ΔICC additional

supply current

per input pin;

VI = VCC - 2.1 V; IO = 0 A;

other pins at VCC or GND;

VCC = 4.5 V to 5.5 V

- - 1.35 - 1.5 - 1.5 mA

CIinput

capacitance

- 3.0 10 - 10 - 10 pF

10. Dynamic characteristics

Table 7. Dynamic characteristics

GND = 0 V; For test circuit see Fig. 7.

25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ[1] Max Min Max Min Max

Unit

74AHC08

nA, nB to nY; see Fig. 6 [2]

VCC = 3.0 V to 3.6 V

CL = 15 pF - 4.0 8.8 1.0 10.5 1.0 11.0 ns

CL = 50 pF - 5.6 12.3 1.0 14 1.0 15.5 ns

VCC = 4.5 V to 5.5 V

CL = 15 pF - 3.0 5.9 1.0 7.0 1.0 7.5 ns

tpd propagation

delay

CL = 50 pF 4.2 7.9 1.0 9.0 1.0 10.0 ns

CPD power

dissipation

capacitance

CL = 50 pF; fi = 1 MHz;

VI = GND to VCC

[3] - 10.0 - - - - - pF

74AHCT08

nA, nB to nY; see Fig. 6 [2]

VCC = 4.5 V to 5.5 V

CL = 15 pF - 3.2 6.9 1.0 8.0 1.0 9.0 ns

tpd propagation

delay

CL = 50 pF - 4.2 7.9 1.0 9.0 1.0 10.0 ns

CPD power

dissipation

capacitance

CL = 50 pF; fi = 1 MHz;

VI = GND to VCC

[3] - 12.0 - - - - - pF

[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).

[2] tpd is the same as tPLH and tPHL.

[3] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC

2 x fi x N + Σ(CL x VCC

2 x fo) where:

fi = input frequency in MHz, fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL x VCC

2 x fo) = sum of the outputs.

Product data sheet Rev. 4 — 26 May 2020 5 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

10.1. Waveform and test circuit

mna224

nA, nB input

nY output

tPLH

tPHL

GND

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 6. The input (nA, nB) to output (nY) propagation delays

Table 8. Measurement points

Input OutputType

VMVM

74AHC08 0.5VCC 0.5VCC

74AHCT08 1.5 V 0.5VCC

001aah768

negative

pulse

GND

positive

pulse

GND

10 %

90 %

10 %

VMVM

VCC

DUT

VIVO

Test data is given in Table 9.

Definitions test circuit:

RT = termination resistance should be equal to output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Fig. 7. Test circuit for measuring switching times

Table 9. Test data

Input LoadType

VItr, tfCL

Test

74AHC08 VCC ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL

74AHCT08 3.0 V ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL

Product data sheet Rev. 4 — 26 May 2020 6 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

11. Package outline

UNIT A

max. A

1 A

2 A

3 b

p c D

(1) E

(1) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

w M

detail X

v M A

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.35

0.34

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.024

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Fig. 8. Package outline SOT108-1 (SO14)

Product data sheet Rev. 4 — 26 May 2020 7 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

UNIT A

1 A

2 A

3 b

p c D

(1) E (2) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.72

0.38

0.13 0.1 0.2 1

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

w M

0.25

1 7

14 8

detail X

(A )

v M A

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Fig. 9. Package outline SOT402-1 (TSSOP14)

Product data sheet Rev. 4 — 26 May 2020 8 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT762-1 MO-241

sot762-1_po

15-04-10

15-05-05

Unit

max

nom

min

1 0.05 3.1 1.65 2.6

0.5 2 0.4

A(1)

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1

A1b

0.30

c D(1) DhE(1) Eh

1.00

e e1k

L v

0.1

w y

0.02 0.2 3.0 1.50 2.5 0.10.25 0.05 0.05

0.30.85 0.20.00 2.9 1.35 2.40.18

0.51.15

0 4 mm2

scale

terminal 1

index area

AA1

2 6

13 9

terminal 1

index area

AC B

detail X

Fig. 10. Package outline SOT762-1 (DHVQFN14)

Product data sheet Rev. 4 — 26 May 2020 9 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

12. Abbreviations

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

CDM Charged Device Model

TTL Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AHC_AHCT08 v.4 20200526 Product data sheet - 74AHC_AHCT08 v.3

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

•Section 1 and Section 2 updated.

•Section 7: Derating values for Ptot total power dissipation have been updated.

•Fig. 7: Test circuit corrected (Errata).

•Package outline drawing of SOT762-1 (Fig. 10) updated.

74AHC_AHCT08 v.3 20071114 Product data sheet - 74AHC_AHCT08 v.2

Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 3: DHVQFN14 package added.

•Section 7: derating values added for DHVQFN14 package.

•Section 11: outline drawing added for DHVQFN14 package.

74AHC_AHCT08 v.2 19990924 Product specification - 74AHC_AHCT08 v.1

74AHC_AHCT08 v.1 19981218 Product specification - -

Product data sheet Rev. 4 — 26 May 2020 10 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

14. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

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the Absolute Maximum Ratings System of IEC 60134) will cause permanent

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Notice: All referenced brands, product names, service names and

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Product data sheet Rev. 4 — 26 May 2020 11 / 12

Nexperia 74AHC08; 74AHCT08

Quad 2-input AND gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................2

5.1. Pinning.........................................................................2

5.2. Pin description............................................................. 2

6. Functional description................................................. 3

7. Limiting values............................................................. 3

8. Recommended operating conditions..........................3

9. Static characteristics....................................................4

10. Dynamic characteristics............................................ 5

10.1. Waveform and test circuit.......................................... 6

11. Package outline.......................................................... 7

12. Abbreviations............................................................ 10

13. Revision history........................................................10

14. Legal information......................................................11

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 26 May 2020

Product data sheet Rev. 4 — 26 May 2020 12 / 12