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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D500-mA-Rated Collector Current
(Single Output)
DHigh-Voltage Outputs ...50 V
DOutput Clamp Diodes
DInputs Compatible With Various Types of
Logic
DRelay-Driver Applications
description/ordering information
The ULN2004AI is a high-voltage, high-current
Darlington transistor array. This device consists
of seven npn Darlington pairs that feature
high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current
rating of a single Darlington pair is 500 mA. The Darlington pairs can be paralleled for higher-current capability.
Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line
drivers, and logic buffers.
The ULN2004AI has a 10.5-kΩ series base resistor for each Darlington pair for operation directly with TTL or
5-V CMOS devices.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP (N) Tube of 25 ULN2004AIN ULN2004AIN
−40°C to 105°C
SOIC (D)
Tube of 40 ULN2004AID
ULN2004AI
−40°C to 105°C
SOIC (D)
Reel of 2500 ULN2004AIDR
ULN2004AI
SOP (NS) Reel of 2000 ULN2004AINSR ULN2004AI
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
D, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
2B
3B
4B
5B
6B
7B
E
1C
2C
3C
4C
5C
6C
7C
COM
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
SLRS055 − APRIL 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram
7C
6C
5C
4C
3C
2C
1C
COM
7
6
5
4
3
2
1
7B
6B
5B
4B
3B
2B
1B
10
11
12
13
14
15
16
9
schematics (each Darlington pair)
Output
C
COM
E
7.2 kΩ3 kΩ
10.5 kΩ
Input
B
All resistor values shown are nominal.
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absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)†
Collector-emitter voltage 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clamp diode reverse voltage (see Note 1) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (see Note 1) 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak collector current (see Notes 2 and 4) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total emitter-terminal current −2.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −40°C to 105°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 2 and 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
electrical characteristics, TA = 25°C
PARAMETER TEST
FIGURE TEST CONDITIONS MIN TYP MAX UNIT
IC = 125 mA 5
VI(on)
On-state input voltage
6
VCE = 2 V
IC = 200 mA 6
V
VI(on) On-state input voltage 6 VCE = 2 V IC = 275 mA 7V
IC = 350 mA 8
II = 250 µA, IC = 100 mA 0.9 1.1
V
CE(sat)
Collector-emitter saturation voltage 5 II = 350 µA, IC = 200 mA 1 1.3 V
VCE(sat)
Collector-emitter saturation voltage
5
II = 500 µA, IC = 350 mA 1.2 1.6
V
ICEX Collector cutoff current 1 VCE = 50 V, II = 0 50 µA
VFClamp forward voltage 8 IF = 350 mA 1.7 2 V
II
Input current
4
VI = 5 V 0.35 0.5
mA
IIInput current 4 VI = 12 V 1 1.45 mA
IRClamp reverse current 7 VR = 50 V 50 µA
CiInput capacitance VI = 0, f = 1 MHz 15 25 pF
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4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, TA = −40°C to 105°C
PARAMETER TEST
FIGURE TEST CONDITIONS MIN TYP MAX UNIT
IC = 125 mA 5
VI(on)
On-state input voltage
6
VCE = 2 V
IC = 200 mA 6
V
VI(on) On-state input voltage 6 VCE = 2 V IC = 275 mA 7V
IC = 350 mA 8
II = 250 µA, IC = 100 mA 0.9 1.1
V
CE(sat)
Collector-emitter saturation voltage 5 II = 350 µA, IC = 200 mA 1 1.3 V
VCE(sat)
Collector-emitter saturation voltage
5
II = 500 µA, IC = 350 mA 1.2 1.6
V
1 VCE = 50 V, II = 0 50
I
CEX
Collector cutoff current
2
VCE = 50 V
II = 0 100 µA
ICEX
Collector cutoff current
2 VCE = 50 V VI = 1 V 500
µA
VFClamp forward voltage 8 IF = 350 mA 1.7 2 V
II(off) Off-state input current 3 VCE = 50 V, IC = 500 µA 50 65 µA
II
Input current
4
VI = 5 V 0.35 0.5
mA
IIInput current 4 VI = 12 V 1 1.45 mA
IRClamp reverse current 7 VR = 50 V 100 µA
CiInput capacitance VI = 0, f = 1 MHz 15 25 pF
switching characteristics, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output See Figure 8 0.25 1 µs
tPHL Propagation delay time, high- to low-level output See Figure 8 0.25 1 µs
VOH High-level output voltage after switching VS = 50 V,
See Figure 9 IO ≈ 300 mA, VS − 20 mV
switching characteristics, TA = −40°C to 105°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output See Figure 8 1 10 µs
tPHL Propagation delay time, high- to low-level output See Figure 8 1 10 µs
VOH High-level output voltage after switching VS = 50 V,
See Figure 9 IO ≈ 300 mA, VS − 500 mV
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PARAMETER MEASUREMENT INFORMATION
Open VCE
Open
ICEX
Figure 1. ICEX Test Circuit
Open VCE
VI
ICEX
Figure 2. ICEX Test Circuit
Open VCE
IC
II(off)
Figure 3. II(off) Test Circuit
Open
Open
II(on)
VI
Figure 4. II Test Circuit
Open
VCE IC
II
hFE = IC
II
NOTE: II is fixed for measuring VCE(sat), variable for
measuring hFE.
Figure 5. h
FE
, V
CE(sat)
Test Circuit
Open
VCE IC
VI(on)
Figure 6. VI(on) Test Circuit
VR
Open
IR
Figure 7. IR Test Circuit
IF
VF
Open
Figure 8. VF Test Circuit
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PARAMETER MEASUREMENT INFORMATION
50% 50%
50% 50%
tPHL
VOLTAGE WAVEFORMS
Input
tPLH
Figure 9. Propagation Delay-Time Waveforms
Output
Input Open
VS
200 Ω
Output
CL = 15 pF
(see Note B)
90% 90%
1.5 V 1.5 V
10% 10%
40 µs
≤10 ns
≤5 ns VIH
(see Note C)
0 V
VOH
VOL
Input
Output
TEST CIRCUIT
VOLTAGE WAVEFORMS
1N3064 2 mH
Pulse
Generator
(see Note A)
NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. For testing, VIH = 3 V
Figure 10. Latch-Up Test Circuit and Voltage Waveforms
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TYPICAL CHARACTERISTICS
Figure 11
COLLECTOR-EMITTER
SATURATION VOLTAGE
vs
COLLECTOR CURRENT
(ONE DARLINGTON)
0
IC − Collector Current − mA
2.5
800
0100 200 300 400 500 600 700
0.5
1
1.5
2
II = 350 µA
II = 500 µA
VCE(sat) − Collector-Emitter Saturation Voltage − V
VCE(sat)
TA = 25°C
II = 250 µA2
1.5
1
0.5
700600500400300200100
0800
2.5
IC(tot) − Total Collector Current − mA
0
COLLECTOR-EMITTER
SATURATION VOLTAGE
vs
TOTAL COLLECTOR CURRENT
(TWO DARLINGTONS IN PARALLEL)
VCE(sat) − Collector-Emitter Saturation Voltage − VVCE(sat)
II = 250 µA
II = 350 µA
II = 500 µA
TA = 25°C
Figure 12
COLLECTOR CURRENT
vs
INPUT CURRENT
0
II − Input Current − µA
500
200
025 50 75 100 125 150 175
50
100
150
200
250
300
350
400
450
VS = 10 V
VS = 8 V
IC − Collector Current − mA
C
I
RL = 10 Ω
TA = 25°C
Figure 13
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APPLICATION INFORMATION
Lam
p
Test
TTL
Output
V
CC
V
1
2
3
4
5
6
9
10
11
12
13
14
15
16
8
7
Figure 14. TTL to Load
V
CC
V
RP
1
2
3
4
5
6
9
10
11
12
13
14
15
16
8
TTL
Output
7
Figure 15. Use of Pullup Resistors
to Increase Drive Current
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ULN2004AID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ULN2004AIDE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ULN2004AIDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ULN2004AIDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ULN2004AIDRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ULN2004AIDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ULN2004AIN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
ULN2004AINE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
ULN2004AINSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ULN2004AINSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ULN2004AINSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 1
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ULN2004AIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
ULN2004AINSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ULN2004AIDR SOIC D 16 2500 333.2 345.9 28.6
ULN2004AINSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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