LMF40CIN-50NOPB - National Semiconductor

TL/H/10557

LMF40 High Performance 4th-Order Switched-Capacitor

Butterworth Low-Pass Filter

December 1994

LMF40 High Performance 4th-Order

Switched-Capacitor Butterworth Low-Pass Filter

General Description

The LMF40 is a versatile, easy to use, precision 4th-order

Butterworth low-pass filter fabricated using National’s high

performance LMCMOS process. Switched-capacitor tech-

niques eliminate external component requirements and al-

low a clock-tunable cutoff frequency. The ratio of the clock

frequency to the low-pass cutoff frequency is internally set

to 50-to-1 (LMF40-50) or 100-to-1 (LMF40-100). A Schmitt

trigger clock input stage allows two clocking options, either

self-clocking (via an external resistor and capacitor) for

stand-alone applications, or for tighter cutoff frequency con-

trol, an external TTL or CMOS logic compatible clock can

be applied. The maximally flat passband frequency re-

sponse together with a DC gain of 1 V/V allows cascading

LMF40 sections together for higher-order filtering.

Features

YCutoff frequency range of 0.1 Hz to 40 kHz

YCutoff frequency accuracy of g1.0%, maximum

YLow offset voltage, g100 mV, maximum, g5V supply

YLow clock feedthrough of 5 mVP-P, typical

YDynamic range of 88 dB, typical

YNo external components required

Y8-pin mini-DIP or 14-pin wide-body small-outline pack-

ages

Y4V to 14V single/dual supply operation

YCutoff frequency set by external or internal clock

YPin-compatible with MF4

Applications

YCommunication systems

YInstrumentation

YAutomated control systems

Block and Connection Diagrams

TL/H/10557–1

*Pin numbers in parentheses are for the 14-pin package

Ordering Information

Industrial (b40§CsTAsa85§C) Package

LMF40CIN-50, LMF40CIN-100 N08E

LMF40CIWM-50 M14B

LMF40CIWM-100 M14B

Military (b55§CsTAsa125§C)

LMF40CMJ-50, LMF40CMJ-100 J08A

Dual-In-Line Package

TL/H/10557–2

Top View

Small-Outline-Wide-Body Package

TL/H/10557–3

Top View

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

(Notes1&2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (Va–Vb) 15V

Voltage at Any Pin Vbb0.2V to Vaa0.2V

Input Current at Any Pin (Note 13) 5 mA

Package Input Current (Note 13) 20 mA

Power Dissipation (Note 14) 500 mW

Storage Temperature b65§Ctoa

150§C

Lead Temperature

N Package, Soldering (10 sec.) a260§C

J Package, Soldering (10 sec.) a300§C

WM Package, Vapor Phase (60 sec.) (Note 16) a215§C

WM Package, Infrared (15 sec.) a220§C

ESD Susceptibility (Note 12) 2000V

Pin 1 CLK IN 1700V

Operating Ratings (Notes1&2)

Temperature Range TMIN sTAsTMAX

LMF40CIN-50, LMF40CIN-100

LMF40CIWM-50,

LMF40CIWM-100 b40§CsTAsa85§C

LMF40CMJ-50, LMF40CMJ-100 b55§CsTAsa125§C

Supply Voltage Range (VabVb) 4Vto14V

Filter Electrical Characteristics

The following specifications apply for fCLK e500 kHz. Boldface limits apply for TAeTJeTMIN to TMAX:All other limits TA

eTJe25§C.

Symbol Parameter Conditions Typical Limits Units

(Note 10) (Note 11) (Limit)

Vaea

5V, Vbeb

fCLK Clock Frequency Range

(Note 17)

5 Hz (min)

2MHz (max)

ISSupply Current CMJ 3.5 / 7.0 mA (max)

CIN, CIJ, CIWM 3.5 / 5.0 mA (max)

HODC Gain RSource s2kXa

0.05 / a0.05 dB (max)

b0.15 / b0.20 dB (min)

fCLK/fcClock to Cutoff

Frequency Ratio

(Note 3)

LMF40-50 49.80 g0.8% / 49.80 g1.0% (max)

LMF40-100 99.00 g0.8% / 99.00 g1.0% (max)

DfCLK/fc/DT Clock to Cutoff Frequency

Ratio Temperature

Coefficient

LMF40-50 5 ppm/§C

LMF40-100 5 ppm/§C

AMIN Stopband Attenuation At 2 fc24.0 dB (min)

Filter Electrical Characteristics (Continued)

The following specifications apply for fCLK e500 kHz. Boldface limits apply for TAeTJeTMIN to TMAX:All other limits TA

eTJe25§C.

Symbol Parameter Conditions Typical Limits Units

(Note 10) (Note 11) (Limit)

Vaea

5V, Vbeb

5V (Continued)

VOS Unadjusted DC

Offset Voltage

LMF40-50 g80 / g100 mV (max)

LMF40-100 g80 / g100 mV (max)

VOOutput Swing RLe5kXa

3.9 / a3.7 V (min)

b4.2 / b4.0 V (max)

ISC Output Short Circuit Source 90 mA

Current (Note 8) Sink 2.2 mA

Dynamic Range 88 dB

(Note 4)

Additional Magnitude

Response Test Points

(Note 6)

LMF40-50 fIN e12 kHz b7.50 g0.26 / b7.50 g0.30 dB (max)

fIN e9 kHz b1.46 g0.12 / b1.46 g0.16 dB (max)

LMF40-100 fIN e6 kHz b7.15 g0.26 / b7.15 g0.30 dB (max)

fIN e4.5 kHz b1.42 g0.12 / b1.42 g0.16 dB (max)

Clock Feedthrough Filter Output 5mV

P–P

VIN e0V

Filter Electrical Characteristics The following specifications apply for fCLK e250 kHz. Boldface limits

apply for TAeTJeTMIN to TMAX:All other limits TAeTJe25§C.

Symbol Parameter Conditions Typical Limits Units

(Note 10) (Note 11) (Limit)

Vaea

2.5V, Vbeb

2.5V

fCLK Clock Frequency Range

(Note 17)

5 Hz (min)

1.0 MHz (max)

ISSupply Current CMJ 2.1 / 4.0 mA (max)

CIN, CIJ, CIWM 2.1 / 3.0 mA (max)

HODC Gain RSs2kXa

0.05 / a0.05 dB (max)

fCLK e250 kHz b0.15 / b0.20 dB (min)

fCLK e500 kHz b0.1 dB

fCLK/fcClock to Cutoff

Frequency Ratio

LMF40-50 fCLK e250 kHz 49.80 g0.8% (max)

fCLK e500 kHz 49.80

g0.6%

LMF40-100 fCLK e250 kHz 99.00 g1.0% / 99.00 g1.2% (max)

(Note 3) fCLK e500 kHz 99.00

g1.2%

Filter Electrical Characteristics (Continued)

The following specifications apply for fCLK e250 kHz. Boldface limits apply for TAeTJeTMIN to TMAX:All other limits TA

eTJe25§C.

Symbol Parameter Conditions Typical Limits Units

(Note 10) (Note 11) (Limit)

Vaea

2.5V, Vbeb

2.5V (Continued)

DfCLK/fc/DT Clock to Cutoff

Frequency Ratio

Temperature Coefficient

LMF40-50 5 ppm/§C

LMF40-100 5 ppm/§C

AMIN Stopband Attenuation At 2 fcb24.0 dB (min)

VOS Unadjusted DC

Offset Voltage

LMF40-50 g80 / g100 mV (max)

LMF40-100 g80 / g100 mV (max)

VOOutput Swing RLe5kXa

1.4 / a1.2 V (min)

b2.0 / b1.8 V (max)

ISC Output Short Circuit Source 42 mA

Current (Note 8) Sink 0.9 mA

Dynamic Range 81 dB

(Note 4)

Additional Magnitude Response

Test Points (Note 6)

LMF40-50 fIN e6 kHz b7.50 g0.26 / b7.50 g0.30 dB (max)

fIN e4.5 kHz b1.46 g0.12 / b1.46 g0.16 dB (max)

LMF40-100 fIN e3 kHz b7.15 g0.26 / b7.15 g0.30 dB (max)

fIN e2.25 kHz b1.42 g0.12 / b1.42 g0.16 dB (max)

Clock Feedthrough Filter Output 5mV

P–P

VIN e0V

Logic Input-Output Characteristics The following specifications apply for Vbe0V unless otherwise

specified. Boldface limits apply for TAeTJeTMIN to TMAX:all other limits TAeTJe25§C.

Symbol Parameter Conditions Typical Limits Units

(Note 10) (Note 11) (Limit)

TTL CLOCK INPUT, CLK R PIN (Note 9)

TTL CLK R Pin Input Voltage Vaea

Vbeb

Logic ‘‘1’’ 2.0 / 2.1 V (min)

Logic ‘‘0’’ 0.8 / 0.8 V (max)

CLK R Input Voltage Vaea

2.5V

Vbeb

2.5V

Logic ‘‘1’’ 2.0 / 2.0 V (min)

Logic ‘‘0’’ 0.6 / 0.4 V (max)

Maximum Leakage Current 2.0 mA

at CLK R Pin

SCHMITT TRIGGER

VTaPositive Going Input Vaea

10V 6.1 / 6.0 V (min)

Threshold Voltage 8.8 / 8.9 V (max)

CLK IN Pin Vaea

5V 3.0 / 2.9 V (min)

4.3 / 4.4 V (max)

Logic Input-Output Characteristics (Continued) The following specifications apply for Vbe0V unless

otherwise specified. Boldface limits apply for TAeTJeTMIN to TMAX:all other limits TAeTJe25§C.

Symbol Parameter Conditions Typical Limits Units

(Note 10) (Note 11) (Limit)

SCHMITT TRIGGER (Continued)

VTbNegative Going Input Vaea

10V 1.4 / 1.3 V (min)

Threshold Voltage 3.8 / 3.9 V (max)

CLK IN Pin Vaea

5V 0.7 / 0.6 V (min)

1.9 / 2.0 V (max)

VTabV

bHysteresis CLK IN Pin Vaea

10V 2.3 / 2.1 V (min)

7.4 / 7.6 V (max)

Vaea

5V 1.1 / 0.9 V (min)

3.6 / 3.8 V (max)

Logical ‘‘1’’ Output IOeb

10 mA

Voltage CLK R Vaea

10V 9.1 / 9.0 V (min)

Pin Vaea

5V 4.6 / 4.5 V (min)

Logical ‘‘0’’ Output IOeb

10 mA

Voltage CLK R Vaea

10V 0.9 / 1.0 V (max)

Pin Vaea

5V 0.4 / 0.5 V (max)

Output Source Current CLK R to Vb

CLK R Pin Vaea

10V 4.9 / 3.7 mA (min)

Vaea

5V 1.6 / 1.2 mA (min)

Output Sink Current CLK R to Va

CLK R Pin Vaea10V 4.9 / 3.7 mA (min)

Vaea

5V 1.6 / 1.2 mA (min)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating range.

Note 2: All voltages are specified with respect to ground.

Note 3: The filter’s cutoff frequency is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter.

Note 4: For g5V supplies the dynamic range is referenced to 2.62 Vrms (3.7V peak) where the wideband noise over a 20 kHz bandwidth is typically 100 mVrms for

the LMF40. For g2.5V supplies the dynamic range is referenced to 0.849 Vrms (1.2V peak) where the wideband noise over a 20 kHz bandwidth is typically

75 mVrms for the LMF40.

Note 5: The specifications for the LMF40 have been given for a clock frequency (fCLK) of 500 kHz at g5V and 250 kHz at g2.5V. Above this clock frequency the

cutoff frequency begins to deviate from the specified error band of g0.8% over the temperature range, but the filter still maintains its magnitude characteristics.

See Application Information, Section 1.4.

Note 6: The filter’s magnitude response is tested at the cutoff frequency, fc,f

Se2f

, and at these other two additional frequencies.

Note 7: For simplicity all logic levels have been referenced to Vbe0V (except for the TTL input logic levels). The logic levels will scale accordingly for g5V and

g2.5V supplies.

Note 8: The short circuit source current is measured by forcing the output that is being tested to its maximum positive swing and then shorting that output to the

negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage and then shorting that output

to the positive supply. These are worst case conditions.

Note 9: The LMF40 is operated with symmetrical supplies and L. Sh. is tied to ground.

Note 10: Typicals are at TJe25§C and represent the most likely parametric norm.

Note 11: Guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Human body model; 100 pF discharged through a 1.5 kXresistor.

Note 13: When the input voltage (VIN) at any pin exceeds the power supply voltages (VIN kVbor VIN lVa) the absolute value of the current at that pin should

be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four.

Note 14: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX,iJA, and the ambient temperature TA. The

maximum allowable power dissipation is PD e(TJMAX bTA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMF40,

TJMAX e125§C, and the typical junction-to-ambient thermal resistance, when board mounted, is 67§C/W for the LMF40CIN, 62§C/W for the LMF40CIJ and

LMF40CMJ, and 78§C/W for the LMC40CIWM.

Note 15: In popular usage the term cutoff frequency defines that frequency at which a filter’s gain drops 3.01 dB below its DC value. Equations (2) and (3) and

design example 2.1, however, use the term cutoff frequency (fb) to define that frequency at which a filter’s gain drops by a variable amount as determined from the

given design specifications.

Note 16: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices or see the section

titled ‘‘Surface Mount’’ in the

Linear Data Book

Note 17: The nominal ratio of the clock frequency to the low-pass cutoff frequency is internally set to 50-to-1 (LMF40-50) or 100-to-1 (LMF40-100).

Typical Performance Characteristics

vs Power Supply Voltage

fCLK/fcDeviation

vs Temperature

fCLK/fcDeviation

vs Clock Frequency

fCLK/fcDeviation

vs Power Supply Voltage

DC Gain Deviation

vs Temperature

DC Gain Deviation

vs Clock Frequency

DC Gain Deviation

vs Power Supply Voltage

fCLK/fcDeviation

vs Temperature

fCLK/fcDeviation

vs Clock Frequency

fCLK/fcDeviation

vs Power Supply Voltage

DC Gain Deviation

vs Temperature

DC Gain Deviation

vs Clock Frequency

DC Gain Deviation

TL/H/10557–5

Typical Performance Characteristics (Continued)

vs Power Supply Voltage

Power Supply Current

vs Temperature

Power Supply Current

vs Power Supply Voltage

Positive Voltage Swing

vs Power Supply Voltage

Negative Voltage Swing

vs Temperature

Positive Voltage Swing

vs Temperature

Negative Voltage Swing

vs Power Supply Voltage

DC Offset Voltage Deviation

vs Temperature

DC Offset Voltage Deviation

vs Power Supply Voltage

CLK R Trigger Threshold

vs Power Supply Voltage

Schmitt Trigger Threshold

TL/H/10557–6

Pin Descriptions

(Numbers in ( ) are for 14-pin package).

Pin Pin Function

ÝName

1 CLK IN A CMOS Schmitt-trigger input

to be used with an external

(1)

CMOS logic level clock. Also

used for self clocking Schmitt-

trigger oscillator (see Section

1.1).

2 CLK R A TTL logic level clock input

when in split supply operation

(3)

(g2.0V to g7V) with L. Sh

tied to system ground. This pin

becomes a low impedance

output when L. Sh is tied to

Vb. Also used in conjunction

with the CLK IN pin for a self

clocking Schmitt-trigger

oscillator (see Section 1.1).

The TTL input signal must not

exceed the supply voltages by

more than 0.2V.

3 L. Sh Level shift pin; selects the

logic threshold levels for the

(5)

clock. When tied to Vbit

enables an internal TRI-

STATEÉbuffer stage between

the Schmitt trigger and the

internal clock level shift stage

thus enabling the CLK IN

Schmitt-trigger input and

making the CLK R pin a low

impedance output. When the

voltage level at this input

exceeds 25% (VabVb)a

Vbthe internal TRI-STATE

buffer is disabled allowing the

CLK R pin to become the

clock input for the internal

clock level-shift stage. The

CLK R threshold level is now

2V above the voltage on the L.

Sh pin. The CLK R pin will be

compatible with TTL logic

levels when the LMF40 is

operated on split supplies with

the L. Sh pin connected to

system ground.

5 FILTER The output of the low-pass

filter.

(8) OUT

6 AGND The analog ground pin. This

pin sets the DC bias level for

(10)

the filter section and must be

tied to the system ground for

split supply operation or to

mid-supply for single supply

operation (see Section 1.2).

When tied to mid-supply this

pin should be well bypassed.

Pin Pin Function

ÝName

7, 4 Va,V

bThe positive and negative

supply pins. The total power

(7, 12)

supply range is 4V, to 14V.

Decoupling these pins with

0.1 mF capacitors is highly

recommended.

8 FILTER The input to the low-pass filter.

To minimize gain errors the

(14) IN

source impedance that drives

this input should be less than

2k (see Section 3). For single

supply operation the input

signal must be biased to mid-

supply or AC coupled through

a capacitor.

1.0 LMF40 Application Information

The LMF40 is a non-inverting unity gain low-pass fourth-or-

der Butterworth switched-capacitor filter. The switched-ca-

pacitor topology makes the cutoff frequency (where the gain

drops 3.01 dB below the DC gain) a direct ratio (100:1 or

50:1) of the clock frequency supplied to the filter. Internal

integrator time constants set the filter’s cutoff frequency.

The resistive element of these integrators is actually a ca-

pacitor which is ‘‘switched’’ at the clock frequency (for a

detailed discussion see Input Impedance section). Varying

the clock frequency changes the value of this resistive ele-

ment and thus the time constant of the integrators. The

clock-to-cutoff-frequency ratio (fCLK/fc) is set by the ratio of

the input and feedback capacitors in the integrators. The

higher the clock-to-cutoff-frequency ratio the closer this ap-

proximation is to the theoretical Butterworth response.

1.1 CLOCK INPUTS

The LMF40 has a Schmitt-trigger inverting buffer which can

be used to construct a simple R/C oscillator. Pin 3 is con-

nected to Vb, making Pin 2 a low impedance output. The

oscillator’s frequency is nominally

fCLK e1

RC In Ð#VCC bVtb

VCC bVtaJ#V

bJ( (1)

which is typically

fCLK j1

1.37 RC (1a)

for VCC e10V.

Note that fCLK is dependent on the buffer’s threshold levels

as well as the resistor/capacitor tolerance (see

Figure 1

Schmitt-trigger threshold voltage levels can change signifi-

cantly causing the R/C oscillator’s frequency to vary greatly

from part to part.

Where accurate cutoff frequency is required, an external

clock can be used to drive the CLK R input of the LMF40.

This input is TTL logic level compatible and also presents a

very light load to the external clock source (E2mA). With

split supplies and the level shift (L. Sh) tied to system

ground, the logic level is about 2V. (See the Pin Description

for L. Sh).

1.0 LMF40 Application Information (Continued)

1.2 POWER SUPPLY

The LMF40 can be powered from a single supply or split

supplies. The split supply mode shown in

Figure 2

is the

most flexible and easiest to implement. Supply voltages of

g5V to g7V enable the use of TTL or CMOS clock logic

levels.

Figure 3

shows AGND resistor-biased to Va/2 for

single supply operation. In this mode only CMOS clock logic

levels can be used, and input signals should be capacitor-

coupled or biased near mid-supply.

1.3 INPUT IMPEDANCE

The LMF40 low-pass filter input (FILTER IN) is not a high

impedance buffer input. This input is a switched-capacitor

resistor equivalent, and its effective impedance is inversely

proportional to the clock frequency. The equivalent circuit of

the filter’s input can be seen in

Figure 4

. The input capacitor

charges to VIN during the first half of the clock period; dur-

ing the second half the charge is transferred to the feed-

back capacitor. The total transfer of charge in one clock

cycle is therefore Q eCIN VIN, and since current is defined

as the flow of charge per unit time, the average input current

becomes

IIN eQ/T

(where T equals one clock period) or

IIN AVE eCIN VIN

TeCIN VIN fCLK

The equivalent input resistor (RIN) then can be expressed

RIN eVIN

IIN

CIN fCLK

The input capacitor is 2 pF for the LMF40-50 and 1 pF for

the LMF40-100, so for the LMF40-100

RIN e1c1012

fCLK

e1c1012

fcc100 e1c1010

and

RIN e5c1011

fCLK

e5c1011

fcc50 e1c1010

for the LMF40-50. The above equation shows that for a

given cutoff frequency (fc), the input resistance of the

LMF40-50 is the same as that of the LMF40-100. The high-

er the clock-to-cutoff-frequency ratio, the greater equivalent

input resistance for a given clock frequency.

This input resistance will form a voltage divider with the

source impedance (RSource). Since RIN is inversely propor-

tional to the cutoff frequency, operation at higher cutoff fre-

quencies will be more likely to attenuate the input signal

which would appear as an overall decrease in gain to the

output of the filter. Since the filter’s ideal gain is unity, the

overall gain is given by:

AVeRIN

RIN aRSource

If the LMF40-50 or the LMF40-100 were set up for a cutoff

frequency of 10 kHz the input impedance would be:

RIN e1c1010

10 kHz e1MX

As an example, with a source impedance of 10 kXthe over-

all gain would be:

AVe1MX

10 kXa1MXe0.99009 or b0.086 dB

Since the maximum overall gain error for the LMF40 is

a0.05, b0.15 dB @25§C with RSs2kXthe actual gain

error for this case would be b0.04 dB to b0.24 dB.

1.4 CUTOFF FREQUENCY RANGE

The filter’s cutoff frequency (fc) has a lower limit due to

leakage currents through the internal switches draining the

charge stored on the capacitors. At lower clock frequencies

these leakage currents can cause millivolts of error. For ex-

ample:

fCLK e100 Hz, ILeakage e1 pA, C e1pF

Ve1pA

1 pF (100 Hz) e10 mV

The propagation delay in the logic and the settling time re-

quired to acquire a new voltage level on the capacitors limit

the filter’s accuracy at high clock frequencies. The ampli-

tude characteristic on g5V supplies will typically stay flat

until fCLK exceeds 1.5 MHz and then peak at about 0.1 dB

at the corner frequency with a 2 MHz clock. As supply volt-

age drops to g2.5V, a shift in the fCLK/fcratio occurs which

will become noticeable when the clock frequency exceeds

500 kHz. The response of the LMF40 is still a good approxi-

mation of the ideal Butterworth low-pass characteristic

shown in

Figure 5

2.0 Designing with the LMF40

Given any low-pass filter specification, two equations will

come in handy in trying to determine whether the LMF40 will

do the job. The first equation determines the order of the

low-pass filter required to meet a given response specifica-

tion:

nelog [(100.1Amin b1)/(100.1Amax b1)]

2 log (fs/fb)(2)

where n is the order of the filter, Amin is the minimum stop-

band attenuation (in dB) desired at frequency fs, and Amax is

the passband ripple or attenuation (in dB) at cutoff frequen-

cy fb(Note 15). If the result of this equation is greater than

4, more than one LMF40 will be required.

The attenuation at any frequency can be found by the fol-

lowing equation:

Attn (f) e10 log [1a(100.1Amax b1)(f/fb)2n]dB (3)

where n e4 for the LMF40.

2.1 A LOW-PASS DESIGN EXAMPLE

Suppose the amplitude response specification in

Figure 6

given. Can the LMF40 be used? The order of the Butter-

worth approximation will have to be determined using (1):

Amin e18 dB, Amax e1.0 dB, fse2 kHz, and fbe1 kHz

nelog[(101.8 b1)/(100.1 b1)]

2 log(2) e3.95

Since n can only take on integer values, n e4. Therefore

the LMF40 can be used. In general, if n is 4 or less a single

LMF40 can be utilized.

2.0 Designing with the LMF40 (Continued)

Likewise, the attenuation at fscan be found using (3) with

the above values and n e4:

Attn (2 kHz) e10 log[1a100.1 b1) (2 kHz/1 kHz)8]

e18.28 dB

This result also meets the design specification given in

Fig-

ure 6

again verifying that a single LMF40 section will be

adequate.

Since the LMF40’s cutoff frequency (fc), which corresponds

to a gain attenuation of b3.01 dB, was not specified in this

example, it needs to be calculated. Solving equation (3)

where f efcas follows:

fcefbÐ100.1(3.01 dB) b1

(100.1Amax b1) (1/(2n)

e1 kHz Ð100.301 b1

100.1 b1(1/8

e1.184 kHz

where fcefCLK /50 or fCLK/100. To implement this exam-

ple for the LMF40-50 the clock frequency will have to be set

to fCLK e50(1.184 kHz) e59.2 kHz, or for the LMF40-100,

fCLK e100 (1.184 kHz) e118.4 kHz.

2.2 CASCADING LMF40s

When a steeper stopband attenuation rate is required, two

LMF40s can be cascaded

(Figure 7)

yielding an 8th order

slope of 48 dB per octave. Because the LMF40 is a Butter-

worth filter and therefore has no ripple in its passband,

when LMF40s are cascaded the resulting filter also has no

ripple in its passband. Likewise the DC and passband gains

will remain at 1V/V. The resulting response is shown in

Fig-

ure 8a

In determining whether the cascaded LMF40s will yield a

filter that will meet a particular amplitude response specifi-

cation, as above, equations (4) and (5) can be used, shown

below.

nelog[(10,0.05Amin b1)/(100.05Amax b1)]

2 log(fs/fb) (4)

Attn (f) e10 log [1a(100.05Amax b1) (f/fb)2]dB (5)

where n e4 (the order of each filter).

Equation (4) will determine whether the order of the filter is

adequate (n s4) while equation (5) can determine the actu-

al stopband attenuation and cutoff frequency (fc) necessary

to obtain the desired frequency response. The design pro-

cedure would be identical to the one shown in Section 2.0.

2.3 CHANGING CLOCK FREQUENCY

INSTANTANEOUSLY

The LMF40 responds well to an instantaneous change in

clock frequency. If the control signal in

Figure 9

is low the

LMF40-50 has a 100 kHz clock making fce2 kHz; when

this signal goes high the clock frequency changes to 50 kHz

yielding fce1 kHz. As

Figure 9

illustrates, the output signal

changes quickly and smoothly in response to a sudden

change in clock frequency.

The step response of the LMF40 in

Figure 10

is dependent

on fc. The LMF40 responds as a classical fourth-order But-

terworth low-pass filter.

2.4 ALIASING CONSIDERATIONS

Aliasing effects have to be considered when input signal

frequencies exceed half the sampling rate. For the LMF40

this equals half the clock frequency (fCLK). When the input

signal contains a component at a frequency higher than half

the clock frequency fCLK/2, as in

Figure 11a

, that compo-

nent will be ‘‘reflected’’ about fCLK/2 into the frequency

range below fCLK/2, as in

Figure 11b

. If this component is

within the passband of the filter and of large enough ampli-

tude it can cause problems. Therefore, if frequency compo-

nents in the input signal exceed fCLK/2 they must be attenu-

ated before being applied to the LMF40 input. The neces-

sary amount of attenuation will vary depending on system

requirements. In critical applications the signal components

above fCLK/2 will have to be attenuated at least to the fil-

ter’s residual noise level.

TL/H/10557–7

fe1

RC In Ð#V

CC bVtb

VCC bVtaJ#V

bJ(

fj1

1.37 RC

(VCC e10V)

FIGURE 1. Schmitt Trigger R/C Oscillator

2.0 Designing with the LMF40 (Continued)

VIH t0.8 VCC

VIL s0.2 VCC

VCC eVabVb

TL/H/10557–8

(a)

TL/H/10557–9

(b)

FIGURE 2. Split Supply Operation with CMOS Level Clock (a), and TTL Level Clock (b)

TL/H/10557–10

FIGURE 3. Single Supply Operation. AGND Resistor Biased to Va/2

TL/H/10557–11

a) Equivalent Circuit for LMF40 Filter Input

TL/H/10557–12

b) Actual Circuit for LMF40 Filter Input

FIGURE 4. LMF40 Filter Input

2.0 Designing with the LMF40 (Continued)

TL/H/10557–13

FIGURE 5a. LMF40-100 Amplitude

Response with g5V Supplies

TL/H/10557–14

FIGURE 5b. LMF40-50 Amplitude

Response with g5V Supplies

TL/H/10557–15

FIGURE 5c. LMF40-100 Amplitude

Response with g2.5V Supplies

TL/H/10557–16

FIGURE 5d. LMF40-50 Amplitude

Response with g2.5V Supplies

TL/H/10557–17

FIGURE 6. Design Example Magnitude Response

Specification. The response of the filter design

must fall within the shaded area of the specification.

2.0 Designing with the LMF40 (Continued)

TL/H/10557–18

FIGURE 7. Cascading Two LMF40s

TL/H/10557–19

FIGURE 8a. One LMF40-50

vs Two LMF40-50s Cascaded

FIGURE 8b. Phase Response

of Two Cascaded LMF40-50s

TL/H/10557–20

FIGURE 9. LMF40-50 Abrupt Clock Frequency Change

TL/H/10557–21

FIGURE 10. LMF40-50 Input Step Response

2.0 Designing with the LMF40 (Continued)

TL/H/10557–22

(a) Input Signal Spectrum

TL/H/10557–23

(b)Output Signal Spectrum. Note that the input signal at

fs/2 af causes an output signal to appear at fs/2 bf.

FIGURE 11. The phenomenon of aliasing in sampled-data systems. An input signal whose

frequency is greater than one-half the sampling frequency will cause an output to appear

at a frequency lower than one-half the sampling frequency. In the LMF40, fsefCLK.

Physical Dimensions inches (millimeters)

Order Number LMF40CMJ-50 or LMF40CMJ-100

NS Package Number J08A

Order Number LMF40CIWM-50 or LMF40CIWM-100

NS Package Number M14B

LMF40 High Performance 4th-Order Switched-Capacitor

Butterworth Low-Pass Filter

Physical Dimensions inches (millimeters) (Continued)

Order Number LMF40CIN-50, or LMF40CIN-100

NS Package Number N08E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (

49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309

Arlington, TX 76017 Email: cnjwge

tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408

Tel: 1(800) 272-9959 Deutsch Tel: (

49) 0-180-530 85 85 Tsimshatsui, Kowloon

Fax: 1(800) 737-7018 English Tel: (

49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (

49) 0-180-532 93 58 Tel: (852) 2737-1600

Italiano Tel: (

49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.