19-1909; Rev 0; 6/01 KIT ATION EVALU LE B A IL A AV Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout ____________________________Features Integrated Termination Eliminates Four External Resistors (MAX9122) Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk Pin Compatible with DS90LV048A Guaranteed 500Mbps Data Rate 300ps Pulse Skew (max) Conform to ANSI TIA/EIA-644 LVDS Standard Single +3.3V Supply Fail-Safe Circuit Ordering Information PART MAX9121EUE MAX9121ESE MAX9122EUE MAX9122ESE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 SO 16 TSSOP 16 SO Pin Configuration appears at end of data sheet. Typical Application Circuit LVDS SIGNALS TX 107 RX TX 107 RX Applications Digital Copiers Laser Printers Cellular Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution LVTTL/LVCMOS DATA INPUT LVTTL/LVCMOS DATA OUTPUT TX 107 RX TX 107 RX MAX9123 MAX9122 100 SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9121/MAX9122 General Description The MAX9121/MAX9122 quad low-voltage differential signaling (LVDS) differential line receivers are ideal for applications requiring high data rates, low power, and low noise. The MAX9121/MAX9122 are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlledimpedance media of approximately 100. The transmission media may be printed circuit (PC) board traces or cables. The MAX9121/MAX9122 accept four LVDS differential inputs and translate them to LVCMOS outputs. The MAX9122 features integrated parallel termination resistors (nominally 107), which eliminate the requirement for four discrete termination resistors and reduce stub lengths. The MAX9121 inputs are high impedance and require an external termination resistor when used in a point-to-point connection. The devices support a wide common-mode input range of 0.05V to 2.35V, allowing for ground potential differences and common-mode noise between the driver and the receiver. A fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or parallel terminated. The EN and EN inputs control the high-impedance output. The enables are common to all four receivers. Inputs conform to the ANSI TIA/EIA644 LVDS standard. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs. The MAX9121/ MAX9122 operate from a single +3.3V supply, and are specified for operation from -40C to +85C. These devices are available in 16-pin TSSOP and SO packages. Refer to the MAX9123 data sheet for a quad LVDS line driver with flow-through pinout. MAX9121/MAX9122 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V EN, EN to GND ...........................................-0.3V to (VCC + 0.3V) OUT_ to GND .............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW 16-Pin SO (derate 8.7mW/C above +70C)................696mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection (Human Body Model, IN_+, IN_-) ....................................8kV Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVDS INPUTS (IN_+, IN_-) Differential Input High Threshold VTH Differential Input Low Threshold VTL Input Current (MAX9121) IIN_+, IIN_- Power-Off Input Current (MAX9121) IINOFF 100 -100 mV mV 0.1V VID 0.6V -20 20 0.6V <VID 1.0V -25 25 A 0.1V VID 0.6V, VCC = 0 -20 20 A 25 A 0.6V <VID 1.0V, VCC = 0 -25 Input Resistor 1 RIN1 VCC = 3.6V or 0, Figure 1 35 k Input Resistor 2 RIN2 VCC = 3.6V or 0, Figure 1 132 k RDIFF VCC = 3.6V or 0, Figure 1 90 107 Open, undriven short, or undriven 100 parallel termination 2.7 3.2 VID = +100mV 2.7 3.2 Open or undriven short 2.7 3.2 VID = +100mV 2.7 Differential Input Resistance (MAX9122) 132 A LVCMOS/LVTTL OUTPUTS (OUT_) IOH = -4.0mA (MAX9121) Output High Voltage (Table 1) VOH IOH = -4.0mA (MAX9122) 2 V 3.2 Output Low Voltage VOL IOL = +4.0mA, VID = -100mV 0.1 0.25 V Output Short-Circuit Current IOS Enabled, VID = 0.1V, VOUT_ = 0 (Note 2) -15 -120 mA Output High-Impedance Current IOZ Disabled, VOUT = 0 or VCC -10 +10 A _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout (V CC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V LOGIC INPUTS (EN, EN) Input High Voltage VIH 2.0 VCC Input Low Voltage VIL 0 0.8 V Input Current IIN VIN_ = VCC or 0 -15 15 A Supply Current ICC Enabled, inputs open 9 15 mA Disabled Supply Current ICCZ Disabled, inputs open 0.07 0.5 mA SUPPLY AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Propagation Delay High to Low tPHLD Figures 2 and 3 1.2 1.93 2.7 ns Differential Propagation Delay Low to High tPLHD Figures 2 and 3 1.2 1.79 2.7 ns Differential Pulse Skew [tPHLD tPLHD] (Note 5) tSKD1 Figures 2 and 3 140 300 ps Differential Channel-to-Channel Skew (Note 6) tSKD2 Figures 2 and 3 400 ps Differential Part-to-Part Skew (Note 7) tSKD3 Figures 2 and 3 0.8 ns Differential Part-to-Part Skew (Note 8) tSKD4 Figures 2 and 3 1.5 ns Rise-Time tTLH Figures 2 and 3 0.55 1.0 ns Fall-Time tTHL Figures 2 and 3 0.54 1.0 ns Disable Time High to Z tPHZ RL = 2k, Figures 4 and 5 14 ns Disable Time Low to Z tPLZ RL = 2k, Figures 4 and 5 14 ns Enable Time Z to High tPZH RL = 2k, Figures 4 and 5 70 ns Enable Time Z to Low tPZL RL = 2k, Figures 4 and 5 70 ns Maximum Operating Frequency (Note 9) fMAX All channels switching 250 300 MHz _______________________________________________________________________________________ 3 MAX9121/MAX9122 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4) Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes scope probe and test jig capacitance. Note 5: tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|. Note 6: tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same part. Note 7: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5C of each other. Note 8: tSKD4 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. Note 9: fMAX generator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, VOH = +1.3V, VOL = +1.1V, MAX9121/MAX9122 output criteria: 60% to 40% duty cycle, VOL = 0.4V (max), VOH = 2.7V (min), load = 15pF. Typical Operating Characteristics (VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CL = 15pF, TA = +25C, unless otherwise noted.) (Figures 2 and 3) 10 9.50 9.00 8.50 8.00 ONE SWITCHING 7.50 0 0.1 1 10 100 1000 30 20 10 -40 -15 10 35 60 3.0 85 3.3 FREQUENCY (MHz) TEMPERATURE (C) SUPPLY VOLTAGE (V) OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE OUTPUT HIGH-IMPEDANCE CURRENT vs. SUPPLY VOLTAGE OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE -80 -75 -70 -65 1.20 1.15 SUPPLY VOLTAGE (V) 3.6 3.5 3.3 3.1 2.9 2.7 1.10 3.3 3.6 MAX9121/22 toc06 1.25 3.7 OUTPUT HIGH VOLTAGE (V) -85 MAX9121/22 toc05 -90 1.30 OUTPUT HIGH-IMPEDANCE CURRENT (nA) MAX9121/22 toc04 -95 3.0 40 0 7.00 0.01 4 10.00 50 DIFFERENTIAL THRESHOLD VOLTAGE (mV) 20 MAX9121/22 toc02 10.50 SUPPLY CURRENT (mA) ALL CHANNELS SWITCHING 11.00 MAX9121/22 toc01 SUPPLY CURRENT (mA) 40 30 DIFFERENTIAL THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE MAX9121/22 toc03 SUPPLY CURRENT vs. FREQUENCY OUTPUT SHORT-CIRCUIT CURRENT (mA) MAX9121/MAX9122 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 3.0 3.3 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.6 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE 96 95 94 93 2.00 tPHLD 1.90 1.80 1.70 92 3.3 2.10 tPHLD 1.90 tPLHD 1.70 1.50 1.60 3.6 3.0 3.3 -40 3.6 -15 10 35 60 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (C) DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE tPHLD 2.00 1.75 tPLHD 1.50 2.0 1.9 tPHLD 1.8 tPLHD 1.7 -0.5 0 0.5 1.0 1.5 2.0 900 1700 3.0 3.3 3.6 SUPPLY VOLTAGE (V) DIFFERENTIAL INPUT VOLTAGE (mV) TRANSITION TIME vs. TEMPERATURE tTLH 550 tTHL MAX9121/22 toc14 MAX9121/22 toc13 650 625 TRANSITION TIME (ps) TRANSITION TIME (ps) 125 2500 TRANSITION TIME vs. SUPPLY VOLTAGE 575 150 100 100 2.5 COMMON-MODE VOLTAGE (V) 600 175 1.6 1.5 1.25 85 MAX9121/22 toc12 2.1 200 DIFFERENTIAL PULSE SKEW (ps) 2.25 2.2 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9121/22 toc10 2.50 DIFFERENTIAL PROPAGATION DELAY (ns) tPLHD MAX9121/22 toc09 2.10 DIFFERENTIAL PROPAGATION DELAY (ns) 97 MAX9121/22 toc08 98 2.20 MAX9121/22 toc11 OUTPUT LOW VOLTAGE (mV) 99 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9121/22 toc07 100 3.0 DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE 600 575 tTLH 550 525 tTHL 500 525 475 450 500 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 -40 -15 10 35 60 85 TEMPERATURE (C) _______________________________________________________________________________________ 5 MAX9121/MAX9122 Typical Operating Characteristics (continued) (VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CL = 15pF, TA = +25C, unless otherwise noted.) (Figures 2 and 3) MAX9121/MAX9122 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout Pin Description PIN NAME FUNCTION 1, 4, 5, 8 IN_- Inverting Differential Receiver Inputs 2, 3, 6, 7 IN_+ Noninverting Differential Receiver Inputs 9, 16 EN, EN 10, 11, 14, 15 OUT_ LVCMOS/LVTTL Receiver Outputs 12 GND Ground 13 VCC Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active. For other combinations of EN and EN, the outputs are disabled and in high impedance. Table 1. Input/Output Function Table ENABLES EN H EN L or open OUTPUT (IN_+) - (IN_-) OUT_ VID +100mV H VID -100mV L MAX9121 Open, undriven short, or undriven 100 parallel termination MAX9122 Open or undriven short All other combinations of ENABLE pins Detailed Description The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9121/MAX9122 are 500Mbps, four-channel LVDS receivers intended for high-speed, point-to-point, low-power applications. Each channel accepts an LVDS input and translates it to an LVTTL/LVCMOS output. The receiver is capable of detecting differential signals as low as 100mV and as high as 1V within an input voltage range of 0 to 2.4V. The 250mV to 400mV differential output of an LVDS driver is nominally centered around a +1.2V offset. This offset, coupled with the receiver's 0 to 2.4V input voltage range, allows an approximate 1V shift in the signal (as seen by the receiver). This allows for a difference in ground refer6 INPUTS Don't care H Z ences of the transmitter and the receiver, the commonmode effects of coupled noise, or both. The LVDS standards specify an input voltage range of 0 to +2.4V referenced to receiver ground. The MAX9122 has an integrated termination resistor that is internally connected across each receiver input. The internal termination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In other words, the transmission line is terminated on the IC. Fail-Safe The fail-safe feature of the MAX9121/MAX9122 sets an output high when: * Inputs are open. * Inputs are undriven and shorted. * Inputs are undriven and terminated. A fail-safe circuit is important because under these conditions, noise at the inputs may switch the receiver and it may appear to the system that data is being _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122 VCC VCC RIN2 RIN2 VCC - 0.3V VCC - 0.3V IN_+ IN_+ RIN1 RIN1 OUT_ OUT_ RDIFF RIN1 RIN1 IN_- IN_MAX9121 MAX9122 Figure 1. Input with Fail-Safe Network received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when the LVDS driver outputs are high impedance. A short condition can occur because of a cable failure. The fail-safe input network (Figure 1) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). When the input is driven to levels specified in the LVDS standards, the input to the common-mode voltage is less than VCC - 0.3V and the fail-safe circuit is not activated. If the inputs are open or if the inputs are undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the fail-safe circuit pulls both inputs above VCC - 0.3V, activating the fail-safe circuit and forcing the output high. Applications Information Power-Supply Bypassing Bypass the VCC pin with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. Differential Traces Input trace characteristics affect the performance of the MAX9121/MAX9122. Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Each channel's differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities. _______________________________________________________________________________________ 7 MAX9121/MAX9122 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout IN_+ PULSE GENERATOR** OUT_ CL IN_50* 50* RECEIVER ENABLED 1/4 MAX9121/MAX9122 *50 REQUIRED FOR PULSE GENERATOR. **WHEN TESTING THE MAX9122, ADJUST THE PULSE GENERATOR OUTPUT TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR. Figure 2. Propagation Delay and Transition Time Test Circuit IN_VID = 0 VID VID = 0 IN_+ tPLHD tPHLD VOH 80% VID = (VIN_+) - (VIN_-) NOTE: VCM = (VIN- + VIN+) 2 80% 50% 50% 20% OUT_ 20% tTLH tTHL VOL Figure 3. Propagation Delay and Transition Time Waveforms Cables and Connectors Transmission media typically have a controlled differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Termination value of the integrated resistor is specified in the DC characteristics. The MAX9121 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance values may range between 90 to 132, depending on the characteristic impedance of the transmission medium. When using the MAX9121, minimize the distance between the input termination resistors and the MAX9121 receiver inputs. Use 1% surface-mount resistors. The MAX9122 has an integrated termination resistor connected across the inputs of each receiver. The 8 _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout 50 DEVICE UNDER TEST IN_- EN S1 RL IN_+ GENERATOR MAX9121/MAX9122 VCC OUT_ CL EN 1/4 MAX9121/MAX9122 CL INCLUDES LOAD AND TEST JIG CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = GND FOR tPZH AND tPHZ MEASUREMENTS. Figure 4. High-Impedance Delay Test Circuit 3V EN WHEN EN = GND OR OPEN 1.5V 1.5V 0 3V 1.5V 1.5V 0 EN WHEN EN = VCC tPZL VCC tPLZ OUTPUT WHEN VID = -100mV 50% 0.5V OUTPUT WHEN VID = +100mV VOL tPZH tPHZ VOH 0.5V 50% GND Figure 5. High-Impedance Delay Waveforms Chip Information Board Layout Because the MAX9121/MAX9122 feature a flow-through pinout, no special layout precautions are required. Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Isolate the input LVDS signals from each other to prevent coupling. Isolate the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. TRANSISTOR COUNT: 1354 PROCESS: CMOS _______________________________________________________________________________________ 9 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122 Functional Diagram VCC VCC IN1+ IN1+ OUT1 IN1- 107 OUT1 107 OUT2 107 OUT3 107 OUT4 IN1- IN2+ IN2+ OUT2 IN2- IN2- IN3+ IN3+ OUT3 IN3- IN3- IN4+ IN4+ OUT4 IN4- IN4- EN EN EN EN MAX9121 MAX9122 GND GND Pin Configuration TOP VIEW IN1- 1 16 EN IN1+ 2 15 OUT1 IN2+ 3 14 OUT2 IN2- 4 IN3- 5 MAX9121 MAX9122 13 VCC 12 GND IN3+ 6 11 OUT3 IN4+ 7 10 OUT4 IN4- 8 9 EN TSSOP/SO 10 ______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout TSSOP,NO PADS.EPS ______________________________________________________________________________________ 11 MAX9121/MAX9122 Package Information Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout SOICN.EPS MAX9121/MAX9122 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.