iChip CO561AD-S iChip CO561AD-C iChip LAN CO561AD-L Datasheet Version 5.20 International: Connect One Ltd. 2 Hanagar Street Kfar Saba 44425, Israel Tel: +972-9-766-0456 Fax: +972-9-766-0461 E-mail: info@connectone.com http://www.connectone.com Pub. No. 11-3100-07, February 10, 2002 USA: Connect One Semiconductors, Inc. 15818 North 9th Ave. Phoenix, AZ 85023 Tel: 408-986-9602 Fax: 602-485-3715 E-mail: info@connectone.com http://www.connectone.com _______________________________________________________________________________________________________________________________________________________ Information provided by Connect One Ltd. is believed to be accurate and reliable. However, Connect One assumes no responsibility for its use, nor any infringement of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent rights of Connect One other than for circuitry embodied in Connect One's products. Connect One reserves the right to change circuitry at any time without notice. This document is subject to change without notice. The software described in this document is furnished under a license agreement and may be used or copied only in accordance with the terms of such a license agreement. It is forbidden by law to copy the software on any medium except as specifically allowed in the license agreement. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including but not limited to photocopying, recording, transmitting via fax and/or modem devices, scanning, and/or information storage and retrieval systems for any purpose without the express written consent of Connect One. iChip, iChip LAN, iChip Plus, Socket iChip, Embedded iModem, Internet Controller, iLAN, iModem, AT+i, and Connect One are trademarks of Connect One Ltd. Copyright 2000 - 2002 Connect One Ltd. All rights reserved. iChip & iChip LAN Datasheet 1-ii Revision History Revision History 11-3100-06 Version 1.0 Date November 1999 4.0 November 2000 5.0 February 2001 5.1 March 2001 5.11 August 2001 5.2 January 2002 iChip & iChip LAN Datasheet Description Original Release for iChip CO561AD-S. Author Amit Resh Updated with iChip LAN CO561AD-L. Author Jakob Apelblat Parallel modem obsolete. Figure 4-1 iChip pin names changed for pin #14, 21, 40, 61 - 66. Figure 4-2 iChip pin names changed for pin #14, 21, 28 - 30, 40, 61 - 63, 65. Removed components for debugging from reference designs. Chapter 2 "Ordering Information" is new. Figure 6-3, pin 61 of U2 connected to VCC, 56 no pin, 55, 54 changed, pin 40 of U1 connected via pull up to VCC, U3A changed to U4. Figure 6-4, pin 40 of U1 connected via pull up to VCC. Figure 7-1, pin 53, 56 changed. Figure 7-3, 55, 54 changed. Table 6-1, #27 P/N changed, #23, R10 added, #17, #28, #29, #32 updated. Table 6-2, #14, R19 added, #11, #22, #24, #25, #27 updated. "2.1 Overview" updated. "2.2.6 Local Bus Connection to Ethernet Controller" updated. "4.3.3 iChip Serial Modem Signals" MMSEL updated. Chapter "6.3 Mechanical Dimensions" has been updated. Chapter 7.6 "PLD Equations" reset removed. Fixed schematic in Fig. 7-3. Updated iChip current consumption. Schematic changed on page 5-1: pin 14. Added crystal parameters. Changed C9 on iModem reference design to 22pF. Added DC characteristic parameters. Added recommendation to short CTS to RTS and DSR to GND when not used. Added reference design for iChip LAN with Realtek RTL8019AS Ethernet LAN controller. iii Contents Contents 1 Introduction ............................................................................................................. 1-1 2 Ordering Information ............................................................................................. 2-3 2.1 2.2 3 Functional Description............................................................................................ 3-1 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 4 iChip CO561AD-S Pin Assignments........................................................... 5-1 iChip LAN Pin Assignments ....................................................................... 5-2 iChip Pin Functional Descriptions ............................................................... 5-3 Local Bus Signals ........................................................................................ 5-3 Host Interface Signals .................................................................................. 5-7 iChip Serial Modem Signals ........................................................................ 5-8 iChip LAN Signals....................................................................................... 5-9 Electrical/Mechanical Specifications ..................................................................... 6-1 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 6.3 7 Host Interface............................................................................................... 4-1 Serial Modem Interface................................................................................ 4-2 Ethernet Controller Interface ....................................................................... 4-3 Pin Descriptions....................................................................................................... 5-1 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.4 6 Overview...................................................................................................... 3-1 Technical Specifications .............................................................................. 3-1 General......................................................................................................... 3-1 Data Rates .................................................................................................... 3-1 Operation...................................................................................................... 3-2 Remote Internet Firmware Update............................................................... 3-2 Host Serial Connection ................................................................................ 3-2 Serial Connection to Dial-up Modem .......................................................... 3-3 Local Bus Connection to Ethernet Controller.............................................. 3-3 Hardware and Software Flow Control ......................................................... 3-3 Hardware Interface................................................................................................. 4-1 4.1 4.2 4.3 5 iChip / iChip LAN Order Number ............................................................... 2-3 Socket iChip Order Number ........................................................................ 2-4 Environmental Specifications ...................................................................... 6-1 Absolute Maximum Ratings ........................................................................ 6-1 DC Operating Characteristics ...................................................................... 6-2 Interface Timing and Waveforms ................................................................ 6-3 Local Bus Read Cycle.................................................................................. 6-3 Local Bus Write Cycle................................................................................. 6-4 Mechanical Dimensions............................................................................... 6-5 iChip Designs ........................................................................................................... 7-1 7.1 General Hardware Architecture ................................................................... 7-1 iChip & iChip LAN Datasheet iv Contents 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 Serial Modem Environment......................................................................... 7-1 Ethernet Controller Environment with CS8900A........................................ 7-1 Ethernet Controller Environment with RTL8019AS................................... 7-1 Reference Design for Embedded iModem Using CO561AD-S .................. 7-2 Bill of Materials for CO561AD-S Reference Design .................................. 7-3 Reference Design for iLAN Using CO561AD-L and CS8900A................. 7-4 Bill of Materials for CO561AD-L+CS8900A Reference Design................ 7-5 PLD Equations ............................................................................................. 7-6 Reference Design for iLAN Using CO561AD-L and RTL8019AS ............ 7-7 Bill of Materials for CO561AD-L and RTL8019AS Reference Design .... 7-9 Socket iChip Carrier Board ................................................................................... 8-1 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 9 Pin Assignments........................................................................................... 8-1 Pin Functional Descriptions......................................................................... 8-2 SocketModem Interface Signals .................................................................. 8-2 Host Interface Signals .................................................................................. 8-3 Socket iChipTM Package Dimensions .......................................................... 8-5 Reference Design for CO561AD-C Based Modem..................................... 8-6 Bill of Materials for CO561AD-C Reference Design.................................. 8-7 PCB Design and Layout Considerations............................................................... 9-1 9.1 9.2 9.2.1 9.2.2 Design Consideration................................................................................... 9-1 PC Board Layout Guidelines ....................................................................... 9-1 Electromagnetic Interference (EMI) Considerations ................................... 9-2 Other Considerations in a Modem Design................................................... 9-3 10 Protocol Compliance................................................................................ 10-1 11 List of Terms and Acronyms .................................................................. 11-1 12 Index.......................................................................................................... 12-1 iChip & iChip LAN Datasheet v Figures Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1-1 iChip Functional Block Diagram................................................................... 1-2 4-1 iChip CO561AD-S with a Serial Modem Interface ....................................... 4-2 4-3 iChip LAN with an Ethernet Controller Interface.......................................... 4-3 5-1 PLCC68 Package for iChip CO561AD-S Serial Version .............................. 5-1 5-3 PLCC68 Package for iChip LANCO561AD-L Serial Version..................... 5-2 5-5 Selecting a Crystal.......................................................................................... 5-6 6-1 Local Bus Read Cycle.................................................................................... 6-3 6-3 Local Bus Write Cycle................................................................................... 6-4 6-5 Mechanical Dimensions................................................................................. 6-5 7-1 Serial Modem Environment........................................................................... 7-1 7-3 CS8900A Ethernet Controller Environment.................................................. 7-1 7-5 RTL8019AS Ethernet Controller Environment ............................................. 7-1 7-6 Reference Design for Embedded iModem Using CO561AD-S .................... 7-2 7-8 Reference Design for iLAN Using CO561AD-L and CS8900A................... 7-4 7-9 Reference Design for iLAN Using CO561AD-L and RTL8019AS .........7-4 7-10 Reference Design for iLAN Using CO561AD-L and RTL8019AS .........7-4 8-1 Carrier Board CO561AD-C Pinout................................................................ 8-1 8-3 Socket iChip Package Dimensions................................................................. 8-5 8-5 Reference Design for CO561AD-C Based Modem....................................... 8-6 iChip & iChip LAN Datasheet vi Tables Tables Table Table Table Table Table Table Table Table Table Table Table Table Table 4-1 Host Data Format............................................................................................ 4-1 5-1 Data Byte Encoding......................................................................................... 5-3 6-1 Environmental Specifications 3.3-Volt Version.............................................. 6-1 6-3 Environmental Specifications 5-Volt Version................................................. 6-1 6-5 DC Operating Characteristics 3.3-Volt Version.............................................. 6-2 6-7 DC Operating Characteristics 5-Volt Version................................................. 6-2 7-1 Bill of Materials for CO561AD-S Reference Design...................................... 7-3 7-3 Bill of Materials for CO561AD-L and CS8900A Reference Design.............. 7-5 7-5 Reference Design for iLAN Using CO561AD-L and RTL8019AS ............... 7-8 7-6 Bill of Materials for CO561AD-L and RTL8019AS Reference Design......... 7-9 8-1 Bill of Materials for CO561AD-C Reference Design..................................... 8-7 10-1 Internet Protocol Compliance...................................................................... 10-1 11-1 Terms and Acronyms.................................................................................. 11-2 iChip & iChip LAN Datasheet vii Introduction 1 Introduction Description The iChipTM Internet ControllerTM is a family of low-cost intelligent peripheral device that provide Internet connectivity solutions to a myriad of embedded devices. Two firmware versions are available: iChip CO561AD-S for dial-up and wireless Internet connectivity, and iChip LANTM CO561AD-L for 10BaseT Ethernet LAN Internet connectivity. For the sake of consistency, the name "iChip" is used herein when referring to both iChip CO561AD-S and iChip LAN. Otherwise, the specific product name is used. The Socket iChipTM Internet Controller, CO561AD-C, is the iChip CO561AD-S on a carrier board that is pin-compatible with Conexant or Multi-Tech socket-type modem. As an embedded, self-contained Internet engine, iChip acts as mediator device between a host processor and an Internet communications platform. By completely offloading Internet connectivity and standard protocols, it relieves the host from the burden of handling Internet communications. From the perspective of a host device, the complexity of establishing and maintaining Internet-related sessions are reduced to simple, straightforward commands that are entirely dealt with within iChip's domain. A serial bus interfaces iChip CO561AD-S to a device's host processor via an on-chip UART. An optional 8/16-bit parallel interface to a host processor is supported as well by adding an external UART for lowbandwidth applications or a dual-port-RAM for high bandwidth applications. iChip CO561AD-S also directly interfaces a serial data modem, through which it supports independent communications on the Internet via a dial-up ISP connection. iChip & iChip LAN Datasheet In addition to supporting dial-up modems, iChip CO561AD-S also supports CDMA, TDMA, GSM GPRS and AMPS wireless modems. Through its host Application Programming Interface (API), iChip accepts commands formatted in Connect One's AT+iTM extension to the renowned Hayes AT command set. Commands are available to store and manipulate functional and Internet-related non-volatile parameter data; transmit and receive textual Email messages; transmit and receive binary (MIME encoded) Email messages; fetch HTML web pages; and download parameter and firmware updates for the host device or iChip itself. Send command variants exist for immediate communications or scheduled "storeand-forward". iChip supports several levels of status reporting to the host. When the host CPU issues standard AT commands, iChip CO561ADS gains direct access to the modem, and automatically operates in transparent mode, emulating a direct host-to-modem environment. iChip LANTM supports 10BaseT Ethernet LANs with the addition of an external 16-bit Cirrus Logic Crystal LAN CS8900A Ethernet controller or Realtek RTL8019AS Ethernet controller. AT commands enable iChip LAN to send and receive Internet commands through the LAN. Upon receiving an AT+i command, iChip operates in Internet mode, controls the modem or Ethernet controller, and independently manages standard Internet protocols to transmit and receive messages. iChip provides all the necessary procedures to log onto an ISP, authenticate the user and establish an Internet session. 1-1 Introduction Functional Block Diagram Pin Diagram PLCC68 RESET iChip 512 KB X2 Rx,Tx,CTS,RTS,DTR 128 KB CPU Core LD0-D15 Local Parallel/Serial Interface FLASH SRAM Host Serial Interface Crystal X1 LA0-A19 ~RD ~WR LNINT CS Modem CO561AD-S/L 50-3150-01 0032 (c)Connect One `00 Rx,Tx,CTS,RTS,DTR Figure 1-1 iChip Functional Block Diagram General Features Microprocessor-controllable through a standard serial connection or optional parallel bus. Supports remote firmware update by host, email, or direct modem-to-modem communications. Includes onboard 128KB SRAM and 512KB flash memory. Supports additional external memory. Driven by Connect One's "AT+i" extension to the AT command set. Stand-alone Internet communication capabilities. Binary Base64 encoding and MIME. Opens up to 10 TCP or UDP sockets and up to 2 Listen (server) sockets. Power save mode reduces power consumption. 3.3 and 5V versions available, CMOS technology. Onboard non-volatile memory stores all functional and Internet-related parameters. Supports several layers of status reports. Internal self-test procedures. Internal "Watch-Dog" guard circuit. Auto baud rate detection. iChip & iChip LAN Datasheet Includes hardware and software flow control. PLCC68 package. General Protocols Supports following Internet Protocols: IP, TCP, UDP, DNS, SMTP, POP3, MIME, HTTP, FTP, Telnet and Web server SerialNET mode. Dial-up Features Supports dial-up Internet Protocols: PPP, LCP, IPCP, and PAP, CHAP, or Script authentication. Supports data modems up to 56 Kbps. Supports CDMA, TDMA, GSM, GPRS and AMPS wireless modems. Stay-on-line feature for multiple send/receive sessions. Transparent mode supports direct modem commands. LAN Features Supports LAN Internet Protocols: ARP, ICMP, and DHCP. Provides 10BaseT Ethernet LAN connectivity via Crystal LAN CS8900A and Realtek RTL8019AS Ethernet controller Supports up to 230 Kbps throughput. 1-2 Introduction 2 Ordering Information 2.1 iChip / iChip LAN Order Number Connect One's standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. CO561AD-S /20 P C - 5 Product Code Version: S = SERIAL L = LAN Clock: 20 = MHz Package: P = PLCC 68 Pin Temperature Range: C = Commercial (0-70) Voltage: 5 = 5V 3 = 3.3V iChip & iChip LAN Datasheet 2-3 Ordering Information 2.2 Socket iChip Order Number Connect One's standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. CO561AD-C /20 D C - 5 Product Code Version: C = Socket Clock: 20 = MHz Package: D = DIP 64 Pin Temperature Range: C = Commercial (0-70) Voltage: 5 = 5V 3 = 3.3V iChip & iChip LAN Datasheet 2-4 Functional Description 3 Functional Description 3.1 Overview Connect One's iChip Internet Controller is an integrated, firmware-driven, self-contained Internet engine that is available in a 68-pin PLCC package. iChip accepts simple ASCII commands from a host CPU via a serial communication bus and manages an Internet communication session to send and receive Email and web pages, and to open and close sockets through a linked modem or Ethernet communications platform. For dial-up and wireless analog modem configurations, iChip CO561AD-S is available in two forms: CO561AD-S interfaces a serial modem. CO561AD-S is also available mounted on a carrier board, CO561AD-C that is pin-compatible with Conexant or MultiTech socket-type modems. For 10BaseT Ethernet applications, iChip LAN CO561AD-L includes the firmware and pin-out necessary to drive external Crystal LAN CS8900A or Realtek RTL8019AS (RTL8019AS for 5-volt version only) 10BaseT Ethernet controllers. iChip CO561AD-S and iChip LAN contain non-volatile FLASH memory to store their firmware and Internet-related operational parameters. Remote firmware and parameter updates are supported through the local host link, by Email, using a Web browser or directly through the communications platform. 3.2 Technical Specifications 3.2.1 General iChip constitutes a complete Internet messaging solution for non-PC embedded devices. It acts as a mediator device to completely offload the host processor of Internet-related software and activities. An industry-standard asynchronous serial link connects iChip to the host processor. Programming, monitoring and control are fully supported using Connect One's AT+i extension to the standard AT command set. An additional industry-standard asynchronous serial link connects iChip CO561AD-S to a standard serial modem, while iChip LAN CO561AD-L connects to an Ethernet MAC for Internet access. In serial modem configurations, iChip supports direct host-to-modem operations using the standard AT command set. 3.2.2 Data Rates iChip supports standard baud rate configurations from 2,400 bps up to 57,600 bps, while iChip LAN supports bandwidth up to 230,000 bps on the host asynchronous serial communications bus. The default baud rate may be changed permanently by using the AT+iBDRF command. iChip & iChip LAN Datasheet 3-1 Functional Description 3.2.3 Operation All iChip Internet and parameter operations are controlled by AT+i commands. 3.2.3.1 Transparent Mode In modem configurations, iChip CO561AD-S defaults to transparent mode, allowing the host to control the modem device directly. Control is implemented by issuing standard AT commands to iChip. In this mode, iChip CO561AD-S transparently echoes the AT commands to the modem, as well as echoing the modem responses back to the host. In addition, hardware flow control signals are emulated on the host side to reflect the levels set by the modem and vice-versa. iChip CO561AD-S supports interlacing AT+i and AT commands, while the modem is in command mode. When the modem is put into data mode, by issuing a dial command, transparent mode is sustained throughout the data-mode session. 3.2.3.2 Command Mode iChip commands are implemented using the AT+i command set. Command flow exists only on the host serial bus between the host and iChip. 3.2.3.3 Internet Mode iChip enters Internet mode after being issued an Internet command such as to send or receive an Email message, open a socket, etc. iChip attempts to establish an Internet connection and carry out the required activity through the communication platform link. While in this mode, AT+i commands are supported to monitor and control the process when needed. 3.2.3.4 Direct Modem Firmware Update Mode In a modem configuration, issuing an AT+iFU command enters this mode. iChip CO561AD-S monitors the modem for an incoming call by detecting the `RING' response. When called, iChip CO561AD-S instructs the modem to answer the call and assumes a YMODEM session to receive a file containing a firmware update. The incoming file contents are downloaded and authenticated. If the new firmware image checks out the existing firmware is replaced in the on-chip flash memory and iChip CO561AD-S is reinitialized. 3.2.4 Remote Internet Firmware Update New firmware may be uploaded from a remote location using standard Internet protocols. The iChip accepts Emails with new firmware attachments, as well as firmware uploads from a remote browser through the iChip's Web server. 3.2.5 Host Serial Connection iChip supports a full-duplex, TTL-level serial communications link with the host processor. Full EIA-232-D hardware flow control, including Tx, Rx, CTS, RTS, and DTR lines, is supported. iChip & iChip LAN Datasheet 3-2 Functional Description 3.2.6 Serial Connection to Dial-up Modem iChip CO561AD-S supports a full-duplex, TTL-level serial communications link with the modem device. Full EIA-232-D hardware flow control, including Tx, Rx, CTS, RTS, and DTR lines, is supported. 3.2.7 Local Bus Connection to Ethernet Controller iChip LAN CO561AD-L directly supports Crystal LAN CS8900A or Realtek RTL8019AS IEEE 802.3 Ethernet controllers in 16-bit memory mode. Interrupts are directly connected to dedicated inputs. A small PLD or discrete logic is required for the CS8900A to generate the MEMRD#/MEMWE# and IORD#/IOWR# signals that form iChip's RD# and WR# signals to simulate memory, and IO accesses. See section 6.4, "Reference Design for Embedded LAN Using iChip LAN CO561AD-L". 3.2.8 Hardware and Software Flow Control Hardware flow control is supported between the host CPU and iChip. Hardware flow control is also provided between the iChip CO561AD-S and the modem. Flow control is programmed via the AT+iFLW command. The default flow control methods are set to Wait/Continue software flow control between iChip and host, and no flow control between iChip and modem. The hardware flow control method frees the host CPU from monitoring and handling the software flow control. The host can program iChip to either use hardware flow control or to use Wait/Continue software flow control between the iChip and the host CPU. The flow control mechanism is based on the RTS/CTS signals. Flow control between iChip and the Modem can be individually programmed to hardware flow control or no flow control. The Crystal CS8900A and Realtek RTL8019AS Ethernet controllers provide sufficient buffers to support the packet flow control on TCP/IP level between iChip LAN and the Ethernet LAN. iChip & iChip LAN Datasheet 3-3 Hardware Interface 4 Hardware Interface iChip CO561AD-S interfaces between a host CPU and a modem. 4.1 Host Interface The host interface is a serial DTE interface. iChip can change the rate and format of the data sent and received from the host CPU. Speeds of 2400, 4800, 7200, 9600, 19200, 38400, and 57600 bps (iChip LAN up to 230,400 bps) are supported in the following data format: Parity Data Length (No. of Bits) No. of Stop Bits None 8 1 Character Length (No. of Bits) 10 Table 4-1 Host Data Format iChip & iChip LAN Datasheet 4-1 Hardware Interface 4.2 Serial Modem Interface iChip CO561AD-S Serial Version Internal FLASH 512 KB Internal RAM 128 KB Local Bus Interface Unit CPU Core Local Addr Bus 20-bit Data Bus 16-bit WR RD RAM expansion CS Rx,Tx, CTS,RTS,DTR,DSR, RI,CD Interrupt Controller DMA Controller UART Host UART with auto baud rate Three 16-bit Timers Rx,Tx, CTS,RTS,DTR,DSR, CD Serial Modem WDT Figure 4-1 iChip CO561AD-S with a Serial Modem Interface In addition to a serial modem interface, iChip supports a memory expansion option that is used to increase the Web site storage buffer. iChip & iChip LAN Datasheet 4-2 Hardware Interface 4.3 Ethernet Controller Interface iChip LAN CO561AD-L For CS8900A Only Figure 4-3 iChip LAN with an Ethernet Controller Interface iChip and iChip LAN support a memory expansion option that is used to increase the Web site storage buffer. iChip & iChip LAN Datasheet 4-3 Pin Descriptions 5 Pin Descriptions 52 34 A2 ~WR 54 53 30 31 32 33 RXDH ~BHE ~RTSM A6 55 A0 A10 GND A9 A11 57 56 29 ~CTSH ~RTSH HLDA ~CDH 61 60 59 58 HOLD 62 65 64 63 ~RD GND ~CDM ~DSRM MMSEL ~DTRH 28 TXDM 26 27 25 24 AD6 AD15 TXDH ~CTSM RXDM AD8 AD12 ~DTRM A1 AD9 21 22 23 AD10 CO561AD-S ~RIH ~LCS AD11 -UCS ~DSRH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC AD5 AD4 AD3 AD2 AD1 AD0 A17 AD7 AD14 AD13 ~RES 68 67 66 5.1 iChip CO561AD-S Pin Assignments 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 A13 A19 A15 A12 A14 A5 A16 CLKO X2 X1 ALE URTINT A18 A8 A7 A4 A3 Figure 5-1 PLCC68 Package for iChip CO561AD-S Serial Version iChip & iChip LAN Datasheet 5-1 Pin Descriptions ~WR 52 55 54 53 A0 A10 GND A9 A11 57 56 ~CTSH ~RTSH ~CDH 34 30 31 32 33 RXDH 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 A13 A19 A15 A12 A14 A5 A16 CLKO X2 X1 ALE URTINT A18 A8 A7 A4 A3 NC A6 A2 29 NC ~BHE 28 25 26 27 24 AD6 AD15 TXDH NC NC AD8 AD12 21 22 23 ~LCS AD10 AD9 CO561AD-L 18 19 20 AD11 ~UCS ~DSRH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 LANDRQ A1 ~RIH VCC AD5 AD4 AD3 AD2 AD1 AD0 A17 AD7 AD14 AD13 ~RES 60 59 58 68 67 66 ~RD GND NC 65 ~LMSEL 64 LANINT 63 ~DTRH HOLD 62 HLDA 61 5.2 iChip LAN Pin Assignments Figure 5-3 PLCC68 Package for iChip LAN CO561AD-L Serial Version iChip & iChip LAN Datasheet 5-2 Pin Descriptions 5.3 iChip Pin Functional Descriptions 5.3.1 Local Bus Signals A19-A0 Address Bus (output, three-state, synchronous) These pins supply non-multiplexed memory or I/O addresses to the system one half of a CLKO period earlier than the multiplexed address and data bus AD15-AD0. During a bus hold or reset condition, the address bus is in a high-impedance state. AD15-AD0 Address and Data Bus (input/output, three-state, synchronous, level-sensitive) AD15-AD0--These time-multiplexed pins supply memory or I/O addresses and data to the system. This bus can supply an address to the system during the first period of a bus cycle. It supplies data to the system during the remaining periods of that cycle. When ~WR is de-asserted, these pins are three-stated. ALE Address Latch Enable (output, synchronous) This pin indicates to the system that an address appears on the address and data bus (AD15-AD0). The address is guaranteed to be valid on the trailing edge of ALE. This pin is not three-stated during a bus hold or reset. ~BHE Bus High Enable (three-state, output, synchronous) During a memory access, this pin and the least-significant address bit (AD0 or A0) indicate to the system, which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The ~BHE and AD0 pins are encoded as shown in the table below. ~BHE 0 1 0 1 AD0 0 0 1 1 Type of bus cycle Word Transfer Even Byte Transfer Odd Byte Transfer N/A Table 5-1 Data Byte Encoding BHE floats during bus hold and reset. During refresh cycles, the A bus and the AD bus are not guaranteed to provide the same address during the address phase of the AD bus cycle. For this reason, the A0 signal cannot be used in place of the AD0 signal to determine refresh cycles. CLKO Clock Output This pin Supplies the internal clock to the system. CLKO remains active during RESET. iChip & iChip LAN Datasheet 5-3 Pin Descriptions ~UCS Upper Chip Select (output, synchronous) This pin indicates to the system that that a memory access is in progress to the Flash memory. Normally this pin should be Open. HOLD Bus Hold Request (input, synchronous, level sensitive) This pin indicates to the iChip that an external bus master needs control of the local bus . Normally this pin should connect to GND. HLDA Bus Hold Acknowledge (output , synchronous, level sensitive) This pin asserted High to indicate to an external bus master that the iChip has release control of local bus. Normally this pin should be Open. ~LCS Low memory Ram Chip Select (output, synchronous) This pin indicates to the system that that a memory access is in progress to the Static Ram memory. Normally this pin should be Open. ~RD Read Strobe (output, synchronous, three-state) This pin indicates to the system that the iChip is performing a memory or I/O read cycle. ~RD is guaranteed to not be asserted before the address and data bus is floated during the address-to-data transition. ~RD floats during a bus hold condition. ~RES Reset (input, asynchronous, level-sensitive) This pin forces the iChip to perform a hardware reset. When ~RES is asserted, the iChip immediately terminates its present activity and clears its internal logic. ~RES must be held Low for at least 1 ms. ~RES can be asserted asynchronously to CLKO because ~RES is synchronized internally. For proper initialization, VCC must be within specifications, and CLKO must be stable for more than four CLKO periods during which RES is asserted. The iChip begins fetching instructions approximately 6.5 CLKO periods after ~RES is de-asserted. This input is provided with a Schmidt trigger to facilitate power-on RES generation via an RC network. URTINT Uart Interrupt (input, asynchronous) This pin is for debugging purpose only and reserved for future use. This pin is connected internally to a pull up resistor. iChip & iChip LAN Datasheet 5-4 Pin Descriptions ~WR Write Strobe (output, synchronous) This pin indicates to the system that the data on the bus is to be written to a memory or I/O device. ~WR floats during reset condition. X1 Crystal Input (input) This pin and the X2 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the iChip with an external clock source, connect the source to the X1 pin and leave the X2 pin unconnected. Duty cycle should be 45%-55%. X1 fall time (from 3.5-v to 1-v for 5-volt version, from 2-v to 1-v for 3.3-volt version) is 5 nsec maximum. X1 rise time (from 1-v to 3.5-v for 5-volt version, from 1-v to 2-v for 3.3-volt version) is 5 nsec maximum. X2 Crystal Output (output) This pin and the X1 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the iChip with an external clock source, leave the X2 pin unconnected and connect the source to the X1 pin. iChip & iChip LAN Datasheet 5-5 Pin Descriptions Selecting a Crystal C1 Crystal X1 X2 C2 Figure 5-5 Selecting a Crystal The characteristics of the built-in inverting amplifier set limits on the following parameters for crystals: Crystal first overtone frequency .................. 18.432 MHz ESR (Equivalent Series Resistance) ............ 40 max Drive Level ................................................. 1 mW max Frequency tolerance .................................... +/- 100ppm Load capacitance......................................... 18pF Shunt capacitance........................................ 7pF Maximum The recommended range of values for C 1 and C 2 are as follows: C 1 ............................................................... 15 pF 20% C 2 ............................................................... 22 pF 20% The specific values for C1 and C2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. GND Ground Ground pins connect the iChip to the system ground. VCC Power Supply (input) These pins supply power (+5-v) to the iChip. iChip & iChip LAN Datasheet 5-6 Pin Descriptions 5.3.2 Host Interface Signals TXDH Transmit Data Host (output, asynchronous) This pin supplies asynchronous serial transmit data to the host system from the serial port. RXDH Receive Data Host (input, asynchronous) This pin supplies asynchronous serial receive data from the host system to the asynchronous serial port. ~CTSH Clear-to-Send Host (input, asynchronous) This pin provides the Clear-to-send signal to the asynchronous host serial port when hardware flow control is enabled for the port. The ~CTSH signal gates the transmission of data from the associated serial port transmit register. When ~CTSH is asserted, the transmitter begins transmission of a frame of data, if any is available. If ~CTSH is deasserted, the transmitter holds the data in the serial port transmit register. The value of ~CTSH is checked only at the beginning of the transmission of the frame. Connect ~CTSH to ~RTSH when not using this pin. ~RTSH Ready-to-Send Host (output, asynchronous) This pin provides the Ready-to-send signal to the asynchronous serial port when the hardware flow control is enabled for the port. The ~RTSH signal is asserted when the associated serial port transmit register contains data which has not yet been transmitted. ~DSRH Data Set Ready Host (input, synchronous) When flow control is enabled, this pin is Data Set Ready Input. Connect ~DSRH to GND when not using this pin. ~DTRH Data Terminal Ready Host (output, synchronous) When flow control is enabled, this pin operates as Data Terminal Ready Output. ~CDH Carrier Detect Host (output, synchronous) This pin indicates to the system that the modem communication device detects a carrier signal. iChip & iChip LAN Datasheet 5-7 Pin Descriptions ~RIH Ring Indicator Host (output, synchronous) This pin indicates to the system that the modem communication device detects a Ring signal. 5.3.3 iChip Serial Modem Signals RXDM Receive Data Modem (input, asynchronous) This pin supplies asynchronous serial receive data from the modem to the asynchronous serial port. TXDM Transmit Data Modem (output, asynchronous) This pin supplies asynchronous serial transmit data to the modem from the serial port. ~CDM Carrier Detect Modem (input, asynchronous, internal pull-up) When configured in Serial-to-Serial mode, this pin is Carrier Detect input. ~DSRM Data Set Ready Modem (input, asynchronous) When Flow control is enabled, this pin is Data Set Ready input. Connect ~DSRM to GND when not using this pin. ~RTSM Ready-to-Send Modem (output, asynchronous) This pin provides the Ready to Send signal for asynchronous serial port when the hardware flow control is enabled for the port. The ~RTSM signal is asserted when the associated serial port transmit register contains data that has not been transmitted. ~CTSM Clear-to-Send Modem (input, asynchronous) Enable-Receiver-Request M (input, asynchronous) This pin provides the Clear to Send signal for asynchronous serial port when flow control option is enabled. The ~CTSM signal gates the transmission of data from the associated serial port transmit register. When ~CTSM is asserted, the transmitter begins transmission of a frame of data, if any is available. If ~CTSM is de-asserted, the transmitter holds the data in the serial port transmit register. The value of ~CTSM is checked only at the beginning of the transmission of the frame. Connect ~CTSM to ~RTSM when not using this pin. ~DTRM Data Terminal Ready Modem (output, asynchronous) When flow control is enabled, this pin is Channel Data Terminal Ready Output. iChip & iChip LAN Datasheet 5-8 Pin Descriptions MMSEL Modem Mode Input (input, asynchronous) (For modem application only) When this pin is held Low during power up, for at least 5 seconds, the iChip will automatically enter firmware update mode. During a firmware update procedure, when an external modem dials to the iChip, pulling this pin down to Low will cause the iChip to immediately answer the call and begin the update session. When this pin is held Low during power up for less than 5 seconds, it forces the iChip into auto baud rate detection. 5.4 iChip LAN Signals LANINT LAN Interrupt (active high input) This pin inputs the interrupt from the Ethernet controller. LANDRQ LAN DMA Request (active high input) This pin inputs the DMA request from the Ethernet controller. LMSEL LAN Mode Input (input, asynchronous) (For LAN application only) When this pin is held Low during power up for at least 5 seconds, the iChip will automatically enter firmware update mode. iChip & iChip LAN Datasheet 5-9 Electrical/Mechanical Specifications 6 Electrical/Mechanical Specifications 6.1 Environmental Specifications 6.1.1 Absolute Maximum Ratings 6.1.1.1 3.3-Volt Version Parameter Voltage at any pin with respect to ground Operating temperature Storage temperature Soldering temperature (max. 10 sec.) Package dissipation Rating -0.5 to VCC + 0.5 Volts 0C to 70C (32 to 158F) -60C to 120C (-76 to 248F) 220C (428F) 1.5 Watts Table 6-1 Environmental Specifications 3.3-Volt Version 6.1.1.2 5-Volt Version Parameter Voltage at any pin with respect to ground Operating temperature Storage temperature Soldering temperature (max. 10 sec.) Package dissipation Rating -0.5 to VCC +0.5 Volts 0C to 70C (32 to 158F) -60C to 120C (-76 to 248F) 220C (428F) 1.5 Watts Table 6-3 Environmental Specifications 5-Volt Version iChip & iChip LAN Datasheet 6-1 Electrical/Mechanical Specifications 6.1.2 DC Operating Characteristics 6.1.2.1 3.3-Volt Version Parameter DC Supply High-level Input High-level Input for X1 Low-level Input High-level Output1 Low-level Output2 Input leakage current Power supply current (Operating Mode)3 Power supply current (Power Save Mode) Input capacitance Min Typical Max 3.0 2.0 VCC-0.8 -0.5 VCC-0.5 3.3 3.6 VCC+0.5 VCC+0.5 0.8 VCC 0.45 +/- 10 80 70 1 Units Volts Volts Volts Volts Volts Volts A mA mA 20 pF Notes: 1 IOH = 0.2mA 2 IOL = 1mA 3 20 MHz clock Table 6-5 DC Operating Characteristics 3.3-Volt Version 6.1.2.2 5-Volt Version Parameter DC Supply High-level Input Low-level Input High-level Output1 High-level Input for X1 Low-level Output2 Input leakage current Power supply current (Operating Mode)3 Power supply current (Power Save Mode) Input capacitance Min Typical Max 4.75 2.0 -0.5 2.4 VCC-0.8 5.0 5.25 VCC+0.5 0.8 VCC VCC+0.5 0.45 +/- 10 220 160 10 Units Volts Volts Volts Volts Volts Volts A mA mA 20 pF Notes: 1 IOH = 2.4mA 2 IOL = 2mA 3 20 MHz clock Table 6-7 DC Operating Characteristics 5-Volt Version iChip & iChip LAN Datasheet 6-2 Electrical/Mechanical Specifications 6.2 Interface Timing and Waveforms 6.2.1 Local Bus Read Cycle Tclk CLKO Tclk-3 Address A19-A0 10 AD15-AD0 (Read) Data 3 UCS LCS 25 25 ALE 2Tclk-15 ~RD ~BHE 0-25 0-25 ~BHE Figure 6-1 Local Bus Read Cycle iChip & iChip LAN Datasheet 6-3 Electrical/Mechanical Specifications 6.2.2 Local Bus Write Cycle Tclk CLKO Tclk-3 Address A19-A0 15 AD15-AD0 (Read) Data 0 UCS LCS 25 25 ALE 2Tclk-10 ~WR ~BHE 0-20 0-25 ~BHE Figure 6-3 Local Bus Write Cycle iChip & iChip LAN Datasheet 6-4 Electrical/Mechanical Specifications 6.3 Mechanical Dimensions 1.27 mm/ 0.050" 24.5mm/ 0.965" CO561AD-S//L 0.5 mm/ 0.020" 25.2 mm/ 0.995" iChipTM /iChip LANTM 4.9 mm/ 2.69 mm/ 0.193" 0.106" 1.78 mm/0.070" Figure 6-5 Mechanical Dimensions iChip & iChip LAN Datasheet 6-5 iChip Designs 7 iChip Designs 7.1 General Hardware Architecture 7.1.1 Serial Modem Environment Embedded CPU (Host) Serial iChip Serial Data Modem Phone Figure 7-1 Serial Modem Environment 7.1.2 Ethernet Controller Environment with CS8900A D0-15 Embedded CPU (Host) iChip LAN Serial A0-19 RD WR PLD IORD IOWR MEMRD MEMWR CS8900A Ethernet Controller LAN AEN IRQ CS Figure 7-3 CS8900A Ethernet Controller Environment 7.1.3 Ethernet Controller Environment with RTL8019AS D0-15 Embedded CPU (Host) Serial iChip LAN RTL8019AS Ethernet Controller A0-19 RD WR LAN IRQ Figure 7-5 RTL8019AS Ethernet Controller Environment iChip & iChip LAN Datasheet 7-1 iChip Designs 7.2 Reference Design for Embedded iModem Using CO561AD-S Figure 7-6 Reference Design for Embedded iModem Using CO561AD-S iChip & iChip LAN Datasheet 7-2 iChip Designs 7.3 Bill of Materials for CO561AD-S Reference Design # 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. Qty 4 4 1 2 1 2 1 16 2 5 1 1 1 1 8 2 1 1 2 3 2 1 1 1 1 1 1 1 1 Reference Designator C1,C2,C3,C4 C5,C8,C14,C16 C6 C7,C13 C9,C10 C11,C12 C15 C17,C18,C19,C20,C21,C22, C23,C24,C25,C26,C27,C28, C29,C30,C31,C32 C33,C34 D1,D2,D3,D4,D5 J1 J2 J3 LS1 L1,L2,L3,L4,L5,L6,L7,L8 L9,L10 RV1 R1 R2,R3 R7,R9,R10 R4,R8 S1 U1 U2 U3 U4 U5 U6 Y1 P/N, Description 1UF/16V, Tantalum 0.1UF, Ceramic 0.047UF Ceramic 10UF/6.3V 22PF, Ceramic 1NF/3KV 1000UF/25V 56pF, Ceramic 10UF/16V LED, 10mA DC-JACK-MALE DB-9/FEMALE RJ11 HPE-1206, Speaker 50 BK2125HS601 2961666681 1.5KE220A 10, 0.125W 18R, 0.75W 4.7K, 0.125W 470, 0.125W PB Switch CO561AD-S SF336D/SP-H1-D5 7805 MC34164P MAX237CWG LM386D 18.432MHz, parallel resonance, 100ppm Manufacturer Taiyoyuden Co. Ltd. Fair Rite Inc. Connect One Ltd. Conexant On Semiconductor Maxim Integrated Products National Semiconductor Table 7-1 Bill of Materials for CO561AD-S Reference Design Item #27 SFXXD/SP-H1-YY, Conexant SocketModem, can be ordered in the following configurations: XX = 56 (56,000 bps), 336 (33,600 bps), 144 (14,400 bps) YY = D5: (U.S), DF (France), DG (Germany), DT (Italy), DE (Spain), DJ (Japan), DC (CTR21: CTR21 countries include Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Norway, Portugal, Spain, Sweden, Switzerland, The Netherlands, and UK. The country is selected by issuing the AT*NC70 command.) iChip & iChip LAN Datasheet 7-3 iChip Designs 7.4 Reference Design for iLAN Using CO561AD-L and CS8900A Figure 7-8 Reference Design for iLAN Using CO561AD-L and CS8900A iChip & iChip LAN Datasheet 7-4 iChip Designs 7.5 Bill of Materials for CO561AD-L+CS8900A Reference Design # 1 2 Qty 1 13 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 1 1 2 5 1 1 1 8 1 1 3 2 1 1 6 1 2 1 1 1 1 1 1 1 1 Reference Designator C10 C1,C2,C3,C4,C5,C6,C7,C11, C12,C13,C16,C22,C24 C14,C15,C17,C18,C19,C20 C21 C23 C8,C9 D1,D2,D3,D4,D5 JP1 J2 J3 L1,L2,L3,L4,L5,L6,L7,L8 L9 R1 R2,R3,R19 R4,R7 R5 R6 R8,R9,R10,R11,R13,R17 R12 R15,R14 S1 U1 U2 U3 U5 U7 U8 Y1 29 1 Y2 P/N, Description 68pF 0.1UF 1UF/16V-A 100UF/16V 10UF/16V-B 22pF LED RJ-7251 DC-JACK-MALE DB-9/FEMALE KNH21471 2961666681 100/1% 4.7K 24.3/1% 100K 0 470 4.99K/1% 10K PB SW CO561AD-L CS8900A TL7705ACD PAL16V8 MAX237CWG 7805 18.432MHz, parallel resonance, 100ppm 20MHz, parallel resonance, 50ppm Manufacturer Transpower AVX Corporation Fair Rite Connect One Ltd. Crystal Texas Instruments Maxim Integrated Products Table 7-3 Bill of Materials for CO561AD-L and CS8900A Reference Design Notes: 1 RJ-725 includes the magnetic and connector component. RJ-725 pinout on the PCB is different from RJ-45 pinout. (Check RJ-725 datasheet for more details.) iChip & iChip LAN Datasheet 7-5 iChip Designs 7.6 PLD Equations ------------------------------------------------------------------- File name: imdlnref.vhd -- Designed by: Leonid Epstein -- Purpose: iLAN board Control Logic. -- The board memory map: -- 0x00000 - 0x1ffff - system SRAM -- 0x20000 - 0x27fff - LAN IO space (32KB) -(default IO 0x300 so the first access s.b. to 0x20300) -- 0x28000 - 0x2ffff - LAN DMA access (32KB) -- 0x38000 - 0x3ffff - LAN memory space (32KB) -- 0x80000 - 0xfffff - System FLASH -----------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; entity imdlnref is port ( a : in std_logic_vector(19 downto 15); wr_n : in std_logic; rd_n : in std_logic; memwr_n : out std_logic; memrd_n : out std_logic; iowr_n : out std_logic; iord_n : out std_logic; aen : out std_logic ); attribute attribute attribute attribute attribute attribute attribute attribute attribute attribute attribute attribute attribute loc : string ; loc of wr_n : signal is "P2" ; loc of rd_n : signal is "P3" ; loc of a15 : signal is "P4" ; loc of a16 : signal is "P5" ; loc of a17 : signal is "P6" ; loc of a18 : signal is "P7" ; loc of a19 : signal is "P8" ; loc of memwr_n : signal is "P13" ; loc of memrd_n : signal is "P14" ; loc of iowr_n : signal is "P15" ; loc of iord_n : signal is "P16" ; loc of aen : signal is "P17" ; end imdlnref; architecture behavioral of imdlnref is signal mem_access: std_logic; signal io_access: std_logic; signal dma_access: std_logic; begin mem_access <= '1' when a(19 downto 16) = "0011" and a(15) = '1' else '0'; -- 0x38000 - 0x3FFFF ; io_access <= '1' when a(19 downto 16) = "0010" and a(15) = '0' else '0'; -- 0x20000 - 0x27FFF ; dma_access <= '1' when a(19 downto 16) = "0010" and a(15) = '1' else '0'; -- 0x28000 - 0x2FFFF ; memwr_n <= wr_n when mem_access = '1' else '1'; memrd_n <= rd_n when mem_access = '1' else '1'; iowr_n <= wr_n when io_access = '1' or dma_access = '1' else '1'; iord_n <= rd_n when io_access = '1' or dma_access = '1' else '1'; aen <= '1' when dma_access = '1' else '0' ; end behavioral; iChip & iChip LAN Datasheet 7-6 iChip Designs 7.7 Reference Design for iLAN Using CO561AD-L and RTL8019AS Figure 7-9 Reference Design for iLAN using CO561AD-L and RTL8019AS iChip & iChip LAN Datasheet 7-7 iChip Designs Figure 7-10 Reference Design for iLAN Using CO561AD-L and RTL8019AS iChip & iChip LAN Datasheet 7-8 iChip Designs 7.8 # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Bill of Materials for CO561AD-L and RTL8019AS Reference Design Qty Reference Designator 14 C1,C6,C7,C8,C12,C15,C17, C18,C19,C22,C23,C24,C25, C26 7 2 2 1 2 1 2 2 1 1 1 2 5 4 1 1 1 1 1 1 1 1 1 1 1 1 1 C2,C3,C4,C5,C11,C13,C14 C20,C21 C9,C10 C16 D2,D1,D6 D3 D5,D4 D8,D7 J1 J2 J3 R16,R1 R2,R3,R8,R10,R11 R4,R5,R6,R7 R9 R12 R13 R14 R15 SW1 U1 U2 U3 U4 U5 X1 X2 P/N, Description 0.1UF 1UF/16V 33PF 22PF 820UF/35V GREEN LED 1N4001 RED LED 1N4148 DB-9/FEMALE DC-JACK-MALE RJ725 10K 470 4.7K 100K 200 1M 0 1K PB_SW MAX3238CAI CO561AD-L/20PC-5 TL7705ACD LM7805 RTL8019AS 18.432Mhz 20Mhz Manufacturer Transpower Maxim Connect One Ltd. T.I Realtek Table 7-6 Bill of Materials for CO561AD-L and RTL8019AS Reference Design iChip & iChip LAN Datasheet 7-9 SQT--109-03--L-S-MW iChip & iChip LAN Datasheet 32 31 30 29 28 27 PT1(TIP) PT32(TXIND) PT31(DTRIND) PT30(RXIND) PT29(DCDIN) PT28(~PULSE) PT27(~RDL) DGND PT25(NC) PT24(~RESET) PT9(RDET/CID) PT8(XFMR2) PT7(XFMR1) PT6(ACOUT2) PT5(ACOUT1) PT4(RDETIN2) PT3(RDETIN1) PT2(RING) SQT--111-03--L-S-MW 26 25 24 9 8 7 6 5 4 3 2 1 33T 34T 35T 36T 37T 38T 39T 40T 41T 54 55 56 57 58 59 60 61 62 63 64 ~RIM ~RTSM RXDM ~CTSH TXDH RXDH ~RIH ~DTRH ~RTSH ~DCDH ~DSRM TXDM GND ~DSRH ~CTSM ~CDM ~DTRM GND PT54(~VC) PT53(~VOICE) PT56 (NC) PT59(TELIN) PT58(TELOU) T PT57(LCS) PT60(MICM) VCC PT62(MICV) GND PT64(SPKR) 33B 34B 35B 36B 38B 37B 39B 40B 41B Socket iChip Carrier Board 8 Socket iChip Carrier Board The Socket iChipTM Internet Controller, CO561AD-C, is the iChip CO561AD-S on a carrier board that is pin-compatible with Conexant's SocketModemTM. 8.1 Pin Assignments TMM-109-01-L-S-SM Print Side Connector MMS-109-02-L-SV-K Component Side SQT--109-03--L-S-MW Figure 8-1 Carrier Board CO561AD-C Pinout 8-1 Socket iChip Carrier Board 8.2 Pin Functional Descriptions 8.2.1 SocketModem Interface Signals PTx Pass-Through connections The board provides pass-through connection between a motherboard and a SocketModem mounted on top of the CO561AD-CT/R. Pins PT1 .. PT9 are dedicated for TNV signals. The CO561AD-CT/R board layout meets EN 60950:1992 +A1/A2:1993 +A3:1995 requirements for creepage distance and clearance. Signal names in brackets correspond to the Conexant SocketModem data sheet. VCC +5VDC DGND Digital Ground Connect to Digital Ground on the interface circuit. ~RESET Modem and iChip Reset The Active Low ~RESET input resets both the iChip and a SocketModem logic and returns the AT command set to the original factory default values and to "stored values" in NVRAM. AGND Analog Ground Connect to Analog Ground on the interface circuit. Note that AGND is connected to DGND on the SocketModem. RXDM, Received Data (TTL Active Low, EIA-232 Active High), Input This pin supplies asynchronous serial receive data from Socket modem to asynchronous serial port. TXDM, Transmitted Data Modem (TTL Active Low, EIA-232 Active High), Output This pin supplies asynchronous serial transmit data to Socket modem from serial port. ~CTSM, Clear To Send Modem (TTL Active Low, EIA-232 Active High), Input This pin provides the Clear to Send signal for asynchronous serial port when flow control option is enabled. The ~CTSM signal gates the transmission of data from the associated serial port transmit register. When ~CTSM is asserted, the transmitter begins transmission of a frame of data, if any is available. If ~CTSM is de-asserted, the iChip & iChip LAN Datasheet 8-2 Socket iChip Carrier Board transmitter holds the data in the serial port transmit register. The value of ~CTSM is checked only at the beginning of the transmission of the frame. ~RTSM, Ready To Send Modem (TTL Active Low, EIA-232 Active High),Output This pin provides the Ready to Send signal for asynchronous serial port when the hardware flow control is enabled for the port. The ~RTSM signal is asserted when the associated serial port transmit register contains data that has not been transmitted. ~DTRM, Data Terminal Ready Modem (TTL Active Low, EIA-232 Active High), Output When flow control is enabled, this pin is Channel Data Terminal Ready Output. ~DSRM, Data Set Ready Modem (TTL Active Low, EIA-232 Active High), Input When Flow control is enabled, this pin is Data Set Ready input. ~RIM, Ring Indicate Modem (TTL Active Low, EIA-232 Active High), Input ~RIM input ON (low) indicates the presence of an ON segment of a ring signal on the telephone line (This signal is ignored by the Socket iChip). ~CDM, Carrier Detect Modem (TTL Active Low, EIA-232 Active High), Input This pin is the Carrier Detect Input from the modem. 8.2.2 Host Interface Signals CO561AD CT/R Interfaces to a Host CPU via asynchronous serial interface with TTL (T) or EIA-232 (R) signal levels. ~ TXDH/TXD232 Transmit Data Host (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from serial port. ~RXDH/RXD232 Receive Data Host (input, asynchronous) This pin supplies asynchronous serial receive data from the system to asynchronous serial port. ~CTSH/CTS232 Clear-to-Send Host (input, asynchronous) This pin provides the Clear to Send signal for asynchronous serial port 1 when the hardware flow control is enabled for the port. The ~CTSH signal gates the transmission of data from the associated serial port transmit register. When ~CTSH is asserted, the transmitter begins transmission of a frame of data, if any is available. If ~CTSH is deasserted, the transmitter holds the data in the serial port transmit register. The value of ~CTSH is checked only at the beginning of the transmission of the frame. iChip & iChip LAN Datasheet 8-3 Socket iChip Carrier Board ~RTSH/RTS232 Ready-to-Send Host (output, asynchronous) This pin provides the Ready to Send signal for asynchronous serial port when the hardware flow control is enabled for the port. The ~RTSH signal is asserted when the associated serial port transmit register contains data which has not been transmitted. ~DSRH/DSR232 Data Set Ready Host (input, synchronous) When flow control is enabled, this pin is Data Set Ready Input. ~DTRH/DTR232 Data Terminal Ready Host (input, synchronous) When flow control is enabled, this pin operates as Data Terminal Ready Output. ~CDH/CD232 Carrier Detect Host (output, synchronous) This pin indicates to the system that the communication device (modem) detected the carrier. ~RIH/RI232 Ring Indicator Host (output, synchronous) This pin indicates to the system that the communication device (modem) detected the Ring signal. iChip & iChip LAN Datasheet 8-4 Socket iChip Carrier Board 8.3 Socket iChipTM Package Dimensions Figure 8-3 Socket iChip Package Dimensions iChip & iChip LAN Datasheet 8-5 Socket iChip Carrier Board 8.4 Reference Design for CO561AD-C Based Modem Figure 8-5 Reference Design for CO561AD-C Based Modem iChip & iChip LAN Datasheet 8-6 Socket iChip Carrier Board 8.5 Bill of Materials for CO561AD-C Reference Design # 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. Qty 4 1 4 2 2 1 16 2 5 1 1 1 2 8 1 2 1 2 2 1 1 1 1 1 1 1 Reference Designator C1,C2,C3,C4 C8 C6,C10,C18,C5 C19,C13,C7 C15,C16 C11 C21,C22,C23,C24,C25 ,C26,C27,C28,C29,C30 ,C31,C32,C33,C34,C35,C36 C37,C39 D1,D2,D3,D4,D5 J12 J11 J9 L2,L3 L4,L5,L6,L7,L8,L9,L10,L11 RV1 R22,R23 R24 R2,R3 R35 S1 U1 U2 U5 U8 U6 LS1 P/N, Description 1UF/16V, Tantalum 0.047UF 0.1UF, Ceramic 10UF/16V 1NF/3KV 100UF/16V 56Pf, Ceramic 0.47UF CERAMIC LED DC-JACK-MALE DB-9/FEMALE RJ11 2961666681 BK2125HS601 1.5KE220A 18R,1W 10R 4.7K 470 PB Switch LM386 CO561AD-C 7805 TL7705ACD MAX237CWG HPE-1206, Speaker 50 Manufacturer Fair Rite Inc. Taiyoyuden Co. Ltd. National Semiconductor Connect One Ltd. Texas Instruments Maxim Integrated Products Table 1-1 Bill of Materials for CO561AD-C Reference Design iChip & iChip LAN Datasheet 8-7 PCB Design and Layout Considerations 9 PCB Design and Layout Considerations 9.1 Design Consideration Good engineering practices must be adhered to when designing a printed circuit board (PCB) containing the SocketModem module. Suppression of noise is essential to the proper operation and performance of the modem itself and for surrounding equipment. Two aspects of noise in an OEM board design containing the Conexant SocketModem module must be considered: on-board/off-board generated noise that can affect analog signal levels and analog-to-digital conversion (ADC)/digital-to-analog conversion (DAC), and on-board generated noise that can radiate off-board. Both on-board and off-board generated noise that is coupled on-board can affect interfacing signal levels and quality, especially in low level analog signals. Of particular concern is noise in frequency ranges affecting modem performance. On-board generated electromagnetic interference (EMI) noise that can be radiated or conducted off-board is a separate, but equally important, concern. This noise can affect the operation of surrounding equipment. Most local governing agencies have stringent certification requirements that must be met for use in specific environments. Proper PC board layout (component placement, signal routing, trace thickness and geometry, etc.), component selection (composition, value, and tolerance), interface connections, and shielding are required for the board design to achieve desired modem performance and to attain EMI certification. 9.2 PC Board Layout Guidelines 1. In a 2-layer design, all unused space around and under components should be filled with copper connected to the board ground on both sides of the board, and connected in such a manner as to avoid small islands. Isolated islands should be avoided by connecting all grounds on the same side at several points and to the ground plane on the opposite side through the board at several points. In a modem design, connect the SocketModem DGND and AGND pins to the ground plane. 2. In a 4-layer design, provide an adequate ground plane covering the entire board. In a modem design, SocketModem DGND and AGND pins are tied together on the SocketModem. Do not split analog and digital ground planes. 3. As a general rule, route digital signals on the component side of the PCB and the analog signals on the solder side. The sides may be reversed to match particular OEM requirements. Route the digital traces perpendicular to the analog traces to minimize signals cross coupling. 4. Route the modem signals to provide maximum isolation between noise sources and noise sensitive inputs. When layout requirements necessitate routing these iChip & iChip LAN Datasheet 9-1 PCB Design and Layout Considerations signals together, they should be separated by neutral signals. For the iChip LAN version, void power/ground plane as well as other digital signals between the CS8900A or RTL8019AS and the RJ45 or RJ725 module. 5. All power and ground traces should be at least 0.05 in. wide. 6. 0.1 UF ceramic capacitors should be placed as close as possible to the power pins. When internal power plane is used, the traces connecting between the power pins of the components and the vias should be kept short and to have bypass capacitor between the via and the pin. 7. In a modem design, TIP and RING signal traces are to be no closer than 0.062" from any other traces for U.S. applications. TIP and RING signal traces are to be no closer than 2.5mm (0.1") from any other traces for European applications. 2.5mm spacing must be used if the host board is to support both U.S. and European Socket Modems. In multi layer design, power and ground planes should be cleared underneath the traces, which belong to the primary (TIP and RING) circuit. For an Ethernet design, route differential signals (RXD, TXD) close together as pairs. Try to avoid vias. 8. In a modem design, if the SocketModem is mounted flush with the host PCB, the host PCB should be clear of all traces directly underneath the SocketModem oscillator section. It is strongly suggested that the SocketModem be mounted at least 0.130 inch above the host board. 9.2.1 Electromagnetic Interference (EMI) Considerations In a modem design, the following guidelines are offered to specifically help minimize EMI generation. Some of these guidelines are the same as, or similar to, the general guidelines but are mentioned again to reinforce their importance. In order to minimize the contribution of the SocketModem-based design to EMI, the designer must understand the major sources of EMI and how to reduce them to acceptable levels. 1. Keep traces carrying high frequency signals as short as possible. 2. Decouple power from ground with decoupling capacitors as close to the active components' power pins as possible. 3. Eliminate ground loops, which are unexpected current return paths to the power source and ground. 4. Decouple the telephone line cables at the telephone line jacks. Typically, use common mode chokes and shunt capacitors. Methods to decouple telephone lines are similar to decoupling power lines, however, telephone line decoupling may be more difficult and deserves additional attention. A commonly used design aid is to place footprints for these components and populate as necessary during performance/EMI testing and certification. iChip & iChip LAN Datasheet 9-2 PCB Design and Layout Considerations 5. Decouple the power cord at the power cord interface with decoupling capacitors. Methods to decouple power lines are similar to decoupling telephone lines. 6. Locate cables and connectors so as to avoid coupling from high frequency circuits. 7. Avoid right angle turns on high frequency traces. Forty-five degree corners are good, however, radius turns are better. 9.2.2 Other Considerations in a Modem Design The pins of all SocketModems are grouped according to function. The DAA interface, host interface, and LED interface pins are all conveniently arranged, easing the host board layout design. Conexant has tested each of the W.Class SocketModems for compliance with their respective country's PTT requirements and has received PTT certificates that cover, without additional expense to the user, all applications that use these SocketModems in their respective countries. The certificates apply only to designs that route TIP and RING (pins 1 and 2) directly to the telco jack. Only specified EMI filtering components are allowed on these two signals. iChip & iChip LAN Datasheet 9-3 Protocol Compliance 10 Protocol Compliance iChip complies with the following Internet standards: RFC 768 RFC 791 RFC 792 RFC 793 RFC 821 RFC 826 RFC 951 RFC 822 RFC 1331 RFC 1332 RFC 1334 RFC 1661 RFC 1939 RFC 1957 RFC 2045 RFC 2046 RFC 2047 RFC 2048 RFC 2049 RFC 2068 RFC 2131 RFC 2132 User Datagram Protocol (UDP) Internet Protocol (IP) Internet Control Message Protocol Transmission Control Protocol (TCP) Simple Mail Transfer Protocol (SMTP) Ethernet Address Resolution Protocol (iChip LAN) Bootstrap Protocol (iChip LAN) Standard for the Format of ARPA Internet Text Messages Point-to-Point Protocol (PPP) (iChip CO561AD-S/P ) PPP Internet Protocol Control Protocol (IPCP) (iChip CO561AD-S) PPP Authentication Protocols (PAP) (iChip CO561AD-S) Point-to-Point Protocol (PPP) (iChip CO561AD-S) Post Office Protocol - Version 3 (POP3) Some Observations on the Implementations of the Post Office Protocol (POP3) Multipurpose Internet Mail Extensions (MIME) Part One: Format of Internet Message Bodies Multipurpose Internet Mail Extensions (MIME) Part Two: Media Types MIME (Multipurpose Internet Mail Extensions) Part Three: Message Header Extensions for Non-ASCII Text Multipurpose Internet Mail Extensions (MIME) Part Four: Registration Procedures Multipurpose Internet Mail Extensions (MIME) Part Five: Conformance Criteria and Examples HyperText Transfer Protocol HTTP/1.1 Dynamic Host Configuration Protocol (iChip LAN) DHCP Options and BOOTP Vendor Extensions (iChip LAN) Table 10-1 Internet Protocol Compliance iChip & iChip LAN Datasheet 10-1 List of Terms and Acronyms 11 List of Terms and Acronyms 10BaseT ARP AT+iTM Base64 CHAP DHCP DNS iChipTM ICMP IP IPCP ISP LAN LCP MAC MAC Address 10-Mbps baseband Ethernet specification using two pairs of twisted-pair cabling (Category 3, 4, or 5): one pair for transmitting data and the other for receiving data. Address Resolution Protocol. Internet protocol used to map an IP address to a MAC address. Connect One's Internet extension to the industry-standard Hayes AT command set. Supports simplified Internet connectivity commands in the spirit of the AT syntax. Encoding scheme, which converts arbitrary binary data into a 64-character subset of US ASCII. The encoded data is 33% larger than the original data. Challenge Authentication Protocol. Extends the PAP procedure by introducing advanced elements of security. Dynamic Host Configuration Protocol. Provides a mechanism for allocating IP addresses dynamically so that addresses can be reused when hosts no longer need them. Domain Name System. Defines the structure of Internet names and their association with IP addresses. Connect One's Internet Controller for embedded Internet connectivity. Internet Control Message Protocol. Network layer Internet protocol that reports errors and provides other information relevant to IP packet processing. Internet Protocol. Provides for transmitting blocks of data, called datagrams, from sources to destinations, which are hosts identified by fixed length addresses. Also provides for fragmentation and reassemble of long datagrams, if necessary. Internet Protocol Control Protocol. Establishes and configures the Internet Protocol over PPP. Also negotiates Van Jacobson TCP/IP header compression with PPP. Internet Service Provider. Commercial company that provides Internet access to end (mostly PC) users through a dial-up connection. Local Area Network. High-speed, low-error data network covering a relatively small geographic area (up to a few thousand meters). Link Control Protocol. Negotiates data link characteristics and tests the integrity of the link. Media Access Control. Lower of the two sublayers of the data link layer defined by the IEEE. The MAC sublayer handles access to shared media, such as whether token passing or contention will be used. Standardized data link layer address required for every port or device that connects to a LAN. Other devices in the network use these addresses to locate specific ports in the network and to create and update routing tables and data structures. MAC addresses are 6 bytes long and are controlled by the IEEE. It is represented as a 12-digit hexadecimal integer, where the first six digits are the Connect One company identification "000394". iChip & iChip LAN Datasheet 11-1 List of Terms and Acronyms MIME PAP ping POP3 PPP RFC SMTP TCP "Leave on Server" Multipurpose Internet Mail Extensions. Extends the format of mail message bodies to allow multi-part textual and non-textual data to be represented and exchanged between Internet mail servers. Password Authentication Protocol. Used optionally by the PPP protocol to identify the user to the ISP. packet internet groper. ICMP echo message and its reply. Often used in IP networks to test the accessibility of a network device. Post Office Protocol Version 3. Allows a workstation/PC to dynamically retrieve mail from a mailbox kept on a remote server. Point-to-Point Protocol. Communications protocol used to send data across serial communication links, such as modems. Request For Comments. Collections of standards that define the way remote computers communicate over the Internet. Simple Mail Transfer Protocol. Provides for transferring mail reliably and efficiently over the Internet. Transmission Control Protocol. Provides reliable stream-oriented connections over the Internet. Works in conjunction with its underlying IP protocol. An option designating whether retrieved Email messages are to be left intact on the server for subsequent downloads or are to be deleted from the server after a successful download. Table 11-1 Terms and Acronyms iChip & iChip LAN Datasheet 11-2 Index 12 Index iChip LAN with an Ethernet Controller Interface ......................................... 4-3 3.3-Volt Version ................................ 6-1 5-Volt Version ................................... 6-2 Absolute Maximum Ratings .............. 6-1 Bill of Materials for CO561AD-C Reference Design ........................... 8-8 Bill of Materials for CO561AD-L Reference Design ........................... 7-5 Bill of Materials for CO561AD-S Reference Design ........................... 7-3 Carrier Board CO561AD-C Pinout.... 8-2 Command Mode................................. 3-2 Data Byte Encoding ........................... 5-3 Data Rates .......................................... 3-1 DC Operating Characteristics 3.3-V Version........................................... 6-2 DC Operating Characteristics 5-V Version........................................... 6-2 DC Operation Characteristics ............ 6-2 Designs Considerations...................... 9-1 Direct Modem Firmware Update Mode ........................................................ 3-2 Electrical/Mechanical Specifications. 6-1 Electromagnetic Interference (EMI) Considerations................................ 9-2 Environmental Specifications ............ 6-1 Environmental Specifications 3.3-V Version........................................... 6-1 Environmental Specifications 5-V Version........................................... 6-1 Ethernet Controller Environment....... 7-1 Ethernet Controller Interface ............. 4-3 Functional Description....................... 3-1 General............................................... 3-1 General Hardware Architecture ......... 7-1 Hardware and Software Flow Control3-3 Hardware Interface............................. 4-1 Host Data Format............................... 4-1 Host Interface..................................... 4-1 Host Interface Signals .................5-7, 8-4 iChip & iChip LAN Datasheet Host Serial Connection ...................... 3-2 iChip / iChip LAN Order Number ..... 2-1 iChip CO561AD-S with a Serial Modem Interface ......................................... 4-2 iChip CO561AD-S/P Pin Assignments 51 iChip Designs..................................... 7-1 iChip Functional Block Diagram ....... 1-2 iChip LAN Pin Assignments ............. 5-2 iChip LAN Signals............................. 5-9 iChip Pin Functional Descriptions ..... 5-3 iChip Version Specific Signals .......... 5-8 Index ................................................ 12-1 Interface Timing and Waveforms ...... 6-3 Internet Mode..................................... 3-2 Internet Protocol Compliance .......... 10-1 Introduction........................................ 1-1 Local Bus Connection to Ethernet Controller ....................................... 3-3 Local Bus Read Cycle........................ 6-3 Local Bus Signals .............................. 5-3 Local Bus Write Cycle....................... 6-4 Mechanical Dimensions..................... 6-5 Modem Interface................................ 4-2 Operation ........................................... 3-2 Ordering Information ......................... 2-1 Other Considerations in a Modem Design ............................................ 9-3 Overview............................................ 3-1 Parallel Modem Environment ............ 7-1 PC Board Layout Guidelines ............. 9-1 PCB Design and Layout Considerations ....................................................... 9-1 Pin Assignments ................................ 8-2 Pin Descriptions ................................. 5-1 Pin Functional Descriptions............... 8-3 PLCC68 Package for iChip CO561AD-S Serial Version ................................ 5-1 PLCC68 Package for iChip LAN CO561AD-L Serial Version .......... 5-2 PLD Equations ................................... 7-1 12-1 Index Protocol Compliance........................ 10-1 Reference Design for CO561AD-C Based Modem ................................ 8-7 Reference Design for Embedded iModem Using CO561AD-S.......... 7-2 Reference Design for Embedded LAN Using CO561AD-L........................ 7-4 Selecting a Crystal ............................. 5-6 Serial Connection to Dial-up Modem 3-3 Serial Modem Environment............... 7-1 iChip & iChip LAN Datasheet Serial Version .................................... 5-1 Socket iChip Order Number .............. 2-2 Socket iChip Package Dimensions .... 8-6 Socket iChipTM Carrier Board............ 8-2 Socket Modem Interface Signals ....... 8-3 Technical Specifications .................... 3-1 Terms and Acronyms....................... 11-2 Transparent Mode .............................. 3-2 Volt Version................................6-1, 6-2 12-2