© Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 19
1Publication Order Number:
MC100LVEP111/D
MC100LVEP111
2.5V / 3.3V 1:10 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100LVEP111 is a low skew 1−to−10 differential driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The PECL input signals can be either differential or
single−ended (if the VBB output is used). HSTL inputs can be used when
the LVEP111 is operating under PECL conditions.
The LVEP111 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure tightest skew, both sides of differential outputs identically
terminate into 50 W even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.
The MC100LVEP111, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Single−ended CLK input operation is limited to a VCC ≥
3.0 V in PECL mode, or VEE v −3.0 V in NECL mode when using VBB
(See Figure 11). Full operating range is available when using an external
voltage reference (See Figure 10). Designers can take advantage of the
LVEP111’s performance to distribute low skew clocks across the
backplane or the board.
Features
•85 ps Typical Device−to−Device Skew
•20 ps Typical Output−to−Output Skew
•Jitter Less than 1 ps RMS
•Maximum Frequency > 3 GHz Typical
•VBB Output
•430 ps Typical Propagation Delay
•The 100 Series Contains Temperature Compensation
•PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = −2.375 V to −3.8 V
•Open Input Default State
•LVDS Input Compatible
•Fully Compatible with MC100EP111
•Pb−Free Packages are Available
32
1
LQFP−32
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
MC100
AWLYYWWG
LVEP111
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*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G= Pb−Free Package
QFN32
MN SUFFIX
CASE 488AM
32
1MC100
LVEP111
AWLYYWW
G
1
MC100LVEP111
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2
VCC
CLK_SEL
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
Q9
Q9
Q8
Q8
Q7
Q7
VCC
VCC
Q0
Q0
Q1
Q1
Q2
Q2
VCC
VEE
VBB
VCC
Q6Q6Q5Q5Q4Q4Q3 Q3
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Active Input
CLK0, CLK0
CLK1, CLK1
CLK_SEL
L
H
FUNCTION
ECL/PECL/HSTL CLK Input
ECL/PECL/HSTL CLK Input
ECL/PECL Outputs
ECL/PECL Active Clock Select Input
Reference Voltage Output
Positive Supply
Negative Supply
The exposed pad (EP) on the package
bottom must be attached to a heat−sink-
ing conduit. The exposed pad may only
be electrically connected to VEE.
PIN
CLK0*, CLK0**
CLK1*, CLK1**
Q0:9, Q0:9
CLK_SEL*
VBB
VCC
VEE
EP
Figure 1. LQFP−32 Pinout (Top View)
CLK0
CLK0
CLK1
CLK1
* Pins will default LOW when left open.
** Pins will default to 2/3VCC when left open.
MC100LVEP111
Table 1. PIN DESCRIPTION
Table 2. FUNCTION TABLE
Figure 2. QFN−32 Pinout (Top View)
MC100LVEP111
VCC
CLK_SEL
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
Q9 Q9 Q8 Q8 Q7 Q7 VCC
VCC Q0 Q0 Q1 Q1 Q2 Q2 VCC
VEE
VBB
VCC
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
CLK0
CLK0
CLK1
CLK1
Exposed Pad (EP)
MC100LVEP111
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Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 kW
Internal Input Pullup Resistor 37.5 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity (Note 1) Pb Pkgs Pb−Free Pkgs
LQFP
QFN
Level 2
Level 1
Level 2
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 602 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
VBB
0
1
CLK0
CLK0
CLK1
CLK1
CLK_SEL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Figure 3. Logic Diagram
VEE
VCC
MC100LVEP111
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Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 6 V
VEE NECL Mode Power Supply VCC = 0 V −6 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI ≤ VCC
VI ≥ VEE
6
−6
V
V
Iout Output Current Continuous
Surge
50
100
mA
mA
IBB VBB Sink/Source ± 0.5 mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W
Tsol Wave Solder Pb
Pb−Free (QFN−32 Only)
< 3 sec @ 248°C
< 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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Table 5. PECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 2)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 60 90 120 60 90 120 60 90 120 mA
VOH Output HIGH Voltage (Note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
VOL Output LOW Voltage (Note 3) 555 730 900 555 730 900 555 730 900 mV
VIH Input HIGH Voltage (Single−Ended)
(Note 4)
1335 1620 1335 1620 1275 1620 mV
VIL Input LOW Voltage (Single−Ended)
(Note 4)
555 875 555 875 555 875 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 5)
1.2 2.5 1.2 2.5 1.2 2.5 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current CLK
CLK
0.5
−150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to −1.3 V.
3. All loading with 50 W to VEE.
4. Do not use VBB at VCC < 3.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 6. PECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 6)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 60 90 120 60 90 120 60 90 120 mA
VOH Output HIGH Voltage (Note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
VOL Output LOW Voltage (Note 7) 1355 1530 1700 1355 1530 1700 1355 1530 1700 mV
VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV
VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV
VBB Output Reference Voltage (Note 8) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
1.2 3.3 1.2 3.3 1.2 3.3 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current CLK
CLK
0.5
−150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to −0.5 V.
7. All loading with 50 W to VCC − 2.0 V.
8. Single ended input operation is limited VCC ≥ 3.0 V in PECL mode.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
MC100LVEP111
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Table 7. NECL DC CHARACTERISTICS VCC = 0 V, VEE = −2.375 V to −3.8 V (Note 10)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 60 90 120 60 90 120 60 90 120 mA
VOH Output HIGH Voltage (Note 11) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV
VOL Output LOW Voltage (Note 11) −1945 −1770 −1600 −1945 −1770 −1600 −1945 −1770 −1600 mV
VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV
VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV
VBB Output Reference Voltage (Note 12) −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
VEE + 1.2 0.0 VEE + 1.2 0.0 VEE + 1.2 0.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current CLK
CLK
0.5
−150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with VCC.
11. All loading with 50 W to VCC − 2.0 V.
12.Single ended input operation is limited VEE ≤ −3.0V in NECL mode.
13.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 8. HSTL DC CHARACTERISTICS VCC = 2.375 to 3.8 V, VEE = 0 V
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
VIH Input HIGH Voltage 1200 1200 1200 mV
VIL Input LOW Voltage 400 400 400 mV
Vx Input Crossover Voltage 680 900 680 900 680 900 mV
ICC Power Supply Current 70 100 120 70 100 120 70 100 120 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
MC100LVEP111
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Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = −2.375 to −3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 14)
Symbol
−40°C 25°C 85°C
Unit
Characteristic Min Typ Max Min Typ Max Min Typ Max
fmaxPECL/HSTL Maximum Frequency (Figure 4) 3 3 3 GHz
tPLH
tPHL
Propagation Delay
(Differential Configuration)
325 400 475 350 430 500 375 510 590 ps
tskew Within−Device Skew (Note 15)
Within−Device Skew @ 2.5 V (Note 15)
Device−to−Device Skew (Note 16)
20
20
85
25
25
150
20
20
85
25
25
150
25
20
85
35
25
150
ps
tJITTER CLOCK Random Jitter (RMS)
@ v0.5 GHz
@ v1.0 GHz
@ v1.5 GHz
@ v2.0 GHz
@ v2.5 GHz
@ v3.0 GHz
0.209
0.200
0.197
0.220
0.232
0.348
0.5
0.5
0.4
0.5
0.4
0.6
0.204
0.214
0.213
0.224
0.290
0.545
0.5
0.6
0.5
0.5
0.5
0.8
0.221
0.229
0.243
0.292
0.522
0.911
0.5
0.5
0.4
0.6
0.8
1.3
ps
tjit(f)Additive RMS Integrated Phase Jitter
(fc = 156.25 MHz, 12 kHz − 20 MHz)
159 fs
VPP Input Swing (Differential Interconnect
Configuration) Measured Single−Ended
150 800 1200 150 800 1200 150 800 1200 mV
tr/tfOutput Rise/Fall Time (20%−80%) 105 200 255 125 200 275 150 230 320 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured with 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
15.Skew is measured between outputs under identical transitions and conditions on any one device.
16.Device−to−Device skew for identical transitions at identical VCC levels.
0
100
200
300
400
500
600
700
800
0 1000 2000 3000 4000 5000 6000
Figure 4. Fmax Typical
FREQUENCY (MHz)
VOUTpp (mV)
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Figure 5. For a 155.52 MHz Carrier, the MC100LVEP111 Phase Noise (dBc/Hz) verses SSB Offset Frequency (Hz)
Integrated Jitter from 12 kHz to 20 MHz (Upper Heavy Line) is 399.1 fs RMS. The VECTRON VCC Oscillator Source
Generator Phase Noise (Lower Light Line) Phase Noise is 361.2 fs RMS. The Additive Phase Jitter is
((399.1^2)−(361.2^2))^0.5, or 169 fs
50 W
VT = VCC − 2.0 V
LVPECL
Driver
Z0 = 50 W
Z0 = 50 W
VCC VCC
VEE VEE
50 W
VTT
CLKx
CLK
Figure 6. LVPECL in Interface
50 W*
LVDS
Driver
Z0 = 50 W
Z0 = 50 W
VCC VCC
GND GND
50 W*
Figure 7. LVDS in Interface
MC100LVEP111 MC100LVEP111
CLKx
CLK
100 W
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9
50 W
HSTL
Driver
Z0 = 50 W
Z0 = 50 W
VCC VCC
VEE VEE
50 W
VDDQ
CLKx
CLK
Figure 8. HSTL in Interface Figure 9. Standard 50 W Load CML in Interface
MC100LVEP111
50 W
CML
Driver
Z0 = 50 W
Z0 = 50 W
VCC VCC
VEE VEE
50 W
VCC
CLKx
CLK
MC100LVEP111
Figure 10. Single−Ended Interface LVCMOS/LVTTL in Interface Using an External Voltage Reference
1k
LVCMOS
LVTTL
Single−Ended
Driver
Z0 = 50 W
VCC VCC
VEE VEE
VCC
CLKx
CLK
MC100LVEP111
1k
Figure 11. Single−Ended Interface LVCMOS/LVTTL in Interface Using VBB
LVCMOS
LVTTL
Single−Ended
Driver
Z0 = 50 W
VCC VCC
VEE VEE
CLKx
CLK
MC100LVEP111
VEE VBB
MC100LVEP111
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Figure 12. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
Figure 13. Tape and Reel Pin 1 Quadrant Orientation
Quadrant
A
Quadrant
B
Quadrant
C
Quadrant
D
User Direction
of Unreeling
Round Sprocket Holes
Designations
Quadrant A = Upper Left
Quadrant B = Upper Right
Quadrant C = Lower Left
Quadrant D = Lower Right
ORDERING INFORMATION
Device Package Shipping†
MC100LVEP111FA LQFP−32 250 Units / Tray
MC100LVEP111FAG LQFP−32
(Pb−Free)
250 Units / Tray
MC100LVEP111FAR2 LQFP−32 2000 / Tape & Reel
(Pin 1 Orientation in Quadrant B, Figure 13)
MC100LVEP111FARG LQFP−32
(Pb−Free)
2000 / Tape & Reel
(Pin 1 Orientation in Quadrant B, Figure 13)
M100LVEP111FATW LQFP−32 2000 / Tape & Reel
(Pin 1 Orientation in Quadrant A, Figure 13)
M100LVEP111FATWG LQFP−32
(Pb−Free)
2000 / Tape & Reel
(Pin 1 Orientation in Quadrant A, Figure 13)
MC100LVEP111MNG QFN−32
(Pb−Free)
74 Units / Rail
MC100LVEP111MNRG QFN−32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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Resource Reference of Application Notes
AN1405/D −ECL Clock Distribution Techniques
AN1406/D −Designing with PECL (ECL at +5.0 V)
AN1503/D −ECLinPSt I/O SPiCE Modeling Kit
AN1504/D −Metastability and the ECLinPS Family
AN1568/D −Interfacing Between LVDS and ECL
AN1672/D −The ECL Translator Guide
AND8001/D −Odd Number Counters Design
AND8002/D −Marking and Date Codes
AND8020/D −Termination of ECL Logic Devices
AND8066/D −Interfacing with ECLinPS
AND8090/D −AC Characteristics of ECL Devices
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PACKAGE DIMENSIONS
ÉÉ
ÉÉ
ÉÉ
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y BASE
N
J
DF
METAL
SECTION AE−AE
G
SEATING
PLANE
R
Q_
WK
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DETAIL AD
A1
B1 V1
4X
S
4X
9
−T−
−Z−
−U−
T-U0.20 (0.008) ZAC
T-U0.20 (0.008) ZAB
0.10 (0.004) AC
−AC−
−AB−
M_
8X
−T−, −U−, −Z−
T-U
M
0.20 (0.008) ZAC
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
MIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B7.000 BSC 0.276 BSC
C1.400 1.600 0.055 0.063
D0.300 0.450 0.012 0.018
E1.350 1.450 0.053 0.057
F0.300 0.400 0.012 0.016
G0.800 BSC 0.031 BSC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.450 0.750 0.018 0.030
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.400 BSC 0.016 BSC
Q1 5 1 5
R0.150 0.250 0.006 0.010
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
__
___ _
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
32 LEAD LQFP
CASE 873A−02
ISSUE C
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PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
SEATING
32 X
K
0.15 C
(A3)
A
A1
D2
b
1
916 17
32
2 X
2 X
E2
32 X
8
24
32 X
L
32 X
BOTTOM VIEW
EXPOSED PAD
TOP VIEW
SIDE VIEW
D
A
B
E
0.15 C
ÉÉ
ÉÉ
PIN ONE
LOCATION
0.10 C
0.08 C
C
25
e
A0.10 B
C
0.05 C
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
DIM MIN NOM MAX
MILLIMETERS
A0.800 0.900 1.000
A1 0.000 0.025 0.050
A3 0.200 REF
b0.180 0.250 0.300
D5.00 BSC
D2 2.950 3.100 3.250
E5.00 BSC
E2
e0.500 BSC
K0.200 −−− −−−
L0.300 0.400 0.500
2.950 3.100 3.250
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DIMENSIONS: MILLIMETERS
0.50 PITCH
3.20
0.28
3.20
32 X
28 X
0.63
32 X
5.30
5.30
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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