IRF840AS, SiHF840AS, IRF840AL, SiHF840AL Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) * Halogen-free According to IEC 61249-2-21 Definition * Low Gate Charge Qg Results in Simple Drive Requirement * Improved Gate, Avalanche and Dynamic dV/dt Ruggedness * Fully Characterized Capacitance and Avalanche Voltage and Current * Effective Coss Specified * Compliant to RoHS Directive 2002/95/EC 500 RDS(on) () VGS = 10 V 0.85 Qg (Max.) (nC) 38 Qgs (nC) 9.0 Qgd (nC) 18 Configuration Single D I2PAK D2PAK (TO-263) (TO-262) APPLICATIONS G G D S * Switch Mode Power Supply (SMPS) * Uninterruptible Power Supply * High Speed Power Switching G D S TYPICAL SMPS TOPOLOGIES * Two Transistor Forward * Half Bridge * Full Bridge S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262) SiHF840AS-GE3 SiHF840ASTRL-GE3a SiHF840ASTRR-GE3a SiHF840AL-GE3a IRF840ASPbF IRF840ASTRLPbFa IRF840ASTRRPbFa IRF840ALPbF SiHF840AS-E3 SiHF840ASTL-E3a SiHF840ASTR-E3a SiHF840AL-E3 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 500 Gate-Source Voltage VGS 30 Continuous Drain Current VGS at 10 V TC = 25 C TC = 100 C Pulsed Drain Currenta ID UNIT V 8.0 5.1 A IDM 32 1.0 W/C Single Pulse Avalanche Energyb EAS 510 mJ Repetitive Avalanche Currenta IAR 8.0 A 13 mJ Linear Derating Factor Repetitive Avalanche Energya Maximum Power Dissipation EAR TC = 25 C TA = 25 C Peak Diode Recovery dV/dtc, e Operating Junction and Storage Temperature Range Soldering Temperature for 10 s PD 125 3.1 dV/dt 5.0 TJ, Tstg - 55 to + 150 300d W V/ns C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 C, L = 16 mH, Rg = 25 , IAS = 8.0 A (see fig. 12). c. ISD 8.0 A, dI/dt 100 A/s, VDD VDS, TJ 150 C. d. 1.6 mm from case. e. Uses IRF840A, SiH840A data and test conditions. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91066 S11-1050-Rev. D, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient (PCB Mount)a PARAMETER RthJA - - 40 Maximum Junction-to-Case (Drain) RthJC - - 1.0 UNIT C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0, ID = 250 A 500 - - V VDS/TJ Reference to 25 C, ID = 1 mAd - 0.58 - V/C VGS(th) VDS = VGS, ID = 250 A 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = 30 V - - 100 nA Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 C - - 250 - - 0.85 3.7 - - S - 1018 - - 155 - 8.0 - Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 4.8 Ab VGS = 10 V VDS = 50 V, ID = 4.8 A A Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Output Capacitance Coss Output Capacitance Effective Output Capacitance Total Gate Charge Coss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - VDS = 1.0 V, f = 1.0 MHz VGS = 0 V Coss eff. VDS = 400 V, f = 1.0 MHz 42 VDS = 0 V to 480 Vc, d 56 Qg - - 38 Gate-Source Charge Qgs - - 9.0 Gate-Drain Charge Qgd - - 18 Turn-On Delay Time td(on) - 11 - tr - 23 - - 26 - - 19 - - - 8.0 - - 32 Rise Time Turn-Off Delay Time Fall Time td(off) VGS = 10 V ID = 8.0 A, VDS = 400 V, see fig. 6 and 13b, d VDD = 250 V, ID = 8.0 A, Rg = 9.1 , RD = 31 , see fig. 10b, d tf pF 1490 nC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 C, IS = 8.0 A, VGS = 0 S Vb TJ = 25 C, IF = 8.0 A, dI/dt = 100 A/sb - - 2.0 V - 422 633 ns - 2.0 3.0 C Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 s; duty cycle 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 %to 80 % VDS. d. Uses IRF840A, SiHF840A data and test conditions www.vishay.com 2 Document Number: 91066 S11-1050-Rev. D, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL Vishay Siliconix TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) 102 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top 10 1 4.5 V 20 s Pulse Width TJ = 25 C 0.1 0.1 1 10 TJ = 150 C TJ = 25 C 1 20 s Pulse Width VDS = 50 V 0.1 102 10 VDS, Drain-to-Source Voltage (V) 91066_01 ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 102 4.0 4.5 V 1 20 s Pulse Width TJ = 150 C 0.1 0.1 91066_02 1 10 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics Document Number: 91066 S11-1050-Rev. D, 30-May-11 7.0 8.0 9.0 Fig. 3 - Typical Transfer Characteristics 102 RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 10 VGS Top 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 6.0 VGS, Gate-to-Source Voltage (V) 91066_03 Fig. 1 - Typical Output Characteristics 102 5.0 91066_04 3.0 ID = 8.0 A VGS = 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (C) Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL Vishay Siliconix VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 104 Ciss 103 Coss 102 10 Crss 102 ISD, Reverse Drain Current (A) C, Capacitance (pF) 105 10 TJ = 150 C TJ = 25 C 1 1 102 10 103 VDS, Drain-to-Source Voltage (V) 91066_05 0.2 20 0.5 0.8 102 Operation in this area limited by RDS(on) ID, Drain Current (A) VDS = 400 V VDS = 250 V VDS = 100 V 12 8 10 s 10 100 s 1 ms 1 10 ms 4 For test circuit see figure 13 0 0 91066_06 10 20 30 Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 TC = 25 C TJ = 150 C Single Pulse 0.1 40 QG, Total Gate Charge (nC) 1.4 Fig. 7 - Typical Source-Drain Diode Forward Voltage ID = 8.0 A 16 1.1 VSD, Source-to-Drain Voltage (V) 91066_07 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage VGS, Gate-to-Source Voltage (V) VGS = 0 V 0.1 1 10 91066_08 102 103 104 VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area Document Number: 91066 S11-1050-Rev. D, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL Vishay Siliconix RD VDS 8.0 VGS D.U.T. Rg + - VDD ID, Drain Current (A) 6.0 10 V Pulse width 1 s Duty factor 0.1 % 4.0 Fig. 10a - Switching Time Test Circuit 2.0 VDS 90 % 0.0 25 50 75 100 125 150 TC, Case Temperature (C) 91066_09 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.50 PDM 0.20 0.1 0.10 t1 0.05 t2 0.02 0.01 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 10-2 10-5 10-4 10-3 10-2 0.1 1 t1, Rectangular Pulse Duration (s) 91066_11 Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS 15 V tp L VDS Rg D.U.T. IAS 20 V tp Driver + A - VDD IAS 0.01 Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91066 S11-1050-Rev. D, 30-May-11 Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL EAS, Single Pulse Avalanche Energy (mJ) Vishay Siliconix 1200 ID 3.6 A 5.1 A Bottom 8.0 A Top 1000 QG 10 V 800 QGS 600 QGD VG 400 Charge 200 0 25 50 75 125 100 150 Fig. 13a - Basic Gate Charge Waveform Starting TJ, Junction Temperature (C) 91066_12c Current regulator Same type as D.U.T. Fig. 12c - Maximum Avalanche Energy vs. Drain Current 50 k 12 V 0.2 F 0.3 F + D.U.T. - VDS 610 VDSav, Avalanche Voltage (V) VGS 600 3 mA 590 IG ID Current sampling resistors 580 Fig. 13b - Gate Charge Test Circuit 570 560 550 540 0.0 91066_12d 1.0 2.0 3.0 4.0 5.0 6.0 IAV, Avalanche Current (A) Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current www.vishay.com 6 Document Number: 91066 S11-1050-Rev. D, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer + - - Rg * * * * + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91066. Document Number: 91066 S11-1050-Rev. D, 30-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0 to 8 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail "A" Rotated 90 CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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