CY62146E MoBL
4-Mbit (256K x 16) St atic RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-07970 Rev . *H Revised June 29, 201 1
Features
■Very high speed: 45 ns
■Wide voltage range: 4.5 V to 5.5 V
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 7 A
■Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automati c power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 44-pin thin small outline package (TSOP)
II package
Functional Description
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH) or during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then da ta
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Table for a complete description
of read and write modes.
256K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BHE
A16
A0
A1
A9
A10
BLE
A17
Logic Block Diagram
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 2 of 14
Contents
Features .............................................................................1
Functional Description ........... ... .............. .. ... ....................1
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ............ ... .............. ... .............. ... ..............4
Electrical Characteristics .................................................4
Capacitance ......................................................................4
Thermal Resistance ..........................................................4
Data Retention Characteristics .......................................5
Switching Characteristics ............................................. ...6
Switching Waveforms ....................... ... ............................7
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagram ............................................................11
Acronyms ........................................................................ 12
Document Conventions .......... ... .............. ... ... ................12
Units of Measure ................... ... .............. ... .. ..............12
Document History Page .................................................13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support ......... ..............14
Products ....................................................................14
PSoC Solutions .................. ... ............................ ... ... ..14
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 3 of 14
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View) [1]
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2
(A)
f = 1 MHz f = fmax
Min Typ[2] Max Typ [2] Max Typ [2] Max Typ [2] Max
CY62146ELL Ind’l/Auto-A 4.5 5.0 5.5 45 2 2.5 15 20 1 7
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
A
5
18
17
20
19 27
28
25
26
22
21 23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
Notes
1. NC pins are not connected on the die.
2. Typical values are included for refere nce only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 4 of 14
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied. .......................................... –55 °C to +125 °C
Supply voltage to ground potential .................–0.5 V to 6.0 V
DC voltage applied to outputs
in high Z state [3, 4] ...........................................–0.5 V to 6.0 V
DC input voltage [3, 4] .......................................–0.5 V to 6.0 V
Output current into outputs (LOW) ..............................20 mA
Static discharge voltage................. ................. ..........>2001 V
(MIL-STD-883, Method 3015)
Latch-up current ......................................................>200 mA
Operating Range
Device Range Ambient
Temperature VCC[5]
CY62146ELL Industrial/
Auto-A –40 °C to +85 °C 4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns (Ind’l/Auto-A) UnitMin Typ[6] Max
VOH Output high voltage IOH = –1.0 mA 2.4 – – V
VOL Output low voltage IOL = 2.1 mA – – 0.4 V
VIH Input high voltage 4.5 < VCC < 5.5 2.2 – VCC + 0.5 V
VIL Input low voltage 4.5 < VCC < 5.5 –0.5 – 0.8 V
IIX Input leakage current GND < VI < VCC –1 – +1 A
IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 A
ICC VCC operating supply
current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA, CMOS levels –15 20mA
f = 1 MHz – 2 2.5
ISB2 [7] Automatic CE power
down curr ent — CM OS
inputs
CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max) –1 7A
Capacitance
Parameter[8] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz,
VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resist ance
Parameter[8] Description Test Conditions TSOP II Unit
JA Thermal resistance
(Junction to ambient) Still Air, soldered on a 3 × 4.5 inch, two layer
printed circuit board 77 C/W
JC Thermal resistance
(Junction to case) 13 C/W
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns for I < 30 mA.
4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. Full Device AC operation assumes a minimum of 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typ i cal values are measured at VCC = VCC(typ), TA = 25 °C.
7. Chip enable (CE) and byte enables (BHE and BLE) ne ed to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs are left floating.
8. Tested initially after any design or process changes that may affect these parameters.
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 5 of 14
Figure 2. AC Test Loads and Waveforms
Parameters 5.0 V Unit
R1 1800
R2 990
RTH 639
VTH 1.77 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ[9] Max Unit
VDR VCC for data retention 2 – – V
ICCDR [10] Data retention current VCC = 2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V –17A
tCDR [11] Chip deselect to data
retention time 0––ns
tR [12] Operation recovery time 45 – – ns
Figure 3. Data Retention Waveform
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
TH
VCC(min)
VCC(min)
tCDR
VDR >2.0 V
DATA RETENTION MODE
tR
VCC
CE
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measu red at VCC = VCC(typ), TA = 25 °C.
10.Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs are left floating.
11.Tested initially and after any design or process changes that may affect these parameters.
12.Full device operation requires linear V CC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 6 of 14
Switching Characteristics
Over the Operating Range
Parameter[13, 14] Description 45 ns (Ind’l/Auto-A) Unit
Min Max
Read Cycle
tRC Read cycle time 45 – ns
tAA Address to data valid – 45 ns
tOHA Data hold from address change 10 – ns
tACE CE LOW to data valid –45 ns
tDOE OE LOW to data valid –22 ns
tLZOE OE LOW to LOW Z[15] 5–ns
tHZOE OE HIGH to High Z[15, 16] –18 ns
tLZCE CE LOW to Low Z[15] 10 –ns
tHZCE CE HIGH to High Z[15, 16] –18 ns
tPU CE LOW to power-up 0 –ns
tPD CE HIGH to power-down –45 ns
tDBE BLE/BHE LOW to data valid –22 ns
tLZBE BLE/BHE LOW to Low Z[15] 5–ns
tHZBE BLE/BHE HIGH to HIGH Z[15, 16] –18 ns
Write Cycle [17]
tWC W rite cycle time 45 – ns
tSCE CE LOW to write end 35 –ns
tAW Address setup to write end 35 – ns
tHA Address hold from write end 0 –ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 35 –ns
tBW BLE/BHE LOW to write end 35 –ns
tSD Data setup to write end 25 – ns
tHD Data hold from write end 0 – ns
tHZWE WE LOW to High Z[15, 16] –18 ns
tLZWE WE HIGH to Low Z[15] 10 –ns
Notes
13.Test conditions for all parameters other than tri-state parameters assume signal transit ion time of 3 ns (1 V/ns) or less, timing reference levels of 1.5 V, input pulse
levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 5.
14.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output s enter a high-impedance stat e.
17.The internal write time of the memory is d efined by the overl ap of WE , CE = VIL, BHE, BLE or both = VIL. All si gnals must be active to init iate a write and an y of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 7 of 14
Switching Waveforms
Figure 4. Read Cycle No.1: Address Trans ition Con t rolled[18, 19]
Figure 5. Read Cycle No. 2: OE Controlled [19, 20]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
18.The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
19.WE is HIGH for read cycle.
20.Address valid before or similar to CE, BHE, BLE transition LOW.
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 8 of 14
Figure 6. Write Cycle No 1: WE Controlled [21, 22, 23]
Figure 7. Write Cycle 2: CE Controlled [21, 22, 23]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 24
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 24
Notes
21.WE is HIGH for read cycle.
22.Data I/O is high im pedance if OE = VIH.
23.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
24.During this period, the I/O s are in output state. Do not apply input signals.
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 9 of 14
Figure 8. Write Cycle 3: WE controlled, OE LOW [25]
Figure 9. Write Cycle 4: BHE/BLE Controll ed, OE LOW [25]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 26
CE
ADDRESS
WE
DATA I/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 26
DATA I/O
ADDRESS
CE
WE
BHE
/BLE
Notes
25.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26.During this period, the I /O s are in output state. Do not apply input signals.
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 10 of 14
Truth Table
CE[27] WE OE BHE BLE Inputs/Outputs Mode Power
HXXX
[27] X[27] High Z Deselect/power down Standby (ISB)
L X X H H High Z Output disabled Active (ICC)
L H L L L Data out (I/O0–I/O15) Read Active (ICC)
L H L H L Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z Read Active (ICC)
L H L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z Read Active (ICC)
L H H L L High Z Output disabled Active (ICC)
L H H H L High Z Output disabled Active (ICC)
L H H L H High Z Output disabled Active (ICC)
L L X L L Data in (I/O0–I/O15) Write Active (ICC)
L L X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data in (I/O 8–I/O15);
I/O0–I/O7 in High Z Write Active (ICC)
Note
27.Chip enable (CE) and byte enables (BHE and BLE) must be at CMOS levels ( not float ing ) to me et th e I SB2 / ICCDR sp ec. Interme diate voltag e leve ls on th ese pi ns is
not permitted.
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 11 of 14
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62146ELL-45ZSXI 51-85087 44-pin thin small outline package II (Pb-free) Industrial
CY62146ELL-45ZSXA 51-85087 44-pin thin small outline package II (Pb-free) Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Package Diagram
Figure 10. 44-Pin TSOP II, 51-85087
Temperature Range: I = Industrial, A = Automotive-A
Package type = 44-pin TSOP II (Pb-free)
Speed Grade
Separator
Low Power
E = Process Te ch no l og y 90 nm
Buswidth = ×16
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY 45 ZSX
621 46ELL -X
MAX
MIN.
DIMENSION IN MM (INCH)
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
EJECTOR MARK
Z
A
Z
Z
Z
Z
X
A
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
TOP VIEW BOTTOM VIEW
PLANE
SEATING
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
BASE PLANE
0.10 (.004)
11.938 (0.470)
PIN 1 I.D.
44
1
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
22
23
51-85087-*C
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 12 of 14
Acronyms
Document Conventions
Units of Measure
Acronym Description
BHE byte high enable
BLE byte low enable
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
VFBGA very fine ball gird array
WE write enable
Symbol Unit of Measure
°C degrees Celsius
Amicroamperes
mA milliamperes
MHz megahertz
ns nanoseconds
pF picofarads
Vvolts
ohms
Wwatts
CY62146E MoBL
Document Number: 001-07970 Rev. *H Page 13 of 14
Document History Page
Document Title: CY62146E MoBL 4-Mbit (256K x 16) Static RAM
Document Number: 001-07970
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 463213 See ECN NXR New Data Sheet
*A 684343 See ECN VKN Added Preliminary Automotive-A Information
Updated Ordering Information Table
*B 925501 See ECN VKN Added footnote #8 rel a te d to ISB2 and ICCDR
Added footnote #13 related AC timing parameters
*C 1045260 See ECN VKN Converted Automotive-A specs from preliminary to final
*D 2073548 See ECN VKN/AESA Corrected typo in the Data Retention Waveform and removed its irrelevant
footnote
*E 2943752 06/03/2010 VKN Added Contents
Added footnote related to chip enable in Truth Table
Updated Package Diagram
Added Sales, Solutions, and Legal Information
*F 3109050 12/13/2010 PRAS Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
*G 3149059 01/20/2011 RAME Updated as per latest template
Corrected Errors in Ordering Code Definitions
Added Acronyms and Units of Measure table
*H 3296704 06/29/11 RAME Removed reference to AN1064 SRAM system guidelines
Document Number: 001-07970 Rev. *H Revised June 29, 2011 Page 14 of 14
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
CY62146E MoBL
© Cypress Semico nducto r Co rpor ation , 20 08-2 011. The information cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply an y license under patent or other rights. Cypres s pro d ucts ar e not war ran t ed no r int e nded to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at ions, unless pursuan t to an express written agreement wit h Cypr ess. Fu rth er mor e, Cypre ss does not auth or iz e it s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee pr oduct to be used only in conjunction with a Cyp ress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOS E. Cypress reserves the right to make changes without further notice to the materials described h erein. Cypres s does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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