HIGH OUTPUT CURRENT
LOW POWER, LOW NOISE
OPERATIONAL AMPLIFIERS
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D SUFFIX
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1
1
8
8
14
1
14 1
PIN CONNECTIONS
PIN CONNECTIONS
DUAL
QUAD
(Top View)
VEE
Inputs 1 Inputs 2
Output 2
Output 1 VCC
–
–
+
+
1
2
3
4
8
7
6
5
(Top View)
1
2
3
4
5
6
78
9
10
11
12
13
14
4
23
1
Inputs 1
Output 1
VCC
Inputs 2
Output 2
Output 4
Inputs 4
VEE
Inputs 3
Output 3
++
––
++
––
1
MOTOROLA ANALOG IC DEVICE DATA
The MC33178/9 series is a family of high quality monolithic amplifiers
employing Bipolar technology with innovative high performance concepts for
quality audio and data signal processing applications. This device family
incorporates the use of high frequency PNP input transistors to produce
amplifiers exhibiting low input offset voltage, noise and distortion. In addition,
the amplifier provides high output current drive capability while consuming
only 420 µA of drain current per amplifier. The NPN output stage used,
exhibits no deadband crossover distortion, large output voltage swing,
excellent phase and gain margins, low open–loop high frequency output
impedance, symmetrical source and sink AC frequency performance.
The MC33178/9 family offers both dual and quad amplifier versions,
tested over the vehicular temperature range, and are available in DIP and
SOIC packages.
•600 Ω Output Drive Capability
•Large Output Voltage Swing
•Low Offset Voltage: 0.15 mV (Mean)
•Low T.C. of Input Offset Voltage: 2.0 µV/°C
•Low Total Harmonic Distortion: 0.0024% (@ 1.0 kHz w/600 Ω Load)
•High Gain Bandwidth: 5.0 MHz
•High Slew Rate: 2.0 V/µs
•Dual Supply Operation: ±2.0 V to ±18 V
•ESD Clamps on the Inputs Increase Ruggedness
without Affecting Device Performance
Representative Schematic Diagram (Each Amplifier)
VEE
VCC
Iref
Vin +
Vin –
Iref
CC
CMVO
ORDERING INFORMATION
Op Amp
Function Fully
Compensated Operating
Temperature Range Package
Dual MC33178D
MC33178P
TA=
–
40
°
to +85
°
C
SO–8
Plastic DIP
Quad MC33179D
MC33179P
T
A = –
40°
to
+
85°C
SO–14
Plastic DIP
Motorola, Inc. 1996 Rev 0
MC33178 MC33179
2MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to VEE) VS+36 V
Input Differential Voltage Range VIDR (Note 1) V
Input Voltage Range VIR (Note 1) V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Maximum Junction Temperature TJ+150 °C
Storage Temperature Range Tstg –60 to +150 °C
Maximum Power Dissipation PD(Note 2) mW
NOTES: 1.Either or both input voltages should not exceed VCC or VEE.
2.Power dissipation must be considered to ensure maximum junction temperature (TJ) is not
exceeded. (See power dissipation performance characteristic, Figure 1.)
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Input Offset Voltage (RS = 50 Ω, VCM = 0 V, VO = 0 V)
(VCC = +2.5 V, VEE = –2.5 V to VCC = +15 V, VEE = –15 V)
TA = +25°C
TA = –40° to +85°C
2 |VIO|
—
—0.15
—3.0
4.0
mV
Average Temperature Coefficient of Input Offset Voltage
(RS = 50 Ω, VCM = 0 V, VO = 0 V)
TA = –40° to +85°C
2∆VIO/∆T
—2.0 —
µV/°C
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = –40° to +85°C
3, 4 IIB —
—100
—500
600
nA
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = –40° to +85°C
|IIO|—
—5.0
—50
60
nA
Common Mode Input Voltage Range
(∆VIO = 5.0 mV, VO = 0 V) 5 VICR –13
—–14
+14 —
+13 V
Large Signal Voltage Gain (VO = –10 V to +10 V, RL = 600 Ω)
TA = +25°C
TA = –40° to +85°C
6, 7 AVOL 50 k
25 k 200 k
——
—
V/V
Output Voltage Swing (VID = ±1.0 V)
(VCC = +15 V, VEE = –15 V)
RL = 300 Ω
RL = 300 Ω
RL = 600 Ω
RL = 600 Ω
RL = 2.0 kΩ
RL = 2.0 kΩ
(VCC = +2.5 V, VEE = –2.5 V)
RL = 600 Ω
RL = 600 Ω
8, 9, 10
VO+
VO–
VO+
VO–
VO+
VO–
VO+
VO–
—
—
+12
—
+13
—
1.1
—
+12
–12
+13.6
–13
+14
–13.8
1.6
–1.6
—
—
—
–12
—
–13
—
–1.1
V
Common Mode Rejection (Vin = ±13 V) 11 CMR 80 110 — dB
Power Supply Rejection
VCC/VEE = +15 V/ –15 V, +5.0 V/ –15 V, +15 V/ –5.0 V 12 PSR 80 110 — dB
Output Short Circuit Current (VID = ±1.0 V, Output to Ground)
Source (VCC = 2.5 V to 15 V)
Sink (VEE = –2.5 V to –15 V)
13, 14 ISC +50
–50 +80
–100 —
—
mA
Power Supply Current (VO = 0 V)
(VCC = 2.5 V, VEE = –2.5 V to VCC = +15 V, VEE = –15 V)
MC33178 (Dual)
TA = +25°C
TA = –40° to +85°C
MC33179 (Quad)
TA = +25°C
TA = –40° to +85°C
15 ID
—
—
—
—
—
—
1.7
—
1.4
1.6
2.4
2.6
mA
MC33178 MC33179
3
MOTOROLA ANALOG IC DEVICE DATA
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Slew Rate
(Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 100 pF, AV = +1.0 V) 16, 31 SR 1.2 2.0 — V/µs
Gain Bandwidth Product (f = 100 kHz) 17 GBW 2.5 5.0 — MHz
AC Voltage Gain (RL = 600 Ω, VO = 0 V, f = 20 kHz) 18, 19 AVO —50 — dB
Unity Gain Frequency (Open–Loop) (RL = 600 Ω, CL = 0 pF) fU—3.0 — MHz
Gain Margin (RL = 600 Ω, CL = 0 pF) 20, 22, 23 Am— 15 — dB
Phase Margin (RL = 600 Ω, CL = 0 pF) 21, 22, 23 φm— 60 — Degree
s
Channel Separation (f = 100 Hz to 20 kHz) 24 CS — –120 — dB
Power Bandwidth (VO = 20 Vpp, RL = 600 Ω, THD ≤ 1.0%) BWp— 32 — kHz
Distortion (RL = 600 Ω,, VO = 2.0 Vpp, AV = +1.0 V)
(f = 1.0 kHz)
(f = 10 kHz)
(f = 20 kHz)
25 THD —
—
—
0.0024
0.014
0.024
—
—
—
%
Open Loop Output Impedance
(VO = 0 V, f = 3.0 MHz, AV = 10 V) 26 |ZO| — 150 — Ω
Differential Input Resistance (VCM = 0 V) Rin —200 — kΩ
Differential Input Capacitance (VCM = 0 V) Cin —10 — pF
Equivalent Input Noise Voltage (RS = 100 Ω,)
f = 10 Hz
f = 1.0 kHz
27 en—
—8.0
7.5 —
—
nV/ Hz√
Equivalent Input Noise Current
f = 10 Hz
f = 1.0 kHz
28 in—
—0.33
0.15 —
—
pA/ Hz√
Figure 1. Maximum Power Dissipation
versus Temperature Figure 2. Input Offset Voltage versus
Temperature for 3 Typical Units
P (MAX), MAXIMUM POWER DISSIPATION (mW)
D
TA, AMBIENT TEMPERATURE (
°
C)
–60 –40 –20 0 20 40 60 80 100 120 180160140
MC33178P/9P
MC33179D
MC33178D
V , INPUT OFFSET VOLT AGE (mV)
IO
TA, AMBIENT TEMPERATURE (
°
C)
–55 –25 0 25 50 75 100 125
Unit 1
Unit 2
Unit 3
VCC = +15 V
VEE = –15 V
RS = 10
Ω
VCM = 0 V
2400
2000
1600
1200
800
400
0
4.0
3.0
2.0
1.0
0
–1.0
–2.0
–3.0
–4.0
MC33178 MC33179
4MOTOROLA ANALOG IC DEVICE DATA
VO, OUTPUT VOLTAGE (V )
pp
Figure 3. Input Bias Current
versus Common Mode Voltage Figure 4. Input Bias Current
versus Temperature
Figure 5. Input Common Mode Voltage
Range versus Temperature Figure 6. Open Loop Voltage Gain
versus Temperature
Figure 7. Voltage Gain and Phase
versus Frequency Figure 8. Output Voltage Swing
versus Supply Voltage
I , INPUT BIAS CURRENT (nA)
IB
VCM, COMMON MODE VOLTAGE (V)
–15 –10 –5.0 0 5.0 10 15
VCC = +15 V
VEE = –15 V
TA = 25
°
C
TA, AMBIENT TEMPERATURE (
°
C)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
VCM = 0 V
, INPUT COMMON MODE VOLT AGE RANGE (V)
ICR
TA, AMBIENT TEMPERATURE (
°
C)
–55 –25 0 25 50 75 100 125
VCC = +5.0 V to +18 V
VEE = –5.0 V to –18 V
∆
VIO = 5.0 mV
TA, AMBIENT TEMPERATURE (
°
C)
VOL, OPEN LOOP VOLTAGE GAIN (kV/V)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
f = 10 Hz
∆
VO = 10 V to +10 V
RL = 600
Ω
f, FREQUENCY (Hz)
VOL
A , OPEN LOOP VOLTAGE GAIN (dB)
, EXCESS PHASE (DEGREES)
2 3 4 5 6 7 8 9 10 20
80
100
120
140
160
180
200
220
240
260
280
φ
1A) Phase (RL = 600
Ω
)
2A) Phase (RL = 600
Ω,
CL = 300 pF)
1B) Gain (RL = 600
Ω
)
2B) Gain (RL = 600
Ω
, CL = 300 pF)
VCC = +15 V
VEE = –15 V
VO = 0 V
TA = 25
°
C
2B
1A
2A
1B
VCC, |VEE|, SUPPLY VOLTAGE (V)
0 5.0 10 15 20
TA = 25
°
C
RL = 10 k
Ω
RL = 600
Ω
I , INPUT BIAS CURRENT (nA)
IB
V
A
160
140
120
100
80
60
40
20
0
120
110
100
90
80
70
60
VCC
VCC –0.5 V
VCC –1.0 V
VCC –1.5 V
VCC –2.0 V
VEE +1.0 V
VEE +0.5 V
VEE
250
200
150
100
50
0
50
40
30
20
10
0
–10
–20
–30
–40
–50
40
35
30
25
20
15
10
5.0
0
MC33178 MC33179
5
MOTOROLA ANALOG IC DEVICE DATA
VO, OUTPUT VOLTAGE (V )
pp
Source
Sink VCC = +15 V
VEE = –15 V
VID =
±
1.0 V
RL < 10
Ω
TA = –55
°
to +125
°
C
VCC = +15 V
VEE = –15 V
∆
VCC =
±
1.5 V
–PSR
+PSR
–
+
∆
VO
ADM
PSR = 20 Log
VCC
VEE
∆
VO/ADM
∆
VCC
Figure 9. Output Saturation Voltage
versus Load Current Figure 10. Output Voltage
versus Frequency
Figure 11. Common Mode Rejection
versus Frequency Over Temperature Figure 12. Power Supply Rejection
versus Frequency Over Temperature
Figure 13. Output Short Circuit Current
versus Output Voltage Figure 14. Output Short Circuit Current
versus Temperature
Vsat
IL, LOAD CURRENT (
±
mA)
0 5.0 10 15 20
VCC = +5.0 V to +18 V
VEE = –5.0 V to –18 V
TA = +125
°
C
TA = –55
°
C
Source
Sink
TA = –55
°
C
f, FREQUENCY (Hz)
1.0 k 10 k 100 k 1.0 M
VCC = +15 V
VEE = –15 V
RL = 600
Ω
AV = +1.0 V
THD =
≤
1.0%
TA = 25
°
C
f, FREQUENCY (Hz)
CMR, COMMON MODE REJECTION (dB)
10 100 1.0 k 10 k 100 k 1.0 M
VCC = +15 V
VEE = –15 V
VCM = 0 V
∆
VCM =
±
1.5 V
TA = –55
°
to +125
°
C
PSR, POWER SUPPLY REJECTION (dB)
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 100 k 1.0 M
I , OUTPUT SHOR T CIRCUIT CURRENT (mA)
SC
–15 –9.0 –3.0 0 3.0 9.0 15
Source
Sink
VCC = +15 V
VEE = –15 V
VID =
±
1.0 V
I , OUTPUT SHOR T CIRCUIT CURRENT (mA)
SC
TA, AMBIENT TEMPERATURE (
°
C)
–55 –25 0 25 50 75 100 125
, OUTPUT SATURATION VOLTAGE (V)
TA = +125
°
C
VO, OUTPUT VOLTAGE (V)
VCC
VCC –1.0 V
VCC –2.0 V
VEE +2.0 V
VEE +1.0 V
VEE
28
24
20
16
8.0
4.0
0
12
120
100
80
60
40
20
0
120
100
80
60
40
20
0
100
80
60
40
20
0
100
90
80
70
60
50
CMR = 20 Log
–
+
∆
VCM
∆
VO
x ADM
ADM
∆
VCM
∆
VO
MC33178 MC33179
6MOTOROLA ANALOG IC DEVICE DATA
2B
1A
1B 2A
1A) Phase VCC =18 V, VEE = –18 V
2A) Phase VCC 1.5 V, VEE = –1.5 V
1B) Gain VCC = 18 V, VEE = –18 V
2B) Gain VCC = 1.5 V, VEE = –1.5 V
TA = 25
°
C
RL =
∞
CL = 0 pF
TA = +125
°
C
TA = +25
°
C
TA = –55
°
C
I , SUPPLY CURRENT/AMPLIFIER ( A)
Figure 15. Supply Current versus Supply
Voltage with No Load Figure 16. Normalized Slew Rate
versus Temperature
Figure 17. Gain Bandwidth Product
versus Temperature Figure 18. Voltage Gain and Phase
versus Frequency
Figure 19. Voltage Gain and Phase
versus Frequency Figure 20. Open Loop Gain Margin
versus Temperature
VCC, |VEE| , SUPPLY VOLTAGE (V)
CC
µ
0 2.0 4.0 6.0 8.0 10 12 14 16 18 TA, AMBIENT TEMPERATURE (
°
C)
SR, SLEW RATE (NORMALIZED)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
∆
Vin = 20 Vpp
TA, AMBIENT TEMPERATURE (
°
C)
GBW, GAIN BANDWIDTH PRODUCT (MHz)
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
f = 100 kHz
RL = 600
Ω
CL = 0 pF
f, FREQUENCY (Hz)
A , VOLTAGE GAIN (dB)
V
, EXCESS PHASE (DEGREES)
100 k
φ
1.0 M 10 M 100 M
Gain
Phase
VCC = +15 V
VEE = –15 V
RL = 600
Ω
TA = 25
°
C
CL = 0 pF
f, FREQUENCY (Hz)
A , VOLTAGE GAIN (dB)
V
, PHASE (DEGREES)
100 k
φ
1.0 M 10 M 100 M TA, AMBIENT TEMPERATURE (
°
C)
A , OPEN LOOP GAIN MARGIN (dB)
m
–55 –25 0 25 50 75 100 125
VCC = +15 V
VEE = –15 V
RL = 600
Ω
CL = 10 pF
CL = 100 pF
CL = 300 pF
625
500
375
250
125
0
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
10
8.0
6.0
4.0
2.0
0
50
40
30
20
10
0
–10
–20
–30
–40
–50
50
40
30
20
10
0
–10
–20
–30
–40
–50
15
12
9.0
6.0
3.0
0
VO
100 pF
600
Ω
–
+
∆
Vin
80
100
120
140
160
180
200
220
240
260
280
80
100
120
140
160
180
200
220
240
260
280
MC33178 MC33179
7
MOTOROLA ANALOG IC DEVICE DATA
VCC = +15 V VO = 2.0 Vpp
VEE = –15 V TA = 25
°
C
RL = 600
Ω
AV = 1000
AV = 100
AV = 10 AV = 1.0
Figure 21. Phase Margin
versus Temperature Figure 22. Phase Margin and Gain Margin
versus Differential Source Resistance
Figure 23. Open Loop Gain Margin and Phase
Margin versus Output Load Capacitance Figure 24. Channel Separation
versus Frequency
Figure 25. Total Harmonic Distortion
versus Frequency Figure 26. Output Impedance
versus Frequency
φ
m
VCC = +15 V
VEE = –15 V
RL = 600
Ω
CL = 10 pF
CL = 100 pF
CL = 300 pF
TA, AMBIENT TEMPERATURE (
°
C)
–55 –25 0 25 50 75 100 125
, PHASE MARGIN (DEGREES)
RT, DIFFERENTIAL SOURCE RESISTANCE (
Ω
)
A , GAIN MARGIN (dB)
m
100 1.0 k 10 k 100 k
m
φ
, PHASE MARGIN (DEGREES)
Gain Margin
Phase Margin
VCC = +15 V
VEE = –15 V
RT = R1+R2
VO = 0 V
TA = 25
°
C
A , OPEN LOOP GAIN MARGIN (dB)
m
m
CL, OUTPUT LOAD CAPACITANCE (pF)
φ
10 100 1.0 k
, PHASE MARGIN (DEGREES)
Phase Margin
Gain Margin
VCC = +15 V
VEE = –15 V
VO = 0 V
f, FREQUENCY (Hz)
CS, CHANNEL SEP ARATION (dB)
100 1.0 k 10 k 100 k 1.0 M
Drive Channel
VCC = +15 V
CEE = –15 V
RL = 600
Ω
TA = 25
°
C
f, FREQUENCY (Hz)
THD, TOTAL HARMONIC DIST OR TION (%)
10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz)
|Z |, OUTPUT IMPEDANCE ( )
O
Ω
1.0 k 10 k 100 k 1.0 M 10 M
1. AV = 1.0
2. AV = 10
3. AV = 100
4. AV = 1000
VCC = +15 V
VEE = –15 V
VO = 0 V
TA = 25
°
C
3
421
60
50
40
30
20
10
0
12
10
8.0
6.0
4.0
2.0
0
18
15
12
9.0
6.0
3.0
0
150
140
130
120
110
100
10
1.0
0.1
0.01
500
400
300
200
100
0
60
50
40
30
20
10
0
60
50
40
30
0
10
20
Vin
R2
R1VO
–
+
VO
600
Ω
–
+
Vin CL
MC33178 MC33179
8MOTOROLA ANALOG IC DEVICE DATA
Figure 27. Input Referred Noise Voltage
versus Frequency Figure 28. Input Referred Noise Current
versus Frequency
Figure 29. Percent Overshoot versus
Load Capacitance Figure 30. Noninverting Amplifier Slew Rate
Figure 31. Small Signal Transient Response Figure 32. Large Signal Transient Response
t, TIME (2.0
µ
s/DIV)
t, TIME (5.0
µ
s/DIV)
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 600
Ω
CL = 100 pF
TA = 25
°
C
t, TIME (2.0 ns/DIV)
VO
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 10 k
e , INPUT REFERRED NOISE VOLT AGE ( )
n
nV/ Hz√
VCC = +15 V
VEE = –15 V
TA = 25
°
C
f, FREQUENCY (Hz)
i , INPUT REFERRED NOISE CURRENT ( )
n
10 100 1.0 k 10 k 100 k
VCC = +15 V
VEE = –15 V
TA = 25
°
C
pA/ Hz√
CL, LOAD CAPACITANCE (pF)
PERCENT OVERSHOOT (%)
10 100 1.0 k 10 k
VCC = +15 V
VEE = –15 V
TA = 25
°
C
RL = 600
Ω
RL = 2.0 k
Ω
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 600
Ω
CL = 100 pF
TA = 25
°
C
VCC = +15 V
VEE = –15 V
AV = +1.0
RL = 600
Ω
CL = 100 pF
TA = 25
°
C
, OUTPUT VOLTAGE (50 mV/DIV)
VO, OUTPUT VOLTAGE (5.0 V/DIV) VO, OUTPUT VOLTAGE (5.0 V/DIV)
20
18
16
14
12
10
8.0
6.0
4.0
2.0
0
0.5
0.4
0.3
0.2
0.1
0
100
90
80
70
60
50
40
30
20
10
0
Input Noise Voltage Test Circuit
+VO
–VO
Input Noise Current Test Circuit
RS
(RS = 10 k
Ω
)
+
–
MC33178 MC33179
9
MOTOROLA ANALOG IC DEVICE DATA
10 k
A1
To
Receiver +
–
1.0
µ
F
300
200 k
120 k
2.0 k A2 820
1N4678
Tip
Phone Line
Ring
A3
VR
From
Microphone –
–
+
+
10 k
10 k
10 k
VR
10 k
0.05
µ
F
Figure 33. Telephone Line Interface Circuit
APPLICATION INFORMATION
This unique device uses a boosted output stage to
combine a high output current with a drain current lower than
similar bipolar input op amps. Its 60° phase margin and 15 dB
gain margin ensure stability with up to 1000 pF of load
capacitance (see Figure 23). The ability to drive a minimum
600 Ω load makes it particularly suitable for telecom
applications. Note that in the sample circuit in Figure 33 both
A2 and A3 are driving equivalent loads of approximately
600 Ω.
The low input offset voltage and moderately high slew rate
and gain bandwidth product make it attractive for a variety of
other applications. For example, although it is not single
supply (the common mode input range does not include
ground), it is specified at +5.0 V with a typical common mode
rejection of 110 dB. This makes it an excellent choice for use
with digital circuits. The high common mode rejection, which
is stable over temperature, coupled with a low noise figure
and low distortion, is an ideal op amp for audio circuits.
The output stage of the op amp is current limited and
therefore has a certain amount of protection in the event of a
short circuit. However , because of its high current output, it is
especially important not to allow the device to exceed the
maximum junction temperature, particularly with the
MC33179 (quad op amp). Shorting more than one amplifier
could easily exceed the junction temperature to the extent of
causing permanent damage.
Stability
As usual with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For example,
long unshielded input or output leads may result in unwanted
input/output coupling. In order to preserve the relatively
low input capacitance associated with these amplifiers,
resistors connected to the inputs should be immediately
adjacent to the input pin to minimize additional stray input
capacitance. This not only minimizes the input pole
frequency for optimum frequency response, but also
minimizes extraneous “pick up” at this node. Supplying
decoupling with adequate capacitance immediately adjacent
to the supply pin is also important, particularly over
temperature, since many types of decoupling capacitors
exhibit great impedance changes over temperature.
Additional stability problems can be caused by high load
capacitances and/or a high source resistance. Simple
compensation schemes can be used to alleviate these
effects.
MC33178 MC33179
10 MOTOROLA ANALOG IC DEVICE DATA
If a high source of resistance is used (R1 > 1.0 kΩ), a
compensation capacitor equal to or greater than the input
capacitance of the op amp (10 pF) placed across the
feedback resistor (see Figure 34) can be used to neutralize
that pole and prevent outer loop oscillation. Since the closed
loop transient response will be a function of that capacitance,
it is important to choose the optimum value for that capacitor .
This can be determined by the following Equation:
CC = (1 +[R1/R2])2
CL (ZO/R2)(1)
where: ZO is the output impedance of the op amp.
For moderately high capacitive loads (500 pF < CL
< 1500 pF) the addition of a compensation resistor on the
order of 20 Ω between the output and the feedback loop will
help to decrease miller loop oscillation (see Figure 35). For
high capacitive loads (CL > 1500 pF), a combined
compensation scheme should be used (see Figure 36). Both
the compensation resistor and the compensation capacitor
affect the transient response and can be calculated for
optimum performance. The value of CC can be calculated
using Equation (1). The Equation to calculate RC is as
follows:
(2)
RC = ZO
R1/R2
Figure 34. Compensation for
High Source Impedance Figure 35. Compensation Circuit for
Moderate Capacitive Loads
Figure 36. Compensation Circuit for
High Capacitive Loads
R2
–
+
R1 ZL
CC
R2
RC
CL
R1
–
+
R2
CC
RC
CL
R1
–
+
MC33178 MC33179
11
MOTOROLA ANALOG IC DEVICE DATA
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
OUTLINE DIMENSIONS
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M––– 10 ––– 10
N0.76 1.01 0.030 0.040
__
SEATING
PLANE
14
58
A0.25 MCBSS
0.25 MBM
h
q
C
X 45
_
L
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.18 0.25
D4.80 5.00
E1.27 BSCe3.80 4.00
H5.80 6.20
h
0 7
L0.40 1.25
q
0.25 0.50
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
EH
A
Be
B
A1
CA
0.10
MC33178 MC33179
12 MOTOROLA ANALOG IC DEVICE DATA
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
OUTLINE DIMENSIONS
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
17
14 8
B
A
F
HG D K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L0.300 BSC 7.62 BSC
M0 10 0 10
N0.015 0.039 0.39 1.01
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE
D14 PL K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
____
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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MC33178/D
*MC33178/D*
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