AS4SD4M16-8DG/IT - Austin Semiconductor, Inc.

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

FEATURES

• Extended T esting Over -55°C to +125° C and

Industrial T emp -40°C to 85° C

• WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can be

changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8 or full page

• Auto Precharge and Auto Refresh Modes

• Self Refresh Mode (Industrial, -40°C to 85° C only)

• 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Longer lead TSOP for improved reliability

(OCPL*)

• Short Flow / Long Flow Test Screening Options

OPTIONS MARKING

• Configurations

4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16

• Plastic Package - OCPL*

54-pin TSOP (400 mil) DG No. 901

•Timing (Cycle Time)

8ns; tAC = 6.5ns @ CL = 3 ( tRP - 24ns) -8

10ns; tAC = 9ns @ CL = 2 -10

•Operating T emperature Ranges

-Military (-55°C to +125° C) XT

-Industrial T emp (-40°C to 85° C) IT

KEY TIMING PARAMETERS

SPEED

CLOCK

SETUP HOLD

GRADE FREQUENCY CL = 2** CL = 3** TIME TIME

-8 125 MHz – 6.5ns 2ns 1ns

-10 100 MHz – 7ns 3ns 1ns

-8 83 MH z 9ns – 2ns 1ns

-10 66 MH z 9ns – 3ns 1ns

ACCESS TIME

*Off-center parting line

**CL = CAS (READ) latency

PIN ASSIGNMENT

(Top View)

54-Pin TSOP

Note: “\” indicates an active low.

Configuration 1 Meg x 16 x 4 banks

Refresh Count 4K

Row Addressing 4K (A0-A11)

Bank Addressing 4 (BA0, BA1)

Column Addressing 256 (A0-A7)

4 Meg x 16

4 Meg x 16 SDRAM

Synchronous DRAM Memory

For more products and information

please visit our web site at

www.austinsemiconductor.com

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

GENERAL DESCRIPTION

The 64Mb SDRAM is a high-speed CMOS, dynamic ran-

dom-access memory containing 67,108,864 bits. It is internally

configured as a quad-bank DRAM with a synchronous inter-

face (all signals are registered on the positive edge of the clock

signal, CLK). Each of the x16’ s 6,777,216-bit banks is organized

as 4,096 rows by 256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a pro-

grammed number of locations in a programmed sequence. Ac-

cesses begin with the registration of an ACTIVE command,

which is then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed (BA0, BA1

select the bank; A0-A11 select the row). The address bits

registered coincident with the READ or WRITE command are

used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with a

burst terminate option. An AUTO PRECHARGE function may

be enabled to provide a self-timed row precharge that is initi-

ated at the end of the burst sequence.

The 64Mb SDRAM uses an internal pipelined architecture

to achieve high-speed operation. This architecture is compat-

ible with the 2n rule of prefetch architectures, but it also allows

the column address to be changed on every clock cycle to

achieve a high-speed, fully random access. Precharging one

bank while accessing one of the other three banks will hide the

precharge cycles and provide seamless, high-speed, random-

access operation.

The 64Mb SDRAM is designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is provided,

along with a power-saving, power-down mode. All inputs and

outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating

performance, including the ability to synchronously burst data

at a high data rate with automatic column-address generation,

the ability to interleave between internal banks in order to hide

precharge time and the capability to randomly change column

addresses on each clock cycle during a burst access.

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

TABLE OF CONTENTS

Functional Block Diagram - 4 Meg x 16 ........................................ 4

Pin Descriptions ............................................................................. 5

Functional Description ................................................................. 6

Initialization ............................................................................. 6

Register Definition ................................................................. 6

Mode Register ................................................................ 6

Burst Length ................................................................... 6

Burst T ype ....................................................................... 7

CAS Latency ................................................................... 8

Operating Mode ............................................................. 8

W rite Burst Mode .......................................................... 8

Commands ....................................................................................... 9

T ruth T able 1 (Commands and DQM Operation) ......................... 9

Command Inhibit .................................................................... 10

No Operation (NOP) .................................................................10

Load Mode Register ............................................................. 10

Active ....................................................................................... 10

Read .......................................................................................... 10

Write ......................................................................................... 10

Precharge ................................................................................. 10

Auto Precharge ...................................................................... 10

Burst T erminate ...................................................................... 11

Auto Refresh .......................................................................... 11

Self Refresh ............................................................................. 11

Operation ..................................................................................... 12

Bank/Row Activation ............................................................ 12

Reads ........................................................................................ 13

Writes ....................................................................................... 19

Precharge................................................................................... 21

Power-Down...............................................................................21

Clock Suspend......................................................................... 22

Burst Read/Single Write ...........................................................22

Concurrent Auto Precharge ................................................. 23

Truth T able 2 (CKE) ......................................................................2 5

T ruth Table 3 (Current State, Same Bank) ................................. 26

Truth Table 4 (Current State, Different Bank) ........................... 28

Absolute Maximum Ratings ........................................................ 30

DC Electrical Characteristics and Operating Conditions......... 30

ICC Specifications and Conditions .............................................. 30

Capacitance ..................................................................................... 31

AC Electrical Characteristics (Timing T able) ............................31

Timing Waveforms

Initialize and Load Mode Register ..................................... 34

Power-Down Mode ................................................................ 35

Clock Suspend Mode ........................................................... 36

Auto Refresh Mode .............................................................. 37

Self Refresh Mode ................................................................. 38

Reads

Read - W ithout Auto Precharge ................................. 39

Read - With Auto Precharge ....................................... 40

Alternating Bank Read Accesses .............................. 41

Read - Full-Page Burst ......................................................... 42

Read - DQM Operation ................................................ 43

Writes

W rite - W ithout Auto Precharge ................................ 44

W rite - With Auto Precharge ...................................... 45

Alternating Bank W rite Accesses .............................. 46

W rite - Full-Page Burst ................................................. 47

W rite - DQM Operation ............................................... 48

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

CKE

CLK

CS\

WE\

CAS\

RAS\

DQML, DQMH

DQ0-DQ15

A0,

A10,

BA

1

2

12 12

ROW

ADDRESS

MUX

ADDRESS

REGISTER

REFRESH

COUNTER 12

CONTROL

LOGIC

COMMAND

DECODE

MODE REGISTER

14

DATA

OUTPUT

REGISTER

DATA

INPUT

REGISTER

16

BANK0

ROW-

ADDRESS

LATCH &

DECODER

12

BANK 0

MEMORY

ARRAY

(4,096 X 256 X 16)

SENSE AMPLIFIERS

4096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

4096

COLUMN

DECODER

256

(X16)

BANK

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

8

2

8

BANK1 BANK2 BANK3

2 2

FUNCTIONAL BLOCK DIAGRAM

4 Meg x 16 SDRAM

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

PIN DESCRIPTION

TSOP

PIN NUMBERS

38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are

sampled on the positive edge of CLK. CLK also increments the internal burst

counter and controls the output registers.

37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF

REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE

in either bank) or CLOCK SUSPEND operation (burst/access in progress).

CKE is synchronous except after the device enters power-down and self

refresh modes, where CKE becomes asynchronous until after exiting the

same mode. The input buffers, including CLK, are disabled during power-down

and self refresh modes, providing low standby power. CKE may be tied

HIGH.

19 CS\ Input Chip Select: CS\ enables (registered LOW) and disables (registered HIGH)

the command decoder. All commands are masked when CS\ is registered

HIGH. CS\ provides for external bank selection on systems with multiple

banks. CS\ is considered part of the command code.

18, 17 RAS\, WE\ Input Command Inputs: RAS\, CAS\, and WE\ (along with CS\) define the

16 CAS\ command being entered.

15, 39 DQML, Input Input/Output Mask: DQM is an input mask signal for write accesses and an

DQMH output enable signal for read accesses. Input data is masked when DQM is

sampled HIGH during a WRITE cycle. The output buffers are placed in a

High-Z state (two-clock latency) when DQM is sampled HIGH during a READ

cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15.

DQML and DQMH are considered same state when referenced as DQM.

20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied.

23-26, 29-34, A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row

22, 35 address A0-A11) and READ/WRITE command (column address A0-A7, with

A10 defining AUTO PRECHARGE) to select one location out of the memory

array in the respective bank. A10 is sampled during a PRECHARGE

command to determine if all banks are to be precharged (A10 HIGH) or bank

selected by BA0,BA1 (LOW). The address inputs also provide the op-code

during a LOAD MODE REGISTER command.

2, 4, 5, 7, 8 DQ0- DQ15 Input/ Data I/O: Data bus.

10, 11, 13, 42 Output

44, 45, 47, 48

50, 51, 53

36, 40 NC — No Connect: These pins should be left unconnected.

3, 9, 43, 49 VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity.

6, 12, 46, 52 VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

1, 14, 27 VDD Supply Power Supply: +3.3V ±0.3V.

28, 41, 54 VSS Supply Ground.

SYMBOL TYPE DESCRIPTION

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

6

FUNCTIONAL DESCRIPTION

In general, the 64Mb SDRAM is quad-bank DRAM (1

Meg x 16 x 4 banks) which operate at 3.3V and include a

synchronous interface (all signals are registered on the

positive edge of the clock signal, CLK). Each of the x16’s

16,777,216-bit banks is organized as 4,096 rows by 256 columns

by 16 bits.

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and continue for

a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command

which is then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed (BA0 and

BA1 select the bank, A0-A11 select the row). The address bits

( x16: A0-A7) registered coincident with the READ or WRITE

command are used to select the starting column location for the

burst access.

Prior to normal operation, the SDRAM must be initial-

ized. The following sections provide detailed information

covering device initialization, register definition, command

descriptions and device operation.

Initalization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other than those

specified may result in undefined operation. Once power is

applied to VDD and VDDQ (simultaneously) and the clock is

stable, the SDRAM requires a 100µs delay prior to applying an

executable command. Starting at some point during this 100µs

period and continuing at least through the end of this period,

COMMAND INHIBIT or NOP commands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having been ap-

plied, a PRECHARGE command should be applied. All banks

must be precharged, thereby placing the device in the all banks

idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles are

complete, the SDRAM is ready for Mode Register program-

ming. Because the Mode Register will power up in an unknown

state, it should be loaded prior to applying any operational

command.

REGISTER DEFINITION

Mode Register

The Mode Register is used to define the specific mode

of operation of the SDRAM. This definition includes the

selection of a burst length, a burst type, a CAS latency, an

operating mode and a write burst mode, as shown in Figure 1.

The Mode Register is programmed via the LOAD MODE

REGISTER command and will retain the stored information until

it is programmed again or the device loses power.

Mode register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or interleaved), M4-

M6 specify the CAS latency, M7 and M8 specify the operating

mode, M9 specifies the WRITE burst mode, and M10 and M11

are reserved for future use.

The Mode Register must be loaded when all banks are

idle, and the controller must wait the specified time before

initiating the subsequent operation. Violating either of these

requirements will result in unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst

oriented, with the burst length being programmable, as shown

in Figure 1. The burst length determines the maximum number

of column locations that can be accessed for a given READ or

WRITE command. Burst lengths of 1, 2, 4, or 8 locations are

available for both the sequential and the interleaved burst types,

and a full-page burst is available for the sequential type. The

full-page burst is used in conjunction with the BURST

TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning

that the burst will wrap within the block if a boundary is reached.

The block is uniquely selected by A1-A7 (x16) when the burst

length is set to two; A2-A7 (x16) when the burst length is set to

four; and by A3-A7 (x16) when the burst length is set to eight.

The remaining (least significant) address bit(s) is (are) used to

select the starting location within the block. Full-page bursts

wrap within the page if the boundary is reached.

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

7

T

y

pe = Se

q

uential T

y

pe = Interleaved

A0

0 0 - 1 0 - 1

1 1-0 1-0

A1

A0

0 0 0,1,2,3 0,1,2,3

0 1 1,2,3,0 1,0,3,2

1 0 2,3,0,1 2,3,0,1

1 1 3,0,1,2 3,2,1,0

A2 A1

A0

0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7

0 0 1 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6

0 1 0 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5

0 1 1 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4

1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3

1 0 1 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2

1 1 0 6,7,0,1,2,3,4,5, 6,7,4,5,2,3,0,1

1 1 1 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0

Cn, Cn+1, Cn+2,

Cn+3, Cn+4… Not Supported

…Cn-1,

Cn…

BURST DEFINITION

Table 1

8

Full Page

(y) n = A0 - A9

location 0 - y

Order of Access Within a Burst

Burst

Length

2

4

Starting Column

Address

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

M3=0 M3=1

000 1 1

001 2 2

010 4 4

011 8 8

1 0 0 Reserved Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved Reserved

1 1 1 Full Page Reserved

M3

0

1

M6 M5 M4

000

001

010

011

100

101

110

111

M8 M7

00

--

M9

0

1

Reserved

2

3

Burst Type

Sequential

* Should program M11,

M10=0,0 to ensure

compatibility with future

devices.

CAS Latency

Single Location Access

M6 - M0

Defined

-

Operating Mode

Standard Operation

All other states reserved

Write Burst Mode

Programmed Burst Length

Interleave

Mode Register(Mx)

Burst Length

M2 M1 M0

11 10 9 8 7 6 5 4 3 2 1 0

Reserved* WB Op Mode CAS Latency BT Burst Length

BURST TYPE

Accesses within a given burst may be programmed to

be either sequential or interleaved; this is referred to as the

burst type and is selected via bit M3.

The ordering of accesses within a burst is determined

by the burst length, the burst type and the starting column

address, as shown in Table 1.

NOTE:

1 . For full-page accesses: y = 256 (x16).

2 . For a burst length of two, A1-A7 (x16)

select the block-of-two burst; A0 selects

the starting column within the block.

3 . For a burst length of four, A2-A7 (x16)

select the block-of-four burst; A0-A1

select the starting column within the

block.

4 . For a burst length of eight, A3-A7 (x16)

select the clock-of-eight burst; A0-A2

select the starting column within the

block.

5. For a full-page burst, the full row is

selected and A0-A7 (x16) select the

starting column.

6. Whenever a boundary of the block is

reached within a given sequence above,

the following access wraps within the

block.

7 . For a burst length of one, A0-A7 (x16)

select the unique column to be accessed,

and Mode Register bit M3 is ignored.

FIGURE 1

MODE REGISTER DEFINITION

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

8

CAS Latency

The CAS latency is the delay , in clock cycles, between

the registration of a READ command and the availability of the

first piece of output data. The latency can be set to two or three

clocks. If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by clock edge

n+m. The DQs will start driving as a result of the clock edge one

cycle earlier (n + m - 1), and provided that the relevant access

times are met, the data will be valid by clock edge n + m. For

example, assuming that the clock cycle time is such that all

relevant access times are met, if a READ command is registered

at T0 and the latency is programmed to two clocks, the DQs will

start driving after T1 and the data will be valid by T2, as shown

in Figure 2. T able 2 below indicates the operating frequencies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown op-

eration or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting

M7and M8 to zero; the other combinations of values for M7

and M8 are reserved for future use and/or test modes. The

programmed burst length applies to both READ and WRITE

bursts. Test modes and reserved states should not be used

because unknown operation or incompatibility with future ver-

sions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-

M2 applies to both READ and WRITE bursts; when M9 = 1,

the programmed burst length applies to READ bursts, but write

accesses are single-location (nonburst) accesses.

CAS LATENCY = 2 CAS LATENCY = 3

-8 ≤ 83 ≤ 125

-10

≤ 66 ≤ 100

SPEED

ALLOWABLE OPERATING FREQUENCY

(MHz)

CAS LATENCY

Table 2

Figure 2

CAS LATENCY

CLK

COMMAMD

DQ

123

T3T2T1T0

123

1

2

3

1

2

3

1

2

3

123

12

NOPREAD

DOUT

NOP

123

1

2

3

1

2

3

123

12

tLZ tOH

tAC

CAS Latency = 2

T4

123

T3T2T1T0

NOP

READ

12345

12

123

NOP

1234

123

1

2

3

1

2

3

1

2

3

123

1

12

DOUT

tAC

tLZ tOH

CAS Latency = 3

CLK

COMMAMD

DQ

123

1

2

3

123

1

2

3

123

DON’T CARE

UNDEFINED

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

TRUTH TABLE 1- Commands and DMQ Operation

(Note: 1)

NAME (FUNCTION) CS\ RAS\ CAS\

WE\

DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (select bank and activate row) L L H H X Bank/Row X 3

READ (select bank and column and start READ burst) L H L H X Bank/Col X 4

WRITE (select bank and column and start WRITE burst) L H L L X Bank/Col Valid 4

BURST TERMINATE L H H L X X Active

PRECHARGE (deactivate row in bank or banks) L L H L X Code X 5

LOAD MODE REGISTER L L L L X OpCode X 2

Write Enable/Output Enable - - - - L - Active 8

Write Inhibit/Output High-Z - - - - H - High-Z 8

X 6,7LHX X

AUTO REFRESH or SELF REFRESH (enter self refresh

mode) LL

COMMANDS

Truth Table 1 provides a quick reference of available commands.

This is followed by a written description of each command.

Two additional Truth Tables appear following the Operation

section; these tables provide current state/next state informa-

tion.

NOTE:

1 . CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A11 define the op-code written to the Mode Register.

3 . A0-A11 provide row address, and BA0, BA1 determine which bank is made active.

4 . A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10

LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.

5 . A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are

“Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW .

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

10

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new

commands from being executed by the SDRAM, regardless of

whether the CLK signal is enabled. The SDRAM is effectively

deselected. Operations already in progress are not affected.

NO OPERA TION (NOP)

The NO OPERATION (NOP) command is used to per-

form a NOP to an SDRAM which is selected (CS\ is LOW). This

prevents unwanted commands from being registered during

idle or wait states. Operations already in progress are not af-

fected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A0-A11. See

Mode Register heading in the Register Definition section. The

LOAD MODE REGISTER command can only be issued when

all banks are idle, and a subsequent executable command can-

not be issued until tMRD is met.

ACTIVEThe ACTIVE command is used to open (or activate) a

row in a particular bank for a subsequent access. The value on

the BA0, BA1 inputs selects the bank, and the address pro-

vided on inputs A0-A1 1 selects the row. This row remains ac-

tive (or open) for accesses until a PRECHARGE command is

issued to that bank. A PRECHARGE command must be issued

before opening a different row in the same bank.

READ The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1 inputs

selects the bank, and the address provided on inputs A0-A7

(x16) selects the starting column location. The value on input

A10 determines whether or not AUTO PRECHARGE is used. If

AUTO PRECHARGE is selected, the row being accessed will

be precharged at the end of the READ burst; if AUTO

PRECHARGE is not selected, the row will remain open for sub-

sequent accesses. Read data appears on the DQs subject to

the logic level on the DQM inputs two clocks earlier . If a given

DQM signal was registered HIGH, the corresponding DQs will

be High-Z two clocks later; if the DQM signal was registered

LOW, the DQs will provide valid data.

WRITE The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1 inputs

selects the bank, and the address provided on inputs A0-A7

(x16) selects the starting column location. The value on input

A10 determines whether or not AUTO PRECHARGE is used. If

AUTO PRECHARGE is selected, the row being accessed will

be precharged at the end of the WRITE burst; if AUTO

PRECHARGE is not selected, the row will remain open for sub-

sequent accesses. Input data appearing on the DQs is written

to the memory array subject to the DQM input logic level ap-

pearing coincident with the data. If a given DQM signal is

registered LOW, the corresponding data will be written to

memory; if the DQM signal is registered HIGH, the correspond-

ing data inputs will be ignored, and a WRITE will not be ex-

ecuted to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the

open row in a particular bank or the open row in all banks. The

bank(s) will be available for a subsequent row access a speci-

fied time (tRP) after the PRECHARGE command is issued. Input

A10 determines whether one or all banks are to be precharged,

and in the case where only one bank is to be precharged, inputs

BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as

“Don’t Care.” Once a bank has been precharged, it is in the idle

state and must be activated prior to any READ or WRITE com-

mands being issued to that bank.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the

same individual-bank PRECHARGE function described above,

without requiring an explicit command. This is accomplished

by using A10 to enable AUTO PRECHARGE in conjunction

with a specific READ or WRITE command. A precharge of the

bank/row that is addressed with the READ or WRITE com-

mand is automatically performed upon completion of the READ

or WRITE burst, except in the full-page burst mode, where

AUTO PRECHARGE does not apply . AUTO PRECHARGE is

nonpersistent in that it is either enabled or disabled for each

individual READ or WRITE command.

AUTO PRECHARGE ensures that the precharge is

initiated at the earliest valid stage within a burst. The user must

not issue another command to the same bank until the precharge

time (tRP) is completed. This is determined as if an explicit

PRECHARGE command was issued at the earliest possible time,

as described for each burst type in the Operation section of this

data sheet.

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

11

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the SDRAM and is analagous to CAS\-BEFORE-RAS\ (CBR)

REFRESH in conventional DRAMs. This command is non-

persistent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh

controller . This makes the address bits “Don’t Care” during an

AUTO REFRESH command. The 64Mb SDRAM requires 4,096

AUTO REFRESH cycles every 64ms *(tREF), regardless of width

option. Providing a distributed AUTO REFRESH command

every 15.625µs/3.906µs will meet the refresh requirement and

ensure that each row is refreshed. Alternatively, 4,096 AUTO

REFRESH commands can be issued in a burst at the minimum

cycle rate (tRC), once every 64ms/ 16ms.

SELF REFRESH

(Industrial -40°C to +85°C Only)

The SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system is powered

down. When in the self refresh mode, the SDRAM retains data

without external clocking. The SELF REFRESH command is

initiated like an AUTO REFRESH command except CKE is

disabled (LOW).

Once the SELF REFRESH command is registered, all

the inputs to the SDRAM become “Don’t Care,” with the

exception of CKE, which must remain LOW .

Once self refresh mode is engaged, the SDRAM

provides its own internal clocking, causing it to perform its own

AUTO REFRESH cycles. The SDRAM must remain in self

refresh mode for a minimum period equal to tRAS and may

remain in self refresh mode for an indefinite period beyond that.

The procedure for exiting self refresh requires a

sequence of commands. First, CLK must be stable prior to CKE

going back HIGH. Once CKE is HIGH, the SDRAM must have

NOP commands issued (a minimum of two clocks) for tXSR,

because time is required for the completion of any internal

refresh in progress.

If during normal operation AUTO REFRESH cycles

are issued in bursts (as opposed to being evenly distributed),

a burst of 4,096 AUTO REFRESH cycles should be completed

just prior to entering and just after exiting the self refresh mode.

The self refresh option is not available for the -55° to

+125° screening option.

*64ms for -40° to +85° C ( Industrial Temperatures) and 16ms for -55° to +125°C (Military Temperatures)

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most recently

registered READ or WRITE command prior to the BURST TER-

MINATE command will be truncated, as shown in the Opera-

tion section of this data sheet.

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

12

OPERATION

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued

to a bank within the SDRAM, a row in that bank must be

“opened.” This is accomplished via the ACTIVE command,

which selects both the bank and the row to be activated.

After opening a row (issuing an ACTIVE command), a

READ or WRITE command may be issued to that row, subject

to the tRCD specification. tRCD (MIN) should be divided by the

clock period and rounded up to the next whole number to deter-

mine the earliest clock edge after the ACTIVE command on

which a READ or WRITE command can be entered. For

example, a tRCD specification of 30ns with a 90 MHz clock

(11.11ns period) results in 2.7 clocks, rounded to 3. This is

reflected in Figure 4, which covers any case where 2 < tRCD

(MIN)/ tCK ≤ 3. (The same procedure is used to convert other

specification limits from time units to clock cycles).

A subsequent ACTIVE command to a different row in

the same bank can only be issued after the previous active row

has been “closed” (precharged). The minimum time interval

between successive ACTIVE commands to the same bank is

defined by tRC.

A subsequent ACTIVE command to another bank can

be issued while the first bank is being accessed, which results

in a reduction of total row-access overhead. The minimum time

interval between successive ACTIVE commands to different

banks is defined by tRRD.

Figure 4

EXAMPLE: MEETING t RCD (MIN) WHEN 2<tRCD (MIN)/tCK<3

1234

1

23

4

1234

DON’T CARE

CLK

COMMAND

tRCD

1234

12

12345

ACTIVE NOP

T0 T1 T2 T3

12345

NOP

T4

12345

READ or

WRITE

Figure 3

ACTIVATING A SPECIFIC ROW IN A

SPECIFIC BANK

CLK

CKE HIGH

CS\

123456789

123456789012

1

2345678901

2

123456789012

12

1

12345

123456789012

1

2345678901

2

123456789012

12

RAS\

123456789

123456789012

1

2345678901

2

123456789012

1

12345

123456789012

1

2345678901

2

123456789012

12

123456789

1

2345678

9

123456789

1

123456

123456789012345

1

2345678901234

5

123456789012345

1

CAS\

123456789

1

2345678

9

123456789

1

123456

123456789012345

1

2345678901234

5

123456789012345

1

WE\

1234

1234567890123456

1

23456789012345

6

1234567890123456

12

123

1234567890123

1

23456789012

3

1234567890123

12

1234

1234567890123456

1

23456789012345

6

1234567890123456

1

12

123

1234567890123

1

23456789012

3

1234567890123

12

1

A0-A11

BA0, 1

ROW ADDRESS

BANK ADDRESS

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

13

READs

READ bursts are initiated with a READ command, as shown in

Figure 5.The starting column and bank addresses are provided

with the READ command, and AUTO PRECHARGE is either

enabled or disabled for that burst access. If AUTO PRECHARGE

is enabled, the row being accessed is precharged at the comple-

tion of the burst. For the generic READ commands used in the

following illustrations, AUTO PRECHARGE is disabled.

During READ bursts, the valid data-out element from

the starting column address will be available following the CAS

latency after the READ command. Each subsequent data-out

element will be valid by the next positive clock edge. Figure 6

shows general timing for each possible CAS latency setting.

Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go High-Z. A

full-page burst will continue until terminated. (At the end of the

page, it will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a

subsequent READ command, and data from a fixed-length READ

burst may be immediately followed by data from a READ

command. In either case, a continuous flow of data can be

maintained. The first data element from the new burst follows

either the last element of a completed burst or the last desired

data element of alonger burst which is being truncated. The

new READ command should be issued x cycles before the clock

edge at which the last desired data element is valid, where x

equals the CAS latency minus one.

Figure 5

READ COMMAND

12345

CLK

CKE HIGH

CS\

12345678

12345678901

1

123456

1234567890

1

RAS\

12345678

12345678901

1

234567890

1

12345678901

1

123456

1234567890

1

23456789

0

1234567890

1

12345678

1

234567

8

12345678

1

1234567890123

1

23456789012

3

1234567890123

1

CAS\

12345678

1

234567

8

12345678

1

123456

1234567890123

1

23456789012

3

1234567890123

1

WE\

123

12345678901234

1

234567890123

4

12345678901234

1

12

1234

12345678901

1

234567890

1

12345678901

1

12

123

12345678901234

1

234567890123

4

12345678901234

1

12

1234

12345678901

1

234567890

1

12345678901

1

12

A0-A7: x16

BA0, 1

COLUMN ADDRESS

BANK ADDRESS

123

12345678

1

123

12345678901234

1

12

1234

12345678901

1

12

123

12345678901234

1

234567890123

4

12345678901234

1

12

1234

12345678901

1

234567890

1

12345678901

1

12

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A8, A9, A11: x16

A10

Figure 6

CAS LATENCY

123

1

2

3

1

2

3

123

1234

1

23

4

1

23

4

1234

DON’T CARE

UNDEFINED

CLK

COMMAND

DQ

tLZ tOH

tAC

CAS Latency = 3

123

12

1234

123

READ NOP

1234567

DOUT

1234

T0 T1 T2 T3

123

NOP

T4

123

NOP

CLK

COMMAND

DQ

tLZ tOH

tAC

CAS Latency = 2

123

12

123

READ NOP

1234567

DOUT

1234

T0 T1 T2 T3

123

NOP

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

14

This is shown in Figure 7 for CAS latencies of two and three;

data element n + 3 is either the last of a burst of four or the last

desired of a longer burst. The 64Mb SDRAM uses a pipelined

architecture and therefore does not require the 2n rule

associated with a prefetch architecture. A READ command can

be initiated on any clock cycle following a previous READ

command. Full-speed random read accesses can be performed

to the same bank, as shown in Figure 8, or each subsequent

READ may be performed to a different bank.

○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4 T5

READ READ

NOP NOP NOP NOP

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

CLK

COMMAND

ADDRESS

DQ

T6

○○○○○○○○○○○○○○○○○○○○

NOP

1234567

123

1

2

3

1

2

3

1

2

3

123

1234567

1234

1

23

4

1

23

4

1

23

4

1234

1234567

123

1

2

3

1

2

3

1

2

3

123

123456

1234567

123

1

2

3

1

2

3

1

2

3

123

123456

1234567

123

1

2

3

1

2

3

1

2

3

123

BANK,

COL

n

BANK,

COL

b

X=1 cycle

CAS Latency = 2

Figure 7

CONSECUTIVE READ BURSTS

NOTE: Each READ command may be to either bank. DQM is LOW.

1234

1

23

4

1

23

4

1234

DON’T CARE

○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4 T5

READ READ

NOP NOP NOP NOP

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

CLK

COMMAND

ADDRESS

DQ

T6

○○○○○○○○○○○○○○○○○○○○

NOP

1234567

123456

1234

1

23

4

1

23

4

1

23

4

1234

1234567

123456

1234

1

23

4

1

23

4

1

23

4

1234

123456

1234567

1234

1

23

4

1

23

4

1

23

4

1234

1234567

1234

1

23

4

1

23

4

1

23

4

1234

1234567

123

1

2

3

1

2

3

1

2

3

123

BANK,

COL

n

BANK,

COL

b

X=2 cycle

CAS Latency = 3

T7

NOP

1234567

123456

123

12

3

12

3

12

3

123

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

15

○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4 T5

READ NOP

READ READ READ NOP

DOUT

n

DOUT

a

DOUT

x

DOUT

m

CLK

COMMAND

ADDRESS

DQ

123456

1234567

123

1

2

3

1

2

3

1

2

3

123

123456

1234

1

23

4

1

23

4

1

23

4

1234

BANK,

COL

n

BANK,

COL

m

CAS Latency = 2

BANK,

COL

a

BANK,

COL

x

Figure 8

RANDOM READ ACCESSES

NOTE: Each READ command may be to either bank. DQM is LOW.

1234

1

23

4

1

23

4

1234

DON’T CARE

○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4 T5

READ READ NOP

DOUT

n

DOUT

a

DOUT

x

DOUT

m

CLK

COMMAND

ADDRESS

DQ

T6

○○○○○○○○○○○○○○○○○○

NOP

123456

1234567

1234

1

23

4

1

23

4

1

23

4

1234

1234567

123

1

2

3

1

2

3

1

2

3

123

123456

1234

1

23

4

1

23

4

1

23

4

1234

BANK,

COL

n

BANK,

COL

a

CAS Latency = 3

123456

BANK,

COL

x

BANK,

COL

m

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

16

Data from any READ burst may be truncated with a

subsequent WRITE command, and data from a fixed-length

READ burst may be immediately followed by data from a WRITE

command (subject to bus turnaround limitations). The WRITE

burst may be initiated on the clock edge immediately following

the last (or last desired) data element from the READ burst,

provided that I/O contention can be avoided. In a given

system design, there may be a possibility that the device

driving the input data will go Low-Z before the SDRAM DQs

go High-Z. In this case, at least a single-cycle delay should

occur between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in

Figures 9 and 10. The DQM signal must be asserted (HIGH) at

least two clocks prior to the WRITE command (DQM latency is

two clocks for output buffers) to suppress data-out from the

READ. Once the WRITE command is registered, the DQs will

go High-Z (or remain High-Z), regardless of the state of the

DQM signal. The DQM signal must be de-asserted prior to the

WRITE command (DQM latency is zero clocks for input

buffers) to ensure that the written data is not masked. Figure 9

shows the case where the clock frequency allows for bus

contention to be avoided without adding a NOP cycle, and

Figure 10 shows the case where the additional NOP is needed.

○○○○○○○○○○○○○○○○○○

Figure 10

READ TO WRITE WITH EXTRA

CLOCK CYCLE

NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank,

and the WRITE command may be to any bank.

○○○○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4

READ WRITE

NOP NOP NOP

12345

123456

123

1

2

3

1

2

3

123

12345

123456

123

1

2

3

1

2

3

123

12345

123456

123

1

2

3

1

2

3

123

BANK,

COL

n

123456

BANK,

COL

b

DOUT

n

DIN

b

CLK

COMMAND

ADDRESS

DQ

1234

tHZ

tDS

T5

NOP

12345

12

123

1

2

3

123

DON’T CARE

DQM

Figure 9

READ TO WRITE

NOTE: A CAS latency of three is used for illustration. The READ command may be to any

bank, and the WRITE command may be to any bank. If a CAS latency of one is used, the

DQM is not required.

○○○○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4

READ WRITE

NOP NOP NOP

123456

123

1

2

3

1

2

3

123

123456

12345

12

12345

123456

123

1

2

3

1

2

3

123

BANK,

COL

n

123456

BANK,

COL

b

DOUT

n

DIN

b

CLK

COMMAND

ADDRESS

DQ

12345

tHZ

tCK

tDS

DQM

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

17

A fixed-length READ burst may be followed by, or

truncated with, a PRECHARGE command to the same bank

(provided that AUTO PRECHARGE was not activated), and a

full-page burst maybe truncated with a PRECHARGE command

to the same bank. The PRECHARGE command should be is-

sued x cycles before the clock edge at which the last desired

data element is valid, where x equals the CAS latency minus

one. This is shown in Figure 11 for each possible CAS latency;

data element n + 3 is either the last of a burst of four or the last

desired of a longer burst. Following the PRECHARGE

command, a subsequent command to the same bank cannot be

issued until tRP is met. Note that part of the row precharge time

is hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the optimum

time (as described above) provides the same operation that

would result from the same fixed-length burst

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○

○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4 T5

READ NOP PRECHARGE NOP

CLK

COMMAND

ADDRESS

DQ

T6

○○○○○○○○○○○○○○○

NOP

123456

1234567

1234

1

23

4

1

23

4

1

23

4

1234

1234567

123

1

23

1

23

1

23

123

1234567

123

1

2

3

1

2

3

123

1234567

123

1

2

3

1

2

3

123

1234567

123

1

2

3

1

2

3

1

2

3

123

BANK

a

,

COL

n

CAS Latency = 2

1234567

T7

○○○○○○○○○○○○○○○

ACTIVE

NOP NOP

BANK

(

a

or all) BANK

a

,

ROW

tRP

X = 1 cycles

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

Figure 11

READ T O PRECHARGE

NOT E: DQM is LO W.

1234

1

23

4

1234

DON’T CARE

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○

○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4 T5

READ NOP PRECHARGE NOP

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

CLK

COMMAND

ADDRESS

DQ

T6

○○○○○○○○○○○○○○○

NOP

1234567

123456

123

1

2

3

1

2

3

123

1234567

123456

1234

1

23

4

1

23

4

1234

1234567

123

1

2

3

1

2

3

123

1234567

123456

1234

1

23

4

1

23

4

1234

123456

1234567

123

1

23

1

23

123

BANK

a

,

COL

n

CAS Latency = 3

1234567

T7

○○○○○○○○○○○○○○○

ACTIVE

NOP NOP

BANK

(

a

or all) BANK

a

,

ROW

tRP

X = 2 cycles

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

18

with AUTO PRECHARGE. The disadvantage of the

PRECHARGE command is that it requires that the command

and address buses be available at the appropriate time to issue

the command; the advantage of the PRECHARGE command is

that it can be used to truncate fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length READ bursts

may be truncated with a BURST TERMINATE command,

provided that AUTO PRECHARGE was not activated. The

BURST TERMINATE command should be issued x cycles

before the clock edge at which the last desired data element is

valid, where x equals the CAS latency minus one. This is shown

in Figure 12 for each possible CAS latency; data element n + 3

is the last desired data element of a longer burst.

○○○○○○○○○○○○○○

○○○○○○○○○○○○○

○○○○○○○○○○○○○○

○○○ ○○○○○○○○○○○

T0 T1 T2 T3 T4 T5

READ NOP BURST

TERMINATE NOP

CLK

COMMAND

ADDRESS

DQ

T6

○○○○○○○○○○○○○○

NOP

1234567

123456

123

1

2

3

1

2

3

123

123456

1234567

1234

1

23

4

1

23

4

1234

1234567

123

1

2

3

1

2

3

123

123456

123

1

2

3

1

2

3

123

123456

1234

1

23

4

1

23

4

1234

123456

1234

1

23

4

1

23

4

1234

BANK,

COL

n

CAS Latency = 2

123456

NOP NOP

X = 1 cycles

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

Figure 12

TERMINATING A READ BURST

NOTE: DQM is LOW.

1234

1

23

4

1234

DON’T CARE

○○○○○○○○○○○○○○

○○○○○○○○○○○○○

○○○○○○○○○○○○○○

T0 T1 T2 T3 T4 T5

READ NOP BURST

TERMINATE NOP

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

CLK

COMMAND

ADDRESS

DQ

T6

○○○○○○○○○○○○○○

NOP

1234567

123456

1234

1

23

4

1

23

4

1234

123456

1234567

1234

1

23

4

1

23

4

1234

1234567

123

1

2

3

1

2

3

123

1234567

123

1

2

3

1

2

3

123

123456

123

1

2

3

1

2

3

123

123456

1234567

123

1

2

3

1

2

3

123

BANK,

COL

n

CAS Latency = 3

123456

T7

○○○○○○○○○○○○○○

NOP

NOP NOP

1234567

123456

123

1

2

3

1

2

3

123

X = 2 cycles

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

19

WRITEsWRITE bursts are initiated with a WRITE command,

as shown in Figure 13.

The starting column and bank addresses are provided

with the WRITE command, and AUTO PRECHARGE is either

enabled or disabled for that access. If AUTO PRECHARGE is

enabled, the row being accessed is precharged at the comple-

tion of the burst. For the generic WRITE commands used in the

following illustrations, AUTO PRECHARGE is disabled.

During WRITE bursts, the first valid data-in element

will be registered coincident with the WRITE command. Subse-

quent data elements will be registered on each successive posi-

tive clock edge. Upon completion of a fixed-length burst, as-

suming no other commands have been initiated, the DQs will

remain High-Z and any additional input data will be ignored

(see Figure 14). A full-page burst will continue until terminated.

(At the end of the page, it will wrap to column 0 and continue.)

Data for any WRITE burst may be truncated with a

subsequent WRITE command, and data for a fixed-length

WRITE burst may be immediately followed by data for a WRITE

command. The new WRITE command can be issued on any

clock following the previous WRITE command, and the data

provided coincident with the new command applies to the new

command. An example is shown in Figure 15. Data n + 1 is either

the last of a burst of two or the last desired of a longer burst.

The 64Mb SDRAM uses a pipelined architecture and therefore

does not require the 2n rule associated with a prefetch architec-

ture. A WRITE command can be initiated on any clock cycle

following a previous WRITE command. Full-speed random write

accesses within a page can be performed to the same bank, as

shown in Figure 16, or each subsequent WRITE may be per-

formed to a different bank.

○○○○○○○○○○○

T0 T1 T2 T3

WRITE NOP

CLK

COMMAND

ADDRESS

DQ

123456

123

1

2

3

123

123456

123

1

2

3

123

123456

123

1

2

3

123

BANK,

COL

n

NOP NOP

DIN

n

DIN

n+1

123456

12345

123456

123

1

2

3

1

2

3

123

123456

123

1

2

3

1

2

3

123

NOTE: Burst length = 2. DQM is LOW.

NOTE: DQM is LO W . Each WRITE command may be to any bank.

Figure 14

WRITE BURST

Figure 15

WRITE TO WRITE

1234

1

23

4

1

23

4

1234

DON’T CARE

○○○○○○○○○○○○

T0 T1 T2

WRITE NOP

CLK

COMMAND

ADDRESS

DQ

123456

123

1

2

3

1

2

3

123

BANK,

COL

n

WRITE

DIN

n

DIN

n+1

123456

DIN

b

BANK,

COL

b

Figure 13

WRITE COMMAND

12345

CLK

CKE HIGH

CS\

12345678

12345678901

1

234567890

1

12345678901

1

12345

12345678901

1

234567890

1

12345678901

12

1

RAS\

12345678

12345678901

1

12345

12345678901

12

1

12345678

1

234567

8

12345678

1

12345678901234

1

234567890123

4

12345678901234

12

1

CAS\

WE\

123

123456789012345

1

2345678901234

5

123456789012345

1

123

123456789012

1

2345678901

2

123456789012

1

12

123

123456789012345

1

2345678901234

5

123456789012345

1

123

123456789012

1

2345678901

2

123456789012

1

12

A0-A7: x16

BA0,1

COLUMN ADDRESS

BANK ADDRESS

123

123456789

1

2345678

9

12

123

123456789012345

1

2345678901234

5

1

123

123456789012

1

2345678901

2

1

12

123

123456789012345

1

2345678901234

5

123456789012345

1

123

123456789012

1

2345678901

2

123456789012

1

12

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A8, A9, A11: x16

A10

12345678

12345678901

1

234567890

1

12345678901

1

123456

1234567890

1

23456789

0

1234567890

12

1

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

20

Data for any WRITE burst may be truncated with a

subsequent READ command, and data for a fixed-length WRITE

burst may be immediately followed by a subsequent READ

command. Once the READ command is registered, the data

inputs will be ignored, and WRITEs will not be executed. An

example is shown in Figure 17. Data n+1 is either the last of a

burst of two or the last desired of a longer burst.

Data for a fixed-length WRITE burst may be followed

by, or truncated with, a PRECHARGE command to the same

bank (provided that AUTO PRECHARGE was not activated),

and a full-page WRITE burst may be truncated with a

PRECHARGE command to the same bank. The PRECHARGE

command should be issued tWR after the clock edge at which

the last desired input data element is registered. The Auto

Precharge mode requires a tWR of at least one clock plus time

(8ns), regardless of frequency. In addition, when truncating a

WRITE burst, the DQM signal must be used to mask input data

for the clock edge prior to, and the clock edge coincident with,

the PRECHARGE command. An example is shown in Figure 18.

Data n + 1 is either the last of a burst of two or the last desired

of a longer burst. Following the PRECHARGE command, a

subsequent command to the same bank cannot be issued until

tRP is met.

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the optimum

time (as described above) provides the same operation that

would result from the same fixed-length burst with AUTO

PRECHARGE. The disadvantage of the PRECHARGE command

is that it requires that the command and address buses be

available at the appropriate time to issue the command; the

advantage of the PRECHARGE command is that it can be used

to truncate fixed-length or full-page bursts.

NOTE: DQM coulc remain LOW in this example if the WRITE burst is a fixed length

of 2.

1234

1

23

4

1234

DON’T CARE

Figure 18

WRITE T O PRECHARGE

○○○○○○○○○○○○○○○

1234

tRP

DQM

COMMAND WRITE NOP PRECHARGENOP NOP NOP

ADDRESS

1234

12345

123

1

2

3

123

BANK

a

,

COL

n

1234

12345

1234

12

1234

12

BANK

(

a

or all)

DQ

1234

12345

12

1234

12

1234

123

1

2

3

123

12345

1234

12

1234

123

1

2

3

123

DIN

n

DIN

n+1

ACTIVE

BANK

a

,

ROW

1234

12

tWR

tWR= 2 CLK (“A2 version”)

T0 T1 T2 T3 T4 T5

CLK T6

○○○○○○○○○○○

T0 T1 T2 T3

WRITE WRITE

CLK

COMMAND

ADDRESS

DQ

BANK,

COL

n

WRITE WRITE

DIN

n

DIN

a

12345

NOTE: Each WRITE command may be to any bank. DQM is

LOW. Figure 16

RANDOM WRITE CYCLES

BANK,

COL

a

BANK,

COL

x

BANK,

COL

m

DIN

x

DIN

m

CLK

COMMAND

ADDRESS

DQ

○○○○○○○○○○○

○○○ ○○○○○○○○

○○○○○○○○○○○

WRITE NOP NOP NOP

12345

123456

123

1

2

3

1

2

3

123

123456

12345

12

12345

123

1

2

3

1

2

3

123

12345

123456

12

BANK,

COL

n

12345

READ NOP

T0 T1 T2 T3 T4 T5

12345

123456

123

1

2

3

1

2

3

123

123456

12345

12

1

2

1

2

12

DIN

n

BANK,

COL

b

DIN

n+1

DOUT

b

DOUT

b+1

NOTE: The WRITE command may be to any bank, and the READ command may be to

any bank. DQM is LO W . CAS latency = 2 for illustr ation.

Figure 17

WRITE TO READ

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

21

Fixed-length or full-page WRITE bursts can be

truncated with the BURST TERMINATE command. When

truncating a WRITE burst, the input data applied coincident

with the BURST TERMINATE command will be ignored. The

last data written (provided that DQM is LOW at that time) will

be the input data applied one clock previous to the BURST

TERMINATE command. This is shown in Figure 19, where data

n is the last desired data element of a longer burst.

PRECHARGE

The PRECHARGE command is used to deactivate the

open row in a particular bank or the open row in all banks. The

bank(s) will be available for a subsequent row access some

specified time (tRP) after the PRECHARGE command is issued.

Input A10 determines whether one or all banks are to be

precharged, and in the case where only one bank is to be

precharged, inputs BA0, BA1 select the bank. When all banks

are to be precharged, inputs BA0, BA1 are treated as “Don’t

Care.” Once a bank has been precharged, it is in the idle state

and must be activated prior to any READ or WRITE commands

being issued to that bank.

POWER-DOWN

Power-down occurs if CKE is registered LOW

coincident with a NOP or COMMAND INHIBIT when no

accesses are in progress. If power-down occurs when all banks

are idle, this mode is referred to as precharge power-down; if

power-down occurs when there is a row active in either bank,

this mode is referred to as active power-down. Entering power-

down deactivates the input and output buffers, excluding CKE,

for maximum power savings while in standby. The device may

not remain in the power-down state longer than the refresh

period (64ms/16ms) since no refresh operations are performed

in this mode.

The power-down state is exited by registering a NOP

or COMMAND INHIBIT and CKE HIGH at the desired clock

edge (meeting tCKS).

○○○○○○○○○○

T0 T1 T2

WRITE

CLK

COMMAND

ADDRESS

DQ

12345

12

BANK,

COL

n

12345

123456

123

1

2

3

1

2

3

123

DIN

n

123456

NOTE: DQMs is LOW. Figure 19

TERMINATING A WRITE BURST

BURST

TERMI-

NATE

(ADDRESS)

(DATA)

CLK

CKE

COMMAND

tCKS >tCKS

NOP

12345678

123456789012345678

1

2345678901234567

8

1

2345678901234567

8

1

2345678901234567

8

1

2345678901234567

8

123456789012345678

1234

NOP ACTIVE

tRCD

tRC

tRAS

Input buffers gated off

All banks idle

Enter power-down mode. Exit power-down mode.

1234

1

23

4

1

23

4

1234

DON’T CARE

Figure 21

POWER-DOWN

CLK

CKE HIGH

CS\

12345678

123456789012

1

2345678901

2

123456789012

1

12

12345

12345678901

1

234567890

1

12345678901

12

RAS\

CAS\

WE\

1234567890123456

12

123456789012345678901234

12

123

1234567890123456

1

23456789012345

6

1234567890123456

12

123

123456789012

1

2345678901

2

123456789012

12

1

A0-A9

BA BANK ADDRESS

Figure 20

PRECHARGE COMMAND

123

123456789012345

1

2345678901234

5

123456789012345

12

123

123456789012

1

2345678901

2

123456789012

12

1

A10

12345678

123456789012

1

2345678901

2

123456789012

1

12

12345

12345678901

1

234567890

1

12345678901

12

12345

12345678

1

234567

8

12345678

1

12345678901234

1

234567890123

4

12345678901234

12

12345678

123456789012

1

12

12345

12345678901

1

12

BANK SELECTED

ALL BANKS

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

22

CLOCK SUSPEND

The clock suspend mode occurs when a column

access/burst is in progress and CKE is registered LOW. In the

clock suspend mode, the internal clock is deactivated,

“freezing” the synchronous logic.

For each positive clock edge on which CKE is sampled

LOW, the next internal positive clock edge is suspended. Any

command or data present on the input pins at the time of a

suspended internal clock edge is ignored; any data present on

the DQ pins remains driven; and burst counters are not

incremented, as long as the clock is suspended. (See examples

in Figures 22 and 23.)

Clock suspend mode is exited by registering CKE

HIGH; the internal clock and related operation will resume on

the subsequent positive clock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by

programming the write burst mode bit (M9) in the Mode

Register to a logic 1. In this mode, all WRITE commands result

in the access of a single column location (burst of one), regard-

less of the programmed burst length. READ commands access

columns according to the programmed burst length and

sequence, just as in the normal mode of operation (M9=0).

NOTE: For this e xample, CAS latency = 2, burst length = 4 or greater , and DQM is LO W .

Figure 23

CLOCK SUSPEND DURING READ

BURST

123

DON’T CARE

CLK

COMMAND

ADDRESS

DQ

CKE

INTERNAL

CLOCK

○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○

T0 T1 T2 T3 T4 T5 T6

1234

12345

12

NOPREAD NOP NOP NOP

NOP

1234

12345

12

1234

12345

12

1234

12345

12

1234

12345

123

1

2

3

123

12345

1234

123

1

2

3

123

BANK,

COL

n

1234

12

DOUT

n

DOUT

n+2

DOUT

n+3

DOUT

n+1

CLK

COMMAND

ADDRESS

DQ

○○○ ○○○○○○○○

○○○○○○○○○○○

12345

123456

1234

1

23

4

1234

123456

123

1

2

3

123

WRITENOP NOP NOP

12345

123

1

2

3

123

12345

123456

123

1

2

3

123

123456

12345

123

1

2

3

123

123456

123

1

2

3

123

12345

12

BANK,

COL

n

12345

12

T0 T1 T2 T3 T4 T5

12345

123

1

2

3

123

12345

123456

123

1

2

3

123

12345

123

1

2

3

123

DIN

n

DIN

n+1

DIN

n+2

NOTE: F or this e xample, burst length = 4 or greater , and DQM is LOW .

Figure 22

CLOCK SUSPEND DURING WRITE

BURST

CKE

INTERNAL

CLOCK

12345

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

23

CONCURRENT AUTO PRECHARGE

An access command (READ or WRITE) to another

bank while an access command with AUTO PRECHARGE en-

abled is executing is not allowed by SDRAMs, unless the

SDRAM supports CONCURRENT AUTO PRECHARGE. ASI

SDRAMs support CONCURRENT AUTO PRECHARGE. Four

cases where CONCURRENT AUTO PRECHARGE occurs are

defined below.

READ with AUTO PRECHARGE

1. Interrupted by a READ (with or without AUTO

PRECHARGE): A READ to bank m will interrupt a READ

on bank n, CAS latency later. The PRECHARGE to bank n

will begin when the READ to bank m is registered

(Figure 24).

2. Interrupted by a WRITE (with or without AUTO

PRECHARGE): A WRITE to bank m will interrupt a READ

on bank n when registered. DQM should be used two

clocks prir to the WRITE command to prevent bus

contention. The PRECHARGE to bank n will begin when

the WRITE to bank m is registered (Figure 25).

Figure 24

READ WITH AUTO PRECHARGE INTERRUPTED BY A READ

NOTE: DQM is LOW.

○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○

DOUT

a

DOUT

a+1

DOUT

d

DOUT

d+1

ADDRESS

DQ

○○○○○○○○○○○○○○○○○○○○

1234567

123456

123

1

2

3

1

2

3

123

123456

1234567

1234

1

23

4

1

23

4

1234

123456

123

1

2

3

1

2

3

123

123456

1234567

1234

1

23

4

1

23

4

1234

1234567

123456

1234567

123

1

2

3

1

2

3

123

BANK

n

,

COL

a

BANK

m

,

COL

d

tRP - BANK

n

CAS Latency = 3 (BANK

n

)

1234567

123456

1234

1

23

4

1

23

4

1234

T0 T1 T2 T3 T4 T5

NOP NOP

READ-AP

BANK

n

NOP NOP

CLK

COMMAND

T6

NOP

T7

NOP

READ-AP

BANK

m

CAS Latency = 3 (BANK

m

)

Page Active READ with burst of 4 Interrupt Burst, Precharge Idle

Precharge

READ with burst of 4

Page Active

Internal

States

BANK n

BANK m

tRP-BANK

m

Figure 25

READ WITH AUTO PRECHARGE INTERRUPTED BY A WRITE

NOTE: 1. DQM is HIGH at T2 to pre vent DOUT-a+1 from contending with DIN-d at T4.

○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○

○○○ ○○○○○○○○○○○○○○○

DOUT

a

DIN

d

DQ

○○○○○○○○○○○○○○○○○

CAS Latency = 3 (BANK

n

)

ADDRESS

1234567

123456

123

1

2

3

1

2

3

123

123456

1234567

123

1

23

1

23

123

123456

123

12

3

12

3

123

123456

1234567

123

1

2

3

1

2

3

123

1234567

123456

1234567

123

1

2

3

1

2

3

123

BANK

n

,

COL

a

BANK

m

,

COL

d

tRP - BANK

n

1234567

123456

123

1

2

3

1

2

3

123

T0 T1 T2 T3 T4 T5

NOP NOP

READ-AP

BANK

n

NOP NOP

CLK

COMMAND

T6

NOP

T7

NOP

WRITE-AP

BANK

m

Page

Active READ with burst of 4 Interrupt Burst, Precharge Idle

Write back

WRITE with burst of 4

Page Active

Internal

States

BANK n

BANK m

DQM1

1234567

123456

123

1

2

3

123

DIN

d+1

DIN

d+2

DIN

d+3

1234

1

23

4

1

23

4

1234

Don’t Care

tWR-BANK

m

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

24

WRITE with AUTO PRECHARGE

3. Interrupted by a READ (with or without AUTO

PRECHARGE): A READ to bank m will interrupt a

WRITE on bank n when registered, with the data-out

appearing CAS latency later. The PRECHARGE to bank

will begin after tWR is met, where tWR begins when the

READ to bank m is registered. The last valid WRITE to

bank n will be data-in registered one clock prior to the

READ to bank m (Figure 26).

4 Interrupted by a WRITE (with or without AUTO

PRECHARGE): A WRITE to bank m will interrupt a

WRITE on bank n when registered. The PRECHARGE to

bank n will begin after tWR is met, where tWR begins when

the WRITE to bank m is registered. The last valid data

WRITE to bank n will be data registered one clock prior

to a WRITE to bank 1 (Figure 27).

○○○○○○○○○○○○○○○○○○

Figure 26

WRITE WITH AUTO PRECHARGE INTERRUPTED BY A READ

NOTE: DQM is LO W .

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○

DIN

a

DIN

a+1

DOUT

d

DOUT

d+1

ADDRESS

DQ

123456

1234567

1234

1

23

4

1

23

4

1234

123456

1234567

123

1

2

3

1

2

3

123

123456

1234567

1234

1

23

4

1

23

4

1234

123456

1234567

123

1

2

3

1

2

3

123

1234567

123456

1234567

123

1

2

3

1

2

3

123

BANK

n

,

COL

a

BANK

m

,

COL

d

tWR - BANK

n

123456

123

1

2

3

1

2

3

123

T0 T1 T2 T3 T4 T5

NOP NOP

WRITE-AP

BANK

n

NOP NOP

CLK

COMMAND

T6

NOP

T7

NOP

WRITE-AP

BANK

m

CAS Latency = 3 (BANK

m

)

Page Active WRITE with burst of 4 Interrupt Burst, Write back Precharge

READ with burst of 4

Page Active

Internal

States

BANK n

BANK m

tRP-BANK

n

tRP-BANK

m

○○○○○○○○○○○○○○○

Figure 27

WRITE WITH AUTO PRECHARGE INTERRUPTED BY A WRITE

NOTE: DQM is LOW.

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○

DIN

a

DIN

a+1

ADDRESS

DQ

123456

1234567

123

1

2

3

1

2

3

123

1234567

123456

123

1

2

3

1

2

3

123

123456

1234567

1234

1

23

4

1

23

4

1234

1234567

123

1

2

3

1

2

3

123

123456

1234567

123456

123

1

2

3

1

2

3

123

BANK

n

,

COL

a

BANK

m

,

COL

d

tWR - BANK

n

123456

1234567

123

1

2

3

1

2

3

123

T0 T1 T2 T3 T4 T5

NOP NOP

WRITE-AP

BANK

n

NOP NOP

CLK

COMMAND

T6

NOP

T7

NOP

WRITE-AP

BANK

m

Page Active WRITE with burst of 4 Interrupt Burst, Write back Precharge

WRITE with burst of 4

Page Active

Internal

States

BANK n

BANK m

tRP-BANK

n

tWR-BANK

m

Write back

DIN

a+2

DIN

d

DIN

d+1

DIN

d+2

DIN

d+3

123

1

2

3

1

2

3

123

Don’t Care

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

25

CKE

n-1

CKE

n

CURRENT STATE COMMAND

n

ACTION

n

NOTES

Power-Down X Maintain Power-Down

Self Refresh X Maintain Self Refresh

Clock Suspend X Maintain Clock Suspend

Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5

Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6

Clock Suspend X Exit Clock Suspend 7

All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry

All Banks Idle AUTO REFRESH Self Refresh Entry

Reading or Writing VALID Clock Suspend Entry

HH See Truth Table 3

LL

LH

HL

NOTE:

1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n .

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1

(provided that tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND

INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A

minimum of two NOP commands must be provided during tXSR period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next

command at clock edge n + 1.

TRUTH TABLE 2-CKE1,2,3,4

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

26

CURRENT STATE CS\ RAS\ CAS\ WE\ COMMAND (ACTION) NOTES

H X X X COMMAND INHIBIT (NOP/Continue previous operation)

L H H H NO OPERATION (NOP/Continue previous operation)

L L H H ACTIVE (Select and activate row)

L L L H AUTO REFRESH 7

L L L L LOAD MODE REGISTER 7

L L H L PRECHARGE 11

L H L H READ (Select column and start READ burst) 10

L H L L WRITE (Select column and start WRITE burst) 10

L L H L PRECHARGE (Deactivate row in bank or banks) 8

L H L H READ (Select column and start new READ burst) 10

L H L L WRITE (Select column and start WRITE burst) 10

L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8

L H H L BURST TERMINATE 9

L H L H READ (Select column and start READ burst) 10

L H L L WRITE (Select column and start new WRITE burst) 10

L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8

L H H L BURST TERMINATE 9

Write ( Auto-

Precharge

Disabled)

ANY

Idle

Row Active

Read ( Auto-

Precharge

Disabled)

NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after tXSR has been met (if the previous

state was self refresh).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed

to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are

in progress.

Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been

terminated.

Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been

terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or

allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the

other bank are determined by its current state and Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met,

the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the

bank will be in the row active state.

Read w/Auto-

Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when

tRP has been met. Once tRP is met, the bank will be in the idle state.

Write w/Auto-

Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when

tRP has been met. Once tRP is met, the bank will be in the idle state.

TRUTH TABLE 3 - CURRENT STATE BANK n - COMMAND TO BANK n

(Notes 1 to 6; notes appear below and on next page)

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

27

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.

Once tRC is met, the SDRAM will be in the all banks idle state.

Accessing Mode

Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD

has been met. Once tMRD is met, the SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.

Once tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank..

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and

READs or WRITEs with AUTO PRECHARGE disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

28

CURRENT STATE CS\ RAS\ CAS\ WE\ NOTES

HXXX

LHHH

Idle X X X X

LLHH

LHLH 7

LHLL 7

LLHL

LLHH

L H L H 7, 10

L H L L 7, 11

LLHL 9

LLHH

LH L H 7, 1

LH L L 7, 13

LLHL 9

LLHH

LH L H 7, 8 ,14

L H L L 7, 8 15

LLHL 9

LLHH

L H L H 7, 8 16

L H L L 7, 8 17

LLHL 9

Row Activating,

Active or

Precharging

Any command otherwise allowed to bank m

ACTIVE (select and activate row)

READ (select column and start READ burst)

Write

(Auto-

Precharge Disabled)

COMMAND/ACTION

COMMAND INHIBIT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

WRITE (select column and start WRITE burst)

PRECHARGE

READ (select column and start READ burst)

Any

Read

(Auto-

Precharge Disabled)

ACTIVE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

Read

(with Auto-

Precharge)

Write

(with Auto-

Precharge)

WRITE (select column and start new WRITE burst)

PRECHARGE

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE

ACTIVE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state

was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are

covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/ accesses and no register

accesses are in progress.

Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been

terminated.

Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been

terminated.

Read w/Auto-

Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled, and ends when tRP has

been met. Once tRP is met, the bank will be in the idle state.

Write w/Auto-

Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled, and ends when tRP has

been met. Once tRP is met, the bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE

enabled and READs or WRITEs with AUTO PRECHARGE disabled.

TRUTH TABLE 4 - CURRENT STATE BANK n - COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

29

NOTE (continued):

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted

by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m

will interrupt the READ on bank n, CAS latency later (Figure 7).

11. For a READ without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank

m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE

command to prevent bus contention.

12. For a WRITE without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m

will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE

to bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank

m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

14. For a READ with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will

interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered

(Figure 24).

15. For a READ with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m

will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus

contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

16. For a WRITE with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m

will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will

begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in

registered one clock prior to the READ to bank m (Figure 26).

17. For a WRITE with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m

will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when

the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m

(Figure 27).

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

30

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD/VDDQ Supply

Relative to VSS ........................................ -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to VSS ........................................ -1V to +4.6V

Operating Temperature, TA (ambient)........-55°C to +125°C

Storage Temperature (plastic) ................-55°C to +150°C

Power Dissipation ................................................. 1W

*Stresses greater than those listed as “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of this

specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage V

DD

/V

DD

Q3 3.6 V

Input High (Logic 1) Voltage, all inputs V

IH

2.2 V

DD

+0.3 V23

Input Low (Logic 0) Voltage, all inputs V

IL

-0.5 0.7 V 23

INPUT LEAKAGE CURRENT

Any input 0V<V

IN

<V

DD

(All other pins not under test = 0V) I

I

-5 5 µΑ

OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V<V

OUT

<V

DD

Q) I

OZ

-5 5 µΑ

V

OH

2.4 -- V

V

OL

-- 0.4 V

OUTPUT LEVELS

Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 6) (-55° ≤ Τ ≤ Τ

≤ Τ ≤ Τ

≤ ΤΑ Α

Α Α

Α ≤ ≤

≤ ≤

≤ +125 °C ; VDD/VDDQ =+3.3 V +0.3V)

IDD SPECIFICATIONS AND CONDITIONS1, 6, 11, 13 (-55°C<TA <+125 °C; VDD/VDDQ =+3.3 V +0.3V)

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SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

31

SYMBOL MAX

UNITS

NOTES

C

I1

4.0 pF 2

C

I2

5.0 pF 2

C

IO

6.5 pF 2

PARAMETER

Input Capacitance: CLK

Input Capacitance: All other input-only pins

Input/Output Capacitance: DQs

MIN MAX MIN MAX

CL = 3 tAC 6.5 7 ns

CL = 2 tAC 99ns22

Address hold time tAH 11ns

Address setup time tAS 23ns

CLK high-level width tCH 3 3.5 ns

CLK low-level width tCL 3 3.5 ns

CL = 3 tCK 810ns24

CL = 2 tCK 12 15 ns 22, 24

CKE hold time tCKH 11ns

CKE setup time tCKS 23ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 11ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 23ns

Data-in hold time tDH 11ns

Data-in setup time tDS 23ns

CL = 3 tHZ 68ns10

CL = 2 tHZ 710ns10

Data-out low-impedance time tLZ 11ns

Data-out hold time tOH 2.5 2.5 ns

ACTIVE to PRECHARGE command tRAS 50 80,000 60 80,000 ns

AUTO REFRESH, ACTIVE command period tRC 80 90 ns 22

ACTIVE to READ or WRITE delay tRCD 20 30 ns 22

Refresh period (4,096 rows) -40 to +85 degrees C tREF 64 64 ms

Refresh period (4,096 rows) -55 to +125 degrees C tREF 16 16 ms

PRECHARGE command period tRP 24 30 ns 22

ACTIVE bank A to ACTIVE bank B command tRRD 20 20 ns

Transition time tT0.3 1.2 1 1.2 ns 7

1 CLK + 1 CLK + - 25

8ns 8ns

15 15 ns 26

Exit SELF REFRESH to ACTIVE command tXSR 80 90 ns 20

Clock cycle time

Data-out high-impedance time

WRITE recovery time A2 version

NOTESPARAMETER SYM

Access time from CLK (pos. edge)

-8 -10 UNITS

tWR

CAPACITANCE

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 5, 6, 8, 9, 11) (-55oC<TA<+125oC)

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

32

SYMBOL

-8

-10 UNITS NOTES

t

CCD

11

t

CK

17

t

CKED

11

t

CK

14

t

PED

11

t

CK

14

t

DQD

00

t

CK

17

t

DQM

00

t

CK

17

t

DQZ

22

t

CK

17

t

DWD

00

t

CK

17

Data-in to ACTIVE command A2 version t

DAL

54

t

CK

15, 21

Data-in to PRECHARGE command A1 version A2 version t

DPL

22

t

CK

16, 21

t

BDL

11

t

CK

17

t

CDL

11

t

CK

17

Last data-in to PRECHARGE command A2 version t

RDL

22

t

CK

16, 21

t

MRD

22

t

CK

27

CL = 3 t

ROH

33

t

CK

17

CL = 2 t

ROH

22

t

CK

17

Data-out to high-impedance from PRECHARGE command

Last data-in to burst STOP command

Last data-in to new READ/WRITE command

LOAD MODE REGISTER command to ACTIVE or REFRESH command

CKE to clock enable or power-down exit setup mode

CKE to clock disable or power-down entry mode

READ/WRITE command to READ/WRITE command

PARAMETER

WRITE command to input data delay

DQM to data high-impedance during READs

DQM to data mask during WRITEs

DQM to input data delay

MIN MAX

CL = 3 t

AC

--- 6 ns 22

CL = 2 t

AC

--- 9 ns 22

CL = 3 t

CK

8 --- ns 22

CL = 2 t

CK

12 --- ns 22

t

RCD

20 --- ns 22

t

RP

24 --- ns 22

t

RCD

80 --- t

CK

21

WRITE recovery time A2 Version t

WR

2 --- --- ---

CLKs ---

PARAMETER

3-2-3

-8

SYM UNITS NOTES

PRECHARGE command period

AUTO REFRESH, ACTIVE command period

100 MHz Speed Reference (CL -t

RCD

-t

RP

)

Clock cycle time

Access times from CLK (pos. edge)

ACTIVE to READ or WRITE delay

AC FUNCTIONAL CHARACTERISTICS5, 6, 7, 8, 9, 11

(-55oC<TA<+125oC)

ELECTRICAL TIMING CHARACTERISTICS for -8 SPEED5, 6, 7, 8, 9, 11, 24

(-55oC<TA<+125oC)

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

33

NOTES

1 . All voltages referenced to VSS.

2 . This parameter is sampled. VDD, VDDQ = +3.3V ; f = 1

MHz, TA = 25°C; pin under test biased at 1.4V.

3. IDD is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle time

and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate

cycle time at which proper operation over the full

temperature range (-55°C ≤ TA ≤ +125°C) is ensured.

6 . An initial pause of 100µs is required after power-up,

followed by two AUTO REFRESH commands, before

proper device operation is ensured. (VDD and VDDQ must

be powered up simultaneously . VSS and VSSQ must be at

same potential.) The two AUTO REFRESH command

wake-ups should be repeated any time the tREF refresh

requirement is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specification,

the clock and CKE must transit between VIH and VIL (or

between VIL and VIH) in a monotonic manner .

9 . Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves the

open circuit condition; it is not a reference to VOH or

VOL. The last valid data element will meet tOH before

going High-Z.

1 1 . AC timing and ICC tests have VIL = 0V and VIH = 3V, with

timing referenced to 1.5V crossover point.

12 . Other input signals are allowed to transition no more

than once in any 30ns period (20ns on -8) and are

otherwise at valid VIH or VIL levels.

13. IDD specifications are tested after the device is properly

initialized.

1 4. Timing actually specified by tCKS; clock(s) specified as a

reference only at minimum cycle rate.

15 . Timing actually specified by tWR plus tRP; clock(s)

specified as a reference only at minimum cycle rate.

1 6 . Timing actually specified by tWR.

1 7 . Required clocks are specified by JEDEC functionality

and are not dependent on any timing parameter.

18 . The ICC current will decrease as the CAS latency is

reduced. This is due to the fact that the maximum cycle

rate is slower as the CAS latency is reduced.

19. Address transitions average one transition every 30ns

(20ns on -8).

2 0 . CLK must be toggled a minimum of two times during this

period.

2 1 . Based on tCK = 100 MHz for -8 and 66 MHz for -10.

22. These five parameters vary between speed grades and

define the differences between the -8 SDRAM speeds:

-8.

23. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse

width ≤ 10ns, and the pulse width cannot be greater than

one third of the cycle rate. VIL undershoot: VIL (MIN) =

-2V for a pulse width ≤ 10ns, and the pulse width cannot

be greater than one third of the cycle rate.

24. The clock frequency must remain constant during access

or precharge states (READ, WRITE, including tWR, and

PRECHARGE commands). CKE may be used to reduce

the data rate.

25. Auto precharge mode only. The precharge timing budget

( tRP) begins 8ns after the first clock delay, after the last

WRITE is executed.

2 6 . Precharge mode only .

2 7. JEDEC and PC100 specify three clocks.

Q

50pF

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

34

TIMING PARAMETERS

* CAS latency indicated in parentheses.

NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.

2 . If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care”.

3 . JEDEC and PC100 specify three clocks.

4. Outputs are guaranteed High-Z after command is issued.

MIN MAX MIN MAX

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK (3)

810ns

t

CK (2)

12 15 ns

t

CKH

11ns

SYMBOL* UNITS

-8 -10

MIN MAX MIN MAX

t

CKS

2 3 ns

t

CMH

1 1 ns

t

CMS

2 3 ns

t

MRD (3)

2 2

t

CK

t

RC

80 90 ns

t

RP

24 30 ns

SYMBOL* UNITS

-8 -10

INITIALIZE AND LOAD MODE REGISTER2

12345

tCK tCH

tCL

T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3

12

1234

1

23

4

1

23

4

1234

123

12345

1

234

5

1

234

5

12345

1

tCKS tCKH

12

1234

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1234

123

12345

123

1

2

3

1

2

3

123

1

NOP

tCMH tCMS

123

PRECHARGE

123

NOP NOP

AUTO

REFRESH

123

AUTO

REFRESH

123

NOP NOP

123

LOAD MODE

REGISTER

123

NOP

123

ACTIVE

123

tCMH tCMS tCMH tCMS

123456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456789

0

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456789

0

123456789012345678901234567890121234567890123456789012345678901212345678901234567890

12345

12345678901234567890123456789012123456789012345678901

1

234567890123456789012345678901212345678901234567890

1

234567890123456789012345678901212345678901234567890

1

12345678901234567890123456789012123456789012345678901

12

CODE ROW

12345

1234

1

23

4

1

23

4

1234

1

12345

1234

1

23

4

1

23

4

1234

12

12345

12345678901

1

234567890

1

234567890

1

234567890

1

12345678901

12

ALL BANKS

SINGLE BANK

12345

123456789012345678901234567890121

1

2345678901234567890123456789012

1

2345678901234567890123456789012

1

2345678901234567890123456789012

1

123456789012345678901234567890121

12

tAS tAH

CODE

tAS tAH

12

ROW

12345

1234

1

23

4

1

23

4

1

23

4

1234

1

12345

1234

1

23

4

1

23

4

1

23

4

1234

12

12345

1234

12345678901

1

234567890

1

234567890

1

234567890

1

12345678901

12

12345

123456789012345678901234567890121234567890123456

1

2345678901234567890123456789012123456789012345

6

1

2345678901234567890123456789012123456789012345

6

1

2345678901234567890123456789012123456789012345

6

123456789012345678901234567890121234567890123456

12

1

ALL

BANKS BANK

12345

1234

1

23

4

1

23

4

1

23

4

1234

12

High-Z

T=100s tRP tRC tMRD

Power-up:

VDD and

CLK stable

Precharge

all banks AUTO REFRESH AUTO REFRESH

tRC

Program Mode Register 1,3,4

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9, A11

A10

BA0, BA1

DQ

12

1234

1

23

4

1

23

4

1234

12

1234

1

23

4

1234

1

23

4

1

23

4

1234

Don’t Care

Undefined

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

35

TIMING P ARAMETERS

* CAS latency indicated in parentheses.

NOTE: 1. Violating refresh requirements during power-down

may result in a loss of data.

1234567890123

1

23456789012

3

1

23456789012

3

1

23456789012

3

1

23456789012

3

1

23456789012

3

tCK tCL tCH

T 0 T1 T 2 Tn +1 Tn +2

123

1

2

3

1

2

3

123

12

123

12

1234

1

23

4

1

23

4

1234

123

12

tCKS tCKH

12345

tCK tCK

12

1234

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1234

123

12

123

12345

123

PRECHARGE NOP

123456

12345

123456789012345678901234567

1

2345678901234567890123456

7

1

2345678901234567890123456

7

1

2345678901234567890123456

7

123456789012345678901234567

12

123

NOP ACTIVE

123

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901

1

23456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901

ROW

12345

1234567890123456789012345678901212345678901234567890123456789012123456

1

23456789012345678901234567890121234567890123456789012345678901212345

6

1

23456789012345678901234567890121234567890123456789012345678901212345

6

1234567890123456789012345678901212345678901234567890123456789012123456

12

123456

123

1

2

3

1

2

3

123

1

12345

ALL BANKS

SINGLE BANK

123456

1234567890123456789012345678901212345678901234567890123456

1

23456789012345678901234567890121234567890123456789012345

6

1

23456789012345678901234567890121234567890123456789012345

6

1234567890123456789012345678901212345678901234567890123456

12

ROW

123456

123

1

2

3

1

2

3

123

1

12345

123456

1234567890123456789012345678901212345678901234567890123456

1

23456789012345678901234567890121234567890123456789012345

6

1

23456789012345678901234567890121234567890123456789012345

6

1234567890123456789012345678901212345678901234567890123456

12

BANK

123456

123

1

2

3

1

2

3

123

1

BANK(S)

tCMS tCMH

NOP

tAS tAH

High-Z

All banks idle

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9, A11

A10

BA0, BA1

DQ

123

1

2

3

123

1234

1

23

4

1

23

4

1234

Don’t Care

Undefined

POWER-DOWN MODE1

Two clock cycles Input bufferd gated off while in

power-down mode

Exit power-down mode

All banks idle, enter

power-down mode

Precharge all

active banks

MIN MAX MIN MAX

t

CK (2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

t

CMH

11ns

t

CMS

23ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK (3)

810ns

UNITSSYMBOL* -8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

36

tCK tCH

tCL

T0 T1 T2 T4 T6 T7 T8 T9T3 T5

12

1

23

4

1

23

4

1

23

4

1234

12

1234

1

23

4

1

23

4

1234

12

12345

123456

tCKS tCKH

12

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1234

12

123

12345

123456

12

1234

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1234

12

123

12345

123

12345

123456

READ NOP

12345

1

234

5

1

234

5

12345

12

tCMS tCMH

tt

CKS CKH

NOP

123

NOP NOP

123

NOP WRITE

123456

12345

1234567

1

23456

7

1

23456

7

1234567

1

12345

NOP

COMMAND

12345

1234567890

1

23456789

0

1

23456789

0

1234567890

12

123

12

1234

1

23

4

1

23

4

1234

123

12

tCMS tCMH

123

1234567890123456789012345678901212345

1

23456789012345678901234567890121234

5

1

23456789012345678901234567890121234

5

1234567890123456789012345678901212345

12

123

12

1234567890123

1

23456789012

3

1

23456789012

3

1234567890123

12

1234

1

23

4

1

23

4

1234

12

12345

COLUMN m2

tAS tAH

12345

123456789012345678901234567890121234567890123456

1

2345678901234567890123456789012123456789012345

6

1

2345678901234567890123456789012123456789012345

6

1

2345678901234567890123456789012123456789012345

6

123456789012345678901234567890121234567890123456

1

12

COLUMN e2

12345

123456789012345678

1

2345678901234567

8

1

2345678901234567

8

1

2345678901234567

8

123456789012345678

1

12

1

2

1

2

1

2

12

1234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789

0

1

23456789012345678901234567890121234567890123456789

0

1

23456789012345678901234567890121234567890123456789

0

1234567890123456789012345678901212345678901234567890

123

12

123456789012345678901

1

2345678901234567890

1

2345678901234567890

1

2345678901234567890

1

123456789012345678901

12

tAS tAH

12

12345

BANK

tAS tAH

12345

123456789012345678901234567890121234567890123456

1

2345678901234567890123456789012123456789012345

6

1

2345678901234567890123456789012123456789012345

6

123456789012345678901234567890121234567890123456

1

12

BANK

12345

123456789012345678

1

2345678901234567

8

1

2345678901234567

8

123456789012345678

1

1234567

12345

1

234

5

1

234

5

1

234

5

12345

12

1

DOUT m

1234567

1234

1

23

4

1

23

4

1

23

4

1234

12

DOUTm+1

12345

1234

1

23

4

1

23

4

1234

1

12

DOUT a DOUT a-1

123456

12345

1234567

1

23456

7

1

23456

7

1234567

12

1

12345

tDS tDH

tHZ

tAC

tOH

tAC

tLZ

CLK

CKE

DQM /

DQML,

DQMH

A0-A9,

A11

A10

BA0,

BA1

DQ

CLOCK SUSPEND MODE1

1234

1

23

4

1234

1

23

4

1

23

4

1234

Don’t Care

Undefined

TIMING P ARAMETERS

* CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.

2. x16: A8, A9 and A11 = “Don’t Care.”

MIN MAX MIN MAX

t

AC(3)

6.5 7 ns

t

AC(2)

99ns

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

SYMBOL* UNITS

-8 -10 MIN MAX MIN MAX

t

CKS

23ns

t

CMH

11ns

t

CMS

23ns

t

DH

11ns

t

DS

23ns

t

HZ(3)

68ns

t

HZ(2)

710ns

t

LZ

11ns

t

OH

2.5 2.5 ns

SYMBOL* UNITS

-8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

37

tCK tCL

tCH

T0 T1 T2 Tn +1 To +1

12

123

1

2

3

1

2

3

123

12

1234

1

23

4

1

23

4

1234

123

tCKS tCKH

123

12

1234

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1234

123

12345

123

PRECHARGE NOP

12

123

ACTIVE

123

123456789012345678901234567890121234567890123456789012345678901212345678901234567

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456

7

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456

7

123456789012345678901234567890121234567890123456789012345678901212345678901234567

ROW

12345

1234567890123456789012345678901212345678901234567890123456789012

1

23456789012345678901234567890121234567890123456789012345678901

2

1

23456789012345678901234567890121234567890123456789012345678901

2

1234567890123456789012345678901212345678901234567890123456789012

12

123456

12345

ALL BANKS

SINGLE BANK

123456

1234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789

0

1

23456789012345678901234567890121234567890123456789

0

1234567890123456789012345678901212345678901234567890

12

ROW

123456

1234

1

23

4

1

23

4

1234

1

12345

123456

1234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789

0

1

23456789012345678901234567890121234567890123456789

0

1234567890123456789012345678901212345678901234567890

12

BANK

123456

12345

1

234

5

1

234

5

12345

1

BANK(S)

tCMS tCMH

AUTO

REFRESH

tAS tAH

High-Z

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9,

A11

A10

BA0, BA1

DQ

12

123

1234

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1234

12

123

12

123

1234

1

23

4

1

23

4

1234

12

123

NOP NOP

123

AUTO

REFRESH

12

NOP NOP

1234

1

23

4

1

23

4

1234

12

tRP tRC tRC

1

2

3

1

2

3

123

12345

1

234

5

1

234

5

12345

Don’t Care

Undefined

AUTO REFRESH MODE1

TIMING PARAMETERS

* CAS latency indicated in parentheses.

MIN MAX MIN MAX

t

AH

1 1 ns

t

AS

2 3 ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK (3)

8 10 ns

t

CK (2)

12 15 ns

SYMBOL* UNITS

-10-8

MIN MAX MIN MAX

t

CKH

11ns

t

CKS

23ns

t

CMH

11ns

t

CMS

23ns

t

RC

80 90 ns

t

RP

24 30 ns

SYMBOL* UNITS

-10-8

NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

38

TIMING PARAMETERS

* CAS latency indicated in parentheseses.

1234567890123

1

23456789012

3

1

23456789012

3

1

23456789012

3

1

23456789012

3

1

23456789012

3

1234567890123

tCK tCL

tCH

TTT TT

12

123

1

2

3

1

2

3

1

2

3

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

tCKS tCKH

123456

tCKS

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12345

123

PRECHARGE NOP

12345

123456

123456789012345

1

2345678901234

5

1

2345678901234

5

123456789012345

1

12

123

NOP AUTO

REFRESH

123

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678901

2

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678901

2

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678901

2

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678901

2

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678901

2

1

234567890123456789012345678901212345678901234567890123456789012123456789012345678901

2

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012

12345

ALL BANKS

SINGLE BANK

12345

12345678901234567890123456789012123456789012345678901234567890121234567890

1

234567890123456789012345678901212345678901234567890123456789012123456789

0

1

234567890123456789012345678901212345678901234567890123456789012123456789

0

12345678901234567890123456789012123456789012345678901234567890121234567890

1

12345

12345678901234567890123456789012123456789012345678901234567890121234567890

1

234567890123456789012345678901212345678901234567890123456789012123456789

0

1

234567890123456789012345678901212345678901234567890123456789012123456789

0

1

234567890123456789012345678901212345678901234567890123456789012123456789

0

12345678901234567890123456789012123456789012345678901234567890121234567890

1

BANK(S)

tCMS tCMH

AUTO

REFRESH

tAS tAH

High-Z

Exit self refresh mode

(Restart refresh time base)

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9, A11

A10

BA0, BA1

DQ

SELF REFRESH MODE1

tRAS

RP

tXSR

t

CLK stable prior to exiting

self refresh mode

Enter self refresh mode

Precharge all

active banks

1234

1

23

4

1234

1

23

4

1

23

4

1234

Don’t Care

Undefined

T

MIN MAX MIN MAX

t

AH

11ns

t

AS

23ns

t

CH

34ns

t

CL

34ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

SYMBOL* UNITS

-8 -10

MIN MAX MIN MAX

tCKS 23ns

tCMH 11ns

tCMS 23ns

tRAS 50 80,000 60 80,000 ns

tRP 24 30 ns

tXSR 80 90 ns

SYMBOL* UNITS

-8 -10

NO TE: 1. Self Refresh Mode available on Industrial T emperature Range option only .

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

39

TIMING PARAMETERS

* CAS latency indicated in parentheseses.

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A8, A9 and A11 = “Don’t Care.”

READ -- WITHOUT A UT O PRECHARGE1

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

CLK tCK tCH

tCL

123456

12

12345

1

234

5

1

234

5

1

234

5

12345

123

12

12345

1

234

5

1

234

5

1

234

5

12345

123

12

12345

1

234

5

1

234

5

1

234

5

12345

123

CKE

tCKS tCKH

tCMS tCMH

1234

COMMAND

123

12

123

1234567

ACTIVE NOP READ NOP NOP NOP PRECHARGE NOP

1234567890123456789

12345

1

234

5

1

234

5

1

234

5

12345

1

234

5

1

234

5

1

234

5

12345

CMH

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

DQM /

DQML, DQMH

123

123456789012345678901234567890

1

2345678901234567890123456789

0

1

2345678901234567890123456789

0

1

2345678901234567890123456789

0

123456789012345678901234567890

1234

A0-A9,

A11

123456

1234567

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

ROW

123456

12345

1

234

5

1

234

5

1

234

5

12345

tCMS t

AH

tAS t

ROW

AH

tAS t

12345

1234567890123456789

1

23456789012345678

9

1

23456789012345678

9

1

23456789012345678

9

1234567890123456789

1234

BA0, BA1

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

BANK

1234567

AH

tAS t

BANK

DQ

12345678

1234

DOUT m

tAC

tLZ

tAC

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

ACTIVE

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

COLUMN m2

1

1234567

123456

12345678901234567890123456789012

1

234567890123456789012345678901

2

1

234567890123456789012345678901

2

1

234567890123456789012345678901

2

12345678901234567890123456789012

1234

1234567

ROW

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

1

123

1234

1234567

12345678901234567890

1

234567890123456789

0

1

234567890123456789

0

12345678901234567890

1234567

123456

12345

1

234

5

1

234

5

1

234

5

12345

123456

12345

1

234

5

1

234

5

1

234

5

12345

ROW

ALL BANKS

SINGLE BANK

DISABLE AUTO PRECHARGE

1234567

12345678901234567

1

234567890123456

7

1

234567890123456

7

1

234567890123456

7

12345678901234567

1234567

123456

12345

1

234

5

1

234

5

1

234

5

12345

123456

12345

1

234

5

1

234

5

1

234

5

12345

BANK

123

DOUT m+1

123

tOH

DOUT m+2 DOUT m+3

12

tRP

tRC

tRAS

tRCD CAS Latency

A10

tAC

tOH

tAC

tOH tOH

tHZ

1234

1

23

4

1234

12345

1

234

5

1

234

5

1

234

5

12345

Don’t Care

Undefined

T0 T1 T2 T3 T4 T5 T6 T7 T8

MIN MAX MIN MAX

t

AC(3)

6.5 7 ns

t

AC(2)

99ns

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

UNITSSYMBOL* -8 -10 MIN MAX MIN MAX

t

CMH

11ns

t

CMS

23ns

t

HZ(3)

68ns

t

HZ(2)

710ns

t

LZ

11ns

t

OH

2.5 2.5 ns

t

RAS

50 80,000 60 80,000 ns

t

RC

80 90 ns

t

RCD

20 30 ns

t

RP

24 30 ns

UNITSSYMBOL* -8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

40

123456

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

tCK tCH

tCL

123456

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

tCKS tCKH

tCMS tCMH

123

12

123

123456

ACTIVE NOP READ NOP NOP NOP NOP

1234567890123456789

12345678

1

234567

8

1

234567

8

1

234567

8

1

234567

8

1

234567

8

12345678

123456

1

2345

6

1

2345

6

1

2345

6

123456

CMH

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

123456789012345678901234567890

1

2345678901234567890123456789

0

1

2345678901234567890123456789

0

1

2345678901234567890123456789

0

123456789012345678901234567890

123

123456

12345678

1

234567

8

1

234567

8

12345678

ROW

1234567

12345

1

234

5

1

234

5

12345

tCMS t

AH

tAS t

ROW

AH

tAS t

123

123456

12345678

1

234567

8

1

234567

8

12345678

BANK

1234567

AH

tAS t

BANK

12

12345

1

234

5

1

234

5

1

234

5

12345

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

ACTIVE

123

12

12345

1

234

5

1

234

5

1

234

5

12345

123

COLUMN m2

1

123456

12345678901234567890123456789012

1

234567890123456789012345678901

2

1

234567890123456789012345678901

2

12345678901234567890123456789012

123

123456

ROW

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

12

123456

12345

1

234

5

1

234

5

1

234

5

12345

ROW

ENABLE AUTO PRECHARGE

1234567890123456789012345678901212

1

23456789012345678901234567890121

2

1

23456789012345678901234567890121

2

1

23456789012345678901234567890121

2

1234567890123456789012345678901212

1234567

12345

1

234

5

1

234

5

1

234

5

12345

BANK

READ -- WITH A UT O PRECHARGE1

123

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123456

1

12345678901234567890123456789012123456

1

234567890123456789012345678901212345

6

1

234567890123456789012345678901212345

6

1

234567890123456789012345678901212345

6

12345678901234567890123456789012123456

12

T0 T1 T2 T3 T4 T5 T6 T7 T8

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

NOP

12345678

1234

DOUT m

tAC

tLZ

AC

123

DOUT m+1

1234

tOH

DOUT m+2 DOUT m+3

12

tRP

tRC

tRAS

tRCD CAS Latency

AC

tOH AC

tOH tOH

tHZ

t

CLK

CKE

COMMAND

DQM /

DQML, DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

123

1

2

3

1

2

3

123

12345

1

234

5

1

234

5

12345

Don’t Care

Undefined

TIMING P ARAMETERS

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2.

2. x16: A8, A9 and A11 = “Don’t Care.”

* CAS latency indicated in parentheseses.

MIN MAX MIN MAX

t

AC(3)

6.5 7 ns

t

AC(2)

99ns

t

AH

11ns

t

AS

23ns

t

CH

33.5ns

t

CL

33.5ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

AC(3)

6.5 7 ns

t

AC(2)

99ns

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

CMH

11ns

t

CMS

23ns

t

HZ(3)

68ns

t

HZ(2)

710ns

t

LZ

11ns

t

OH

2.5 2.5 ns

t

RAS

50 80,000 60 80,000 ns

t

RC

80 90 ns

t

RCD

20 30 ns

t

RP

24 30 ns

UNITSSYMBOL* -8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

41

TIMING P ARAMETERS

* CAS latency indicated in parentheseses.

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2.

2 . x16: A8, A9 and A11 = “Don’t Care.”

AL TERNATING BANK READ ACCESSES1

12345

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

tCK tCH

tCL

123456

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

tCKS tCKH

tCMS tCMH

123

12

123

123456

ACTIVE NOP READ NOP ACTIVE NOP NOP

123456789012345678

12345

1

234

5

1

234

5

1

234

5

12345

1

234

5

1

234

5

1

234

5

12345

CMH

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1234567

12345

1

234

5

1

234

5

1

234

5

12345

ROW

123456

12345

1

234

5

1

234

5

1

234

5

12345

tCMS t

AH

tAS t

ROW

AH

tAS t

AH

tAS t

12345678

123

DOUT m

tAC

tLZ

tAC

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

COLUMN m2

123

123456

ROW

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

12

123456

12345

1

234

5

1

234

5

1

234

5

12345

ROW

ENABLE AUTO PRECHARGE

123

DOUT m+1

AC

t

1234

tOH

tAC tOH

tOH

DOUT m+2 DOUT m+3

tRP - BANK 0

tRRD

tRC - BANK 0

tRCD - BANK 0 CAS Latency - BANK 0

12

123

1234

1

23

4

1

23

4

1

23

4

1234

123

12

READ

1234567

12

tRAS - BANK 0

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123456

12345

1

234

5

1

234

5

1

234

5

12345

ROW

123456

12345

1

234

5

1

234

5

1

234

5

12345

COLUMN b2

123456

12345

1

234

5

1

234

5

1

234

5

12345

123456

ROW

12345

1

234

5

1

234

5

1

234

5

12345

1234567

1

23456

7

1

23456

7

1

23456

7

1

23456

7

1

23456

7

1234567

12345

123456

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

12

ENABLE AUTO PRECHARGE

12345678

12

123456

1234

1

23

4

1

23

4

1

23

4

1234

12345

1234

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

123

1234

12345678901234

1234

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

1234

1234567890123

123

12345

1

2345

1

2345

1

2345

12345

1234

123

DOUT b

1234

tAC tOH

tAC

T0 T1 T2 T3 T4 T5 T6 T7 T8

12

12345

1

234

5

1

234

5

1

234

5

12345

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

ACTIVE

BANK 0 BANK 0 BANK 0

BANK 4

CAS Latency - BANK 1

RCD - BANK 1

tRCD - BANK 0

CLK

CKE

COMMAND

DQM /

DQML, DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

123

1

2

3

1

2

3

123

1234

1

23

4

1

23

4

1

23

4

1234

Don’t Care

Undefined

MIN MAX MIN MAX

t

AC(3)

6.5 7 ns

t

AC(2)

99ns

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

CMH

11ns

t

CMS

23ns

t

LZ

11ns

t

OH

2.5 2.5 ns

t

RAS

50 80,000 60 80,000 ns

t

RC

80 90 ns

t

RCD

20 30 ns

t

RP

24 30 ns

t

RRD

20 20 ns

UNITSSYMBOL* -8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

42

TIMING P ARAMETERS

* CAS latency indicated in parentheseses.

NOTE: 1. For this example, the CAS latency = 2.

2. x16: A8, A9 and A11 = “Don’t Care.”

3. Page left open, no tRP.

MIN MAX MIN MAX

t

AC(3)

6.5 7 ns

t

AC(2)

99ns

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

CMH

11ns

t

CMS

23ns

t

HZ(3)

68ns

t

HZ(2)

710ns

t

LZ

11ns

t

OH

2.5 2.5 ns

t

RCD

20 30 ns

UNITSSYMBOL* -8 -10

READ -- FULL-PA GE BURST1

12

123

1

2

3

1

2

3

123

12

tCK

tCH

tCL

12345

123

12

1234

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1234

12

123

tCKS tCKH

tCMS tCMH

123

12

123

12

ACTIVE NOP READ NOP NOP NOP NOP

12345678901234567

123456

12345

6

12345

6

12345

6

12345

6

12345

6

123456

12345

1

234

5

1

234

5

1

234

5

12345

CMH

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1234567890123

1

23456789012

3

1

23456789012

3

1234567890123

1234

123

123456

12345

1234567

1

23456

7

1

23456

7

1234567

ROW

tCMS t

AH

tAS t

AH

tAS t

123

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

BANK

123456

AH

tAS t

BANK

12345678

123

DOUT m

tAC

tLZ

tAC

12

1234

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1234

12

123

BURST

TERM

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

COLUMN

m2

1

123456

12345678901234567890123456789012123456789012345678901

1

234567890123456789012345678901212345678901234567890

1

234567890123456789012345678901212345678901234567890

1

12345678901234567890123456789012123456789012345678901

123

123456

ROW

1234567890123456789012345678901212345678901234567890123456789012123456

123456789012345678901234567890121234567890123456789012345678901212345

6

123456789012345678901234567890121234567890123456789012345678901212345

6

123456789012345678901234567890121234567890123456789012345678901212345

6

1234567890123456789012345678901212345678901234567890123456789012123456

12

12345678901234567890123456789012123456789012345678901

1

234567890123456789012345678901212345678901234567890

1

234567890123456789012345678901212345678901234567890

1

234567890123456789012345678901212345678901234567890

1

12345678901234567890123456789012123456789012345678901

123

DOUT m+1

AC

t

123

tOH

tAC tOH

tOH

DOUTm+2 DOUT m-1

12

1

tHZ

tRCD CAS Latency

12

1234

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1234

12

123

NOP

12

123

NOP NOP

12

1234

1

23

4

1

23

4

1

23

4

1234

12

1234

1

23

4

1

23

4

1234

12

123

12

123

1234

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1234

123

12

123

DOUT m DOUT m+1

tOH

tAC tOH

tAC

256 (x16) locations within same row.

T0 T1 T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4

Full page completed.

Full-page burst does not self-terminate. 3

Can use BURST TERMINATE command.

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

123

1

2

3

123

12345

1

234

5

1

234

5

12345

Don’t Care

Undefined

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

43

TIMING PARAMETERS

* CAS latency indicated in parentheseses.

NOTE: 1. For this example, the burst length = 4 , the CAS latency = 2.

2. x16: A8, A9 and A11 = “Don’t Care.”

MIN MAX MIN MAX

t

AC(3)

6.5 7 ns

t

AC(2)

99ns

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

CMH

11ns

t

CMS

23ns

t

HZ(3)

68ns

t

HZ(2)

710ns

t

LZ

11ns

t

OH

2.5 2.5 ns

t

RCD

20 30 ns

UNITSSYMBOL* -8 -10

READ -- DQM OPERATION1

123456

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

tCK tCH

tCL

123456

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

tCKS tCKH

tCMS tCMH

123

12

123

12

123

123456

ACTIVE NOP READ NOP NOP NOP NOP

1234567890123456789

12345

1

234

5

1

234

5

1

234

5

12345

123456

1

2345

6

1

2345

6

1

2345

6

123456

CMH

1234

123456789012345678901234567890

1

2345678901234567890123456789

0

1

2345678901234567890123456789

0

1

2345678901234567890123456789

0

123456789012345678901234567890

1234

123

1234567

123456

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

ROW

tCMS t

AH

tAS t

AH

tAS t

123

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

BANK

123456

AH

tAS t

BANK

12345678

DOUT m

tAC

tLZ

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

12345

1

234

5

1

234

5

1

234

5

12345

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

12345

1

234

5

1

234

5

1

234

5

12345

123

NOP

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

COLUMN m2

12

1234567

12345678901234567890123456789012123456789012345678

1

234567890123456789012345678901212345678901234567

8

1

234567890123456789012345678901212345678901234567

8

1

234567890123456789012345678901212345678901234567

8

12345678901234567890123456789012123456789012345678

123

1234567

ROW

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

1

ENABLE AUTO PRECHARGE

AC

t

1234

tOH

tAC tOH

tOH

DOUT m+2 DOUT m+3

tHZ

tRCD CAS Latency

NOP

12

1234567890123456789012345678901212345678901234567

1

23456789012345678901234567890121234567890123456

7

1

23456789012345678901234567890121234567890123456

7

1

23456789012345678901234567890121234567890123456

7

1234567890123456789012345678901212345678901234567

1

12

12345

1

234

5

1

234

5

1

234

5

12345

123

123456

123456789

tLZ

DISABLE AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8

12

tHZ

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

123

1

2

3

123

1234

1

23

4

1

23

4

1

23

4

1234

Don’t Care

Undefined

12345678901234567890123456789012123456789012345678

1

234567890123456789012345678901212345678901234567

8

1

234567890123456789012345678901212345678901234567

8

12345678901234567890123456789012123456789012345678

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

44

WRITE -- WITHOUT A U T O PRECHARGE 1

12

1234

1

23

4

1

23

4

1

23

4

1234

123

tCK tCH

tCL

123456

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

tCKS tCKH

tCMS tCMH

1234

123

12

123456

ACTIVE NOP WRITE NOP NOP NOP PRECHARGE NOP

1234567890123456789

12345

1

234

5

1

234

5

1

234

5

12345

1

234

5

1

234

5

1

234

5

12345

CMH

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12345678901234567890123456789

1

234567890123456789012345678

9

1

234567890123456789012345678

9

1

234567890123456789012345678

9

12345678901234567890123456789

1234

123456

1234567

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

ROW

123456

12345

1

234

5

1

234

5

1

234

5

12345

tCMS t

AH

tAS t

ROW

AH

tAS t

12345

1234567890123456789

1

23456789012345678

9

1

23456789012345678

9

1

23456789012345678

9

1234567890123456789

1234

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

BANK

123456

AH

tAS t

BANK

12

DIN m+1

tDS

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

123

ACTIVE

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123

1234

1

23

4

1

23

4

1

23

4

1234

12

COLUMN

m2

1

123456

12345678901234567890123456789012

1

234567890123456789012345678901

2

1

234567890123456789012345678901

2

1

234567890123456789012345678901

2

12345678901234567890123456789012

123

123456

ROW

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

1

1234

123456

1234567890123456789

1

23456789012345678

9

1

23456789012345678

9

1

23456789012345678

9

1234567890123456789

1234567

123456

12345

1

234

5

1

234

5

1

234

5

12345

123456

12345

1

234

5

1

234

5

1

234

5

12345

ROW

ALL BANKS

SINGLE BANK

DISABLE AUTO PRECHARGE

123456

12345678901234567

1

234567890123456

7

1

234567890123456

7

1

234567890123456

7

12345678901234567

1234567

123456

12345

1

234

5

1

234

5

1

234

5

12345

123456

12345

1

234

5

1

234

5

1

234

5

12345

BANK

123

DIN m+2

12345

DIN m+3

tWR tRP

tRC

tRAS

tRCD

123456

12345678901234567

1

234567890123456

7

1

234567890123456

7

1

234567890123456

7

12345678901234567

DIN m

123

tDH tDS tDH tDS tDH tDS tDH

123456789012345678901234567

1

2345678901234567890123456

7

1

2345678901234567890123456

7

1

2345678901234567890123456

7

123456789012345678901234567

12

1

T0 T1 T2 T3 T4 T5 T6 T7 T8

123

2

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

123

1

2

3

1

2

3

123

1234

1

23

4

1

23

4

1234

Don’t Care

Undefined

TIMING P ARAMETERS

* CAS latency indicated in parentheseses.

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 15ns are required between <DINm+3> and the PRECHARGE command, regardless of frequency.

3. x16: A8, A9 and A11 = “Don’t Care.”

MIN MAX MIN MAX

t

CMH

11ns

t

CMS

23ns

t

DH

11ns

t

DS

23ns

t

RAS

50 80,000 60 80,000 ns

t

RC

80 90 ns

t

RCD

20 30 ns

t

RP

24 30 ns

t

WR

15 15 ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

AC(3)

6.5 7 ns

t

AC(2)

99ns

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

UNITSSYMBOL* -8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

45

WRITE -- WITH AUT O PRECHARGE1

T0 T1 T2 T3 T4 T5 T6 T7 T8

12345

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

tCK tCH

tCL

123456

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

tCKS tCKH

tCMS tCMH

123

12

123

1234567

ACTIVE NOP WRITE NOP NOP NOP NOP NOP

123456789012345678

12345

1

234

5

1

234

5

12345

1

234

5

1

234

5

12345

CMH

12

123

1234

1

23

4

1

23

4

1234

12

123

12345678901234567890123456789012123

1

234567890123456789012345678901212

3

1

234567890123456789012345678901212

3

12345678901234567890123456789012123

1234

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

ROW

123456

tCMS t

AH

tAS t

ROW

AH

tAS t

1234567890123456789012345678901212345678901

1

23456789012345678901234567890121234567890

1

23456789012345678901234567890121234567890

1

1234567890123456789012345678901212345678901

1234

123456

1

2345

6

1

2345

6

1

2345

6

123456

BANK

AH

tAS t

BANK

12

DIN m+1

tDS

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

123

1

2

3

1

2

3

1

2

3

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

123

ACTIVE

12

1234

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1234

123

COLUMN

m2

1

123456

1234567890123456789012345678901212345678

1

23456789012345678901234567890121234567

8

1

23456789012345678901234567890121234567

8

1

23456789012345678901234567890121234567

8

1234567890123456789012345678901212345678

1234

123456

ROW

123456

ROW

ENABLE AUTO PRECHARGE

123456

BANK

123

DIN m+2

12345

DIN m+3

tWR tRP

tRC

tRAS

tRCD

123456

1234567890123456

1

23456789012345

6

1

23456789012345

6

1234567890123456

DIN m

12

tDH tDS tDH tDS tDH tDS tDH

12345678901234567890123456789012

1

234567890123456789012345678901

2

1

234567890123456789012345678901

2

12345678901234567890123456789012

1

12345

123456

123456789012345678901234567890121234567

1

2345678901234567890123456789012123456

7

1

2345678901234567890123456789012123456

7

1

2345678901234567890123456789012123456

7

123456789012345678901234567890121234567

12345

1234567

1

23456

7

1

23456

7

1234567

1

1234567890123456789012345678901212345678901

1

23456789012345678901234567890121234567890

1

23456789012345678901234567890121234567890

1

1234567890123456789012345678901212345678901

T9

123

12

123

1

2

3

1

2

3

1

2

3

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

NOP

12

2

123

1

2

3

123

1234

1

23

4

1

23

4

1234

Don’t Care

Undefined

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

TIMING PARAMETERS

* CAS latency indicated in parentheseses.

NOTE: 1. For this example, the burst length = 4, i.e., two-clock minimum for tWR.

2. x16: A8, A9 and A11 = “Don’t Care.”

MIN MAX MIN MAX

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

t

CMH

11ns

t

CMS

23ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

DH

11ns

t

DS

23ns

t

RAS

50 80,000 60 80,000 ns

t

RC

80 90 ns

t

RCD

20 30 ns

t

RP

24 30 ns

t

WR

1 CLK+

8ns 1 CLK+

8ns ns

UNITSSYMBOL* -8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

46

TIMING P ARAMETERS

* CAS latency indicated in parentheseses.

NOTES: 1. For this example, the burst length = 4, i.e., two-clock minimum for tWR.

2. Requires once clock plus time (8ns) with AUTO PRECHARGE or 15ns with PRECHARGE.

3. x16: A8, A9 and A11 = “Don’t Care.”

MIN MAX MIN MAX

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

t

CKS

23ns

t

CMH

11ns

t

CMS

23ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

DH

11ns

t

DS

22ns

t

RAS

50 80,000 60 80,000 ns

t

RC

80 90 ns

t

RCD

20 30 ns

t

RP

24 30 ns

t

RRD

20 20 ns

t

WR

1 CLK+

8ns

1 CLK+

8ns ns

UNITSSYMBOL* -8 -10

ALTERNA TING B ANK WRITE ACCESSES1

12345

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

tCK tCH

tCL

12345

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

tCKS tCKH

tCMS tCMH

123

12

123

12

123

12

1234567

ACTIVE NOP WRITE NOP ACTIVE NOP NOP

123456789012345678

1234

1

23

4

1

23

4

1

23

4

1234

123456

1

2345

6

1

2345

6

1

2345

6

123456

CMH

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

123456

1234

1

23

4

1

23

4

1

23

4

1234

ROW

123456

tCMS t

AH

tAS t

ROW

AH

tAS t

AH

tAS t

12

123

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

ACTIVE

12

COLUMN

m3

123

123456

ROW

1234567

1

23456

7

1

23456

7

1234567

12

123456

ROW

ENABLE AUTO PRECHARGE

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

WRITE

1234567

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1

2

3

1

2

3

1

2

3

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

123456

12345

1

234

5

1

234

5

12345

ROW

123456

1234

123

4

123

4

1234

COLUMN b3

123456

12345678901234

1

234567890123

4

1

234567890123

4

1

234567890123

4

123456

ROW

12345

1

234

5

1

234

5

12345

1

234

5

1

234

5

12345

123456

1234567

1

23456

7

1

23456

7

1234567

1

ENABLE AUTO PRECHARGE

12345678901234567

1

123456

12345

1

234

5

1

234

5

12345

1234

123

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

1234

123

12345678901234

1234

123

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

123

1234

12345678901234567890

1234

12345

1

234

5

1

234

5

1

234

5

12345

1234

BANK 0 BANK 0 BANK 0

BANK 1 BANK 1

123

DIN m+1

tDS

123

DIN m+2 DIN m+3

tWR - BANK 0 tRP - BANK 0

tRRD

tRC - BANK 0

tRCD - BANK 0

123456

12345678901234567

1

234567890123456

7

1

234567890123456

7

1

234567890123456

7

12345678901234567

DIN m

12

tDH tDS tDH tDS tDH tDS tDH

123

DIN b

DS DH

12

DIN b+1

DS DH

12

DIN b+2

DS DH

12

tttttt

tRAS - BANK 0

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1

23

4

1234

123

12

NOP

123

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

DIN b+3

DS DH

123

tt

tRCD - BANK 1 tWR - BANK 1

tRCD - BANK 0

1234

1

23

4

1234

12345

1

234

5

1

234

5

12345

Don’t Care

Undefined

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

47

WRITE -- FULL-PA GE BURST

123

1234

1

23

4

1

23

4

1

23

4

1

23

4

1234

123

12

tCK

tCH

tCL

123456

12

123

1234

1

23

4

1

23

4

1

23

4

1

23

4

1234

12

123

12

12345

1

234

5

1

234

5

1

234

5

1

234

5

12345

123

tCKS tCKH

tCMS tCMH

1234

123

12

123

ACTIVE NOP WRITE NOP NOP NOP

1234567890123456789

12345678

1

234567

8

1

234567

8

1

234567

8

1

234567

8

1

234567

8

12345678

123456

1

2345

6

1

2345

6

1

2345

6

123456

CMH

12

12345

1

234

5

1

234

5

1

234

5

12345

123

1234

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

1234

1234567

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

ROW

tCMS t

AH

tAS t

AH

tAS t

1234

1234567

123456

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

BANK

123456

AH

tAS t

BANK

123

12

1234

1

23

4

1

23

4

1

23

4

1

23

4

1234

123

12

12345

1

234

5

1

234

5

1

234

5

1

234

5

12345

123

12

123

1234

1

23

4

1

23

4

1

23

4

1

23

4

1234

12

123

1234

1

23

4

1

23

4

1

23

4

1

23

4

1234

123

12

12345

1

234

5

1

234

5

1

234

5

1

234

5

12345

123

12

BURST

TERM

12

1234

1

23

4

1

23

4

1

23

4

1234

123

COLUMN

m1

123456

1234567890123456789012345678901212345678901234

1

23456789012345678901234567890121234567890123

4

1

23456789012345678901234567890121234567890123

4

1

23456789012345678901234567890121234567890123

4

1

23456789012345678901234567890121234567890123

4

1234567890123456789012345678901212345678901234

1234

123456

ROW

1234567890123456789012345678901212345678901234567890123456789012123

1

23456789012345678901234567890121234567890123456789012345678901212

3

1

23456789012345678901234567890121234567890123456789012345678901212

3

1

23456789012345678901234567890121234567890123456789012345678901212

3

1234567890123456789012345678901212345678901234567890123456789012123

12

1234567890123456789012345678901212345678901234

1

23456789012345678901234567890121234567890123

4

1

23456789012345678901234567890121234567890123

4

1

23456789012345678901234567890121234567890123

4

1234567890123456789012345678901212345678901234

tRCD

NOP

12

NOP

12

1234

1

23

4

1

23

4

1

23

4

1234

12

123

12

12345

1

234

5

1

234

5

1

234

5

12345

123

1234

1

23

4

1

23

4

1

23

4

1234

123

256 (x16) locations within same row.

Full page completed.

Full-page burst does not

self-terminate. Can use

BURST TERMINATE

command.2,3

123

DIN m+1

tDS

123

DIN m+2 DIN m+3

123456

123456789012345678

1

2345678901234567

8

1

2345678901234567

8

1

2345678901234567

8

1

2345678901234567

8

123456789012345678

DIN m

123

tDH tDS tDH tDS tDH tDS tDH

123

DIN m-1

DS DH

12

1234567

123456

1234

1

23

4

1

23

4

1

23

4

1234

DS DH

tttt

123456789

12

1

T0 T1 T2 T3 T4 T5 Tn+1 Tn+2 Tn+3

1234

1

23

4

1

23

4

1234

1

234

1

234

1234

Don’t Care

Undefined

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

TIMING PARAMETERS

* CAS latency indicated in parentheseses.

NOTES: 1. x16: A8, A9 and A11 = “Don’t Care.”

2. tWR must be satisfied prior to PRECHARGE command.

3. Page left open, no tRP.

MIN MAX MIN MAX

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

CKS

23ns

t

CMH

11ns

t

CMS

23ns

t

DH

11ns

t

DS

23ns

t

RCD

20 30 ns

UNITSSYMBOL* -8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

48

WRITE -- DQM OPERATION1

1234567

12

12345

1

234

5

1

234

5

1

234

5

12345

123

tCK tCH

tCL

1234567

tCKS tCKH

tCMS tCMH

123

12

123456

ACTIVE NOP WRITE NOP NOP NOP NOP

123456789012345678901

123456

1

2345

6

1

2345

6

1

2345

6

123456

1

2345

6

1

2345

6

1

2345

6

123456

CMH

1234

1234567890123456789012

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1234

1234567

123456789

1

2345678

9

1

2345678

9

1

2345678

9

123456789

ROW

tCMS t

AH

tAS t

AH

tAS t

1234

1234567

123456

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

BANK

1234567

AH

tAS t

BANK

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

12345

1

234

5

1

234

5

1

234

5

12345

123

12

1234

1

23

4

1

23

4

1

23

4

1234

123

12

12345

1

234

5

1

234

5

1

234

5

12345

12

123

COLUMN

m2

12

1234567

1234567890123456789012345678901212345678901

1

23456789012345678901234567890121234567890

1

23456789012345678901234567890121234567890

1

23456789012345678901234567890121234567890

1

1234567890123456789012345678901212345678901

1234

1234567

ROW

12345678

1

234567

8

1

234567

8

1

234567

8

12345678

1

ENABLE AUTO PRECHARGE

12345678901234567890123456789012123456789012

1

234567890123456789012345678901212345678901

2

1

234567890123456789012345678901212345678901

2

1

234567890123456789012345678901212345678901

2

12345678901234567890123456789012123456789012

tRCD

NOP

1

123456789012345678901234567890121234567890

1

2345678901234567890123456789012123456789

0

1

2345678901234567890123456789012123456789

0

1

2345678901234567890123456789012123456789

0

123456789012345678901234567890121234567890

1

12

12345

1

234

5

1

234

5

1

234

5

12345

123

123456

DISABLE AUTO PRECHARGE

123456

1234567

12345

1

234

5

1

234

5

1

234

5

12345

tDS

123

DIN m+2 DIN m+3

1234567

1234567890123456789

1

23456789012345678

9

1

23456789012345678

9

1

23456789012345678

9

1234567890123456789

DIN m

tDH tDS tDH tDS tDH

12345678

12345678901234567

1

234567890123456

7

1

234567890123456

7

1

234567890123456

7

12345678901234567

1

12

12345

1

234

5

1

234

5

1

234

5

12345

123

1234

1

23

4

1

23

4

1

23

4

1234

123

12

12345

1

234

5

1

234

5

1

234

5

12345

123

CLK

CKE

COMMAND

DQM /

DQML,

DQMH

A0-A9,

A11

BA0, BA1

DQ

A10

123

1

2

3

123

1234

1

23

4

1

23

4

1234

Don’t Care

Undefined

TIMING PARAMETERS

* CAS latency indicated in parentheseses.

NOTES: 1. For this example, the burst length = 4.

2. x16: A8, A9 and A11 = “Don’t Care.”

T0 T1 T2 T3 T4 T5 T6 T7

MIN MAX MIN MAX

t

AH

11ns

t

AS

23ns

t

CH

3 3.5 ns

t

CL

3 3.5 ns

t

CK(3)

810ns

t

CK(2)

12 15 ns

t

CKH

11ns

UNITSSYMBOL* -8 -10

MIN MAX MIN MAX

t

CKS

23ns

t

CMH

11ns

t

CMS

23ns

t

DH

11ns

t

DS

23ns

t

RCD

20 30 ns

UNITSSYMBOL* -8 -10

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

49

NOTE: 1. All dimensions in inches (millimeters) or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.

MAX

MIN

MECHANICAL DEFINITIONS

ASI Case #901 (Package Designator DG)

SDRAM

AS4SD4M16

Austin Semiconductor, Inc.

AS4SD4M16

Rev. 1.0 9/99

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

50

ORDERING INFORMATION

Device Number Package

Type Speed ns Process

AS4SD4M16 DG - 8 /*

AS4SD4M16 DG -10 /*

EXAMPLE: AS4SD4M16DG-10/IT

*AVAILABLE PROCESSES

IT = Industrial Temperature Range -40oC to +85oC

XT = Extended T emperature Range -55oC to +125oC