PCM1760P/U DF1760P/U (R) Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM FEATURES DESCRIPTION DUAL 20-BIT MONOLITHIC MODULATOR (PCM1760) AND MONOLITHIC DECIMATING DIGITAL FILTER (DF1760) HIGH PERFORMANCE: THD+N: -92dB typ, -90dB max Dynamic Range: 108dB typ SNR: 108dB min, 110dB typ Channel Separation: 98dB typ, 94dB min The PCM1760 and DF1760 combine for a low-cost, high-performance dual 20-bit, 48kHz sampling analog-to-digital conversion system which is specifically designed for dynamic applications. The PCM1760/DF1760 pair form a 4-bit, 4th order, 64X oversampling analog-to-digital converter. 64X OVERSAMPLING CO-PHASE CONVERSION RUNS ON 256fs OR 384fs SYSTEM CLOCK VERSATILE INTERFACE CAPABILITY: 16-, 20-Bit Output MSB First or LSB First Format OPTIONAL FUNCTIONS: Offset Error Calibration Overflow Detection Power Down Mode (DF1760) RUNS ON 5V SUPPLIES (PCM1760) AND 5V SUPPLY (DF1760) COMPACT 28-PIN PACKAGES: 28-Pin DIP and SOIC The PCM1760 is a delta-sigma modulator that uses a 4-bit quantizer within the modulation loop to achieve very high dynamic range. The DF1760 is a high-performance decimating digital filter. The DF1760 accepts 4-bit 64fs data from the PCM1760 and decimates to 20-bit 1fs data. The FIR filter of the DF1760 has pass-band ripple of less than 0.001dB and greater than 100dB of the reject band attenuation. PCM1760 Analog Input (L) 4 Stage, 4-Bit Delta-Sigma Modulator 64fs Analog Input (R) 4 Stage, 4-Bit Delta-Sigma Modulator DF1760 64fs Timing Control and Interface SBAS025 1993 Burr-Brown Corporation 4fs FIR Filter fs Data Timing Control and Interface 256fs International Airport Industrial Park * Mailing Address: PO Box 11400 Tel: (520) 746-1111 * Twx: 910-952-1111 * Cable: BBRCORP * (c) 1/16 Filter System Clock 256/384fs * Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 PDS-1174C Printed in U.S.A. July, 1994 SPECIFICATIONS ELECTRICAL At TA = +25C, VCC, Vdd = +5V, +VDD = +5V, fS = 48kHz and ext. components = 2% unless otherwise noted. PCM1760/DF1760 PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 20 UNITS Bits ANALOG INPUT 2.5 RIN1 RIN1 = 2.2k RIN1 = 2.2k Input Range Input Impedance Vp-p SAMPLING FREQUENCY Integrator Constants: Application(1) Cover Range of fs 30 48 50 kHz 0.5 1.0 0.5 0.4 dB dB % FSR(2) ppmfs/C ppmfs/C -90 -88 -70 -70 -42 -42 dB dB dB dB dB dB dB dB dB dB dB dB ACCURACY Gain Error Gain Mismatch Bipolar Zero Error Gain Drift Bipolar Zero Drift VIN = 0 at 20s After Power-On 0C to +70C 0C to +70C 100 20 DYNAMIC CHARACTERISTICS(4) THD+N/(0dBFS) P, U P-L, U-L THD+N/(-20dBFS) P, U P-L, U-L THD+N/(-60dBFS) P, U P-L, U-L Dynamic Range P, U P-L, U-L SNR P, U P-L, U-L Frequency Response Channel Separation fIN = 1kHz fIN = 1kHz fIN = 1kHz fIN = 1kHz, VIN = -60dBFS, A Filter VIN = 0, A Filter fIN = 20kHz fIN = 1kHz, A Filter 104 104 108 106 94 -92 -90 -76 -76 -44 -44 108 108 110 110 0.1 98 DIGITAL FILTER Over Sample Rate Ripple in Band Stopband Attenuation -1 Stopband Attenuation -2 64 0.0001 0 - 0.04535fs 0.5465fs - 63.4535fs 0.5465fs - 3.4535fs -94 -100 fs dB dB dB LOGIC INPUTS AND OUTPUTS Logic Family Input Frequency (System Clock 1) Frequency (System Clock 2) Duty Cycle (System Clock 1) Duty Cycle (System Clock 2) Data Clock Input Logic Family Output Data Clock Output Data Coding Data Bit Length Data Format Output Data Delay 256fs 384fs 256fs 384fs 40 45 32 16 fs = 48kHz TTL Level Compatible CMOS 12.288 18.432 50 50 48 CMOS 64 Two's Complement 20 Selectable 1.5 60 55 64 MHz MHz % % fs fs Bits ms POWER SUPPLY REQUIREMENTS Supply Voltage VCC Vdd +VDD Supply Current +ICC -ICC +Idd -IDD +IDD -1 +IDD -2 Power Consumption 4.75 4.75 4.75 PCM1760 PCM1760 DF1760 PCM1760 PCM1760 PCM1760 PCM1760 DF1760, Normal Mode DF1760, Power-Down Mode PCM1760 DF1760, Normal Mode DF1760, Power-Down Mode 5.0 5.0 5.0 5.25 5.25 5.25 V V V 24 -30 12 -8 40 4 370 200 20 36 -45 18 -12 55 6.6 500 275 33 mA mA mA mA mA mA mW mW mW +25 +70 +125 C C TEMPERATURE RANGE Operating Storage PCM1760/DF1760 PCM1760/DF1760 0 -50 NOTES: (1) Integrator Constants are determined by the external components shown in the block diagram. (2) FSR means Full Scale Range, digital output code is from 90000H to 70000H, FSR = 5.0V. (3) Use 20-bit DAC, 20kHz LPF, 400Hz HPF, average response. (4) Average response using a 20-bit reconstruction DAC with 20kHz low-pass filter and 400Hz high-pass filter. (R) PCM1760P/U DF1760P/U 2 ABSOLUTE MAXIMUM RATINGS--PCM1760 ABSOLUTE MAXIMUM RATINGS--DF1760 Supply Voltage ..................................................................................... 6V Voltage Mismatch ............................................................................... 0.1V Analog Input ........................................................................................ VCC Digital Input ............................................................................... +VDD +0.3V GND -0.3V Power Dissipation/P ....................................................................... 580mW Power Dissipation/U ....................................................................... 550mW Lead Temperature/P (soldering, 10s) .............................................. 260C Lead Temperature/U (soldering, 10s) .............................................. 235C Operating Temperature ......................................................... 0C to +70C Storage Temperature ...................................................... -50C to +125C Supply Voltage .................................................................................... 7.0V Voltage Mismatch ............................................................................... 0.1V Digital Input ............................................................................... +VDD +0.5V VSS -0.5V Input Current 20mA Power Dissipation/P ....................................................................... 460mW Power Dissipation/U ....................................................................... 440mW Lead Temperature/P (soldering, 10s) .............................................. 260C Lead Temperature/U (soldering, 10s, reflow) ................................... 235C Operating Temperature .......................................................... 0C to +70c Storage Temperature ...................................................... -50C to +125C ORDERING INFORMATION MODEL PACKAGE INFORMATION PACKAGE THD +N (fs) SNR PDIP SOIC PDIP SOIC PDIP SOIC -90dB -90dB -88dB -88dB NA NA 108dB 108dB 106dB 106dB NA NA PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE PACKAGE DRAWING NUMBER(1) PCM1760P PCM1760U PCM1760P-L PCM1760U-L 28-Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC 800 804 800 804 DF1760P DF1760U 28-Pin PDIP 28-Pin SOIC 801 805 MODEL NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. PIN ASSIGNMENTS PCM1760 Top View SOIC/DIP Out-2R 1 28 NC In-2R 2 27 BPODC-R Out-1R 3 26 D3 In-1R 4 25 D2 SERVO DC 5 24 D1 +VCC 6 23 D0 AGND 7 PCM1760 22 +VDD -VCC 8 21 DGND BGDC 9 20 -VDD NC 10 19 256fs In-1L 11 18 Strobe Out-1L 12 17 L/RCK In-2L 13 Out-2L 14 16 BPODC-L 15 NC PIN I/O(1) NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 O I O I - - - - - - I O I O - - O O I - - - O O O O - - Out-2R In-2R Out-1R In-1R SERVO DC +VCC AGND -VCC BGDC NC In-1L Out-1L In-2L Out-2L NC BPODC-L L/RCK Strobe 256fs -VDD DGND +VDD D0 D1 D2 D3 BPODC-R NC DESCRIPTION Right Channel Second Integrator Output Right Channel Second Integrator Input Right Channel First Integrator Output Right Channel First Integrator Input Servo Amp Decoupling Capacitor +5V Analog Supply Voltage Analog Common -5V Analog Supply Voltage Band Gap Reference Decoupling Capacitor No Connection Left Channel First Integrator Input Left Channel First Integrator Output Left Channel Second Integrator Input Left Channel Second Integrator Output No Connection Left Channel Bipolar Offset Decoupling Capacitor LR Clock Output (64fs) Data Strobe Output (128fs) 256fs Clock Input -5V Digital Supply Voltage Digital Common +5V Digital Supply Voltage D0 Data Output (LSB) D1 Data Output D2 Data Output D3 Data Output (MSB) Right Channel Bipolar Offset Decoupling Capacitor No Connection NOTE: (1) O = Output terminal; I = Input terminal. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) 3 PCM1760P/U DF1760P/U PIN ASSIGNMENTS DF1760 Top View SOIC/DIP OVL 1 28 VSS2 OVR 2 27 VDD2 D3 3 26 TP2 D2 4 25 CLKSEL D1 5 24 S/M D0 6 23 Mode 1 TP1 7 22 Mode 2 DF1760 VSS1 8 21 /PD VDD1 9 20 LRSC 256fs 10 19 FSYNC Strobe 11 18 SDATA LRCK 12 17 L/R CALD 13 16 SCLK CAL 14 15 SYSCLK PIN I/O(1) NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 O O I I I I - - - O I I I O I I /O I /O O I /O I I I I I OVL OVR D3 D2 D1 D0 TP1 VSS1 VDD1 256fs Strobe LRCK CALD CAL SYSCLK SCLK L/R SDATA FSYNC LRSC /PD Mode2 Mode1 S/M 25 26 27 28 I - - - CLKSEL TP2 VDD2 VSS2 DESCRIPTION Left Channel Overflow Output (Active High) Right Channel Overflow Output (Active High) D3 Data Input (MSB) D2 Data Input D1 Data Input D0 Data Input (LSB) Test Pin (No Connection) Common Channel 1 +5V Channel 1 256fs Clock Output Data Strobe Clock Input (128fs) LR Clock Input Calibration Function Enable (Active Low) Calibration Output (High During Calibration) System Clock Input (256fs or 384fs) Data Clock LR Channel Phase Clock Serial Data Output (1fs) Frame Clock (2fs) Phase Control of LR Channel Phase Clock Power Down Mode Enable Input (Active Low) Output Format Selection Input 2 Output Format Selection Input 1 Slave/Master Mode Selection Input (High Makes Slave Mode System Clock Selection Input (High Makes 256fs) Test Pin (No Connection) +5V Channel 2 Common Channel 2 NOTE: (1) O = Output terminal; I = Input terminal. BLOCK DIAGRAM OF DF1760 D3 D2 D1 D0 Strobe LRCK VSS1 VDD1 256fs 1/16 Decimation Filter Input LAT Boost Filter CALD CAL Input RAM Main Timing Control Multiplier ALU Calibration Output Control Coefficient Overflow DET Temporary RAM Test SYSCLK CLKSEL /PD S/M TP1 OVL SDATA TP2 OVR MODE 1 (16-, 20-Bit) MODE 2 LRSC FSYNC L/R SCLK VSS2 VDD2 (R) PCM1760P/U DF1760P/U P/S 4 BLOCK DIAGRAM OF PCM1760 C1R C3R C2R C4R RT1R RT2R RZ1R RIN1R + RIN2R NC 4 RCH, VIN 3 In-1R 2 1 In-2R Out-1R 28 BPODC-R S/HINR 1R 27 Out-2R RCH S/H 2R SERVO DC D3 5 26 D2 RCH BPO + 25 D e c o d e r IOUTR RCH ADC RCH DAC IOUTR +VCC +5V D1 24 D0 23 +VDD 6 + AGND Band Gap Bias 7 + + DGND Servo Amp T i m i n g -VCC 8 -5V +5V 22 IOUTL Sub LCH DAC IOUTL + LCH ADC C T L BGDC 1L 20 + -5V 256fs 19 Strobe 18 L/R CK LCH BPO 9 21 -VDD 17 LCH S/H 2L S/HINL NC 10 In-1L Out-1L 11 In-2L 12 Out-2L 13 NC 14 15 BPODC-L 16 + RIN1L RIN2L RZ1L LCH, VIN C1L C2L C3L C4L RT1L RT2L External Components Condition RIN 1R/L C1, C2 R/L 2.2k 2200pF C3, C4 R/L RT2 R/L 1800pF 560 RTIR/L 470 RZ1 R/L 1.2k RIN 2R/L 1.3k (R) 5 PCM1760P/U DF1760P/U TYPICAL PERFORMANCE CURVES OVERALL CHARACTERISTICS OF THE DF1760 1.0 50 0.5 0 (dB) (dB) OVERALL PASS-BAND CHARACTERISTICS OF THE DF1760 0 -50 -100 -0.5 -150 -1.0 fs / 4 0 fs / 2 0 16 32 46 64 (fs) TOTAL PASS-BAND FREQUENCY RESPONSE, COMBINATION OF PCM1760 AND DF1760 PASS-BAND CHARACTERISTICS OF THE FIR PORTION OF THE DF1760 0.3 0.0010 0.2 Amplitude (dB) (dB) 0.0005 0 0.1 0 -0.1 -0.0005 -0.2 -0.3 -0.0010 fs / 2 fs / 4 0 0.1 1 10 Frequency (kHz) TYPICAL FFT ANALYSIS OF THE 1kHz fs INPUT SIGNAL 0 -20 Amplitude (dB) -40 -60 -80 -100 -120 -140 -160 -180 -200 6 0 12 18 24 Frequency (kHz) fs = 48.000000kHz FC1 = 1.171876kHz (R) PCM1760P/U DF1760P/U 6 100 LCH In RCH In RIN 2.2k RIN 2.2k 7 560 470 2200pF -5V VCC +5V VCC 2200pF 470 560 1800pF 1800pF 2200pF + 10F 10F + 2200pF 1800pF 1800pF 1.2k 0.1F 0.1F 1.2k 1.3k 3.3F + 3.3F + 1.3k 8 9 11 12 13 14 7 1 2 3 4 5 6 -VCC BG DC In-1L Out-1L In-2L Out-2L AGND -VDD 256fs STB L/R CLK BPO DCL DGND BPO DCR D3 D2 D1 D0 +VDD PCM1760 Out-2R In-2R Out-1R In-1R Servo DC +VCC 20 19 18 17 16 21 27 26 25 24 23 22 + + 10F 0.1F 0.1F + 10F + -5V VDD 3.3F 3.3F +5V +5V VDD VDD + 3.3F + D3 D2 D1 D0 VSS1 3.3F 9 V 10 DD1 256fs 11 STB 12 LRCK 0.1F 3 4 5 6 8 28 VSS2 27 VDD2 0.1F +5V VDD FSYNC SDATA L/R SCLK SYSCLK + 47F +5V VDD Power on Reset 10k 0.1F + 3.3F Digital I/O SYS CLK 19 18 17 16 15 25 CLKSEL 24 S/M 23 Mode 1 22 Mode 2 21 PD DF1760 +5V VDD BASIC CONNECTION DIAGRAM OF PCM1760 AND DF1760 (R) PCM1760P/U DF1760P/U FUNCTIONS OF THE DIGITAL FILTER OFFSET CALIBRATION MODE The offset error is calibrated by storing the digital data when the input is zero in registers and subtracting it from the future data with actual signal input. SYSTEM CLOCK The DF1760 can accept a system clock of either 256fs or 384fs. If a 384fs system clock is used, the DF1760 divides by 2/3 to create the 256fs system clock required for the PCM1760. The system clock is applied to pin 15 (SYSCLK input). The actual clock selection is done by setting pin 25 (CLKSEL input) "high" for 256fs clock and "LOW" for 384fs clock. SYSCLK H L 256fs 384fs MASTER/SLAVE MODE The DF1760 can be used in both the master mode and slave mode. In the master mode, the DF1760 outputs L/R (left/ right channel phase clock), SCLK (data clock) and FSYNC (frame clock 2fs) signals. In the slave mode, the DF1760 accepts L/R, SCLK and FSYNC signals. The mode selection is done by taking pin 24 (S/M INPUT) "HIGH" for slave mode and "LOW" for master mode. S/M MODE H L Slave Master MODE 2 FORMATS H L H L H H L L MSB First, 16 Bits, Falling Edge MSB First, 20 Bits, Falling Edge MSB First, 20 Bits, Rising Edge LSB First, 20 Bits, Falling Edge Disable Enable POWER DOWN MODE/RESET The /PD input (Pin 21) has two functions. First, it should be set at "HIGH" after application or restoration of power (VSS and/or VDD) to accomplish the power-on/mode reset function. The detail timing requirements for this function are shown in Figure 3f. Second, the DF1760 is placed in the power down mode by setting the /PD input (Pin 21) "LOW". Set the /PD input (Pin 21) "HIGH" for normal operation mode. OUTPUT DATA FORMAT The serial output data has four possible formats. The selection of the formats can be done by the Mode 1 and Mode 2 inputs. MODE 1 CALIBRATION H L To enable the calibration mode, set the CALD input (Pin 13) "LOW". The calibration mode is disabled by setting the CALD input (Pin 13) "HIGH". The calibration cycle is initiated by setting the /PD input (Pin 21) "LOW" for more than 2 system clock periods and then setting it "HIGH". During the calibration cycle, the CAL output (Pin 14) becomes "HIGH", all the serial data is forced to "LOW", and the L/R (Pin 17), SCLK (Pin 16) and FSYNC (Pin 19) pins become input terminals after the completion of the calibration cycle. The CAL output is "LOW". The detailed timing requirements for the system clock are shown in Figure 3c. CLKSEL CALD /PD OPERATION H L Normal Power Down The power dissipation of the DF1760 in the power down mode is about 1/10 of the normal operation mode. During the power down mode, the L/R, SCLK, and FSYNC pins become input pins and all the serial data is forced "LOW". The 256fs output is enabled even in the power down mode. The detailed timing of the power down mode operation and the offset calibration is shown in Figure 3b. LR CHANNEL PHASE CLOCK The status of the LR channel phase clock can be set by the LRSC input. +Detect Level LRSC L/R CLOCK AND CHANNEL H H = LCH, L = RCH L L = LCH, H = RCH -Detect Level TOR OVERFLOW DETECTION When a near-to-clipping input condition is detected, OVL output (Pin 1), or OVR output (Pin 2), becomes "HIGH" for a duration of 4096/fs (about 85ms) depending upon on the channel detected. TOR TOF OVL (OVR) DESCRIPTION The OVL and OVR output return to "LOW" after 4096/fs duration automatically. NAME MIN Delay from Overflow Detection to OVL (OVR) Output TYP MAX TOR OVL (OVR) Output Pulse Width TOF - - 0 ns - 4096 - 1/fs FIGURE 3a. DF1760 Overflow Detection. (R) PCM1760P/U DF1760P/U TOF 8 UNITS TSLKH TSLKL TPDW /PD TPCF TPCR SCKL TDSS CAL TPSF TCSV TDSV SDATA SDATA TSLR TSDR L/R DESCRIPTION NAME MIN TYP MAX UNITS Pulse Width of /PD Input TPDW 2 - - 1/Fclk Delay from /PD Input to CAL Output TPCR - - 6 1/Fclk Calibration Cycle Duration TPCF - 4096 - 1/fs Delay from /PD Input to SDATA L TPSF - - 6 1/Fclk Delay from Completion of Calibration to SDATA Valid - TCSV 1 - TSF FSYNC DESCRIPTION 1/fs FIGURE 3b. DF1760 Power Down and Offset Calibration. TCLKH TCLKL 2.0V 1.4V 0.8V TLH THL SYSTEM CLOCK: 256fs DESCRIPTION NAME MIN TYP MAX UNITS Low Level Duration TCLKL 31 - - ns High Level Duration TCLKH 31 - - ns NAME MIN TYP MAX UNITS Low Level Duration TCLKL 24 - - ns High Level Duration TCLKH 24 - - ns Rise Time TLH - - 6 ns Fall Time THL - - 6 ns NAME MIN TYP MAX SCLK Frequency FSLK 32fs 48fs 64fs UNITS - Low Duration of FSCLK TSLKL 100 - - ns High Duration of FSCLK TSLKH 100 - - ns Delay from SCLK to L/R Edge TSLR -70 - 70 ns Delay from Falling Edge of SCLK to SDATA Valid TDSS - - 50 ns Delay from SCLK to FSYNC Edge TSF -70 - 0 ns Delay from Rising Edge of SCLK to SDATA Valid TDSV 100 - - ns Delay from SDATA Valid to Rising Edge of SCLK TSDR 100 - - ns FIGURE 3e. Timing of Slave Mode, DF1760. <LRSC = "H" SYSTEM CLOCK: 384fs DESCRIPTION Power L/R TSP PD TSP TPDW FIGURE 3c. System Clock Timing Requirements of DF1760. TPDW <LRSC = "L" TDSV Power SCLK TDSV TDSS SDATA T L/R TDSS TSP T SLR L/R FSYNC TSP SDR PD TPDW TSF TSF DESCRIPTION DESCRIPTION SCLK Frequency NAME MIN TYP MAX FSLK - 64fs - - 50 - SCLK Frequency Duty Cycle FSYNC Frequency FSYNC FSYNC Frequency Duty Cycle UNITS % TPDW NAME MIN Power on to PD TPDW 2 PD to L/R (LRSC = "H") TSP -1 TSP -1 TYP UNITS(1) APPLIES TO MODE 1/fs Master/Slave +1 1/Fclk Slave +1 1/Fclk Slave MAX - 2fs - - 50 - % PD to L/R (LRSC = "L") NOTE: (1) fs: sampling rate. Fclk: system clock frequency. Delay from SCLK to L/R Edge TSLR -20 - 50 ns Delay from Falling Edge of SCLK to SDATA Valid TDSS - - 50 ns Delay from SCLK to FSYNC Edge TSF -20 - 50 ns Delay from Rising Edge of SCLK to SDATA Valid TSDR 100 - - ns Delay from SDATA Valid to Rising Edge of SCLK TDSV 100 - - ns FIGURE 3f. Power On and Mode Reset Timing. FIGURE 3d. Output Timing of Master Mode, DF1760. (R) 9 PCM1760P/U DF1760P/U THEORY OF OPERATION The DF1760 accepts the four-bit 64fs noise shaped data stream from the PCM1760 and decimates to 1/16 with an initial filter, and then decimates to 1fs 20-bit data using a 4x oversampling filter. MULTI-BIT ENHANCED NOISE SHAPING A block diagram of a typical 1-bit delta-sigma modulator is shown in Figure 4. The PCM1760 and DF1760 combination achieves a dynamic range of 108dB and SNR of 110dB even with a single-ended input. In Figure 4, the quantizer consists of a single bit which has two possible states, either "0" or "1". The input signal is sampled at a much higher sample rate than the nyquist sampling frequency. The quantizer output data stream is digitally filtered for higher resolution nyquist data. The theoretical SNR is determined by the number of the order of the integrator and the oversampling rate. Integrator + 28 27 DF1760 Quantizer Input (2) Output 8 9 (1) z-1 FIGURE 4. Single Stage 1-Bit Delta-Sigma. Integrator + (1) nBit Input (1) 22 Output 21 20 ADC PCM1760 nBit DAC 6 7 (1) 8 (1) FIGURE 5. Single Stage Multi-bit Delta-Sigma. Digital Common There is a practical limit to increasing the numbers of order of the integrator due to an inherent oscillation in the modulator. There is also a limit to increasing the sample rate due to the increase in jitter sensitivity associated with high clock frequencies. +5V Input + + GND -5V Power Supply FIGURE 7. Recommended Power Supply Connection and Decoupling. LAYOUT PRECAUTIONS Analog common and digital common of the PCM1760 are not connected internally. These should be connected together with the common of the DF1760 as close to the unit as possible, preferably to a large ground plane under the PCM1760. The use of a separate +5V supply is recommended for the PCM1760 and DF1760, and to connect the common at one point as described above. Low impedance analog and digital commons returns are essential for better performance. 4Bits Output ADC The power supplies should be bypassed with tantalum capacitors as close as possible to the units. See Figure 7 for recommended common connections and power supplies bypassing. 4Bits DAC FIGURE 6. Multi-bit Enhanced Noise Shaping. (R) PCM1760P/U DF1760P/U +5V NOTE: (1) Tantalum 3.3F. (2) Ceramic 0.1F. A block diagram of the PCM1760 modulator is shown in Figure 6. The PCM1760 is a fourth-order integrator that samples at 64x oversampling, and samples left and right channel input signal simultaneously. 2nd Order Integrator GND Power Supply The PCM1760 utilizes a four-bit quantizer instead of the conventional one-bit method. The quantizing noise of a fourbit quantizer is 1/16 of the one-bit version. Using the fourbit quantizer allows for a lesser order number of the integrator and a lower oversampling rate to achieve similar performance to that of a more complex one-bit system. 2nd Order Integrator Analog Common 10 OUTPUT TONE ELIMINATION When the sampling frequency (fs) is between 40kHz and 50 kHz and the L/R relative offset voltage (Vs) is less than or equal to 0.05% of full scale range, the PCM1760 may output a tone similar to an idle tone. This tone is very low and its frequency depends on the input L/R relative offset voltage, Vs. This tone never occurs when the sampling frequency (fs) is 32kHz. To avoid this tone, the offset voltage should be summed using an amplifier, buffer, active low pass filter, etc., to cause the input L/R relative offset voltage (Vs) to be greater than 0.05% of full scale range. RIN1-L 11 2.2k VIL = -20mV 10% PCM1760 RIN1-R It is recommended that: (A) Sum offset at both L/R channels Lch: VIL = -20mV 10% Rch: VIR = +10mV 10% 4 2.2k VIR = +10mV 10% (B) Sum offset at L channel Lch: VIL = -30mV 10% Rch: VIR = 1mV (by a precircuit) FIGURE 8. Application Example to Eliminate the Tone (offset voltage implementation for both channels). When FSR = 5V (2.5V). Figure 8 shows an application circuit for summing the offset at both L/R channels. Alternately, Figure 9 shows an application circuit for use when fs = 48kHz which changes the external integrator circuit of the PCM1760. OFFSET ERROR CALIBRATION The offset voltage of the PCM1760 and the input stage of the system can be compensated by using the calibration mode of the DF1760. Offset calibration is shown in Figure 10. An optional analog switch is driven by a CAL output of the DF1760. The PD input of the DF1760 is used to initiate the calibration cycle. MODULATOR COMPONENTS AND SAMPLING FREQUENCY The PCM1760/DF1760 are capable to 30kHz to 50kHz fs sampling frequency by condition with external components value which are shown in Basic Connection Diagram. ANALOG INPUT AND DIGITAL OUTPUT Ideal output digital code range for 20-bit resolution is from 8000H (-Full Scale) to 7FFFFH (+Full Scale). The characteristics of the modulator's integrator can be set by external components. The values in the block diagram on page five are recommended for optimized performance. Low leakage, low voltage coefficient capacitors are recommended for integration capacitors. The DF1760, combined with 70000H (FSR) of the PCM1760, produces a digital output code range at FSR input of 90000H (-FSR). The relationship between analog input and digital output is shown in Table I. The tolerance of external components should be better than 2%. C1 RT1 C2 C3 CZ1 RZ1 RIN1 C4 RT2 RZ2 RIN2 11 12 RIN1 = 2.2k RT2 = 2.2k C1, C2, C3, C4 = 1200pF RT1 = 470 RZ1 = 470 CZ1 = 220pF RIN2 = 1.3k RZ2 = 910 OP1 PCM1760 13 14 OP2 FIGURE 9. Application Example to Eliminate the Tone (alternative modulator's integrator circuit. Only for fs = 48kHz). (R) 11 PCM1760P/U DF1760P/U TABLE I. Output Codes. POWER-ON RESET AND MODE RESET The timing requirements for POWER-ON RESET and MODE RESET are shown in Figure 3f. The DF1760 requires POWER-ON RESET when power is applied or restored. MODE RESET is required when any of the following has been changed: system clock, master/slave mode, output data format, L/R clock, calibration after POWER-ON in slave mode. This reset should be done by holding the /PD input (pin 21) low for more than 2/fs. Suggested reset circuits are given in Figures 11, 12 and 13. POWER SUPPLY SEQUENCING CLOCK INPUT ANALOG INPUT +2.55V +2.50V to +2.55V CONDITION +Max Input 72000H Overflow 70000H to 72000H(2) +2.50V 0V +FSR 70000H BPZ (Ideal) 00000H (1) -2.50V -2.83V to -2.85V -2.85V DIGITAL OUTPUT -FSR 90000H Overflow 82FFFH to 82000H(2) -Max Input 82000H NOTES: (1) Incase of BPZ Error = 0. (2) Overflow detection level is over 70000H or under 82FFFH of digital output code. The PCM1760 requires VCC and VDD power supplies. To avoid any possibility of latch-up, the VCC and VDD power should all be applied simultaneously or the +VCC and +VDD applied first followed by -VCC and -VDD. After power is applied to the DF1760, the system clock should be provided continuously. The DF1760 employs a dynamic logic architecture. Analog Input VOS VOS PCM1760 ANALOG INPUT DF1760 CAL PD ANALOG INPUT +fs +fs Digital Output Digital Output VOS BPZ -fs BPZ -fs -fs 0V +fs -fs FIGURE 10. Illustration of Offset Calibration. (R) PCM1760P/U DF1760P/U 12 0V +fs Power-On Reset Circuit DF1760P/U VDD S/M 10k /PDIN /PDIN(1) /PD /PDOUT VDD SDATA SDATA L/R 15 1588 L/R SCLK SCLK 10k 47F + NOTE: (1) External /PD input: Time "L" > 2/fs. FIGURE 11. Master Mode Reset Circuit. Power-On Reset Circuit DF1760P/U VDD /PDIN(1) VDD S/M 10k /PDIN D CLK VDD PR /PD LRSC Q VDD SDATA L/R L/R SCLK 74HC74 10k 47F /PDOUT SDATA CL 15 1588 Q VDD SCLK L/R + NOTE: (1) External /PD input: Time "L" > 2/fs. FIGURE 12. Slave Mode Reset Circuit, (LRSC = H). Power-On Reset Circuit DF1760P/U VDD /PDIN(1) VDD /PDIN PR 10k Q /PDOUT LRSC SDATA CL 15 1588 VDD /PD D CLK VDD 47F S/M 10k Q L/R SCLK 74HC74 + SDATA L/R SCLK L/R NOTE: (1) External /PD input: Time "L" > 2/fs. FIGURE 13. Slave Mode Reset Circuit, (LRSC = L). (R) 13 PCM1760P/U DF1760P/U TIMING CHARACTERISTICS 256fs D3 Lch Rch D2 Lch Rch D1 Lch Rch D0 Lch Rch LRCK STROBE FIGURE 14. Input and Output Format of the DF1760 and PCM1760. L/R (I) SCLK (I) FSYNC (I) SDATA (O) M LM L FIGURE 15a. Slave Mode and SCLK = 32fs. (Output format of the DF1760). L/R (I) SCLK (I) FSYNC (I) * MSB First 20-Bit (1) SDATA (O) * MSB First 20-Bit (2) SDATA (O) M M * MSB First 16-Bit SDATA (O) * LSB First 20-Bit SDATA (O) M L L M M FIGURE 15b. Slave Mode and SCLK = 48fs. (R) PCM1760P/U DF1760P/U M L L 14 M L L M L L M L/R (1) SCLK (1) FSYNC (1) * MSB First 20-Bit (1) SDATA (0) * MSB First 20-Bit (2) SDATA (0) * MSB First 16-Bit SDATA (0) * LSB First 20-Bit SDATA (0) FIGURE 15c. Slave Mode and SCLK = 64fs. L/R (0) SCLK (0) * MSB First 20 Bit (1) FSYNC (0) SDATA (0) * MSB First 20 Bit (2) FSYNC (0) SDATA (0) * MSB First 16 Bit FSYNC (0) SDATA (0) * LSB First 20 Bit FSYNC (0) SDATA (0) FIGURE 15d. Master Mode. (R) 15 PCM1760P/U DF1760P/U PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DF1760P NRND PDIP N 28 13 Pb-Free (RoHS) Call TI N / A for Pkg Type Samples Not Available DF1760U NRND SO NS 20 26 Pb-Free (RoHS) Call TI Level-3-260C-168 HR Samples Not Available PCM1760P NRND PDIP NTD 28 TBD Call TI Call TI Samples Not Available PCM1760P-L NRND PDIP NTD 28 TBD Call TI Call TI Samples Not Available PCM1760U NRND SOIC DW 28 TBD Call TI Call TI Samples Not Available PCM1760U-L NRND SOIC DW 28 TBD Call TI Call TI Samples Not Available PCM1760U-L/1K NRND SOIC DW 28 TBD Call TI Call TI Samples Not Available PCM1760U/1K NRND SOIC DW 28 TBD Call TI Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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