SC26C92
Dual universal asynchronous
receiver/transmitter (DUART)
Product specification
Supersedes data of 1998 Nov 09
IC19 Data Handbook
2000 Jan 31
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2
2000 Jan 31 853–1585 23061
DESCRIPTION
The SC26C92 is a pin and function replacement for the SCC2692
and SCN2681 with added features and deeper FIFOs. Its
configuration on power up is that of the 2692. Its differences from
the 2692 are: 8 character receiver, 8 character transmit FIFOs,
watch dog timer for each receiver, mode register 0 is added,
extended baud rate and overall faster speeds, programmable
receiver and transmitter interrupts. (The SCC2692 is not being
discontinued.)
The Philips Semiconductors SC26C92 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
CMOS-LSI communications device that provides two full-duplex
asynchronous receiver/transmitter channels in a single package. It
interfaces directly with microprocessors and may be used in a polled
or interrupt driven system and provides modem and DMA interface.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of 27 fixed baud
rates, a 16X clock derived from a programmable counter/timer, or an
external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver and transmitter is buffered by eight character FIFOs
to minimize the potential of receiver overrun, transmitter underrun
and to reduce interrupt overhead in interrupt driven systems. In
addition, a flow control capability is provided via RTS/CTS signaling
to disable a remote transmitter when the receiver buffer is full.
Also provided on the SC26C92 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
The SC26C92 is available in three package versions: 40-pin 0.6”
wide DIP, a 44-pin PLCC and 44–pin plastic quad flat pack (PQFP).
FEATURES
•Dual full-duplex independent asynchronous receiver/transmitters
•8 character FIFOs for each receiver and transmitter
•Programmable data format
–5 to 8 data bits plus parity
–Odd, even, no parity or force parity
–1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•16-bit programmable Counter/T imer
•Programmable baud rate for each receiver and transmitter
selectable from:
–27 fixed rates: 50 to 230.4k baud
–Other baud rates to 230.4k baud at 16X
–Programmable user-defined rates derived from a
programmable counter/timer
–External 1X or 16X clock
•Parity, framing, and overrun error detection
•False start bit detection
•Line break detection and generation
•Programmable channel mode
–Normal (full-duplex)
–Automatic echo
–Local loopback
–Remote loopback
–Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
•Multi-function 7-bit input port
–Can serve as clock, modem, or control inputs
–Change of state detection on four inputs
–Inputs have typically >100k pull-up resistors
•Multi-function 8-bit output port
–Individual bit set/reset capability
–Outputs can be programmed to be status/interrupt signals
–FIFO states for DMA and modem interface
•Versatile interrupt system
–Single interrupt output with eight maskable interrupting
conditions
–Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
–Each FIFO can be programmed for four different interrupt levels
–W atch dog timer for each receiver
•Maximum data transfer rates:
1X – 1Mb/sec, 16X – 1Mb/sec
•Automatic wake-up mode for multidrop applications
•Start-end break interrupt/status
•Detects break which originates in the middle of a character
•On-chip crystal oscillator
•Power down mode
•Receiver timeout mode
•Single +5V power supply
•Powers up to emulate SCC2692
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL1INDUSTRIAL
DWG #
DESCRIPTION
VCC = +5V ±10%, TA = 0 to +70°C VCC = +5V ±10%, T A = -40 to +85°C
DWG
#
40-Pin Plastic Dual In-Line Package (DIP) SC26C92C1N SC26C92A1N SOT129-1
44-Pin Plastic Leaded Chip Carrier (PLCC) SC26C92C1A SC26C92A1A SOT187-2
44–Pin Plastic Quad Flat Pack (PQFP) SC26C92C1B SC26C92A1B SOT307–2
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 3
NOTE:
1. Commercial devices are tested for the –40 to +85_C.
PIN CONFIGURATIONS
PIN/FUNCTION PIN/FUNCTION
1NC 23NC
2 A0 24 INTRN
3 IP3 25 D6
4A1 26D4
5 IP1 27 D2
6A2 28D0
7 A3 29 OP6
8 IP0 30 OP4
9 WRN 31 OP2
10 RDN 32 OP0
11 RXDB 33 TXDA
12 NC 34 NC
13 TXDB 35 RXDA
14 OP1 36 X1/CLK
15 OP3 37 X2
16 OP5 38 RESET
17 OP7 39 CEN
18 D1 40 IP2
19 D3 41 IP6
20 D5 42 IP5
21 D7 43 IP4
22 VSS 44 VCC
SD00667
24
23
22
2120
19
18
17
16
15
28
27
12
10
11
9
8
7
6
5
4
3
2
1
14
13
26
25
29
30
31
32
33
34
35
36
37
38
39
40
DIP
VCC
IP4
IP5
IP6
IP2
CEN
RESET
X2
X1/CLK
RxDA
TxDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTRN
A0
IP3
A1
IP1
A2
A3
IP0
WRN
RDN
RxDB
TxDB
OP1
OP3
OP5
OP7
D1
D3
D5
D7
VSS
1
39
17
28
40
29
18
7
PLCC
6
TOP VIEW
INDEX
CORNER
PIN/FUNCTION PIN/FUNCTION
1 A3 23 N/C
2 IP0 24 OP6
3 WRN 25 OP4
4 RDN 26 OP2
5 RxDB 27 OP0
6 TxDB 28 TxDA
7 OP1 29 RxDA
8 OP3 30 X1/CLK
9 OP5 31 X2
10 OP7 32 RESET
11 N/C 33 CEN
12 D1 34 IP2
13 D3 35 IP6
14 D5 36 IP5
15 D7 37 IP4
16 GND 38 VCC
17 GND 39 VCC
18 INTRN 40 A0
19 D6 41 IP3
20 D4 42 A1
21 D2 43 IP1
22 D0 44 A2
33
11
22
34
23
12
1
PQFP
44
TOP VIEW
Figure 1. Pin Configurations
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 4
BLOCK DIAGRAM
8
D0–D7
RDN
WRN
CEN
A0–A3
RESET
INTRN
X1/CLK
X2
4
BUS BUFFER
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTERRUPT CONTROL
IMR
ISR
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL OSC
CSRA
CSRB
ACR
CTPL
CHANNEL A
8 BYTE TRANSMIT
FIFO
TRANSMIT
SHIFT REGISTER
8 BYTE RECEIVE
FIFO
MRA0, 1, 2
CRA
SRA
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPCR
TxDA
RxDA
IP0-IP6
OP0-OP7
VCC
VSS
CONTROL
TIMING
INTERNAL DATABUS
CHANNEL B
(AS ABOVE)
IPCR
ACR
OPR
CTPL
U
RxDB
TxDB
8
7
WATCH DOG TIMER
RECEIVE SHIFT
REGISTER
SD00153
Figure 2. Block Diagram
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 5
PIN DESCRIPTION
SYMBOL
PKG PIN
NAME AND FUNCTION
SYMBOL
40,44 TYPE
NAME
AND
FUNCTION
D0-D7 X I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART
and the CPU. D0 is the least significant bit.
CEN X I Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are
enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the D0-D7 lines
in the 3-State condition.
WRN X I W rite Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed
register. The transfer occurs on the rising edge of the signal.
RDN X I Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
A0-A3 X I Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET X I Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in the
High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and
TxDB outputs in the mark (High) state. Sets MR pointer to MR1 and resets MR0.
INTRN X O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight
maskable interrupting conditions are true. Requires a pullup resistor.
X1/CLK X I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock T iming.
X2 X I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used this pin must be left open or not driving
more than one TTL equivalent load.
RxDA X I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
RxDB X I Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
TxDA X O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback mode.
“Mark” is High, “space” is Low.
TxDB X O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is High, ‘space’ is Low.
OP0 X O Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
OP1 X O Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
OP2 X O Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver
1X clock output.
OP3 X O Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter
1X clock output, or Channel B receiver 1X clock output.
OP4 X O Output 4: General purpose output or Channel A open-drain, active-Low, RxA interrupt ISR[1] output.
OP5 X O Output 5: General purpose output or Channel B open-drain, active-Low, RxB interrupt ISR[5] output.
OP6 X O Output 6: General purpose output or Channel A open-drain, active-Low, TxA interrupt ISR[0] output.
OP7 X O Output 7: General purpose output, or Channel B open-drain, active-Low, TxB interrupt ISR[4] output.
IP0 X I Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal
VCC pull-up device supplying 1 to 4 mA of current.
IP1 X I Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal
VCC pull-up device supplying 1 to 4 mA of current.
IP2 X I Input 2: General purpose input or counter/timer external clock input. Pin has an internal VCC pull-up device
supplying 1 to 4 mA of current.
IP3 X I Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
IP4 X I Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
IP5 X I Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
IP6 X I Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
VCC X I Power Supply: +5V supply input.
GND X I Ground
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 6
ABSOLUTE MAXIMUM RATINGS1
SYMBOL PARAMETER RATING UNIT
TAOperating ambient temperature range2Note 4 °C
TSTG Storage temperature range -65 to +150 °C
VCC Voltage from VCC to GND3-0.5 to +7.0 V
VSVoltage from any pin to GND3-0.5 to VCC +0.5 V
PDPackage power dissipation (DIP40) 2.8 W
PDPackage power dissipation (PLCC44) 2.4 W
PDPackage power dissipation (PQFP44) 1.78 W
Derating factor above 25_C (PDIP40) 22 mW/_C
Derating factor above 25_C (PLCC44) 19 mW/_C
Derating factor above 25_C (PQFP44) 14 mW/_C
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
DC ELECTRICAL CHARACTERISTICS1, 2
VCC = 5V ± 10%, TA = –40_C to 85_C, unless otherwise specified. LIMITS
SYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT
VIL Input low voltage 0.8 V
VIH Input high voltage (except X1/CLK) –40 to +85°C 2.5 V
VIH Input high voltage (X1/CLK) 0.8 VCC V
VOL
VOH Output low voltage
Output high voltage (except OD outputs)3IOL = 2.4mA
IOH = -400µAVCC -0.5 0.4 V
V
IIX1PD
IILX1
IIHX1
X1/CLK input current - power down
X1/CLK input low current - operating
X1/CLK input high current - operating
VIN = 0 to VCC
VIN = 0
VIN = VCC
-0.5
-130 +0.5
130
µA
µA
µA
IIInput leakage current:
All except input port pins
Input port pins VIN = 0 to VCC
VIN = 0 to VCC -0.5
-8 +0.5
+0.5 µA
µA
IOZH
IOZL Output off current high, 3-State data bus
Output off current low, 3-State data bus VIN = VCC
VIN = 0V –0.5 0.5 µA
µA
IODL
IODH Open-drain output low current in off-state
Open-drain output high current in off-state VIN = 0
VIN = VCC –0.5 0.5 µA
µA
ICC Power supply current4
Operating mode
Power down mode5CMOS input levels
CMOS input levels 5
210
15 mA
mA
NOTES:
1. Parameters are valid over specified temperature range.
2. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
3. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KΩ to VCC.
4. All outputs are disconnected. Inputs are switching between CMOS levels of VCC -0.2V and VSS + 0.2V.
5. See UART application note for power down currents of 5µA or less.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 7
AC CHARACTERISTICS1, 2, 4
VCC = 5V ± 10%, TA = –40_C to 85_C, unless otherwise specified. LIMITS
SYMBOL PARAMETER Min Typ3Max UNIT
Reset Timing (See Figure 3)
tRES RESET pulse width 200 ns
Bus Timing5 (See Figure 4)
tAS A0-A3 setup time to RDN, WRN Low 10 ns
tAH A0-A3 hold time from RDN, WRN Low 25 ns
tCS CEN setup time to RDN, WRN Low 0 ns
tCH CEN hold time from RDN, WRN High 0 ns
tRW WRN, RDN pulse width 70 ns
tDD Data valid after RDN Low 55 ns
tDF Data bus floating after RDN High 25 ns
tDS Data setup time before WRN or CEN High 25 ns
tDH Data hold time after WRN or CEN High 0 ns
tRWD High time between reads and/or writes5, 630 ns
Port Timing5 (See Figure 5)
tPS Port input setup time before RDN Low 0 ns
tPH Port input hold time after RDN High 0 ns
tPD OPn output valid from WRN High 100 ns
Interrupt Timing (See Figure 6)
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RxFIFO (RxRDY/FFULL interrupt) 100 ns
Write TxFIFO (TxRDY interrupt) 100 ns
tIR Reset command (break change interrupt) 100 ns
Stop C/T command (counter interrupt) 100 ns
Read IPCR (input port change interrupt) 100 ns
Write IMR (clear of interrupt mask bit) 100 ns
Clock Timing (See Figure 7)
tCLK X1/CLK High or Low time 50 ns
fCLK X1/CLK frequency 0.1 3.6864 8 MHz
tCTC CTCLK (IP2) High or Low time 55 ns
fCTC CTCLK (IP2) frequency 0 8 MHz
tRX RxC High or Low time (16X) 30 ns
fRX RxC frequency (16X)
(1X)80
016
1MHz
MHz
tTX TxC High or Low time (16X) 30 ns
fTX TxC frequency (16X)
(1X)80
016
1MHz
MHz
Transmitter Timing (See Figure 8)
tTXD TxD output delay from TxC external clock input on IP pin 60 ns
tTCS Output delay from TxC low at OP pin to TxD data output 5 30 ns
Receiver Timing (See Figure 9)
tRXS RxD data setup time before RxC high at external clock input on IP pin 50 ns
tRXH RxD data hold time after RxC high at external clock input on IP pin 50 ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KΩ to VCC.
5. T iming is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
7. Minimum frequencies are not tested but are guaranteed by design. Crystal frequencies 2 to 4 MHz.
8. Clocks for 1X mode should be symmetrical.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 8
Block Diagram
The SC26C92 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port.
Refer to the Block Diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus.
Interrupt Control
A single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be
asserted. The ISR can be read by the CPU to determine all
currently active interrupting conditions.
Outputs OP3-OP7 can be programmed to provide discrete interrupt
outputs for the transmitter, receivers, and counter/timer.
When OP3 to OP7 are programmed as interrupts, their output
buffers are changed to the open drain active low configuration.
These pins may be used for DMA and modem control.
TIMING CIRCUITS
Crystal Clock
The timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer , and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
X1/CLK. The clock serves as the basic timing reference for the
Baud Rate Generator (BRG), the counter/timer, and other internal
circuits. A clock signal within the limits specified in the
specifications section of this data sheet must always be supplied to
the DUART.
If an external is used instead of a crystal, X1 should be driven using
a configuration similar to the one in Figure 7.
BRG
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 27 commonly used data
communications baud rates ranging from 50 to 38.4K baud.
Programming bit 0 of MR0 to a “1” gives additional baud rates to
230.4kB. These will be in the 16X mode. A 3.6864MHz crystal or
external clock must be used to get the standard baud rates. The
clock outputs from the BRG are at 16X the actual baud rate. The
counter/timer can be used as a timer to produce a 16X clock for any
other baud rate by counting down the crystal clock or an external
clock. The four clock selectors allow the independent selection, for
each receiver and transmitter, of any of these baud rates or external
timing signal.
Counter–Timer
The Counter/T imer is a programmable 16–bit divider that is used for
generating miscellaneous clocks or generating timeout periods.
These clocks may be used by any or all of the receivers and trans-
mitters in the DUART or may be directed to an I/O pin for miscella-
neous use.
Counter/Timer programming
The counter timer is a 16–bit programmable divider that operates in
one of three modes: counter, timer, and time out.
•T imer mode generates a square wave.
•Counter mode generates a time delay.
•T ime out mode counts time between received characters.
The C/T uses the numbers loaded into the Counter/T imer Lower
Register (CTPL) and the Counter/T imer Upper Register (CTPU) as
its divisor. The counter timer is controlled with six commands: Start/
Stop C/T, Read/Write Counter/Timer lower register and Read/Write
Counter/Timer upper register. These commands have slight differ-
ences depending on the mode of operation. Please see the detail of
the commands under the CTPL/CTPU register descriptions.
Baud Rate Generation with the C/T
When the timer is selected as baud rates for receiver or transmitter
via the Clock Select register their output will be configured as a 16x
clock. Therefore one needs to program the timer to generate a
clock 16 times faster than the data rate. The formula for calculating
’n’, the number loaded to the CTPU and CTPL registers, based on a
particular input clock frequency is shown below.
For the timer mode the formula is as follows:
n= Clockinputfrequency
2 16 Baudratedesired
NOTE: ‘n’ may not assume values of 0 and 1.
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and receiv-
er state machines include divide by 16 circuits, which provide the
final frequency and provide various timing edges used in the qualify-
ing the serial data bit stream. Often this division will result in a non–
integer value: 26.3 for example. One may only program integer
numbers to a digital divider. There for 26 would be chosen. If 26.7
were the result of the division then 27 would be chosen. This gives
a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage
error of 1.14% or 1.12% respectively, well within the ability of the
asynchronous mode of operation. Higher input frequency to the
counter reduces the error effect of the fractional division
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is com-
municating may also have a small error in the precise baud rate. In
a ”clean” communications environment using one start bit, eight data
bits and one stop bit the total difference allowed between the trans-
mitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
Communications Channels A and B
Each communications channel of the SC26C92 comprises a
full-duplex asynchronous receiver/transmitter (UART). The
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 9
operating frequency for each receiver and transmitter can be
selected independently from the baud rate generator, the
counter/timer, or from an external input.
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin.
The receiver accepts serial data on the RxD pin, converts this serial
input to parallel format, checks for start bit, stop bit, parity bit (if any),
or break condition and sends an assembled character to the CPU
via the receive FIFO. Three status bits (Break Received, Framing
and Parity Errors) are also FIFOed with each data character.
Input Port
The inputs to this unlatched 7-bit port can be read by the CPU by
performing a read operation at address H’D’. A High input results in
a logic 1 while a Low input results in a logic 0. D7 will always read
as a logic 1. The pins of this port can also serve as auxiliary inputs
to certain portions of the DUART logic or modem and DMA control.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
transition of these inputs, lasting longer than 25 - 50µs, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
The input port pulse detection circuitry uses a 38.4KHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25µs (this assumes that
the clock input is 3.6864MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25µs if
the transition occurs “coincident with the first sample pulse”. The
50µs time refers to the situation in which the change-of-state is “just
missed” and the first change-of-state is not detected until 25µs later.
All the IP pins have a small pull-up device that will source 1 to 4 mA
of current from VCC. These pins do not require pull-up devices or
VCC connections if they are not used.
Output Port
The output ports are controlled from five places: the OPCR register,
SOPR, ROPR, the MR registers and the command register (CR).
The OPCR register controls the source of the data for the output
ports OP2 through OP7. The data source for output ports OP0 and
OP1 is controlled by the MR and CR registers. Normally the data
source for the OP pins is from the OPR register. The OP pin drive
the inverted level (complement) of the OPR register. Example:
when the SOPR is used to set the OPR bit to a logical 1 then the
associated OP pin will drive a logical 0.
The content of the OPR register is controlled by the “Set Output Port
Bits Command” and the “Reset Output Bits Command”. These com-
mands are at E and F, respectively. When these commands are
used, action takes place only at the bit locations where ones exist.
For example, a one in bit location 5 of the data word used with the
“Set Output Port Bits” command will result in OPR(5) being set to
one. The OP5 would then be set to zero (VSS ). Similarly, a one in
bit position 5 of the data word associated with the “Reset Output
Ports Bits” command would set OPR(5) to zero and, hence, the pin
OP5 to a one (Vdd).
Please note that these pins drive both high and low. However when
they are programmed to represent interrupt type functions (such as
RxRDY) they will be switched to an open drain configuration. In this
configuration an external pull–up device will be required
OPERATION
Transmitter
The SC26C92 is conditioned to transmit data when the transmitter is
enabled through the command register. The SC26C92 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP0, OP1 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMT bits will be set
in the status register. When a character is loaded to the transmit
FIFO the TxEMT bit will be reset. The TxEMT will not set until: 1)
the transmit FIFO is empty and the transmit shift register has
finished transmitting the stop bit of the last character written to the
transmit FIFO, or 2) the transmitter is disabled and then re–enabled.
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the TxEMT bit in the Status Register (SR) will be set to 1.
T ransmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled, it continues operating until the charac-
ter currently being transmitted and any characters in the TxFIFO
including parity and stop bit(s) have been completed.
Note the differences between the transmitter disable and the trans-
mitter reset: reset stops all transmission immediately, effectively
clears the TxFIFO and resets all status and Tx interrupt conditions.
T ransmitter disable clears all Tx status and interrupts BUT allows
the Tx to complete the transmission of all data in the TxFIFO and in
the shift register. While the Tx is disabled the TxFIFO can not be
loaded with data.
The transmitter can be forced to send a continuous Low condition by
issuing a send break command from the command register. The
transmitter output is returned to the normal high with a stop break
command.
The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation.
If the CTS option is enabled (MR2[4] = 1), the CTSN input at IP0 or
IP1 must be low in order for the character to be transmitted. The
transmitter will check the state of the CTS input at the beginning of
each character transmitted. If it is found to be High, the transmitter
will delay the transmission of any following characters until the CTS
has returned to the low state. CTS going high during the serializa-
tion of a character will not affect that character.
Transmitter “RS485 turnaround”
The transmitter can also control the RTSN outputs, OP0 or OP1 via
MR2[5]. When this mode of operation is set, the meaning of the
OP0 and OP1 signal will usually be ‘end of message’. See
description of the MR2[5] bit for more detail.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 10
This feature may be used automatically “turnaround” a transceiver
when operating in a simplex system.
Transmitter Disable Note (W.R.T. Turnaround)
When the TxEMT bit is set the sequence of instructions: enable
transmitter — load transmit holding register — disable transmitter
will often result in nothing being sent. In the condition of the TxEMT
being set do not issue the disable until the TxRDY bit goes active
again after the character is loaded to the TxFIFO. The data is not
sent if the time between the end of loading the transmit holding
register and the disable command is less that 3/16 bit time in the
16x mode. One bit time in the 1x mode.
This is sometimes the condition when the RS485 automatic “turn-
around” is enabled . It will also occur when only one character is to
be sent and it is desired to disable the transmitter immediately after
the character is loaded.
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
be sure the TxRDY bit is active immediately before issuing the
transmitter disable instruction. (TxEMT is always set if the transmit-
ter has underrun or has just been enabled), TxRDY sets at the end
of the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
Transmitter Flow control
The transmitter may be controlled by the CTSN input when enabled
by MR2(4). The CTSN input would be connected to RTSN output of
the receiver to which it is communicating. See further description in
the MR 1 and MR2 register descriptions.
Receiver
The SC26C92 is conditioned to receive data when enabled through
the command register. The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16X
clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of
the bit time clock (1X clock mode). If RxD is sampled High, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still Low, a valid start bit is assumed and the receiver continues to
sample the input at one bit time intervals at the theoretical center of
the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive FIFO and the RxRDY bit in the SR is set to a 1. This
condition can be programmed to generate an interrupt at OP4 or
OP5 and INTRN. If the character length is less than 8 bits, the most
significant unused bits in the RxFIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains Low for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
The parity error, framing error, and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected (RxD is Low for the
entire character including the stop bit), a character consisting of all
zeros will be loaded into the RxFIFO and the received break bit in
the SR is set to 1. The RxD input must return to high for two (2)
clock edges of the X1 crystal clock for the receiver to recognize the
end of the break condition and begin the search for a start bit. This
will usually require a high time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to
the X1 clock.
Receiver FIFO
The RxFIFO consists of a First-In-First-Out (FIFO) stack with a
capacity of eight characters. Data is loaded from the receive shift
register into the topmost empty position of the FIFO. The RxRDY bit
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all eight stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RxFIFO outputs the data at the top
of the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
Receiver Status Bits
There are five (5) status bits that are evaluated with each byte (or
character) received: received break, framing error, parity error, over-
run error, and change of break. The first three are appended to
each byte and stored in the RxFIFO. The last two are not necessar-
ily related to the byte being received or a byte that is in the RxFIFO.
They are however developed by the receiver state machine.
The received break, framing error, parity error and overrun error (if
any) are strobed into the RxFIFO at the received character bound-
ary, before the RxRDY status bit is set. For character mode (see
below) status reporting the SR (Status Register) indicates the condi-
tion of these bits for the character that is the next to be read from the
FIFO
The ”received break” will always be associated with a zero byte in
the RxFIFO. It means that zero character was a break character
and not a zero data byte. The reception of a break condition will
always set the ”change of break” (see below) status bit in the Inter-
rupt Status Register (ISR). The Change of break condition is reset
by a reset error status command in the command register
Break Detection
If a break condition is detected (RxD is Low for the entire character
including the stop bit), a character consisting of all zeros will be
loaded into the RxFIFO and the received break bit in the SR is set to
1. The change of break bit also sets in the ISR The RxD input must
return to high for two (2) clock edges of the X1 crystal clock for the
receiver to recognize the end of the break condition and begin the
search for a start bit.
This will usually require a high time of one X1 clock period or 3
X1 edges since the clock of the controller is not synchronous
to the X1 clock.
Framing Error
A framing error occurs when a non–zero character whose parity bit
(if used) and stop; bit are zero. If RxD remains low for one half of
the bit period after the stop bit was sampled, then the receiver
operates as if the start bit of the next character had been detected.
The parity error indicates that the receiver–generated parity was not
the same as that sent by the transmitter.
The framing, parity and received break status bits are reset when
the associated data byte is read from the RxFIFO since these “error”
conditions are attached to the byte that has the error
Overrun Error
The overrun error occurs when the RxFIFO is full, the receiver shift
register is full, and another start bit is detected. At this moment the
receiver has 9 valid characters and the start bit of the 10th has been
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 11
seen. At this point the host has approximately 6/16–bit time to read
a byte from the RxFIFO or the overrun condition will be set. The
10th character then overruns the 9th and the 11th the 10th and so on
until an open position in the RxFIFO is seen. (“seen” meaning at
least one byte was read from the RxFIFO.)
Overrun is cleared by a use of the “error reset” command in the
command register .
The fundamental meaning of the overrun is that data has been lost.
Data in the RxFIFO remains valid. The receiver will begin placing
characters in the RxFIFO as soon as a position becomes vacant.
Note: Precaution must be taken when reading an overrun FIFO.
There will be 8 valid characters in the receiver FIFO. There will
be one character in the receiver shift register. However it will
NOT be known if more than one “over–running” character has
been received since the overrun bit was set. The 9th character
is received and read as valid but it will not be known how many
characters were lost between the two characters of the 8th and
9th reads of the RxFIFO
The ”Change of break” means that either a break has been detected
or that the break condition has been cleared. This bit is available in
the ISR. The break change bit being set in the ISR and the received
break bit being set in the SR will signal the beginning of a break. At
the termination of the break condition only the change of break in
the ISR will be set. After the break condition is detected the ter-
mination of the break will only be recognized when the RxD input
has returned to the high state for two successive edges of the 1x
clock; 1/2 to 1 bit time (see above).
The receiver is disabled by reset or via CR commands. A disabled
receiver will not interrupt the host CPU under any circumstance in
the normal mode of operation. If the receiver is in the multi–drop or
special mode, it will be partially enabled and thus may cause an
interrupt. Refer to section on W ake–Up and the register description
for MR1 for more information.
Receiver Status Modes (block and character)
In addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character–by–charac-
ter basis; the status applies only to the character at the top of the
FIFO. In the ‘block’ mode, the status provided in the SR for these
three bits is the logical–OR of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command was issued.
In either mode reading the SR does not affect the FIFO. The FIFO
is ‘popped’ only when the RxFIFO is read. Therefore the status
register should be read prior to reading the FIFO.
Receiver Flow Control
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re–asserted automati-
cally. This feature can be used to prevent an overrun, in the receiv-
er, by connecting the RTSN output to the CTSN input of the
transmitting device.
Note: The transmitter may also control the “RTSN” pin. When
under transmitter control the meaning is completely changed.
The meaning is the transmission has ended. This signal is
usually used to switch (turnaround) a bi–directional driver from
transmit to receive.
If the receiver is disabled, the FIFO characters can be read. Howev-
er, no additional characters can be received until the receiver is
enabled again. If the receiver is reset, the FIFO and all of the re-
ceiver status, and the corresponding output ports and interrupt are
reset. No additional characters can be received until the receiver is
enabled again.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled in the receiver shift register is lost. Data and status in
the FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected. A receiver reset will discard
the present shift register date, reset the receiver ready bit (RxRDY),
clear the status of the byte at the top of the FIFO and re-align the
FIFO read/write pointers.
A ‘watchdog timer’ is associated with each receiver. Its interrupt is
enabled by MR0[7]. The purpose of this timer is to alert the control
processor that characters are in the RxFIFO which have not been
read and/or the data stream has stopped. This situation may occur
at the end of a transmission when the last few characters received
are not sufficient to cause an interrupt.
This counter times out after 64 bit times. It is reset each time a
character is transferred from the receiver shift register to the
RxFIFO or a read of the RxFIFO is executed.
Receiver Timeout Mode
In addition to the watch dog timer described in the receiver section,
the counter/timer may be used for a similar function. Its
programmability, of course, allows much greater precision of time
out intervals.
The timeout mode uses the received data stream to control the
counter. Each time a received character is transferred from the shift
register to the RxFIFO, the counter is restarted. If a new character
is not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the RxFIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTU and CTL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new
data during the programmed time interval, the counter ready bit will
get set, and an interrupt can be generated.
The timeout mode is enabled by writing the appropriate command to
the command register. Writing an ‘Ax’ to CRA or CRB will invoke
the timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will
disable the timeout mode. The timeout mode should only be used
by one channel at once, since it uses the C/T. If, however , the
timeout mode is enabled from both receivers, the timeout will occur
only when both receivers have stopped receiving data for the
timeout period. CTU and CTL must be loaded with a value greater
than the normal receive character period. The timeout mode
disables the regular START/STOP Counter commands and puts the
C/T into counter mode under the control of the received data stream.
Each time a received character is transferred from the shift register
to the RxFIFO, the C/T is stopped after 1 C/T clock, reloaded with
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 12
the value in CTU and CTL and then restarted on the next C/T clock.
If the C/T is allowed to end the count before a new character has
been received, the counter ready bit, ISR[3], will be set. If IMR[3] is
set, this will generate an interrupt. Receiving a character after the
C/T has timed out will clear the counter ready bit, ISR[3], and the
interrupt. Invoking the ‘Set T imeout Mode On’ command, CRx = ‘Ax’,
will also clear the counter ready bit and stop the counter until the
next character is received.
Time Out Mode Caution
When operating in the special time out mode, it is possible to
generate what appears to be a “false interrupt”, i.e., an interrupt
without a cause. This may result when a time-out interrupt occurs
and then, BEFORE the interrupt is serviced, another character is
received, i.e., the data stream has started again. (The interrupt
latency is longer than the pause in the data stream.) In this case,
when a new character has been receiver, the counter/timer will be
restarted by the receiver, thereby withdrawing its interrupt. If, at this
time, the interrupt service begins for the previously seen interrupt, a
read of the ISR will show the “Counter Ready” bit not set. If nothing
else is interrupting, this read of the ISR will return a x’00 character.
The CTS, RTS, CTS Enable Tx signals
CTS (Clear To Send) is usually meant to be a signal to the transmit-
ter meaning that it may transmit data to the receiver. The CTS input
is on pin IP0 or IP1 for the transmitter. The CTS signal is active low;
thus, it is called CTSN. RTS is usually meant to be a signal from the
receiver indicating that the receiver is ready to receive data. It is
also active low and is, thus, called RTSN. RTSN is on pin OP0 or
OP1. A receiver’s R TS output will usually be connected to the CTS
input of the associated transmitter. Therefore, one could say that
RTS and CTS are different ends of the same wire!
MR2(4) is the bit that allows the transmitter to be controlled by the
CTS pin ( IP0 or IP1). When this bit is set to one AND the CTS
input is driven high, the transmitter will stop sending data at the end
of the present character being serialized. It is usually the RTS out-
put of the receiver that will be connected to the transmitter’s CTS
input. The receiver will set RTS high when the receiver FIFO is full
AND the start bit of the ninth character is sensed. T ransmission
then stops with nine valid characters in the receiver. When MR2(4)
is set to one, CTSN must be at zero for the transmitter to operate. If
MR2(4) is set to zero, the IP0 or IP1 pin will have no effect on the
operation of the transmitter.
MR1(7) is the bit that allows the receiver to control OP0 or OP1.
When OP0 or OP1 is controlled by the receiver, the meaning of that
pin will be RTS. However, a point of confusion arises in that these
pins may also be controlled by the transmitter. When the transmit-
ter is controlling them the meaning is not RTS at all. It is, rather, that
the transmitter has finished sending its last data byte.
Programming the OP0 or OP1 pin to be controlled by the receiver
and the transmitter at the same time is allowed, but would usually be
incompatible.
RTS can also be controlled by the commands 1000 and 1001 in the
command register. RTS is expressed at the OP0 or OP1 pin which
is still an output port. Therefore, the state of OP0 or OP1 should be
set low (either by commands of the CR register or by writing to the
SOPR or ROPR (Set or Reset Output Port Registers) for the receiv-
er to generate the proper RTS signal. The logic at the output is
basically a NAND of the bit in OPR(0) or OPR(1) register and the
RTS signal as generated by the receiver. When the RTS flow con-
trol is selected via the MR1(7) bit the state of the OPR(0) or OPR(1)
register is not changed. Terminating the use of “Flow Control” (via
the MR registers) will return the OP pins pin to the control of the
OPR register.
Multidrop Mode (9-bit or W ake-Up)
The DUART is equipped with a wake up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3]
or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this
mode of operation, a ‘master’ station transmits an address character
followed by data characters for the addressed ‘slave’ station. The
slave stations, with receivers that are normally disabled, examine
the received data stream and ‘wakeup’ the CPU (by setting RxRDY)
only upon receipt of an address character. The CPU compares the
received address to its station address and enables the receiver if it
wishes to receive the subsequent data characters. Upon receipt of
another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted
A/D bit is selected by the CPU by programming bit
MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the
A/D bit position, which identifies the corresponding data bits as data
while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position,
which identifies the corresponding data bits as an address. The
CPU should program the mode register prior to loading the
corresponding data bits into the TxFIFO.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RxFIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RxFIFO. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
PROGRAMMING
The operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Each channel has 3 mode registers (MR0, 1, 2) which control the
basic configuration of the channel. Access to these registers is
controlled by independent MR address pointers. These pointers are
set to 0 or 1 by MR control commands in the command register
“Miscellaneous Commands”. Each time the MR registers are
accessed the MR pointer increments, stopping at MR2. It remains
pointing to MR2 until set to 0 or 1 via the miscellaneous commands
of the command register. The pointer is set to 1 on reset for
compatibility with previous Philips Semiconductors UART software.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 13
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved
registers at addresses H‘02’ and H‘0A’ should never be read during
normal operation since they are reserved for internal diagnostics.
Table 1. SC26C92 Register Addressing
A3 A2 A1 A0 READ (RDN = 0) WRITE (WRN = 0)
0 0 0 0 Mode Register A (MR0A, MR1A, MR2A) Mode Register A (MR0A, MR1A, MR2A)
0 0 0 1 Status Register A (SRA) Clock Select Register A (CSRA)
0 0 1 0 Reserved Command Register A (CRA)
0 0 1 1 Rx Holding Register A (RxFIFOA) Tx Holding Register A (TxFIFOA)
0 1 0 0 Input Port Change Register (IPCR) Aux. Control Register (ACR)
0 1 0 1 Interrupt Status Register (ISR) Interrupt Mask Register (IMR)
0 1 1 0 Counter/Timer Upper Value (CTU) C/T Upper Preset Value (CTPU)
0 1 1 1 Counter/Timer Lower Value (CTL) C/T Lower Preset Value (CTPL)
1 0 0 0 Mode Register B (MR0B, MR1B, MR2B) Mode Register B (MR0B, MR1B, MR2B)
1 0 0 1 Status Register B (SRB) Clock Select Register B (CSRB)
1 0 1 0 Reserved Command Register B (CRB)
1 0 1 1 Rx Holding Register B (RxFIFOB) Tx Holding Register B (TxFIFOB)
1 1 0 0 User Defined Flag/Status Flag User Defined Flag/Status Flag
1 1 0 1 Input Ports IP0 to IP6 Output Port Conf. Register (OPCR)
1 1 1 0 Start Counter Command Set Output Port Bits Command (SOP12)
1 1 1 1 Stop Counter Command Reset Output Port Bits Command (ROP12)
NOTE:
The three MR Registers are accessed via the MR Pointer and Commands 1xh and Bxh. (Where “x” represents receiver and transmitter enable/
disable control)
The following named registers are the same for Channels
A and B
Mode Register MRnA MRnB R/W
Status Register SRA SRB R only
Clock Select CSRA CSRB W only
Command Register CRA CRB W only
Receiver FIFO RxFIFOA RxFIFOB R only
T ransmitter FIFO TxFIFOA TxFIFOB W only
These registers control the functions which service both
Channels
Input Port Change Register IPCR R
Auxiliary Control Register ACR W
Interrupt Status Register ISR R
Interrupt Mask Register IMR W
Counter T imer Upper Value CTU R
Counter T imer Lower Value CTL R
Counter T imer Preset Upper CTPU W
Counter T imer Preset Lower CTPL W
Input Port Register IPR R
Output Configuration Register OPCR W
Set Output Port Bits SOPR W
Reset Output Port Bits ROPR W
Table 2. Register Bit Formats
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MR0A, MR0B
MR0B[3:0] are
d
Rx WATCH
DOG RxINT BIT 2 TxINT (1:0) DON’T
CARE BAUD RATE
EXTENDED II TEST 2 BAUD RATE
EXTENDED 1
reserved
Returns F on read 0 = Disable
1 = Enable See Tables in
MR0 description Set to 0
Returns 1 on read 0 = Normal
1 = Extend II Set to 0 0 = Normal
1 = Extend
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MR1A
MR1B
Rx CONTROLS
RTS Rx INT
BIT 1 ERROR
MODE PARITY MODE PARITY
TYPE BITS PER
CHARACTER
MR1B
0x00 0 = No
1 = Yes 0 = RxRDY
1 = FFULL 0 = Char
1 = Block
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
0 = Even
1 = Odd
00 = 5
01 = 6
10 = 7
11 = 8
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 14
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MR2A
MR2B
CHANNEL MODE Tx CONTROLS
RTS CTS
ENABLE Tx STOP BIT LENGTH*
MR2B
0x00 00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
0 = No
1 = Yes 0 = No
1 = Yes
0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875
2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
NOTE: *Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
CSRA BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CSRA
CSRB
001
RECEIVER CLOCK SELECT TRANSMITTER CLOCK SELECT
0
x
01
See Text See Text
CRA
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CRA
CRB
MISCELLANEOUS COMMANDS* DISABLE Tx ENABLE Tx DISABLE Rx ENABLE Rx
CRB
0x01 See Text 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes
NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 15
Table 2. Register Bit Formats (Continued)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SRA
SRB
001
RECEIVED
BREAK* FRAMING
ERROR* PARITY
ERROR* OVERRUN
ERROR TxEMT TxRDY FFULL RxRDY
0x01 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits
(7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are
discarded when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using
the error reset command (command 4x) or a receiver reset.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OC
OP7 OP6 OP5 OP4 OP3 OP2
OPCR
0x0D 0 = OPR[7]
1 = TxRDYB 0 = OPR[6]
1 = TxRDYA
0 = OPR[5]
1 = RxRDY/
FFULLB
0 = OPR[4]
1 = RxRDY/
FFULLA
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1X)
11 = RxCB(1X)
00 = OPR[2]
01 = TxCA(16X)
10 = TxCA(1X)
11 = RxCA(1X)
SOPR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x0E See Note See Note See Note See Note See Note See Note See Note See Note
NOTE: 0 = No Change; 1 = Set
ROPR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x0F See Note See Note See Note See Note See Note See Note See Note See Note
NOTE: 0 = No Change; 1 = Reset
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OPR
OP 7 OP 6 OP 5 OP 4 OP 3 OP 2 OP 1 OP 0
OPR
0 = Pin High
1 = Pin Low 0 = Pin High
1 = Pin Low 0 = Pin High
1 = Pin Low 0 = Pin High
1 = Pin Low 0 = Pin High
1 = Pin Low 0 = Pin High
1 = Pin Low 0 = Pin High
1 = Pin Low 0 = Pin High
1 = Pin Low
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ACR
0x04
BRG SET
SELECT COUNTER/TIMER
MODE AND SOURCE DELTA
IP 3 INT DELTA
IP 2 INT DELTA
IP 1 INT DELTA
IP 0 INT
0x04
0 = set 1
1 = set 2 See Table 6 0 = Off
1 = On 0 = Of f
1 = On 0 = Off
1 = On 0 = Off
1 = On
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IPCR
0x04
DELTA
IP 3 DELTA
IP 2 DELTA
IP 1 DELTA
IP 0 IP 3 IP 2 IP 1 IP 0
0x04
0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = Low
1 = High 0 = Low
1 = High 0 = Low
1 = High 0 = Low
1 = High
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ISR
0x05
INPUT
PORT
CHANGE
DELTA
BREAK B RxRDY/
FFULLB TxRDYB COUNTER
READY DELTA
BREAK A RxRDY/
FFULLA TxRDYA
0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes 0 = No
1 = Yes
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IMR
0x05
IN. PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDY/
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDY/
FFULLA
INT
TxRDYA
INT
0 = Off
1 = On 0 = Off
1 = On 0 = Off
1 = On 0 = Off
1 = On 0 = Off
1 = On 0 = Off
1 = On 0 = Off
1 = On 0 = Off
1 = On
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 16
CTPU
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CTPU
0x06
C/T[15] C/T[14] C/T[13] C/T[12] C/T[11] C/T[10] C/T[9] C/T[8]
0x06
CTPL
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CTPL
0x07
C/T[7] C/T[6] C/T[5] C/T[4] C/T[3] C/T[2] C/T[1] C/T[0]
0x07
REGISTER DESCRIPTIONS Mode Registers
MR0 is accessed by setting the MR pointer to 0 via the command
register command B.
MR0A
MR0[7] – This bit controls the receiver watch dog timer. 0 = disable,
1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6] – Bit 2 of receiver FIFO interrupt level. This bit along with Bit
6 of MR1 sets the fill level of the 8 byte FIFO that generates the
receiver interrupt.
Table 3. Receiver FIFO Interrupt Fill Level
MR0[6] MR1[6] Interrupt Condition
0 0 1 or more bytes in FIFO
(Rx RDY)
0 1 3 or more bytes in FIFO
1 0 6 or more bytes in FIFO
1 1 8 bytes in FIFO
(Rx FULL)
For the receiver these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
MR0[5:4] – Tx interrupt fill level.
Table 4. Transmitter FIFO Interrupt Fill Level
MR0[5] MR0[4] Interrupt Condition
0 0 8 bytes empty
(Tx EMPTY)
0 1 4 or more bytes empty
1 0 6 or more bytes empty
1 1 1 or more bytes empty
(Tx RDY)
For the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is completely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
MR0[3] – Not used. Should be set to 0.
MR0[2:0] – These bits are used to select one of the six baud rates
(see Table 5).
000 Normal mode
001 Extended mode I
100 Extended mode II
Other combinations should not be used
Note: MR0[3:0] are not used in channel B and should be set to 0.
MR1A
MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CR command 1. After reading or writing MR1A, the
pointer will point to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Control
(Flow Control)
This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0].
MR1A[7] = 1 causes RTSAN to be negated (OP0 is driven to a ‘1’
[VCC]) upon receipt of a valid start bit if the Channel A FIFO is full.
This is the beginning of the reception of the ninth byte. If the FIFO is
not read before the start of the tenth byte, an overrun condition will
occur and the tenth byte will be lost. However, the bit in OPR[0] is
not reset and RTSAN will be asserted again when an empty FIFO
position is available. This feature can be used for flow control to
prevent overrun in the receiver by using the RTSAN output signal to
control the CTSN input of the transmitting device.
MR1[6] – Bit 1 of the receiver interrupt control. See description
under MR0[6].
MR1A[5] – Channel A Error Mode Select
This bit select the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
MR1A[4:3| – Channel A Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it
selects the polarity of the A/D bit.
MR1A[1:0] – Channel A Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 17
MR2A – Channel A Mode Register 2
MR2A is accessed when the Channel A MR pointer points to MR2,
which occurs after any access to MR1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6] – Channel A Mode Select
Each channel of the DUART can operate in one of four modes.
MR2A[7:6] = 00 is the normal mode, with the transmitter and
receiver operating independently.
MR2A[7:6] = 01 places the channel in the automatic echo mode,
which automatically retransmits the received data. The following
conditions are true while in automatic echo mode:
1. Received data is reclocked and retransmitted on the TxDA out-
put.
2. The receive clock is used for the transmitter. Data is received on
the rising edge of the RxC1x clock and retransmitted on the next
fall of the RxC!x clock.
3. The receiver must be enabled, but the transmitter need not be
enabled.
4. The Channel A TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for trans-
mission, i.e. transmitted parity bit is as received.
6. Character framing is checked, but the stop bits are retransmitted
as received.
7. A received break is echoed as received until the next valid start
bit is detected.
8. CPU to receiver communication continues normally , but the CPU
to transmitter link is disabled.
MR2A(7:6) = 10 selects the local loop back diagnostic mode. In this
mode:
1. The transmitter output is internally connected to the receiver
input.
2. The transmit clock is used for the receiver.
3. The TxDA output is held High.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the receiver need not be
enabled.
6. CPU to transmitter and receiver communications continue nor-
mally.
MR2A[7:6] = 11 selects a remote loop back diagnostic mode. In this
mode:
1. Received data is reclocked and retransmitted on the TxDA out-
put.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status
conditions are inactive.
4. The received parity is not checked and is not regenerated for
transmission, i.e., transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked, and the stop bits are retrans-
mitted as received.
7. A received break is echoed as received until the next valid start
bit is detected.
8. A delay of one bit time is seen at the remote receiver.
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes: if the
de-selection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop has been re-transmitted.
MR2A[5] – Channel A Transmitter Request-to-Send Control
This bit controls the deactivation of the RTSAN output (OP0) by the
transmitter. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0].
MR2A[5] = 1 caused OPR[0] to be reset automatically one bit time
after the characters in the Channel A transmit shift register and in
the TxFIFO, if any , are completely transmitted including the
programmed number of stop bits. If the transmitter is not enabled,
this feature can be used to automatically terminate the transmission
of a message as follows:
1. Program auto-reset mode: MR2A[5] = 1.
2. Enable transmitter.
3. Asset RTSAN: OPR[0] = 1.
4. Send message.
5. Disable transmitter after the last character is loaded into the
Channel A TxFIFO. Tx status and Tx interrupts will be disabled
at this time.
6. The last character will be transmitted and OPR[0] will be reset
one bit time after the last stop bit, causing RTSAN to be negated.
In this mode, the meaning of “RTSAN” is that the transmission is
ended.
MR2A[4] – Channel A Clear-to-Send Control
If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a
1, the transmitter checks the state of CTSAN (IPO) each time it is
ready to send a character. If IPO is asserted (Low), the character is
transmitted. If it is negated (High), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes
low. Changes in CTSAN while a character is being transmitted do
not affect the transmission of that character..
MR2A[3:0] – Channel A Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1-9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1-1/16
to 2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a ‘mark’ condition at the center
of the stop bit position (one–half bit time after the last data bit, or
after the parity bit if enabled is sampled).
If an external 1X clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted.
MR0B – Channel B Mode Register 0
MR0B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR0 by RESET or by a ‘set pointer’ command
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 18
applied via CRB. After reading or writing MR0B, the pointer will
point to MR1B.
The bit definitions for this register are identical to MR0A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs. MR0B[3:0] are reserved.
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will
point to MR2B.
The bit definitions for this register are identical to MR1A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs.
MR2B – Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode register are identical to the bit
definitions for MR2A, except that all control actions apply to the
Channel B receiver and transmitter and the corresponding inputs
and outputs.
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A receiver.
The field definition is shown in Table 5.
CSRB[7:4] ACR[7] = 0 ACR[7] = 1
1110
1111 IP4-16X
IP4-1X IP4-16X
IP4-1X
The receiver clock is always a 16X clock except for CSRB[7:4] = 1111.
CSRA[3:0] – Channel A Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as shown in Table 5, except as follows:
CSRA[3:0] ACR[7] = 0 ACR[7] = 1
1110
1111 IP3-16X
IP3-1X IP3-16X
IP3-1X
The transmitter clock is always a 16X clock except for CSR[3:0] = 1111.
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock Select
This field selects the baud rate clock for the Channel B receiver.
The field definition is as shown in Table 5, except as follows:
CSRB[7:4] ACR[7] = 0 ACR[7] = 1
1110
1111 IP6-16X
IP6-1X IP6-16X
IP6-1X
The receiver clock is always a 16X clock except for CSRB[7:4] = 1111.
CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as shown in Table 5, except as follows:
CSRB[3:0] ACR[7] = 0 ACR[7] = 1
1110
1111 IP5-16X
IP5-1X IP5-16X
IP5-1X
The transmitter clock is always a 16X clock except for
CSRB[3:0] = 1111.
Table 5. Baud Rate (Base on a 3.6864MHz crystal clock)
MR0[0] = 0 (Normal Mode) MR0[0] = 1 (Extended Mode I) MR0[2] = 1 (Extended Mode II)
CSRA[7:4] ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1
0000 50 75 300 450 4,800 7,200
0001 110 110 110 110 880 880
0010 134.5 134.5 134.5 134.5 1,076 1,076
0011 200 150 1200 900 19.2K 14.4K
0100 300 300 1800 1800 28.8K 28.8K
0101 600 600 3600 3600 57.6K 57.6K
0110 1,200 1,200 7200 7,200 115.2K 115.2K
0111 1,050 2,000 1,050 2,000 1,050 2,000
1000 2,400 2,400 14.4K 14.4K 57.6K 57.6K
1001 4,800 4,800 28.8K 28.8K 4,800 4,800
1010 7,200 1,800 7,200 1,800 57.6K 14.4K
1011 9,600 9,600 57.6K 57.6K 9,600 9,600
1100 38.4K 19.2K 230.4K 115.2K 38.4K 19.2K
1101 Timer T imer Timer Timer Timer Timer
1110 IP4-16X IP4-16X IP4-16X IP4-16X IP4-16X IP4-16X
1111 IP4-1X IP4-1X IP4-1X IP4-1X IP4-1X IP4-1X
NOTE: The receiver clock is always a 16X clock except for CSRA[7:4] = 1111.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 19
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
CRA[7:4] – Miscellaneous Commands
Execution of the commands in the upper four bits of this register
must be separated by 3 X1 clock edges. Other reads or writes
(including writes tot he lower four bits) may be inserted to achieve
this separation.
CRA[7:4] – Command
0000 No command.
0001 Reset MR pointer. Causes the Channel A MR pointer to point
to MR1.
0010 Reset receiver. Resets the Channel A receiver as if a
hardware reset had been applied. The receiver is disabled
and the FIFO is flushed.
0011 Reset transmitter. Resets the Channel A transmitter as if a
hardware reset had been applied.
0100 R eset error status. Clears the Channel A Received Break, Parity
Error, and Overrun Error bits in the status register (SRA[7:4]).
Used in character mode to clear OE status (although RB, PE
and FE bits will also be cleared) and in block mode to clear all
error status after a block of data has been received.
0101 Reset Channel A break change interrupt. Causes the
Channel A break detect change bit in the interrupt status
register (ISR[2]) to be cleared to zero.
0110 Start break. Forces the TxDA output Low (spacing). If the
transmitter is empty the start of the break condition will be
delayed up to two bit times. If the transmitter is active the
break begins when transmission of the character is
completed. If a character is in the TxFIFO, the start of the
break will be delayed until that character, or any other loaded
subsequently are transmitted. The transmitter must be
enabled for this command to be accepted.
0111 Stop break. The TxDA line will go High (marking) within two
bit times. TxDA will remain High for one bit time before the
next character, if any, is transmitted.
1000 Assert RTSN. Causes the RTSN output to be asserted
(Low).
1001 Negate RTSN. Causes the RTSN output to be negated
(High).
1010 Set T imeout Mode On. The receiver in this channel will
restart the C/T as each receive character is transferred from
the shift register to the RxFIFO. The C/T is placed in the
counter mode, the START/STOP counter commands are
disabled, the counter is stopped, and the Counter Ready Bit,
ISR[3], is reset. (See also W atchdog timer description in the
receiver section.)
1011 Set MR pointer to ‘0’
1100 Disable T imeout Mode. This command returns control of the
C/T to the regular START/STOP counter commands. It does
not stop the counter, or clear any pending interrupts. After
disabling the timeout mode, a ‘Stop Counter’ command
should be issued to force a reset of the ISR(3) bit.
1101 Not used.
1110 Power Down Mode On. In this mode, the DUART oscillator is
stopped and all functions requiring this clock are suspended.
The execution of commands other than disable power down
mode (1111) requires a X1/CLK. While in the power down
mode, do not issue any commands to the CR except the
disable power down mode command. The contents of all
registers will be saved while in this mode. . It is
recommended that the transmitter and receiver be disabled
prior to placing the DUART into power down mode. This
command is in CRA only.
1111 Disable Power Down Mode. This command restarts the
oscillator. After invoking this command, wait for the oscillator
to start up before writing further commands to the CR. This
command is in CRA only. For maximum power reduction
input pins should be at VSS or VDD.
CRA[3] – Disable Channel A Transmitter
This command terminates transmitter operation and reset the
TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the TxFIFO when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state.
CRA[2] – Enable Channel A Transmitter
Enables operation of the Channel A transmitter. The TxRDY and
TxEMT status bits will be asserted if the transmitter is idle.
CRA[1] – Disable Channel A Receiver
This command terminates operation of the receiver immediately – a
character being received will be lost. The command has no effect
on the receiver status bits or any other control registers. If the
special multidrop mode is programmed, the receiver operates even
if it is disabled. See Operation section.
CRA[0] – Enable Channel A Receiver
Enables operation of the Channel A receiver. If not in the special
wakeup mode, this also forces the receiver into the search for
start-bit state.
CRB – Channel B Command Register
CRB is a register used to supply commands to Channel B. Multiple
commands can be specified in a single write to CRB as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
The bit definitions for this register are identical to the bit definitions
for CRA, with the exception of commands “Ex” and “Fx” which are
used for power downmode. These two commands are not used in
CRB. All other control actions that apply to CRA also apply to CRB.
SRA – Channel A Status Register
SRA[7] – Channel A Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received: further entries to the
FIFO are inhibited until the RxDA line returns to the marking state
for at least one-half a bit time two successive edges of the internal
or external 1X clock. This will usually require a high time of one
X1 clock period or 3 X1 edges since the clock of the controller
is not synchronous to the X1 clock.
When this bit is set, the Channel A ‘change in break’ bit in the ISR
(ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected.
The break detect circuitry can detect breaks that originate in the
middle of a received character. However, if a break begins in the
middle of a character, it must persist until at least the end of the next
character time in order for it to be detected.
This bit is reset by command 4 (0100) written to the command
register or by receiver reset.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 20
SRA[6] – Channel A Framing Error
This bit, when set, indicates that a stop bit was not detected (not a
logical 1) when the corresponding data character in the FIFO was
received. The stop bit check is made in the middle of the first stop
bit position.
SRA[5] – Channel A Parity Error
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity.
In the special multidrop mode the parity error bit stores the receive
A/D (Address/Data) bit.
SRA[4] – Channel A Overrun Error
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost.
This bit is cleared by a ‘reset error status’ command.
SRA[3] – Channel A Transmitter Empty (TxEMTA)
This bit will be set when the transmitter underruns, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when
the transmitter is first enabled and at any time it is re-enabled after
either (a) reset, or (b) the transmitter has assumed the disabled
state. It is always set after transmission of the last stop bit of a
character if no character is in the THR awaiting transmission.
It is reset when the THR is loaded by the CPU, a pending
transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the underrun condition.
SRA[2] – Channel A Transmitter Ready (TxRDYA)
This bit, when set, indicates that the transmit FIFO is not full and
ready to be loaded with another character. This bit is cleared when
the transmit FIFO is loaded by the CPU and there are (after this
load) no more empty locations in the FIFO. It is set when a
character is transferred to the transmit shift register. TxRDYA is
reset when the transmitter is disabled and is set when the
transmitter is first enabled. Characters loaded to the TxFIFO while
this bit is 0 will be lost. This bit has different meaning from ISR[0].
SRA[1] – Channel A FIFO Full (FFULLA)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all eight FIFO positions are occupied. It is reset
when the CPU reads the receive FIFO. If a character is waiting in
the receive shift register because the FIFO is full, FFULLA will not
be reset when the CPU reads the receive FIFO. This bit has
different meaning from ISR1 when MR1 6 is programmed to a ‘1’.
SRA[0] – Channel A Receiver Ready (RxRDYA)
This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the FIFO and reset
when the CPU reads the receive FIFO, only if (after this read) there
are no more characters in the FIFO. The RxFIFO becomes empty.
SRB – Channel B Status Register
The bit definitions for this register are identical to the bit definitions
for SRA, except that all status applies to the Channel B receiver and
transmitter and the corresponding inputs and outputs.
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
0 The complement of OPR[7].
1 The Channel B transmitter interrupt output which is the comple-
ment of ISR[4]. When in this mode OP7 acts as an open- drain
output. Note that this output is not masked by the contents of the
IMR.
OPCR[6] – OP6 Output Select
This bit programs the OP6 output to provide one of the following:
0 The complement of OPR[6].
1 The Channel A transmitter interrupt output which is the comple-
ment of ISR[0]. When in this mode OP6 acts as an open- drain
output. Note that this output is not masked by the contents of the
IMR.
OPCR[5] – OP5 Output Select
This bit programs the OP5 output to provide one of the following:
0 The complement of OPR[5].
1 The Channel B receiver interrupt output which is the complement
of ISR[5]. When in this mode OP5 acts as an open-drain output.
Note that this output is not masked by the contents of the IMR.
OPCR[4] – OP4 Output Select
This field programs the OP4 output to provide one of the following:
0 The complement of OPR[4].
1 The Channel A receiver interrupt output which is the complement
of ISR[1]. When in this mode OP4 acts as an open-drain output.
Note that this output is not masked by the contents of the IMR.
OPCR[3:2] – OP3 Output Select
This bit programs the OP3 output to provide one of the following:
00 The complement of OPR[3].
01 The counter/timer output, in which case OP3 acts as an open-
drain output. In the timer mode, this output is a square wave at
the programmed frequency. In the counter mode, the output
remains High until terminal count is reached, at which time it
goes Low. The output returns to the High state when the counter
is stopped by a stop counter command. Note that this output is
not masked by the contents of the IMR.
10 The 1X clock for the Channel B transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted, a
free running 1X clock is output.
11 The 1X clock for the Channel B receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1X clock is output.
OPCR[1:0] – OP2 Output Select
This field programs the OP2 output to provide one of the following:
00 The complement of OPR[2].
01 The 16X clock for the Channel A transmitter. This is the clock
selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] =
1111.
10 The 1X clock for the Channel A transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted, a
free running 1X clock is output.
11 The 1X clock for the Channel A receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1X clock is output.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 21
SOPR – Set the Output Port Bits (OPR)
SOPR[7:0] – Ones in the byte written to this register will cause the
corresponding bit positions in the OPR to set to 1. Zeros have no
effect.
ROPR – Reset Output Port Bits (OPR)
ROPR[7:0] – Ones in the byte written to the ROPR will cause the
corresponding bit positions in the OPR to set to 0. Zeros have no effect.
Table 6. Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
NORMAL RATE
(BAUD) ACTUAL 16X
CLOCK (kHz) ERROR (%)
50 0.8 0
75 1.2 0
110 1.759 -0.069
134.5 2.153 0.059
150 2.4 0
200 3.2 0
300 4.8 0
600 9.6 0
1050 16.756 -0.260
1200 19.2 0
1800 28.8 0
2000 32.056 0.175
2400 38.4 0
4800 76.8 0
7200 115.2 0
9600 153.6 0
14.4K 230.4 0
19.2K 307.2 0
28.8K 460.8 0
38.4K 614.4 0
57.6K 921.6 0
115.2K 1843.2K 0
230.4K 3686.4K 0
NOTE: Duty cycle of 16X clock is 50% ± 1%.
Asynchronous UART communications can tolerate frequency error
of 4.1% to 6.7% in a “clean” communications channel. The percent
of error changes as the character length changes. The above
percentages range from 5 bits not parity to 8 bits with parity and one
stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a
stop bit length of 9/16 is used, the error tolerance will approach 0
due to a variable error of up to 1/16 bit time in receiver clock phase
alignment to the start bit.
ACR – Auxiliary Control Register
ACR[7] – Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG (see Table 5).
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 6.
Table 7. ACR 6:4 Field Definition
ACR
6:4 MODE CLOCK SOURCE
000 Counter External (IP2)
001 Counter TxCA – 1X clock of Channel A
transmitter
010 Counter TxCB – 1X clock of Channel B
transmitter
011 Counter Crystal or external clock
(X1/CLK) divided by 16
100 T imer (square wave) External (IP2)
101 T imer (square wave) External (IP2) divided by 16
110 Timer (square wave) Crystal or external clock
(X1/CLK)
111 T imer (square wave) Crystal or external clock
(X1/CLK) divided by 16
NOTE: The timer mode generates a squarewave.
ACR[6:4] – Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 7.
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR[7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR[7], which results in
the generation of an interrupt output if IMR[7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
IPCR – Input Port Change Register
IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR[7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
IPCR[3:0] – IP3, IP2, IP1, IP0 Change-of-State
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins at the
time the IPCR is read.
ISR – Interrupt Status Register
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the Interrupt Mask
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit
in the IMR is also a ‘1’, the INTRN output will be asserted (Low). If
the corresponding bit in the IMR is a zero, the state of the bit in the
ISR has no effect on the INTRN output. Note that the IMR does not
mask the reading of the ISR – the true status will be provided
regardless of the contents of the IMR. The contents of this register
are initialized to H‘00’ when the DUAR T is reset.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 22
ISR[7] – Input Port Change Status
This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.
ISR[6] – Channel B Change In Break
This bit, when set, indicates that the Channel B receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel B ‘reset break change interrupt’
command.
ISR[5] – RxB Interrupt
This bit indicates that the channel B receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.
ISR[4] – TxB Interrupt
This bit indicates that the channel B transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.
ISR[3] – Counter Ready.
In the counter mode, this bit is set when the counter reaches
terminal count and is reset when the counter is stopped by a stop
counter command.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time that the counter/timer reaches zero
count). The bit is reset by a stop counter command. The command,
however, does not stop the counter/timer.
ISR[2] – Channel A Change in Break
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel A ‘reset break change interrupt’
command.
ISR[1] – RxA Interrupt
This bit indicates that the channel A receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.
ISR[0] – TxA Interrupt
This bit indicates that the channel A transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.
IMR – Interrupt Mask Register
The programming of this register selects which bits in the ISR
causes an interrupt output. If a bit in the ISR is a ‘1’ and the
corresponding bit in the IMR is also a ‘1’ the INTRN output will be
asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the
IMR does not mask the programmable interrupt outputs OP3-OP7 or
the reading of the ISR.
CTPU and CTPL – Counter/Timer Registers
The CTPU and CTPL hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which
may be loaded into the CTPU/CTPL registers is H‘0002’. Note that
these registers are write-only and cannot be read by the CPU.
In the timer mode, the C/T generates a square wave whose period is
twice the value (in C/T clock periods) of the CTPU and CTPL. The
waveform so generated is often used for a data clock. The formula
for calculating the divisor n to load to the CTPU and CTPL for a
particular 1X data clock is shown below.
n+counter clock frequency
16x2xbaud rate desired
Often this division will result in a non-integer number; 26.3, for
example. One can only program integer numbers in a digital divider.
Therefore, 26 would be chosen. This gives a baud rate error of
0.3/26.3 which is 1.14%; well within the ability asynchronous mode
of operation.
If the value in CTPU and CTPL is changed, the current half-period
will not be affected, but subsequent half periods will be. The C/T will
not be running until it receives an initial ‘Start Counter’ command
(read at address A3-A0 = 1110). After this, while in timer mode, the
C/T will run continuously. Receipt of a start counter command (read
with A3-A0 = 1110) causes the counter to terminate the current
timing cycle and to begin a new cycle using the values in CTPU and
CTPL.
The counter ready status bit (ISR[3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command (read
with A3-A0 = H’F’). The command however, does not stop the C/T.
The generated square wave is output on OP3 if it is programmed
to be the C/T output.
In the counter mode, the value C/T loaded into CTPU and CTPL by
the CPU is counted down to 0.. Counting begins upon receipt of a
start counter command. Upon reaching terminal count H‘0000’, the
counter ready interrupt bit (ISR[3]) is set. The counter continues
counting past the terminal count until stopped by the CPU. If OP3 is
programmed to be the output of the C/T, the output remains High
until terminal count is reached, at which time it goes Low. The
output returns to the High state and ISR[3] is cleared when the
counter is stopped by a stop counter command. The CPU may
change the values of CTPU and CTPL at any time, but the new
count becomes effective only on the next start counter commands.
If new values have not been loaded, the previous count values are
preserved and used for the next count cycle
In the counter mode, the current value of the upper and lower 8 bits
of the counter (CTU, CTL) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent
potential problems which may occur if a carry from the lower 8 bits
to the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTPU and CTPL.
When the C/T clock divided by 16 is selected, the maximum divisor
becomes 1,048,575.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 23
RESETN
tRES
SD00133
Figure 3. Reset Timing
A0–A3
CEN
tAS
tCS tCH
RDN
tRW tRWD
D0–D7
(READ)
tDD tDF
FLOAT FLOATVALID
NOT
VALID
WDN
tRWD
VALID
D0–D7
(WRITE)
tDS
tDH
tAH
SD00087
Figure 4. Bus Timing
(b) OUTPUT PINS
RDN
IP0–IP6
WRN
OP0–OP7
tPS tPH
tPD
OLD DATA NEW DATA
(a) INPUT PINS
SD00135
Figure 5. Port Timing
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 24
NOTES:
1. INTRN or OP3-OP7 when used as interrupt outputs.
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
test environment are pronounced and can greatly affect the resultant measurement.
VM
VOL +0.5V
VOL
WRN
INTERRUPT1
OUTPUT
tIR
VM
VOL +0.5V
VOL
RDN
INTERRUPT1
OUTPUT
tIR
SD00136
Figure 6. Interrupt Timing
C1 = C2 ∼ 24pF FOR CL = 20pF
tCLK
tCTC
tRx
tTx
X1/CLK
CTCLK
RxC
TxC
tCLK
tCTC
tRx
tTx
+5V
470Ω
X1
X2*
CLK
*NOTE: X2 MUST BE LEFT OPEN.
X2
3.6864MHz
X1
C1
C2
SC26C92
NOTE:
RESISTOR REQUIRED
FOR TTL INPUT.
TO UART
CIRCUIT
50kΩ
to
100kΩ
3pF
3pF
C1 and C2 should be chosen according to the crystal manufacturer’s specification.
C1 and C2 values will include any parasitic capacitance of the wiring and X1 X2 pins.
Gain at 3.6864MHz: 9 to 13 dB
Phase at 3.6864MHz: 272 to 276 degrees.
2pF
4pF
Package capacitance approximately 4pF.
SD00697
Figure 7. Clock Timing
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 25
tTXD
tTCS
1 BIT TIME
(1 OR 16 CLOCKS)
TxD
TxC
(INPUT)
TxC
(1X OUTPUT)
SD00138
Figure 8. Transmitter External Clocks
tRXS tRXH
RxC
(1X INPUT)
RxD
SD00139
Figure 9. Receiver External Clock
TRANSMITTER
ENABLED
TxD D1 D2 D3 D4 D6BREAK
TxRDY
(SR2)
WRN
D1 D8 D9 D10 D12START
BREAK STOP
BREAK D11 WILL
NOT BE
WRITTEN TO
THE TxFIFO
CTSN1
(IP0)
RTSN2
(OP0)
OPR(0) = 1 OPR(0) = 1
NOTES:
1. Timing shown for MR2(4) = 1.
2. Timing shown for MR2(5) = 1.
SD00155
Figure 10. Transmitter Timing
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 26
D1 D2 D8 D9 D10 D11 D12 D13
RxD
D12, D13 WILL BE LOST
DUE TO RECEIVER DISABLE.
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDY/
FFULL
(OP5)2
RDN
STATUS DATA
D1
STATUS DATA
D2
STATUS DATA
D3
STATUS DATA
D10
D11 WILL BE LOST
DUE TO OVERRUN
OVERRUN
(SR4) RESET BY COMMAND
RTS1
(OP0)
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1.
2. Shown for OPCR(4) = 1 and MR(6) = 0.
SD00156
Figure 11. Receiver Timing
TRANSMITTER
ENABLED
TxD ADD#1
TxRDY
(SR2)
WRN
MR1(4–3) = 11
MR1(2) = 1
1
BIT 9
D0 0
BIT 9
ADD#2 1
BIT 9
MASTER STATION
ADD#1MR1(2) = 0 D0 MR1(2) = 1 ADD#2
RxD ADD#1 1
BIT 9
D0 0
BIT 9
ADD#2 1
BIT 9
PERIPHERAL STATION
0
BIT 9
0
BIT 9
RECEIVER
ENABLED
RxRDY
(SR0)
RDN/WRN
MR1(4–3) = 11 ADD#1 STATUS DATA
D0
STATUS DATA
ADD#2
SD00096
Figure 12. Wake-Up Mode
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31 27
INTRN
D0–D7
TxDA/B
OP0–OP7
50pF
+5V
2.7K
150pF
+5V
I = 2.4mA VOL
I = 400µA VOH
SD00157
Figure 13. Test Conditions on Outputs
Dual universal asynchronous receiver/transmitter
(DUART)
Philips Semiconductors Product specification
SC26C92
2000 Jan 31 28
DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1
Dual universal asynchronous receiver/transmitter
(DUART)
Philips Semiconductors Product specification
SC26C92
2000 Jan 31 29
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
Dual universal asynchronous receiver/transmitter
(DUART)
Philips Semiconductors Product specification
SC26C92
2000 Jan 31 30
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
Dual universal asynchronous receiver/transmitter
(DUART)
Philips Semiconductors Product specification
SC26C92
2000 Jan 31 31
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Date of release: 01-00
Document order number: 9397 750 06829
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
