SE050 Plug & Trust Secure Element Rev. 1.3 -- 7 June 2019 504913 1 Objective data sheet Introduction The SE050 is a ready-to-use IoT secure element solution. It provides a root of trust at the IC level and it gives an IoT system state-of-the-art, edge-to-cloud security capability right out of the box. SE050 allows for securely storing and provisioning credentials and performing cryptographic operations for security critical communication and control functions. SE050 is versatile in IoT security use cases such as secure connection to public/private clouds, device-to-device authentication or protection of sensor data. SE050 has an independent Common Criteria EAL 6+ security certification up to OS level and supports both RSA & ECC asymmetric cryptographic algorithms with high key length and future proof ECC curves. The latest security measures protect the IC even against sophisticated non-invasive and invasive attack scenarios. The SE050 is a turnkey solution that comes with Java Card operating system and an applet optimized for IoT security use cases pre-installed. This is complemented by a comprehensive product support package, enabling fast time to market & easy designin with Plug & Trust middleware for host applications, easy to use development kits, reference designs, and extensive documentation for product evaluation. The SE050 is a product platform that comes in several pin-to-pin compatible product variants, see [4]. Additional information on the integration can be found in several application notes on www.nxp.com. Also see [3]. 1.1 SE050 use cases * * * * * * * * * Secure connection to public/private clouds, edge computing platforms, infrastructure Device-to-device authentication Secure data protection Secure commissioning support Secure CL/MIFARE/Wi-Fi interactions Device ID for blockchain Secure key storage Secure provisioning of credentials Ecosystem protection 1.2 SE050 target applications * * * * Smart Industry Smart Home Smart Cities Smart Supply Chains SE050 NXP Semiconductors Plug & Trust Secure Element SE050 Host MCU/MPU Plug & Trust MW NFC DEVICE SENSOR IoT APPLET I2C 14443 JCOP OS I2C 14443 7816 SDA SCL SDA SCL SCL SDA LA LB CLK IO2: SCL RST IO:SDA I2C slave SW I2C master aaa-032990 Figure 1.SE050 solution block diagram Note: SE050 is designed to be used as a part of an IoT system. It works as an auxiliary security device attached to a host controller. The host controller communicates with SE050 through an IC interface (with the host controller being the master and the SE050 being the slave). Besides the mandatory connection to the host controller, the SE050 device can optionally be connected to a sensor node or similar element through a separate IC interface. In this case, the SE050 device is the master and the sensor node the slave. Lastly, SE050 has a connection for a native contactless antenna, providing a wireless interface to an external device like a smartphone. 1.3 SE050 naming convention The following table explains the naming conventions of the commercial product name of the SE050 platform. Every SE050 product gets assigned a commercial name, which includes application specific data. The SE050 commercial names have the following format. Sx05yagddd/Zrrff All letters are explained in Table 1 . Table 1.SE050 commercial name format Variable Meaning Values Description x Interfaces E E=I C Slave, Master, y JCOP version 0 a Applet Config A B C Configuration options with different key provisioning options, see [4] g Temperature range 1 2 standard operational ambient temperature 1 = -25 C - 90 C , 2 = -40 C - 105 C ddd Delivery Type HQ1 HX2QFN20 Letters and numbers NXP internal code to identify individual configurations mrrff SE050 Objective data sheet 2 All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 2 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 2 Features and benefits 2.1 Key benefits * Plug & Trust for fast and easy design with complete product support package * Easy integration with different MCU & MPU platforms and OS (Linux, RTOS, Windows, Android, etc.) * Turnkey solution ideal for system-level security without the need to write security code * Secure credential injection for root of trust at IC level * Secure, zero-touch connectivity to public & private clouds * Real end-to-end security, from sensor to cloud * Ready-to-use example code for each of the key use cases 2.2 Key features The SE050 is based on NXP's Integral Security Architecture 3.0TM providing a secure and efficient protection against various security threats. The efficiency of the security measures is proven by a Common Criteria EAL6+ certification. The SE050 operates fully autonomously based on an integrated Javacard operating system and applet. Direct memory access is possible by the fixed functionalities of the applet only. With that, the content from the memory is fully isolated from the host system. * Built on NXP Integral Security Architecture 3.0 TM * Uses advanced 40 nm silicon foundry technology * CC EAL 6+ certified HW and OS as environment to run NXP IoT applications, supporting fully encrypted communications and secured lifecycle management * Effective protection against advanced attacks, including Power Analysis and Fault Attacks of various kinds * Multiple logical and physical protection layers, including metal shielding, end-to-end encryption, memory encryption, tamper detection * Support for RSA and ECC asymmetric cryptography algorithms, future proof curves and high key length, e.g. Brainpool, Edwards and Montgomery curves * Support for AES and DES symmetric cryptographic algorithms for encryption and decryption * HMAC, CMAC, SHA-1, SHA-224/256/384/512 operations * Various options for key derivation functions, including HKDF, MIFARE KDF, PRF (TLSPSK) * Optional extended temperature range for industrial applications (-40 C to +105 C) * Small footprint HX2QFN20 package (3x3 mm) 2 2 * Standard physical interface I C slave (High-speed mode, 3.4 Mbps), I C master (Fast mode, 400 kbps). Both can be active at the same time * Dedicated CL wireless interface for IoT use cases simplifying configuration set-up, maintenance in the field and late stage configuration * Secured user flash memory up to 50 kB for secure data or key storage * Support for SCP03 protocol (bus encryption and encrypted credential injection) to securely bind the host with the secure element * Support for applet level secure messaging channels to allow end-to-end encrypted communication in multi-tenant ecosystems SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 3 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 2.3 Features in detail Table 2.Feature Overview Categories Subcategory Value Standards Security certification CC EAL6+ (HW+JCOP) JavaCard version 3.0.5 GlobalPlatform specification version GP 3.0 ECC ECDSA, ECDH, ECDHE, ECDAA, EDDSA Hash HMAC, secure HMAC, CMAC SHA SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 Key derivation HKDF, PBKDF, Wi-Fi KDF,OPC_UA KDF PRF (TLS-PSK) AES AES cipher for de-/encryption RSA RSA cipher for de-/encryption (up to 4096 bit) ECC ECC NIST (192 to 521 bit) Cryptography Crypto curves Brainpool (160 to 512 bit) Twisted Edwards Ed25519 Montgomery Curve25519 Koblitz (192 to 256 bit) Barreto-Naehrig Curve 256 bit 50 kB User memory up to 100 Mio write cycles / 25 years Memory reliability Interfaces Power saving modes Temperature Packaging SE050 Objective data sheet 2 High-speed mode (3.4 Mbps) 2 I C Master Fast Mode (400 kbit/s) Contactless ISO14443 Idle ~1.8 mA Power-Down (with state retention) ~430 A Deep Power-Down (no state retention) <5 A Standard -25 - 85 C Extended -40 - +105 C Plastic QFN 3x3 mm (HX2QFN20) I C Slave All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 4 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 3 Functional description 3.1 Functional diagram Figure 2.SE050 functional diagram - example Open SSL 2 The SE050 uses I C as communication interface. Section 4 gives more details. The 2 SE050 commands are wrapped using the Smartcard T=1 over IC (T=1o I C) protocol. 2 The detailed documentation of the SE050 commands (see [3]) and T=1 over I C protocol encapsulation is available in NXP DocStore. In order to simplify the product usage a host library which abstracts for SE050 commands 2 and T=1 over I C protocol encapsulation is provided. The host library supporting various platforms is available for download including complete source code on the SE050 website. SE050 IoT applet features a generic file system capable of securely storing secure objects and associated privilege management. All objects can either be stored in persistent memory or in RAM with the capability to securely export and import them to be stored in an externally provided storage. All secure objects feature basic file operations such as write, read, delete and update. 3.1.1 Supported secure object types A secure object is an entry in the file system of SE050. Each secure object has certain features and capabilities. The following secure object types are available: * * * * * * * SE050 Objective data sheet Symmetric Key (AES, DES) ECC Key RSA Key HMAC Key Binary File User ID Counter All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 5 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element * Hash-Extend register 3.1.1.1 Symmetric Key The Symmetric Key object can securely store symmetric keys of AES 128, 192 and 256 bit and DES keys with single DES, 2K3DES and 3K3DES. The following specific operations are available on symmetric key objects: * * * * * Encrypt Decrypt Derive CMAC Secure Import 3.1.1.2 ECC Key The ECC Key object has the ability to securely store ECC keys of the following curves and key sizes: * * * * * * * ECC NIST curve: NIST P-192, NIST P-224, NIST P-256, NIST P-384, NIST P-521 ECC Brainpool curve: 160 bit, 192 bit, 224 bit, 256 bit, 320 bit, 384 bit, 512 bit ECC Ed25519 curve: 256 bit ECC Montgomery Curve25519: 256 bit ECC Koblitz curves: secp160k1, secp192k1, secp224k1, secp256k1 ECC curves: secp192r1, secp224r1, secp256r1, secp384r1, secp521r1 ECC Barreto-Naehrig 256 bit curve The following operations are available on ECC key objects (not all operations are applicable to all curves): * * * * * * * ECDSA/EDDSA Sign ECDSA/EDDSA Verify ECDH Generate Shared Secret ECDAA Sign ECDAA Verify Generate Key Secure Import 3.1.1.3 RSA Key The RSA Key object has the ability to securely store RSA Keys up to 4096 bit. The following specific operations are available on RSA key objects: * * * * * RSA Sign RSA Verify RSA Encrypt RSA Decrypt Secure Import 3.1.1.4 HMAC Key object An HMAC key object allows to securely store an HMAC key. The following operations are supported on HMAC Key objects to compute an HMAC: * Init SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 6 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element * Update * Finalize 3.1.1.5 Binary file objects Binary file objects are byte arrays of a generic type. As in a standard file system, the values can be accessed using read/write operations. 3.1.1.6 Counter Objects Counter objects are special kinds of binary file objects with specific functionality interpreting the content of the file. The supported operations for counters are: * Set * Get * Increment 3.1.1.7 Hash-Extend register A hash-extend register secure object stores a hash over all data provided to that secure object. It therefore contains the complete history of values provided to that register since last reboot or since creation and can be used for attestation purposes. 3.1.1.8 User ID secure object User ID secure objects can be used to create sessions based on the User ID in cases where multi-tenant support without cryptographic credential usage is required. 3.1.2 Access control Each secure object can be linked to object specific access control policies. An access control policy associates a user identified by an authentication with a set of privileges such as read, write, ... To scale the functionality into a broad range of ecosystems, a set of different authentication options is provided: * User-ID based authentication * Symmetric key based authentication with and without secure messaging * Asymmetric key based authentication with and without secure messaging At creation of a secure object, an optional set of policies is associated with that secure object. Each policy assigns a set of allowed operations on that object to an authentication object. 3.1.3 Sessions and multi-threading The SE050 IoT applet is prepared for ecosystems where multi-threading and multitenant use cases are needed on APDU level. To enable that, the applet supports 2 simultaneous sessions that can span full secure messaging sessions, self-authenticated APDUs for tenants not requiring long-lasting sessions and on top one default session for single tenant use cases . SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 7 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 3.1.4 Attestation and trust provisioning SE050 applet comes with a set of trust provisioned root credentials allowing the owner of the device to securely attest all generated secure keys. Next to that, a customer has the possibility to define own attestation keys. 3.1.5 Application support For specific ecosystems, SE050 IoT applet has built-in crypto features to simplify the deployment of specific use cases such as * * * * * * MIFARE SAM functionality Wifi password protection ECC-Key and RSA-Key based cloud connectivity 2 Secure Sensor readout using I C master Remote attestation and trust provisioning Platform Configuration Registers 3.2 Credential Storage & Memory Within SE050, all credentials and secure objects are stored inside a dynamic file structure. At creation, a user has to associate a file identifier with the object created. This identifier is then used in subsequent operations to access the object. The number of objects that can be allocated is only limited by the available memory in the system. After usage, objects can be deleted and the associated memory is freed up again. There is also the possibility to create transient objects. Transient objects have an object descriptor stored in non-volatile memory, but the object content is stored in RAM. Together with the import/export functionality of SE050, transient objects can be used securely store secret keys in a remote memory system. 3.3 Ease of use configuration All SE050 variants are offered pre-configured for ease of use during development phase. Therefore customers have all keys pre-injected in SE050 that are required for the main use cases. 4 Communication interfaces 2 4.1 I C Interfaces 2 2 The SE050 has one I C interface supporting slave and one I C interface supporting master mode. 2 The I C slave interface is the main communication interface of the device and is used by the host controller to send arbitrary APDUs to the device. It supports clock frequencies 2 up to 3.4 MHz when operated in High-Speed Mode (HS). The I C interface is using the 2 Smartcard T=1 over I C protocol. The default slave address of the SE050 is configured to 0x48. 2 The I C master interface is supposed to be used with slave devices that need to be securely written and read. This interface features a maximum SCL clock rate of 400 kHz. SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 8 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 2 4.1.1 Supported I C frequencies 2 2 The SE050 I C slave interface supports the I C high-speed mode with a maximum SCL clock of up to 3.4 MHz when clock stretching is enabled. In case clock stretching is disabled the maximum supported SCL clock frequency is 1.7 MHz. Clock stretching is enabled by default. Clock stretching will occur for frequencies 2 higher than 600 kHz. In case clock stretching is not supported by the I C master a dedicated configuration with disabled clock stretching has to be used to ensure the above mentioned maximum clock frequency. 2 The SE050 I C master interface supports maximum 400 kHz SCL clock frequency. 4.2 ISO7816 and ISO14443 Interface 2 The SE050 supports in addition to the I C interface ISO7816 and ISO14443 Smartcard interfaces. For the ISO7816 interface SmartCard protocols T=0 and T=1 are supported. For the ISO14443 interface protocol T=CL is used. The supported resonance input capacitance is 56 pF. In addition one additional GPIO pad IO2 is supported. The RST_N pin can only be used as external reset source if the ISO7816 interface is 2 enabled. If only the I C interface is enabled the RST_N pad has no effect. If the SE050 is kept in reset state the current consumption is as defined for idle, see Table 12. 5 Power-saving modes The device provides two power-saving operation modes. The Power-down mode (with state retention) and the Deep Power-down mode (no state retention). These modes are activated via pad ENA (Deep Power-down mode) or by the SW (Power-down mode). 5.1 Power-down mode The Power-down mode has the following properties: * * * * All internal clocks are frozen CPU enters power-saving mode with program execution being stopped CPU registers keep their contents RAM keeps its contents The SE050 enters into Power-down mode by receiving "End of APDU session request" 2 via the T=1 over I C protocol. In Power-down mode, all internal clocks are frozen. The IOs hold the logical states they had at the time Power-down mode was activated. There are two ways to exit from the Power-down mode: * A reset signal on RST_N (in case the ISO7816 interface is enabled). After wake-up from Power-down mode via RST_N the device is in idle mode (see Table 12) 2 * An external interrupt edge triggered by a falling edge on I C_SDA 5.2 Deep Power-down mode The SE050 provides a special power-saving mode offering maximum power saving. This mode is activated by pulling enable PIN (ENA) to a logic zero level. SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 9 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element While in Deep Power-down mode the internal power is switched off completely and only 2 the I C pads stay supplied. To leave the Deep Power-down mode pad ENA has to be pulled up to to a logic 1" level. For usage of Deep Power-down mode the SE050 must be supplied via pad Vin and pad Vout. 6 Ordering information 6.1 Ordering options Table 3.SE050 Ordering information 12NC Type number SE050 Variant Orderable part number 9353 867 22472 SE050A1HQ1/Z01SG SE050A1 SE050A1HQ1/Z01SGZ 9353 869 84472 SE050A2HQ1/Z01SH SE050A2 SE050A2HQ1/Z01SHZ 9353 869 85472 SE050B1HQ1/Z01SE SE050B1 SE050B1HQ1/Z01SEZ 9353 869 86472 SE050B2HQ1/Z01SF SE050B2 SE050B2HQ1/Z01SFZ 9353 869 87472 SE050C1HQ1/Z01SC SE050C1 SE050C1HQ1/Z01SCZ 9353 869 88472 SE050C2HQ1/Z01SD SE050C2 SE050C2HQ1/Z01SDZ Table 4.SE050 Ordering information for development kit 12NC Type number Description 9353 832 82598 OM-SE050ARD SE050 Arduino-compatible development kit , SE050C configuration 6.2 Ordering SE050 samples Samples can be ordered from NXP Semiconductors via nxp.com using the "Buy Direct" button on the product information page for SE050. Note that NXP Semiconductors can provide up to five pieces free of charge. Larger quantities have to be ordered commercially. 6.3 Configuration Detailed information about the configuration and available variants of the SE050 are available in a separate NXP Application Note, see [4] SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 10 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 7 Pinning information 7.1 Pinning 16 ISO 7816 IO2 17 ISO 14443 LA 19 VSS 20 n.c. terminal 1 index area 18 VCC 7.1.1 Pinning HX2QFN20 ISO 14443 LB 1 15 VOUT n.c. 2 14 ISO 7816 RST_N ISO 7816 IO1 SE050 3 13 ISO 7816 CLK 11 ENA l2C_SDA n.c. n.c. n.c. l2C_SCL 10 5 9 n.c. 8 12 VIN 7 4 6 n.c. aaa-031924 Transparent top view Figure 3.Pin configuration for HX2QFN20 (SOT1969-1) Table 5.Pin description HX2QFN20 Symbol Pin Description ISO 14443 LB 1 ISO14443 Antenna Connection n.c. 2 not connected ISO 7816 IO1 3 ISO 7816 IO or GPIO or I C master SDA n.c. 4 not connected n.c. 5 not connected n.c. 6 not connected n.c. 7 not connected n.c. 2 8 not connected 2 9 I C slave data I C_SCL 2 10 I C slave clock ENA 11 Deep Power-down mode enable VIN 12 power supply voltage input for I C pads and ISO 7816/14443 interface and logic supply in case Deep Power-down mode is used ISO 7816 CLK 13 ISO 7816 clock input ISO 7816 RST_N 14 ISO 7816 reset input low active I C_SDA SE050 Objective data sheet 2 2 2 All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 11 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Symbol Pin Description VOUT 15 supply voltage output to be connected with pad VCC on PCB level, if Deep Power-down mode is used ISO 7816 IO2 16 ISO7816 IO2 and GPIO pad or I C master SCL ISO 14443 LA 17 ISO14443 antenna connection VCC 18 logic and ISO7816/ISO1443 interface power supply voltage input, to be connected with pad Vout on PCB level, if Deep Power-down mode to be used VSS 19 ground n.c. 20 not connected 2 The center pad of the IC is not connected, although it is recommended to connect it to ground for thermal reasons. 8 Package SE050 is offered in HX2QFN20 package. The dimensions are 3 mm x 3 mm x 0,32 mm with a 0,4 mm pitch. Please refer to the package data sheet [2], SOT1969-1. 9 Marking Table 6.Marking codes Type number Marking code Sx050... Line A: S50 Line B: ***** (***** = 5-digit Batch code) Line C: nDyww D: RHF-2006 indicator n: Assembly Center Y: Year WW: Week 10 Packing information 10.1 Reel packing The SE050 product is available in tape on reel. Table 7.Reel packing options Symbol Parameter Numbers of units per reel HX2QFN20 7" tape on reel 3000 SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 12 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 11 Electrical and timing characteristics The electrical interface characteristics of static (DC) and dynamic (AC) parameters for 2 2 pads and functions used for I C are in accordance with the NXP I C specification (see [1]). 12 Limiting values Table 8.Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V). Symbol Parameter VDD supply voltage VI input voltage II Conditions any signal pad input current Unit -0.3 +6 V [1] -0.3 +6 V 2 - 10 mA 2 2 - 10 mA - pad I C_SDA, I C_SCL output current pad I C_SDA, I C_SCL Ilu latch-up current VI < 0 V or VI > VDD Vesd_hbm electrostatic discharge voltage (Human Body Model) pads VCC, VSS, RST_N, 2 2 I C_SDA, I C_SCL [2] Vesd_cdm electrostatic discharge voltage (Charge Device Model) pads VCC, VSS, RST_N, 2 2 I C_SDA, I C_SCL [3] Ptot Total power dissipation Tstg Storage temperature [2] [3] [4] Max 2 IO [1] Min [4] 100 mA 2.0 kV 500 V - 600 mW -55 +125 C Maximum supported supply voltage is 6 V. The SE050 is characterized for the specified operating supply voltage range of 1.62 V to 3.6 V.In case of supply voltages above 3.6 V, Deep Power-down mode current <5 A is not guaranteed. MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 k; Tamb = -40 C to +105 C. JESD22-C101, JEDEC Standard Field induced charge device model test method. Depending on appropriate thermal resistance of the package. 13 Recommended operating conditions The SE050 is characterized by its specified operating supply voltage range of 1.62 V to 3.6 V. Table 9.Recommended operating conditions Symbol Parameter Conditions VDD Supply voltage Nominal supply voltage 1.62 VI DC input voltage on digital inputs and digital I/O pads - H Field strength Contactless interface operation Tamb Operating ambient temperature [1] [2] [2] Min Typ Max Unit 1.8 3.6 V -0.3 VDD +0.3 V 1.5 7.5 A/m -40 +105 C [1] Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 A is not guaranteed. All product properties and values specified within this data sheet are only valid within the operating ambient temperature range. SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 13 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 1.62 V 3.6 V aaa-015200_ Figure 4.Characteristic supply voltage operating range 1 14 Characteristics 14.1 DC characteristics Measurement conventions Testing measurements are performed at the contact pads of the device under test. All voltages are defined with respect to the ground contact pad VSS. All currents flowing into the device are considered positive. 14.1.1 General and General Purpose I/O interface Table 10.Electrical DC characteristics of Input/Output: IO1/IO2. Conditions: VDD = 1.62 V to 3.6 V (see ; VSS = 0 V; Tamb = -40 C to + 105 C, unless otherwise specified Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 A is not guaranteed. Symbol Parameter Conditions VIH HIGH level input voltage VIL LOW level input voltage IIH HIGH level input current in "weak pull-up" input mode IIL ITL Min Max Unit 0.7 VDD VDD + 0.3 V -0.3 0.25 VDD V 0.7 VDD VI VDD Test conditions for the maximum absolute value: IIH(max):VI = 0.7 VDD, VDD=VDD(max) -20 A LOW level input current 0 V VI 0.3 VDD; Test conditions for the maximum absolute value: IIL(max):VI = 0 V, VDD = VDD(max) -50 A HIGH-to-LOW transition input current (only "quasibidirectional" mode) 0.3 VDD < VI VDD; Test conditions for the maximum absolute value: VI = 0.5 VDD, VDD = VDD(max) -250 A [1] Typ 1 Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 A is not guaranteed. SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 14 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Symbol Parameter Conditions II Input current in "weak pull-up" 0 V VI VDD; Test input mode conditions for the maximum absolute value: II(max):VI = 0 V, VDD = VDD(max) IILIH IILIL Min Max Unit -50 A Leakage input current at input VDD < VI VDD + 0.3 V; voltage beyond VDD in "weak -40 C pull-up" input mode Tamb +105 C; Test conditions: VI = VDD + 0.3 V; VDD = VDD(max)Tamb = +105 C 20 A Leakage input current at input -0.3 V VI < 0 V; -40 C voltage below VSS in "weak Tamb pull-up" input mode +30 C Test conditions: VI = -0.3 V; VDD= VDD(max)Tamb = +30 C -50 A -0.3 V VI < 0 V;+30 C Tamb +105 C Test conditions: VI = -0.3 V; VDD= VDD(max)Tamb = +105 C -1000 A 0 Typ IILIHQ Leakage input current at input voltage beyond VDD (only in "quasi-bidirectional" mode) VDD < VI VDD + 0.3 V; -40 C Tamb +105 C Test conditions: VI = VDD + 0.3 V;VDD = VDD(max); Tamb = +105 C 100 A IILILQ Leakage input current at input voltage below VSS (only in "quasi-bidirectional" mode) -0.3 V VI < 0 V; -40 C Tamb +30 C Test conditions: VI = -0.3 V; VDD = VDD(max)Tamb= +30 C -120 A -0.3 V VI < 0 V;+30 C Tamb +105 C Test conditions: VI = -0.3 V; VDD = VDD(max)Tamb= +105 C -1000 A VOH HIGH level output voltage SE050 Objective data sheet IOH = -20 A; [2] 0.7 VDD All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 V (c) NXP B.V. 2019. All rights reserved. 15 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Symbol Parameter Conditions VOL LOW level output voltage IOL = 1.0 mA IOL = 0.5 mA [1] [2] Min Typ Max Unit 0.3 0.15 VDD V IO1/IO2 source a transition current when being externally driven from HIGH to LOW. This transition current (ITL) reaches its maximum value when the input voltage VI is approximately 0.5 VDD. Current IIL is tested at input voltage VI= 0.3 V. Figure 6 shows the input characteristic of this quasi-bidirectional port mode. External pull-up resistor 20 k to VDD assumed. The worst case test condition for parameter VOH is present at minimum VDD. VI II IIL1maxu -0.3 V IIH1maxu VDD 0 0 VIL1max VIH1min IILI1maxI IIHI1maxI aaa-029327 Figure 5.Input characteristic of RST_N II 0 IILIHQ VI -0.3 V 0 V VILmax 0.5 VDD VIHmin VDD VDD +0.3 V IILmax IILILQmax ITLmax aaa-006774 Figure 6.Input characteristic of IO1/IO2 in "quasi-bidirectional" mode Vl ll lImin -0.3 V 0 V lILIHmax lIHmin VILmax VIHmin VDD 0 VDD +0.3 V lILmax lImax lIHmax lILILmax aaa-007192 Figure 7.Input characteristic of IO1/IO2 in "weak pull-up" mode SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 16 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element II VI IIL1max II1max IILIH1max IIH1max -0.3 V 0 0V VIL1max VIH1min VDD +0.3 V VDD IIL1min IlLlL1max II1min aaa-007191 Figure 8.Input characteristic of CLK when the IC is not in reset and of RST_N II VI II2min VIL2max -0.3 V 0 V IlLIH2max IIH2min VIH2min VDD 0 VDD +0.3 V IIL2max IILIL2max II2max IIH2max aaa-007190 Figure 9.Input characteristic of CLK during IC reset 2 14.1.2 I C Interface 2 Table 11.Electrical DC characteristics of I C pads SDA, SCL. Conditions: VDD = 1.62 V to 3.6 V; VSS = 0 V; Tamb = -40 C to + 105 C, unless otherwise specified* Maximum supported supply voltage is 6 V. In case of supply voltages above 3.6 V, Deep Power-down mode current <5 A is not guaranteed. 2 SCL, SDA pads either in open-drain or push-pull mode (I C Master high-speed mode only). Symbol Parameter VIH HIGH level input voltage VIL LOW level input voltage VOH(PP) HIGH level output voltage (push-pull-mode) IOH = 3 mA; VOL(PP) LOW level output voltage (push-pull mode) IOL = 3.0 mA VHYS Input hysteresis voltage - 0.081 V VOL(OD) Low level output voltage (open-drain mode) IOL = 3.0 mA 0 SE050 Objective data sheet Conditions Min Max Unit 0.7 VDD VDD + 0.3 V -0.3 0.25 VDD V 0.7 VDD V 0.3 All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 Typ V V 0.4 V (c) NXP B.V. 2019. All rights reserved. 17 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Symbol Parameter Conditions Min Typ Max Unit IOL(OD) Low level output current (open-drain mode) VOL = 0.6 V 0.6 IWPU weak pull-up current VIO = 0 V -265 -180 -70 A IWPD weak pull-down current VIO = VDD 105 200 -300 A IILIH Leakage input current high level VSDA = 3.6 V, VSCL = 3.6 V 0.27 15 A mA 14.1.3 Power consumption Table 12.Electrical characteristics of IC supply voltage VDD; VSS = 0 V; Tamb = -40 C to +105 C Symbol Parameter Conditions Min Typ Max Unit supply voltage range VDD = 1.62 - 3.6 V 1.62 1.80 3.6 V fCPU= 48 MHz, fMST = 96 MHz 1.8 2.9 mA no coprocessor active fCPU= 48 MHz, fMST = 96 MHz 4.4 5.1 mA AES coprocessor active (AES 48 MHz) CPU in idle mode 6.5 7.5 mA FAME coprocessor active (FAME 48 MHz) CPU in idle mode 14.4 16.1 mA DES coprocessor active (DES 96 MHz) CPU in idle mode 6.5 7.6 mA IDD(PD) supply current Power-down mode VDDmin VDD VDDmax; Clock to input CLK stopped, Tamb= 25 C 430 480 A IDDD (DPD) supply current Deep Power-down mode VDDmin VDD VDDmax; Clock to input CLK stopped, Tamb= 25 C 3 5 A Supply VDD operating mode: Idle mode IDD supply current idle mode operating mode: typical CPU 14.2 AC characteristics Table 13.Non-volatile memory timing characteristics Conditions: VDD = 1.62 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions tEEP FLASH erase + program time tEEE [1] Min Typ [2] Max Unit 2.3 ms FLASH erase time 0.9 ms tEEW FLASH program time 1.4 ms tEER FLASH data retention time NEEC Tamb = +55 C [3] Intrinsic FLASH endurance (number of programming cycles) SE050 Objective data sheet 25 1 x 10 All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 years 5 5 x 10 5 cycles (c) NXP B.V. 2019. All rights reserved. 18 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Symbol Parameter NEEC [1] [2] [3] Conditions [1] Min FLASH endurance (maximum number of programming cycles applied to the whole memory block performed by NXP static and dynamic wear leveling algorithm) Typ 20 x 10 6 100 x 6 10 Max Unit cycles Typical values are only referenced for information. They are subject to change without notice. Given value specifies physical access times of FLASH memory only. Usage of NXP wear leveling algorithm mandatory. 2 2 [1] Table 14.Electrical AC characteristics of I C_SDA, I C_SCL, and RST_N ; VDD = 1.8 V 10% or 3 V 10% V; VSS = 0 V; Tamb = -40 C to +105 CC Symbol Parameter 2 Conditions Min Typ Max Unit 2 Input/Output: I C_SDA, I C_SCL in open-drain mode trIO tfIO I/O Input rise time I/O Input fall time Input/reception mode [2] 1 s Input/reception mode [2] 1 s Output/transmission mode; CL = 30 pF [2] 0.3 s - 400 kHz 40 60 % tfOIO I/O Output fall time fCLK External clock frequency in I C tCLKW, Tamb and VDD in their applications specified imits tCLKW Clock pulse width i.r.t. clock period (positive pulse duty cycle of CLK) 2 2 [3] 2 2 Input/Output: I C_SDA, I C_SCL in push-pull mode (I C master in high-speed mode) trIO I/O Input rise time Input/reception mode 0.25 s tfIO I/O Input fall time Input/reception mode 0.25 s tfOIO I/O Output fall time Output/transmission mode 0.1 s 3.4 MHz 2.1 % 400 s 2 fCLK External clock frequency in I C Input/reception mode applications tCLKW Clock pulse width i.r.t. clock period (positive pulse duty cycle of CLK) - Inputs: RST_N tRW Reset pulse width (RST_N low) without entering Deep Powerdown mode 40 tRDSLP Reset pulse width (RST_N low) to enter Deep Power-down mode 500 tWKP Wake-up time from Powerdown mode fCLKmin < fCLK < fCLKmax - 8 10 s tWKPIO Pad LOW time for wake-up from Power-down mode level triggered ext.int. - 8 10 s edge triggered ext.int. - 8 10 s SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 s (c) NXP B.V. 2019. All rights reserved. 19 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Symbol Parameter Conditions Min tWKPRST RST_N LOW time for wake-up from Power-down mode tWKWT Time from Power-down mode 2 wake/up event to I C_SDA valid CPIN Pin capacitances RST_N, 2 2 I C_SDA, /I C_SCL [1] [2] [3] Typ 40 50 Test frequency = 1 MHz; Tamb = 25 C - Max Unit - s 100 ns 10 pF All appropriately marked values are typical values and only referenced for information. They are subject to change without notice. tr is defined as rise time between 30% and 70% of the signal amplitude. tf is defined as fall time between 70% and 30% of the signal amplitude. 2 2 During AC testing the inputs RST_N, I C_SDA, I C_SCL are driven at 0 V to +0.3 V for a LOW input level and at VDD -0.3 V to VDD for a HIGH input level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD. 2 2 Figure 10.External clock drive and AC test timing reference points of I C_SDA, I C_SCL, 2 3 and RST_N (see and ) in open-drain mode Table 15.Electrical AC characteristics of IO1, IO2, CLK and RST_N Conditions: VDD = 1.8 V 10 % or 3 V 10 % V; VSS = 0 V; Tamb = -40 C to +105 C, unless otherwise specified. Typical values are only referenced for information. They are subject to change without notice. Symbol Parameter Conditions Min Typ Max Unit 1 s Input/Output: IO1/IO2 trIO I/O Input rise time [1] Input/reception mode [2] [3] [2] tfIO I/O Input fall time [1] Input/reception mode [2] [3] [2] 0.25 x s tIOWx_min 1 s 0.25 x s tIOWx_min trOIO I/O Output rise time Output/transmission mode; CL = 30 pF [2] 0.1 s tfOIO I/O Output fall time Output/transmission mode; CL = 30 pF [2] 0.1 s Inputs: CLK and RST_N 2 2 2 During AC testing the inputs RST_N, I C_SDA, I C_SCL are driven at 0 V to +0.3 V for a LOW input level and at VDD -0.3 V to VDD for a HIGH input level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD. 3 tr is defined as rise time between 30% and 70% of the signal amplitude. tf is defined as fall time between 70% and 30% of the signal amplitude. SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 20 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Symbol Parameter Conditions tCLKW, tamb and VDD in their specified limits Min [4] Typ Max Unit 0.85 11.5 MHz 40 60 % fCLK External clock frequency in ISO/IEC 7816 UART applications tCLKW Clock pulse width i.r.t. clock period (positive pulse duty cycle of CLK) trCLK CLK input rise time [5] [6] tfCLK CLK input fall time [2] [6] trRST RST_N input rise time [2] 400 s tfRST RST_N input fall time [2] 400 s tRW Reset pulse width (RST_N low) tWKP Wake-up time from Power-Down fCLKmin fCLK fCLKmax mode 17 tWKPIO I/Ox LOW time for wake-up from level triggered ext.int. Power-down mode edge triggered ext.int. 20 [6] [7] 40 s 20 s s 20 tWKPRST RST_N LOW time for wake-up from Power-down mode v Inputs: CLK, RST_N, IO1, IO2 CPIN [1] [2] [3] [4] [5] [6] [7] Pin capacitances CLK, RST_ N, IO1, IO2 Test frequency = 1 MHz; tamb = 25 C 20 pF At minimum IO1 input signal HIGH or LOW level voltage pulse width of 3.2 s. This timing specification applies to ISO7816 configurations down to a minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example. tr is defined as rise time between 10% and 90% of the signal amplitude. At minimum IO1 input signal HIGH or LOW level voltage pulse width of less than 3.2 s. This timing specification applies to ISO7816 configurations beyond the conditions listed in note [2], down to a minimum etu duration of 8 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x97, (Fi/ Di)=(512/64)), for example. An 8 CLKs/etu @ fclk = 5 MHz configuration results in tIOWx_min = 1.6 s, and in a time of 400 ns for trIO_max and tfIO_ max, matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221. ISO/IEC 7816 I/O applications have to supply a clock signal to input CLK in the frequency range of 1 MHz to 10 MHz nominal.A 15 % tolerance range yields the allowed limits of 0.85 MHz and 11.5 MHz. During AC testing the inputs CLK, RST_N, and IO1 are driven at 0 V to +0.3 V for a LOW input level and at VDD - 0.3 V to VDD for a HIGH input level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD, see Figure 18. The maximum CLK rise and fall time is 10% of the CLK period 1/fCLK - with the following exception: In the CLK frequency range of 1 MHz to 5 MHz the maximum allowed CLK rise and fall time is 50 ns, if 10% of the CLK period is shorter than 50 ns. The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 s, respectively. Table 16.Electrical AC characteristics of LA, LB; Conditions: Tamb = -40 C to 105 C, unless otherwise specified Conditions: Tamb = -25 C to +85 C, unless otherwise specified. Symbol Parameter Conditions [1] Typ Max Unit Input/Output: LA, LB [2] CLALB Pin capacitance LA, LB Bare die (SO 28, empty package ground-off) SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 21 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Symbol Parameter [2] fLALB [1] [2] [3] [4] [5] Typ VLA,LB = 2.1 V (rms) VLA,LB = 0.3 V (rms) [3] [4] Configured for antenna input [5] with 56 pF capacitance Test frequency = 13.56 MHz; Tamb= 25 C VLA,LB = 2.1 V (rms) [3] [4] VLA,LB = 0.3 V (rms) [4] Wake-up time from Power-Down mode fCLKmin fCLK fCLKmax 17 Operating frequency LA, LB level triggered ext.int. 13.56 Configured for antenna input with 56 pF capacitance Test frequency = 13.56 MHz; Tamb= 25 C RLALB [1] Conditions [4] Max Unit 54.3 50.1 pF 0.913 k Pin capacitance LA, LB Bare die (SO 28, empty package ground-off) 20 s MHZ Typical values ( 10%) are only referenced for information. They are subject to change without notice. The CLALB and RLALB values stated here assume a parallel RC equivalent circuit for the chip. The value stated here was measured at estimated start of chip operation and is comparable to the values stated in other SmartMX3 family member data sheets. Measured with sine wave at LA, LB. 56 pF selection supports all data rates with ID1 antenna (Class 1), however, only 106 kbit/s with 1/2 ID1 antenna (Class 2). 14.3 EMC/EMI EMC and EMI resistance according to IEC 61967-4. Note: tf is defined as fall time between 90% and 10% of the signal amplitude. 15 Abbreviations Table 17.Abbreviations Acronym Description AES Advanced Encryption Standard APDU Application Protocol Data Unit CL Contactless CLK External clock signal input contact pad CC Common Criteria CMAC Cipher-based MAC CRC Cyclic Redundancy Check CRI Cryptography Research Incorporated DES Digital Encryption Standard DPA Differential Power Analysis DSS Digital Signature Standard EAL6 Evaluation Assurance Level ECC Elliptic Curve Cryptography EMC Electromagnetic compatibility SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 22 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Acronym Description EMI Electro Magnetic Immunity FM Fast-Mode FM+ Fast-Mode+ GP Global Platform GPIO General-purpose input/output HS High-Speed-Mode HKDF HMAC-based Extract-and-Expand Key Derivation Function HMAC Keyed-Hash Message Authentication Code HW Hardware IC Integrated Circuit 2 I C Inter-Integrated Circuit I/O Input/Output IoT Internet of Things JCOP Java Card Open Platform LA ISO 14443 Antenna Pad LB ISO 14443 Antenna Pad NFC Near Field Communication MAC Message Authentication Code MCU Microcontroller unit MPU Microprocessor MW Middleware OS Operating System NIST National Institute for Standards and Technology PCB Protocol Control Byte PKI Public Key Infrastructure PRF Pseudo Random Function RAM Random Access Memory RSA Rivest-Shamir-Adleman RST Reset SAM Secure Access Module SCL Serial clock SDA Serial data SPA Simple Power Analysis SFI Single Fault Injection SHA Secure Hash Algorithm SW Software TLS Transport Layer Security SE050 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 23 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Acronym Description VCC Supply Voltage Input VIN Voltage Input VOUT Voltage Output VSS Ground 16 References [1] [2] [3] [4] 2 NXP SE05x T=1 Over I C Specificationl User Manual, Document Number SOT1969-1; HX2QFN20; Reel packing and package data sheet SE050 IoT Applet APDU Specification, document number AN 12413 SE050 configurations Application Note, document number AN12436 17 Revision history Table 18.Revision history Document ID Release date Data sheet status 504913 20190607 Objective data sheet Modifications: * Changed data sheet status from COMPANY PROPRIETARY to PUBLIC * Updated Table 12 * Updated Section 15 504912 20190510 Modifications: * * * * * * * * * * * * * * * * * * * * 504911 20181122 SE050 Objective data sheet Change notice Objective data sheet Supersedes 504912 504911 Changed structure of document Updated Section 1 Updated Section 2.3 Updated Use Cases and target applications Updated Section 3.1 Added Section 3.3 Updated Section 3.1.2 Updated Section 3.1.5 Updated Section 3.2 Updated chapter Section 4 Updated and renamed chapter Section 5 Updated chapter Section 6 Updated Section 7.1.1 Updated Section 8 Updated Section 3.1.3 Updated Section 3.1.1 Updated Table 1 Updated Section 12 Updated Table 10 Updated Section 15 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 24 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element 18 Legal information 18.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 18.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without SE050 Objective data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 25 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. SE050 Objective data sheet Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Licenses ICs with DPA Countermeasures functionality NXP ICs containing functionality implementing countermeasures to Differential Power Analysis and Simple Power Analysis are produced and sold under applicable license from Cryptography Research, Inc. 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2 I C-bus -- logo is a trademark of NXP B.V. MIFARE -- is a trademark of NXP B.V. FabKey -- is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 26 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. SE050 commercial name format ....................... 2 Feature Overview .............................................. 4 SE050 Ordering information ............................10 SE050 Ordering information for development kit ............................................... 10 Pin description HX2QFN20 ............................. 11 Marking codes .................................................12 Reel packing options .......................................12 Limiting values ................................................ 13 Recommended operating conditions ............... 13 Electrical DC characteristics of Input/Output: IO1/IO2. Conditions: VDD = 1.62 V to 3.6 V (see ; VSS = 0 V; Tamb = -40 C to + 105 C, unless otherwise specified ........................ 14 Electrical DC characteristics of I2C pads SDA, SCL. Conditions: VDD = 1.62 V to 3.6 Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. V; VSS = 0 V; Tamb = -40 C to + 105 C, unless otherwise specified* ............................. 17 Electrical characteristics of IC supply voltage VDD; VSS = 0 V; Tamb = -40 C to +105 C ........................................................... 18 Non-volatile memory timing characteristics ..... 18 Electrical AC characteristics of I2C_SDA, I2C_SCL, and RST_N; VDD = 1.8 V 10% or 3 V 10% V; VSS = 0 V; Tamb = -40 C to +105 CC ...................................................19 Electrical AC characteristics of IO1, IO2, CLK and RST_N ............................................. 20 Electrical AC characteristics of LA, LB; Conditions: Tamb = -40 C to 105 C, unless otherwise specified ..........................................21 Abbreviations ...................................................22 Revision history ...............................................24 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. SE050 solution block diagram ...........................2 SE050 functional diagram - example Open SSL ....................................................................5 Pin configuration for HX2QFN20 (SOT1969-1) ....................................................11 Characteristic supply voltage operating range ............................................................... 14 Input characteristic of RST_N ......................... 16 Input characteristic of IO1/IO2 in "quasibidirectional" mode ..........................................16 SE050 Objective data sheet Fig. 7. Fig. 8. Fig. 9. Fig. 10. Input characteristic of IO1/IO2 in "weak pullup" mode .........................................................16 Input characteristic of CLK when the IC is not in reset and of RST_N .................................... 17 Input characteristic of CLK during IC reset ...... 17 External clock drive and AC test timing reference points of I2C_SDA, I2C_SCL, and RST_N (see and ) in open-drain mode ........... 20 All information provided in this document is subject to legal disclaimers. Rev. 1.3 -- 7 June 2019 504913 (c) NXP B.V. 2019. All rights reserved. 27 / 28 SE050 NXP Semiconductors Plug & Trust Secure Element Contents 1 1.1 1.2 1.3 2 2.1 2.2 2.3 3 3.1 3.1.1 3.1.1.1 3.1.1.2 3.1.1.3 3.1.1.4 3.1.1.5 3.1.1.6 3.1.1.7 3.1.1.8 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.3 4 4.1 4.1.1 4.2 5 5.1 5.2 6 6.1 6.2 6.3 7 7.1 7.1.1 8 9 10 10.1 11 12 13 14 14.1 14.1.1 14.1.2 14.1.3 14.2 14.3 Introduction ......................................................... 1 SE050 use cases .............................................. 1 SE050 target applications ..................................1 SE050 naming convention .................................2 Features and benefits .........................................3 Key benefits .......................................................3 Key features ...................................................... 3 Features in detail ...............................................4 Functional description ........................................5 Functional diagram ............................................ 5 Supported secure object types .......................... 5 Symmetric Key .................................................. 6 ECC Key ............................................................6 RSA Key ............................................................ 6 HMAC Key object .............................................. 6 Binary file objects .............................................. 7 Counter Objects .................................................7 Hash-Extend register ......................................... 7 User ID secure object ........................................7 Access control ................................................... 7 Sessions and multi-threading ............................ 7 Attestation and trust provisioning .......................8 Application support ............................................ 8 Credential Storage & Memory ........................... 8 Ease of use configuration ..................................8 Communication interfaces ................................. 8 I2C Interfaces .................................................... 8 Supported I2C frequencies ................................9 ISO7816 and ISO14443 Interface ..................... 9 Power-saving modes .......................................... 9 Power-down mode .............................................9 Deep Power-down mode ................................... 9 Ordering information ........................................ 10 Ordering options .............................................. 10 Ordering SE050 samples ................................ 10 Configuration ....................................................10 Pinning information .......................................... 11 Pinning ............................................................. 11 Pinning HX2QFN20 ......................................... 11 Package ..............................................................12 Marking ...............................................................12 Packing information ..........................................12 Reel packing ....................................................12 Electrical and timing characteristics ...............13 Limiting values .................................................. 13 Recommended operating conditions .............. 13 Characteristics .................................................. 14 DC characteristics ............................................14 General and General Purpose I/O interface .....14 I2C Interface .................................................... 17 Power consumption ......................................... 18 AC characteristics ............................................18 EMC/EMI ..........................................................22 15 16 17 18 Abbreviations .................................................... 22 References ......................................................... 24 Revision history ................................................ 24 Legal information .............................................. 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. (c) NXP B.V. 2019. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 June 2019 Document number: 504913