Plug & Trust Secure Element

Rev. 1.3 — 7 June 2019 Objective data sheet

1 Introduction

The SE050 is a ready-to-use IoT secure element solution. It provides a root of trust at the

IC level and it gives an IoT system state-of-the-art, edge-to-cloud security capability right

and supports both RSA & ECC asymmetric cryptographic algorithms with high key length

and future proof ECC curves. The latest security measures protect the IC even against

sophisticated non-invasive and invasive attack scenarios.

The SE050 is a turnkey solution that comes with Java Card operating system and an

applet optimized for IoT security use cases pre-installed. This is complemented by a

comprehensive product support package, enabling fast time to market & easy design-

in with Plug & Trust middleware for host applications, easy to use development kits,

reference designs, and extensive documentation for product evaluation.

The SE050 is a product platform that comes in several pin-to-pin compatible product

variants, see [4].

1.2 SE050 target applications

Note: SE050 is designed to be used as a part of an IoT system. It works as an auxiliary

security device attached to a host controller. The host controller communicates with

SE050 through an I²C interface (with the host controller being the master and the SE050

being the slave). Besides the mandatory connection to the host controller, the SE050

device can optionally be connected to a sensor node or similar element through a

separate I²C interface. In this case, the SE050 device is the master and the sensor node

the slave. Lastly, SE050 has a connection for a native contactless antenna, providing a

All letters are explained in Table 1 .

Table 1. SE050 commercial name format

Configuration options with different key provisioning

options, see [4]

2 Features and benefits

2.1 Key benefits

Windows, Android, etc.)

system and applet. Direct memory access is possible by the fixed functionalities of the

applet only. With that, the content from the memory is fully isolated from the host system.

supporting fully encrypted communications and secured lifecycle management

Attacks of various kinds

encryption, memory encryption, tamper detection

mode, 400 kbps). Both can be active at the same time

maintenance in the field and late stage configuration

securely bind the host with the secure element

GlobalPlatform specification version GP 3.0

ECC ECDSA, ECDH, ECDHE, ECDAA,

Hash HMAC, secure HMAC, CMAC

SHA SHA-1, SHA-224, SHA-256, SHA-384,

Key derivation HKDF, PBKDF, Wi-Fi KDF,OPC_UA

PRF (TLS-PSK)

AES AES cipher for de-/encryption

3 Functional description

3.1 Functional diagram

3.1.2 Access control

Each secure object can be linked to object specific access control policies. An access

control policy associates a user identified by an authentication with a set of privileges

such as read, write, …

To scale the functionality into a broad range of ecosystems, a set of different

authentication options is provided:

At creation of a secure object, an optional set of policies is associated with that

APDUs for tenants not requiring long-lasting sessions and on top one default session for

single tenant use cases .

3.1.4 Attestation and trust provisioning

SE050 applet comes with a set of trust provisioned root credentials allowing the owner of

the device to securely attest all generated secure keys. Next to that, a customer has the

possibility to define own attestation keys.

3.1.5 Application support

For specific ecosystems, SE050 IoT applet has built-in crypto features to simplify the

deployment of specific use cases such as

Within SE050, all credentials and secure objects are stored inside a dynamic file

structure. At creation, a user has to associate a file identifier with the object created. This

identifier is then used in subsequent operations to access the object. The number of

objects that can be allocated is only limited by the available memory in the system. After

usage, objects can be deleted and the associated memory is freed up again.

There is also the possibility to create transient objects. Transient objects have an object

descriptor stored in non-volatile memory, but the object content is stored in RAM.

Together with the import/export functionality of SE050, transient objects can be used

securely store secret keys in a remote memory system.

3.3 Ease of use configuration

master mode.

The I2C slave interface is the main communication interface of the device and is used by

the host controller to send arbitrary APDUs to the device. It supports clock frequencies

up to 3.4 MHz when operated in High-Speed Mode (HS). The I2C interface is using the

Smartcard T=1 over I2C protocol.

The default slave address of the SE050 is configured to 0x48.

The I2C master interface is supposed to be used with slave devices that need to be

securely written and read. This interface features a maximum SCL clock rate of 400 kHz.

clock of up to 3.4 MHz when clock stretching is enabled.

In case clock stretching is disabled the maximum supported SCL clock frequency is

1.7 MHz.

interfaces. For the ISO7816 interface SmartCard protocols T=0 and T=1 are supported.

For the ISO14443 interface protocol T=CL is used. The supported resonance input

capacitance is 56 pF. In addition one additional GPIO pad IO2 is supported.

The RST_N pin can only be used as external reset source if the ISO7816 interface is

enabled. If only the I2C interface is enabled the RST_N pad has no effect. If the SE050 is

kept in reset state the current consumption is as defined for idle, see Table 12.

5 Power-saving modes

The device provides two power-saving operation modes. The Power-down mode (with

state retention) and the Deep Power-down mode (no state retention). These modes are

The SE050 enters into Power-down mode by receiving "End of APDU session request"

via the T=1 over I2C protocol. In Power-down mode, all internal clocks are frozen. The

IOs hold the logical states they had at the time Power-down mode was activated.

There are two ways to exit from the Power-down mode:

from Power-down mode via RST_N the device is in idle mode (see Table 12)

5.2 Deep Power-down mode

The SE050 provides a special power-saving mode offering maximum power saving. This

[1] IO1/IO2 source a transition current when being externally driven from HIGH to LOW. This transition current (ITL) reaches its maximum value when the

input voltage VI is approximately 0.5 VDD. Current IIL is tested at input voltage VI= 0.3 V. Figure 6 shows the input characteristic of this quasi-bidirectional

port mode.

[2] External pull-up resistor 20 kΩ to VDD assumed. The worst case test condition for parameter VOH is present at minimum VDD.

Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N

Conditions: VDD = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Typical

values are only referenced for information. They are subject to change without notice.

Power-down mode edge triggered ext.int. 20

minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example.

[2] tr is defined as rise time between 10% and 90% of the signal amplitude.

[3] At minimum IO1 input signal HIGH or LOW level voltage pulse width of less than 3.2 μs. This timing specification applies to ISO7816 configurations

beyond the conditions listed in note [2], down to a minimum etu duration of 8 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x97, (Fi/

Di)=(512/64)), for example. An 8 CLKs/etu @ fclk = 5 MHz configuration results in tIOWx_min = 1.6 μs, and in a time of 400 ns for trIO_max and tfIO_

max, matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221.

[4] ISO/IEC 7816 I/O applications have to supply a clock signal to input CLK in the frequency range of 1 MHz to 10 MHz nominal.A ± 15 % tolerance range

yields the allowed limits of 0.85 MHz and 11.5 MHz.

[5] During AC testing the inputs CLK, RST_N, and IO1 are driven at 0 V to +0.3 V for a LOW input level and at VDD − 0.3 V to VDD for a HIGH input level.

Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD, see Figure 18.

Bare die (SO 28, empty package

Test frequency = 13.56 MHz;

Tamb= 25 °C

Wake-up time from Power-Down

[1] Typical values (± 10%) are only referenced for information. They are subject to change without notice.

[2] The CLALB and RLALB values stated here assume a parallel RC equivalent circuit for the chip.

[3] The value stated here was measured at estimated start of chip operation and is comparable to the values stated in other SmartMX3 family member data

[4] Measured with sine wave at LA, LB.

[5] 56 pF selection supports all data rates with ID1 antenna (Class 1), however, only 106 kbit/s with 1/2 ID1 antenna (Class 2).

17 Revision history

Table 18. Revision history

18 Legal information

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

purchase of NXP Semiconductors products by customer.