74ALS112A
Dual J-K negative edge-triggered flip-flop
Product specification 1996 June 27
INTEGRATED CIRCUITS
IC05 Data Handbook
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
2
1996 Jun 27 853-1846 16995
DESCRIPTION
The 74ALS112A, dual negative edge-triggered JK-type flip-flop
features individual J, K, clock (CPn), set (SD), and reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the function table regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and the flip-flop will perform
according to the function table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
TYPE TYPICAL
fMAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS112A 50MHz 3.0mA
PIN CONFIGURATION
16
15
14
13
12
11
107
6
5
4
3
2
1
Q1
VCC
K1
J1
SD1
CP1
RD0
RD1
CP0
K0
Q0
J0
SD0
Q0
98GND Q1
SF00103
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
DRAWING
NUMBER
16-pin plastic DIP 74ALS112AN SOT38-4
16-pin plastic SO 74ALS112AD SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74ALS (U.L.)
HIGH/LOW LOAD VALUE
HIGH/LOW
CP0, CP1 Clock Pulse input (active falling edge) 1.0/1.0 20µA/0.1mA
J0, J1 J inputs 1.0/2.0 20µA/0.2mA
K0, K1 K inputs 1.0/2.0 20µA/0.2mA
SD0, SD1 Set inputs (active-Low) 1.0/2.0 20µA/0.2mA
RD0, RD1 Reset inputs (active-Low) 1.0/2.0 20µA/0.2mA
Q0, Q1, Q0, Q1 Data outputs 20/80 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
Q0 Q0 Q1 Q1
56 97
V
CC = Pin 16
GND = Pin 8
1
4
15
13
10
14
CP0
SD0
RD0
CP1
SD1
RD1
J1 K0
212
SF00104
K1J0
311
IEC/IEEE SYMBOL
SF00105
6
3
1
2
15
4
11
13
12
14
10
5
9
7
1J
C1
1K
R
S
2J
C2
2K
R
S
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
1996 Jun 27 3
LOGIC DIAGRAM
5, 9
4, 10
2, 12
1, 13
6, 7
15, 14
3, 11
Qn
SDn
Kn
Qn
RDn
Jn
CPn
SF00106
VCC = Pin 16
GND = Pin 8
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
SD RD CP J K Q Q
OPERATING
MODE
L H X X X H L Asynchronous Set
H L X X X L H Asynchronous Reset
L L X X X H* H* Undetermined *
H H ↓h h q q Toggle
H H ↓h l H L Load “1” (Set)
H H ↓l h L H Load “0” (Reset)
H H ↓l l q q Hold “no change”
H H H X X q q Hold “no change”
H = High voltage level
h = High state must be present one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low state must be present one setup time prior to High-to-Low clock transition
q = Lower case indicate the state of the referenced output prior to the High-to-Low clock transition
X = Don’t care
↓= High-to-Low clock transition
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously
Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level. Set and reset are independent of clock.
Simultaneous Low on both SD and RD makes both Q and Q High.
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
1996 Jun 27 4
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5 mA
VOUT Voltage applied to output in High output state –0.5 to VCC V
IOUT Current applied to output in Low output state 16 mA
Tamb Operating free-air temperature range 0 to +70 °C
Tstg Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5.0 5.5 V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IIk Input clamp current –18 mA
IOH High-level output current –0.4 mA
IOL Low-level output current 8 mA
Tamb Operating free-air temperature range 0 +70 °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS1
MIN TYP2MAX
UNIT
VOH High-level output voltage VCC = ±10%,
VIL = MAX, VIH = MIN IOH = –0.4mA VCC – 2 V
VO
Low level out
p
ut voltage
VCC = MIN, VIL = MAX, IOL = 4mA 0.25 0.40 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VIH = MIN IOL = 8mA 0.35 0.50 V
VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.5 V
IIInput current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA
IIH High-level input current VCC = MAX, VI = 2.7V 20 µA
CPn –0.1 mA
IIL Low-level input current SDn, RDn,
Jn, Kn VCC = MAX, VI = 0.4V –0.2 mA
IOOutput current
3
VCC = MAX, VO = 2.25V –30 –112 mA
ICC Supply current (total) VCC = MAX 2.5 4.5 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, IOS.
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
1996 Jun 27 5
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500ΩUNIT
MIN MAX
fMAX Maximum clock frequency W aveform 1 35 MHz
tPLH
tPHL Propagation delay
CPn to Qn or Qn W aveform 1 2.0
4.0 10.0
10.5 ns
tPLH
tPHL Propagation delay
SDn or RD to Qn or Qn W aveform 2, 3 1.5
3.5 8.0
9.5 ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500ΩUNIT
MIN MAX
tsu (H)
tsu (L) Setup time, High or Low
Jn, Kn to CPnW aveform 1 8.0
8.0 ns
th (H)
th (L) Hold time, High or Low
Jn, Kn to CPnW aveform 1 0.0
0.0 ns
tw (H)
tw (L) CPn Pulse width
high or Low W aveform 1 11.0
8.0 ns
tw (L) SDn or RDn Pulse width
Low W aveform 2, 3 6.0 ns
tREC Recovery time,
SDn or RDn to CPn W aveform 2, 3 8.0 ns
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
1996 Jun 27 6
AC WAVEFORMS
For all waveforms, VM = 1.3V.
The sahded areas indicate when the input is permitted to change for predictable output performance.
VM
VM
CPn
VMVMVMVM
VMVM
tsu(H) th(H)
Jn, Kn
Qn
VM
tw(L)
1/fmax
tsu(L) th(L)
VM
VM
tPLH
Qn
tw(H)
tPHL
tPHL
tPLH
SC00136
W aveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, Clock Pulse Width, and Maximum Clock
Frequency
VM
CPn
Qn
VM
VM
Qn
tPHL
tPLH
SDn VM
VMtw(L)
SC00049
Jn, Kn
tREC
W aveform 2. Propagation Delay for Set to Output,
Set Pulse Width, and Recovery Time for Set to Clock
VM
CPn
Qn
VM
VM
Qn
tPLH
tPHL
RDn VM
VMtw(L)
SC00050
Jn, Kn
tREC
W aveform 3. Propagation Delay for Reset to Output,
Reset Pulse Width, and Recovery Time for Reset to Clock
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
1996 Jun 27 7
TEST CIRCUIT AND WAVEFORMS
tw90%
VM
10%
90%
VM10%
90%
VM10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0.3V
0.3V
tTHL (tff)
INPUT PULSE REQUIREMENTS
Rep.Rate twtTLH tTHL
1MHz 500ns 2.0ns 2.0ns
Input Pulse Definition
VCC
Family
74ALS
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN VOUT
Test Circuit for Totem-pole Outputs
DEFINITIONS:
RL= Load resistor;
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT= Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )AMP (V)
Amplitude
3.5V 1.3V
VM
SC00005
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
1996 Jun 27 8
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
1996 Jun 27 9
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Philips Semiconductors Product specification
74ALS112ADual J-K negative edge-triggered flip-flop
1996 Jun 27 10
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appl iances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
