LM3409,LM3409HV
LM3409 / LM3409HV LM3409Q / LM3409QHV PFET Buck Controller for High Power
LED Drivers
Literature Number: SNVS602H
LM3409 / LM3409HV
LM3409Q / LM3409QHV
April 12, 2010
PFET Buck Controller for High Power LED Drivers
General Description
The LM3409/09HV are P-channel MosFET (PFET) con-
trollers for step-down (buck) current regulators. They offer
wide input voltage range, high-side differential current sense
with low adjustable threshold voltage, fast output enable/dis-
able function and a thermally enhanced eMSOP-10 package.
These features combine to make the LM3409/09HV ideal for
use as constant current sources for driving LEDs where for-
ward currents up to 5A are easily achievable. The
LM3409/09Q/09HV/09QHV uses Constant Off-Time (COFT)
control to regulate an accurate constant current without the
need for external control loop compensation. Analog and
PWM dimming are easy to implement and result in a highly
linear dimming range with excellent achievable contrast ra-
tios. Programmable UVLO, low-power shutdown, and thermal
shutdown complete the feature set.
Features
LM3409Q/LM3409QHV is an Automotive Grade product
that is AEC-Q100 grade 1 qualified
2Ω, 1A Peak MosFET Gate Drive
VIN Range: 6V to 42V (LM3409/LM3409Q)
VIN Range: 6V to 75V (LM3409HV/LM3409QHV)
Differential, High-side Current Sense
Cycle-by-Cycle Current Limit
No Control Loop Compensation Required
10,000:1 PWM Dimming Range
250:1 Analog Dimming Range
Supports All-Ceramic Output Capacitors and Capacitor-
less Outputs
Low Power Shutdown
Thermal Shutdown Protection
Thermally Enhanced eMSOP-10 Package
Applications
LED Driver
Constant Current Source
Automotive Lighting
General Illumination
Industrial Lighting
Typical Application
30085601
© 2011 National Semiconductor Corporation 300856 www.national.com
LM3409 / LM3409HV / LM3409Q / LM3409QHV PFET Buck Controller for High Power LED Drivers
Connection Diagram
LM3409/09Q/09HV/09QHV
30085602
10-Lead Exposed Pad eMSOP Package
Ordering Information
Order Number NSC Package
Drawing
Top Marking Supplied As Feature
LM3409MY MUC10A SXFB 1000 Units on tape and reel
LM3409MYX MUC10A SXFB 3500 Units on tape and reel
LM3409HVMY MUC10A SYHB 1000 Units on tape and reel
LM3409HVMYX MUC10A SYHB 3500 Units on tape and reel
LM3409QMY MUC10A SZDB 1000 Units on tape and reel AEC-Q100 Grade 1 qualified.
Automotive Grade
Production Flow*
LM3409QMYX MUC10A SZDB 3500 Units on tape and reel
LM3409QHVMY MUC10A SZEB 1000 Units on tape and reel
LM3409QHVMYX MUC10A SZEB 3500 Units on tape and reel
*Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.
Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified
with the letter Q. For more information go to http://www.national.com/automotive.
Pin Descriptions
Pin(s) Name Description Application Information
1 UVLO Input under-voltage lockout Connect to a resistor divider from VIN and GND. Turn-on threshold is
1.24V and hysteresis for turn-off is provided by a 22µA current source.
2 IADJ Analog LED current adjust Apply a voltage between 0 - 1.24V, connect a resistor to GND, or leave
open to set the current sense threshold voltage.
3 EN Logic level enable /
PWM dimming
Apply a voltage >1.74V to enable device, a PWM signal to dim, or a
voltage <0.5V for low power shutdown.
4 COFF Off-time programming Connect a resistor from VO, and a capacitor from GND to set the off-
time.
5 GND Ground Connect to the system ground.
6 PGATE Gate drive Connect to the gate of the external PFET.
7 CSN Negative current sense Connect to the negative side of the sense resistor.
8 CSP Positive current sense Connect to the positive side of the sense resistor (also connected to
VIN).
9 VCC VIN- referenced
linear regulator output
Connect at least a 1µF ceramic capacitor to VIN. The regulator provides
power for the PFET drive.
10 VIN Input voltage Connect to the input voltage.
DAP DAP Thermal pad on bottom of IC Connect to pin 5 (GND). Place 4-6 vias from DAP to bottom layer GND
plane.
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LM3409/LM3409HV/LM3409Q/LM3409QHV
Absolute Maximum Ratings
LM3409/09Q/09HV/09QHV (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN, EN, UVLO to GND -0.3V to 45V
(76V LM3409HV/
09QHV)
VIN to VCC, PGATE -0.3V to 7V
VIN to PGATE -2.8V for 100ns
9.5V for 100ns
VIN to CSP, CSN -0.3V to 0.3V
COFF to GND -0.3V to 4V
COFF current ±1 mA continuous
IADJ Current ±5 mA continuous
Junction Temperature 150°C
Storage Temp. Range -65°C to 125°C
ESD Rating (Note 2)
LM3409/09HV 1 kV
LM3409Q/09QHV 2 kV
Soldering Information
Lead Temperature (Soldering,
10sec) 260°C
Infrared/Convection Reflow (15sec) 260°C
Operating Ratings (LM3409/09Q/
09HV/09QHV)
(Note 1)
VIN 6V to 42V
(75V LM3409HV/
09QHV)
Junction Temperature Range −40°C to +125°C
Thermal Resistance θJA
(eMSOP-10 Package)
(Note 5) 50°C/W
Electrical Characteristics VIN = 24V unless otherwise indicated. Typicals and limits appearing in plain type apply
for TA = TJ = +25°C (Note 3). Limits appearing in boldface type apply over full Operating Temperature Range. Datasheet min/
max specification limits are guaranteed by design, test, or statistical analysis.
LM3409/09Q/09HV/09QHV
Symbol Parameter Conditions Min
(Note 4)
Typ
(Note 3)
Max
(Note 4)
Units
PEAK CURRENT COMPARATOR
VCST VCSP – VCSN average peak
current threshold
(Note 6)
VADJ = 1.0V 188 198 208 mV
VADJ = VADJ-OC 231 246 261
AADJ VADJ to VCSP – VCSN threshold
gain
0.1 < VADJ < 1.2V
VADJ = VADJ-OC
0.2 V/V
VADJ-OC IADJ pin open circuit voltage 1.189 1.243 1.297 V
IADJ IADJ pin current 3.8 56.4 µA
tDEL CSN pin falling delay CSN fall - PGATE rise 38 ns
SYSTEM CURRENTS
IIN Operating current Not switching 2 mA
ISD Shutdown hysteresis current EN = 0V 110 µA
PFET DRIVER
RPGATE Driver output resistance Sourcing 50 mA 2
Sinking 50 mA 2
VCC REGULATOR
VCC VIN pin voltage - VCC pin
voltage
VIN > 9V
0 < ICC < 20 mA
5.5 66.5 V
VCC-UVLO VCC under voltage lockout
threshold
VCC increasing 3.73 V
VCC-HYS VCC UVLO hysteresis VCC decreasing 283 mV
ICC-LIM VCC regulator current limit 30 45 mA
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LM3409/LM3409HV/LM3409Q/LM3409QHV
Symbol Parameter Conditions Min
(Note 4)
Typ
(Note 3)
Max
(Note 4)
Units
OFF-TIMER AND ON-TIMER
VOFT Off-time threshold 1.122 1.243 1.364 V
tD-OFF COFF threshold to PGATE
falling delay
25 ns
tON-MIN Minimum on-time 115 211 ns
tOFF-MAX Maximum off-time 300 µs
UNDER VOLTAGE LOCKOUT
IUVLO UVLO pin current VUVLO = 1V 10 nA
VUVLO-R Rising UVLO threshold 1.175 1.243 1.311 V
IUVLO-HYS UVLO hysteresis current 22 µA
ENABLE
IEN EN pin current 10 nA
VEN-TH EN pin threshold VEN rising 1.74 V
VEN falling .5
VEN-HYS EN pin hysteresis 420 mV
tEN-R EN pin rising delay EN rise - PGATE fall 42 ns
tEN-F EN pin falling delay EN fall - PGATE rise 21 ns
THERMAL RESISTANCE
θJA Junction to Ambient eMSOP-10 Package (Note 5) 50 °C/W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and the device should not be
operated beyond such conditions.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin.
Note 3: Typical values represent most likely parametric norms at the conditions specified and are not guaranteed.
Note 4: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National's Average Outgoing Quality Level (AOQL).
Note 5: θJA of 50°C/W with DAP soldered to a minimum of 2 square inches of 1oz. copper on the top or bottom PCB layer. Actual value will be different depending
upon the application enviroment.
Note 6: The current sense threshold limits are calculated by averaging the results from the two polarities of the high-side differential amplifier.
Note 7: The measurements were made using the Bill of Materials from Design #3.
Note 8: The measurements were made using the Bill of Materials from Design #3 except the LM3409 was substituted for the LM3409HV.
Note 9: The waveforms were acquired using the standard evaluation board from AN-1953.
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LM3409/LM3409HV/LM3409Q/LM3409QHV
Typical Performance Characteristics
TA = +25°C, VIN = 24V, and characteristics are identical for LM3409 and LM3409HV unless otherwise specified.
VCST vs. Junction Temperature
300856b5
VCC vs. Junction Temperature
300856b6
VADJ vs. Junction Temperature
300856b8
IADJ vs. Junction Temperature
300856b7
VOFT vs. Junction Temperature
300856b9
tON-MIN vs. Junction Temperature
300856c0
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LM3409/LM3409HV/LM3409Q/LM3409QHV
LM3409 Efficiency vs. Input Voltage
VO = 17V (5 LEDs); ILED = 2A (Note 8)
300856f0
LM3409HV Efficiency vs. Input Voltage
VO = 17V (5 LEDs); ILED = 2A (Note 7)
300856b3
LM3409 LED Current vs. Input Voltage
VO = 17V (5 LEDs) (Note 8)
300856f1
LM3409HV LED Current vs. Input Voltage
VO = 17V (5 LEDs) (Note 7)
300856b4
Normalized Switching Frequency
vs. Input Voltage
300856c1
Amplitude Dimming Using IADJ Pin
VO = 17V (5 LEDs); VIN = 24V
300856b2
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LM3409/LM3409HV/LM3409Q/LM3409QHV
Internal EN Pin PWM Dimming
VO = 17V (5 LEDs); VIN = 24V
300856b0
External Parallel FET PWM Dimming
VO = 17V (5 LEDs); VIN = 24V
300856b1
20kHz 50% EN pin PWM dimming
VO = 42V (12 LEDs); VIN = 48V (Note 9)
300856f5
100kHz 50% External FET PWM dimming
VO = 42V (12 LEDs); VIN = 48V (Note 9)
300856f6
20kHz 50% EN pin PWM dimming (rising edge)
VO = 42V (12 LEDs); VIN = 48V (Note 9)
300856f7
100kHz 50% External FET PWM dimming (rising edge)
VO = 42V (12 LEDs); VIN = 48V (Note 9)
300856f8
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LM3409/LM3409HV/LM3409Q/LM3409QHV
Block Diagram
30085603
Theory of Operation
The LM3409/09HV are P-channel MosFET (PFET) con-
trollers for step-down (buck) current regulators which are
ideal for driving LED loads. They have wide input voltage
range allowing for regulation of a variety of LED loads. The
high-side differential current sense, with low adjustable
threshold voltage, provides an excellent method for regulating
output current while maintaining high system efficiency. The
LM3409/09HV uses a Controlled Off-Time (COFT) architec-
ture that allows the converter to be operated in both continu-
ous conduction mode (CCM) and discontinuous conduction
mode (DCM) with no external control loop compensation,
while providing an inherent cycle-by-cycle current limit. The
adjustable current sense threshold provides the capability to
amplitude (analog) dim the LED current over the full range
and the fast output enable/disable function allows for high
frequency PWM dimming using no external components.
When designing, the maximum attainable LED current is not
internally limited because the LM3409/09HV is a controller.
Instead it is a function of the system operating point, compo-
nent choices, and switching frequency allowing the
LM3409/09HV to easily provide constant currents up to 5A.
This simple controller contains all the features necessary to
implement a high efficiency versatile LED driver.
BUCK CURRENT REGULATORS
The buck regulator is unique among non-isolated topologies
due to the direct connection of the inductor to the load during
the entire switching cycle. An inductor will control the rate of
change of current that flows through it, therefore a direct con-
nection to the load is excellent for current regulation. A buck
current regulator, using the LM3409/09HV, is shown in the
Typical Application section on the first page of this datasheet.
During the time that the PFET (Q1) is turned on (tON), the input
voltage charges up the inductor (L1). When Q1 is turned off
(tOFF), the re-circulating diode (D1) becomes forward biased
and L1 discharges. During both intervals, the current is sup-
plied to the load keeping the LEDs forward biased. Figure 1
shows the inductor current (iL(t)) waveform for a buck con-
verter operating in CCM.
The average inductor current (IL) is equal to the average out-
put LED current (ILED), therefore if IL is tightly controlled, ILED
will be well regulated. As the system changes input voltage
or output voltage, duty cycle (D) is varied to regulate IL and
ultimately ILED. For any buck regulator, D is simply the con-
version ratio divided by the efficiency (η):
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LM3409/LM3409HV/LM3409Q/LM3409QHV
30085604
FIGURE 1. Ideal CCM Buck Converter Inductor Current iL(t)
CONTROLLED OFF-TIME (COFT) ARCHITECTURE
The COFT architecture is used by the LM3409/09HV to con-
trol ILED. It is a combination of peak current detection and a
one-shot off-timer that varies with output voltage. D is indi-
rectly controlled by changes in both tOFF and tON, which vary
depending on the operating point. This creates a variable
switching frequency over the entire operating range. This type
of hysteretic control eliminates the need for control loop com-
pensation necessary in many switching regulators, simplify-
ing the design process and providing fast transient response.
Adjustable Peak Current Control
At the beginning of a switching period, PFET Q1 is turned on
and inductor current increases. Once peak current is detect-
ed, Q1 is turned off, the diode D1 forward biases, and inductor
current decreases. Figure 2 shows how peak current detec-
tion is accomplished using the differential voltage signal cre-
ated as current flows through the current setting resistor
(RSNS). The voltage across RSNS (VSNS) is compared to the
adjustable current sense threshold (VCST) and Q1 is turned
off when VSNS exceeds VCST, providing that tON is greater than
the minimum possible tON (typically 115ns).
30085605
FIGURE 2. Peak Current Control Circuit
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LM3409/LM3409HV/LM3409Q/LM3409QHV
There are three different methods to set the current sense
threshold (VCST) using the multi-function IADJ pin:
1. IADJ pin left open: 5µA internal current source biases the
Zener diode and clamps the IADJ pin voltage (VADJ) at
1.24V causing the maximum threshold voltage:
2. External voltage (VADJ) of 0V to 1.24V: Apply to the IADJ
pin to adjust VCST from 0V to 248mV. If the VADJ voltage
is adjustable, analog dimming can be achieved.
3. External resistor (REXT) placed from IADJ pin to ground:
5µA current source sets the VADJ voltage and
corresponding threshold voltage:
Controlled Off-Time
Once Q1 is turned off, it remains off for a constant time
(tOFF) which is preset by an external resistor (ROFF), an ex-
ternal capacitor (COFF), and the output voltage (VO) as shown
in Figure 3. Since ILED is tightly regulated, VO will remain
nearly constant over widely varying input voltage and tem-
perature yielding a nearly constant tOFF.
30085606
FIGURE 3. Off-Time Control Circuit
At the start of tOFF, the voltage across COFF (vCOFF(t)) is zero
and the capacitor begins charging according to the time con-
stant provided by ROFF and COFF. When vCOFF(t) reaches the
off-time threshold (VOFT = 1.24V), then the off-time is termi-
nated and vCOFF(t) is reset to zero. tOFF is calculated as
follows:
In reality, there is typically 20 pF parasitic capacitance at the
off-timer pin in parallel with COFF, which is accounted for in
the calculation of tOFF. Also, it should be noted that the tOFF
equation has a preceding negative sign because the result of
the logarithm should be negative for a properly designed cir-
cuit. The resulting tOFF is a positive value as long as VO >
1.24V. If VO < 1.24V, the off-timer cannot reach VOFT and an
internally limited maximum off-time (typically 300µs) will oc-
cur.
30085607
FIGURE 4. Exponential Charging Function vCOFF(t)
Although the tOFF equation is non-linear, tOFF is actually very
linear in most applications. Ignoring the 20pF parasitic ca-
pacitance at the COFF pin, vCOFF(t) is plotted in Figure 4. The
time derivative of vCOFF(t) can be calculated to find a linear
approximation to the tOFF equation:
When tOFF << ROFF x COFF (equivalent to when VO >> 1.24V),
the slope of the function is essentially linear and tOFF can be
approximated as a current source charging COFF:
Using the actual tOFF equation, the inductor current ripple
(ΔiL-PP) of a buck current regulator operating in CCM is:
Using the tOFF approximation, the equation is reduced to:
ΔiL-PP is independent of both VIN and VO when in CCM!
The ΔiL-PP approximation only depends on ROFF, COFF, and
L1, therefore the ripple is essentially constant over the oper-
ating range as long as VO >> 1.24V (when the tOFF approxi-
mation is valid). An exception to the tOFF approximation
occurs if the IADJ pin is used to analog dim. As the LED/in-
ductor current decreases, the converter will eventually enter
DCM and the ripple will decrease with the peak current thresh-
old. The approximation shows how the LM3409/09HV
achieves constant ripple over a wide operating range, how-
ever tOFF should be calculated using the actual equation first
presented.
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LM3409/LM3409HV/LM3409Q/LM3409QHV
AVERAGE LED CURRENT
For a buck converter, the average LED current is simply the
average inductor current.
30085611
FIGURE 5. Sense Voltage vSNS(t)
Using the COFT architecture, the peak transistor current (IT-
MAX) is sensed as shown in Figure 5, which is equal to the
peak inductor current (IL-MAX) given by the following equation:
Because IL-MAX is set using peak current control and ΔiL-PP is
set using the controlled off-timer, IL and correspondingly
ILED can be calculated as follows:
The threshold voltage VCST seen by the high-side sense com-
parator is affected by the comparator’s input offset voltage,
which causes an error in the calculation of IL-MAX and ulti-
mately ILED. To mitigate this problem, the polarity of the com-
parator inputs is swapped every cycle, which causes the
actual IL-MAX to alternate between two peak values (IL-MAXH
and IL-MAXL), equidistant from the theoretical IL-MAX as shown
in Figure 6. ILED remains accurate through this averaging.
30085612
FIGURE 6. Inductor Current iL(t) Showing IL-MAX Offset
INDUCTOR CURRENT RIPPLE
Because the LM3409/09HV swaps the polarity of the differ-
ential current sense comparator every cycle, a minimum in-
ductor current ripple (ΔiL-PP) is necessary to maintain
accurate ILED regulation. Referring to Figure 6, the first tON is
terminated at the higher of the two polarity-swapped thresh-
olds (corresponding to IL-MAXH). During the following tOFF, iL
decreases until the second tON begins. If tOFF is too short, then
as the second tON begins, iL will still be above the lower peak
current threshold (corresponding to IL-MAXL) and a minimum
tON pulse will follow. This will result in degraded ILED regula-
tion. The minimum inductor current ripple (ΔiL-PP-MIN) should
adhere to the following equation in order to ensure accurate
ILED regulation:
SWITCHING FREQUENCY
The switching frequency is dependent upon the actual oper-
ating point (VIN and VO). VO will remain relatively constant for
a given application, therefore the switching frequency will vary
with VIN (frequency increases as VIN increases). The target
switching frequency (fSW) at the nominal operating point is
selected based on the tradeoffs between efficiency (better at
low frequency) and solution size/cost (smaller at high fre-
quency). The off-time of the LM3409/09HV can be pro-
grammed for switching frequencies up to 5 MHz (theoretical
limit imposed by minimum tON). In practice, switching fre-
quencies higher than 1MHz may be difficult to obtain due to
gate drive limitations, high input voltage, and thermal consid-
erations.
At CCM operating points, fSW is defined as:
At DCM operating points, fSW is defined as:
In the CCM equation, it is apparent that the efficiency (η) fac-
tors into the switching frequency calculation. Efficiency is hard
to estimate and, since switching frequency varies with input
voltage, accuracy in setting the nominal switching frequency
is not critical. Therefore, a general rule of thumb for the
LM3409/09HV is to assume an efficiency between 85% and
100%. When approximating efficiency to target a nominal
switching frequency, the following condition must be met:
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LM3409/LM3409HV/LM3409Q/LM3409QHV
30085614
FIGURE 7. LED Current iLED(t) During EN Pin PWM Dimming
PWM DIMMING USING THE EN PIN
The enable pin (EN) is a TTL compatible input for PWM dim-
ming of the LED. A logic low (below 0.5V) at EN will disable
the internal driver and shut off the current flow to the LED
array. While the EN pin is in a logic low state the support cir-
cuitry (driver, bandgap, VCC regulator) remains active in order
to minimize the time needed to turn the LED array back on
when the EN pin sees a logic high (above 1.74V).
Figure 7 shows the LED current (iLED(t)) during PWM dimming
where duty cycle (DDIM) is the percentage of the dimming pe-
riod (TDIM) that the PFET is switching. For the remainder of
TDIM, the PFET is disabled. The resulting dimmed average
LED current (IDIM-LED) is:
The LED current rise and fall times (which are limited by the
slew rate of the inductor as well as the delay from activation
of the EN pin to the response of the external PFET) limit the
achievable TDIM and DDIM. In general, dimming frequency
should be at least one order of magnitude lower than the
steady state switching frequency in order to prevent aliasing.
However, for good linear response across the entire dimming
range, the dimming frequency may need to be even lower.
HIGH VOLTAGE NEGATIVE BIAS REGULATOR
The LM3409/09HV contains an internal linear regulator where
the steady state VCC pin voltage is typically 6.2V below the
voltage at the VIN pin. The VCC pin should be bypassed to
the VIN pin with at least 1µF of ceramic capacitance connect-
ed as close as possible to the IC.
INPUT UNDER-VOLTAGE LOCKOUT (UVLO)
Under-voltage lockout is set with a resistor divider from VIN to
GND and is compared against a 1.24V threshold as shown in
Figure 8. Once the input voltage is above the preset UVLO
rising threshold (and assuming the part is enabled), the inter-
nal circuitry becomes active and a 22µA current source at the
UVLO pin is turned on. This extra current provides hysteresis
to create a lower UVLO falling threshold. The resistor divider
is chosen to set both the UVLO rising and falling thresholds.
30085613
FIGURE 8. UVLO Circuit
The turn-on threshold (VTURN-ON) is defined as follows:
The hysteresis (VHYS) is defined as follows:
LOW POWER SHUTDOWN
The LM3409/09HV can be placed into a low power shutdown
(typically 110µA) by grounding the EN terminal (any voltage
below 0.5V) until VCC drops below the VCC UVLO threshold
(typically 3.73V). During normal operation this terminal should
be tied to a voltage above 1.74V and below absolute maxi-
mum input voltage rating.
THERMAL SHUTDOWN
Internal thermal shutdown circuitry is provided to protect the
IC in the event that the maximum junction temperature is ex-
ceeded. The threshold for thermal shutdown is 160°C with 15°
C of hysteresis (both values typical). During thermal shut-
down the PFET and driver are disabled.
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LM3409/LM3409HV/LM3409Q/LM3409QHV
Design Considerations
OPERATION NEAR DROPOUT
Because the power MosFET is a PFET, the LM3409/09HV
can be operated into dropout which occurs when the input
voltage is approximately equal to output voltage. Once the
input voltage drops below the nominal output voltage, the
switch remains constantly on (D=1) causing the output volt-
age to decrease with the input voltage. In normal operation,
the average LED current is regulated to the peak current
threshold minus half of the ripple. As the converter goes into
dropout, the LED current is exactly at the peak current thresh-
old because it is no longer switching. This causes the LED
current to increase by half of the set ripple current as it makes
the transition into dropout. Therefore, the inductor current rip-
ple should be kept as small as possible (while remaining
above the previously established minimum) and output ca-
pacitance should be added to help maintain good line regu-
lation when approaching dropout.
LED RIPPLE CURRENT
Selection of the ripple current through the LED array is anal-
ogous to the selection of output ripple voltage in a standard
voltage regulator. Where the output voltage ripple in a voltage
regulator is commonly ±1% to ±5% of the DC output voltage,
LED manufacturers generally recommend values for ΔiLED-
PP ranging from ±5% to ±20% of ILED. For a nominal system
operating point, a larger ΔiLED-PP specification can reduce the
necessary inductor size and/or allow for smaller output ca-
pacitors (or no output capacitors at all) which helps to mini-
mize the total solution size and cost. On the other hand, a
smaller ΔiLED-PP specification would require more output in-
ductance, a higher switching frequency, or additional output
capacitance.
BUCK CONVERTERS W/O OUTPUT CAPACITORS
Because current is being regulated, not voltage, a buck cur-
rent regulator is free of load current transients, therefore
output capacitance is not needed to supply the load and
maintain output voltage. This is very helpful when high fre-
quency PWM dimming the LED load. When no output capac-
itor is used, the same design equations that govern ΔiL-PP also
apply to ΔiLED-PP.
BUCK CONVERTERS WITH OUTPUT CAPACITORS
A capacitor placed in parallel with the LED load can be used
to reduce ΔiLED-PP while keeping the same average current
through both the inductor and the LED array. With an output
capacitor, the inductance can be lowered, making the mag-
netics smaller and less expensive. Alternatively, the circuit
can be run at lower frequency with the same inductor value,
improving the efficiency and increasing the maximum allow-
able average output voltage. A parallel output capacitor is
also useful in applications where the inductor or input voltage
tolerance is poor. Adding a capacitor that reduces ΔiLED-PP to
well below the target provides headroom for changes in in-
ductance or VIN that might otherwise push the maximum
ΔiLED-PP too high.
300856f2
FIGURE 9. Calculating Dynamic Resistance rD
Output capacitance (CO) is determined knowing the desired
ΔiLED-PP and the LED dynamic resistance (rD). rD can be cal-
culated as the slope of the LED’s exponential DC character-
istic at the nominal operating point as shown in Figure 9.
Simply dividing the forward voltage by the forward current at
the nominal operating point will give an incorrect value that is
5x to 10x too high. Total dynamic resistance for a string of n
LEDs connected in series can be calculated as the rD of one
device multiplied by n. The following equations can then be
used to estimate ΔiLED-PP when using a parallel capacitor:
In general, ZC should be at least half of rD to effectively reduce
the ripple. Ceramic capacitors are the best choice for the out-
put capacitors due to their high ripple current rating, low ESR,
low cost, and small size compared to other types. When se-
lecting a ceramic capacitor, special attention must be paid to
the operating conditions of the application. Ceramic capaci-
tors can lose one-half or more of their capacitance at their
rated DC voltage bias and also lose capacitance with ex-
tremes in temperature. Make sure to check any recommend-
ed deratings and also verify if there is any significant change
in capacitance at the operating voltage and temperature.
OUTPUT OVER-VOLTAGE PROTECTION
Because the LM3409/09HV controls a buck current regulator,
there is no inherent need to provide output over-voltage pro-
tection. If the LED load is opened, the output voltage will only
rise as high as the input voltage plus any ringing due to the
parasitic inductance and capacitance present at the output
node. If a ceramic output capacitor is used in the application,
it should have a minimum rating equal to the input voltage.
Ringing seen at the output node should not damage most ce-
ramic capacitors, due to their high ripple current rating.
13 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
INPUT CAPACITORS
Input capacitors are selected using requirements for mini-
mum capacitance and RMS ripple current. The PFET current
during tON is approximately ILED, therefore the input capacitors
discharge the difference between ILED and the average input
current (IIN) during tON. During tOFF, the input voltage source
charges up the input capacitors with IIN. The minimum input
capacitance (CIN-MIN) is selected using the maximum input
voltage ripple (ΔvIN-MAX) which can be tolerated. ΔvIN-MAX is
equal to the change in voltage across CIN during tON when it
supplies the load current. A good starting point for selection
of CIN is to use ΔvIN-MAX of 2% to 10% of VIN. CIN-MIN can be
selected as follows:
An input capacitance at least 75% greater than the calculated
CIN-MIN value is recommended. To determine the RMS input
current rating (IIN-RMS) the following approximation can be
used:
Since this approximation assumes there is no inductor ripple
current, the value should be increased by 10-30% depending
on the amount of ripple that is expected. Ceramic capacitors
are the best choice for input capacitors for the same reasons
mentioned in the Buck Converters with Output Capacitors
section. Careful selection of the capacitor requires checking
capacitance ratings at the nominal operating voltage and tem-
perature.
P-CHANNEL MosFET (PFET)
The LM3409/09HV requires an external PFET (Q1) as the
main power MosFET for the switching regulator. Q1 should
have a voltage rating at least 15% higher than the maximum
input voltage to ensure safe operation during the ringing of
the switch node. In practice all switching converters have
some ringing at the switch node due to the diode parasitic
capacitance and the lead inductance. The PFET should also
have a current rating at least 10% higher than the average
transistor current (IT):
The power rating is verified by calculating the power loss
(PT) using the RMS transistor current (IT-RMS) and the PFET
on-resistance (RDS-ON):
It is important to consider the gate charge of Q1. As the input
voltage increases from a nominal voltage to its maximum in-
put voltage, the COFT architecture will naturally increase the
switching frequency. The dominant switching losses are de-
termined by input voltage, switching frequency, and PFET
total gate charge (Qg). The LM3409/09HV has to provide and
remove charge Qg from the input capacitance of Q1 in order
to turn it on and off. This occurs more often at higher switching
frequencies which requires more current from the internal
regulator, thereby increasing internal power dissipation and
eventually causing the LM3409/09HV to thermally cycle. For
a given range of operating points the only effective way to
reduce these switching losses is to minimize Qg.
A good rule of thumb is to limit Qg < 30nC (if the switching
frequency remains below 300kHz for the entire operating
range then a larger Qg can be considered). If a PFET with
small RDS-ON and a high voltage rating is required, there may
be no choice but to use a PFET with Qg > 30nC.
When using a PFET with Qg > 30nC, the bypass capacitor
(CF) should not be connected to the VIN pin. This will ensure
that peak current detection through RSNS is not affected by
the charging of the PFET input capacitance during switching,
which can cause false triggering of the peak detection com-
parator. Instead, CF should be connected from the VCC pin
to the CSN pin which will cause a small DC offset in VCST and
ultimately ILED, however it avoids the problematic false trig-
gering.
In general, the PFET should be chosen to meet the Qg spec-
ification whenever possible, while minimizing RDS-ON. This will
minimize power losses while ensuring the part functions cor-
rectly over the full operating range.
RE-CIRCULATING DIODE
A re-circulating diode (D1) is required to carry the inductor
current during tOFF. The most efficient choice for D1 is a
Schottky diode due to low forward voltage drop and near-zero
reverse recovery time. Similar to Q1, D1 must have a voltage
rating at least 15% higher than the maximum input voltage to
ensure safe operation during the ringing of the switch node
and a current rating at least 10% higher than the average
diode current (ID):
The power rating is verified by calculating the power loss
through the diode. This is accomplished by checking the typ-
ical diode forward voltage (VD) from the I-V curve on the
product datasheet and calculating as follows:
In general, higher current diodes have a lower VD and come
in better performing packages minimizing both power losses
and temperature rise.
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LM3409/LM3409HV/LM3409Q/LM3409QHV
30085616
FIGURE 10. Ideal LED Current iLED(t) During Parallel FET Dimming
EXTERNAL PARALLEL FET PWM DIMMING
Any buck topology LED driver is a good candidate for parallel
FET dimming because high slew rates are achievable, due to
the fact that no output capacitance is required. This allows for
much higher dimming frequencies than are achievable using
the EN pin. When using external parallel FET dimming, a sit-
uation can arise where maximum off-time occurs due to a
shorted output. To mitigate this situation, capacitive coupling
to the enable pin can be employed.
30085617
FIGURE 11. External Parallel FET Dimming Circuit
As shown in Figure 11, a small capacitor (CEXT) is connected
from the gate drive signal of the parallel Dim FET to the EN
pin and a pull-up resistor (REXT) is placed from the EN pin to
the external VDD supply for the Dim FET gate driver. This
forces the on-timer to restart corresponding to every rising
edge of the LED voltage, ensuring that the unwanted maxi-
mum off-time condition does not occur. With this type of
dimming, the EN pin does not control the dimming; it simply
resets the controller. A good design choice is to size REXT and
CEXT to give a time constant smaller than tOFF:
The ideal LED current waveform iLED(t) during parallel FET
PWM dimming is very similar to the EN pin PWM dimming
shown previously. The LED current does not rise and fall in-
finitely fast as shown in Figure 10 however with this method,
only the speed of the parallel Dim FET ultimately limits the
dimming frequency and dimming duty cycle. This allows for
much faster PWM dimming than can be attained with the EN
pin.
CIRCUIT LAYOUT
The performance of any switching converter depends as
much upon the layout of the PCB as the component selection.
Following a few simple guidelines will maximimize noise re-
jection and minimize the generation of EMI within the circuit.
Discontinuous currents are the most likely to generate EMI,
therefore care should be taken when routing these paths. The
main path for discontinuous current in the LM3409/09HV buck
converter contains the input capacitor (CIN), the recirculating
diode (D1), the P-channel MosFET (Q1), and the sense re-
sistor (RSNS). This loop should be kept as small as possible
and the connections between all three components should be
short and thick to minimize parasitic inductance. In particular,
the switch node (where L1, D1 and Q1 connect) should be
just large enough to connect the components without exces-
sive heating from the current it carries.
The IADJ, COFF, CSN and CSP pins are all high-impedance
control inputs which couple external noise easily, therefore
the loops containing these high impedance nodes should be
minimized. The most sensitive loop contains the sense resis-
tor (RSNS) which should be placed as close as possible to the
CSN and CSP pins to maximize noise rejection. The off-time
capacitor (COFF) should be placed close to the COFF and
GND pins for the same reason. Finally, if an external resistor
(REXT) is used to bias the IADJ pin, it should be placed close
to the IADJ and GND pins, also.
In some applications the LED or LED array can be far away
(several inches or more) from the LM3409/09HV, or on a sep-
arate PCB connected by a wiring harness. When an output
capacitor is used and the LED array is large or separated from
the rest of the converter, the output capacitor should be
placed close to the LEDs to reduce the effects of parasitic
inductance on the AC impedance of the capacitor.
15 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
Design Guide
TYPICAL APPLICATION
30085601
SPECIFICATIONS
Nominal input voltage: VIN
Maximum input voltage: VIN-MAX
Nominal output voltage (# of LEDs x forward voltage): VO
LED string dynamic resistance: rD
Switching frequency (at nominal VIN, VO): fSW
Average LED current: ILED
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Input voltage ripple: ΔvIN-PP
UVLO characteristics: VTURN-ON and VHYS
Expected efficiency: η
1. NOMINAL SWITCHING FREQUENCY
Calculate switching frequency (fSW) at the nominal operating
point (VIN and VO). Assume a COFF value (between 470pF and
1nF) and a system efficiency (η). Solve for ROFF:
2. INDUCTOR RIPPLE CURRENT
Set the inductor ripple current (ΔiL-PP) by solving for the ap-
propriate inductor (L1):
3. AVERAGE LED CURRENT
Set the average LED current (ILED) by first solving for the peak
inductor current (IL-MAX):
Peak inductor current is detected across the sense resistor
(RSNS). In most cases, assume the maximum value (VADJ =
1.24V) at the IADJ pin and solve for RSNS:
If the calculated RSNS is far from a standard value, the begin-
ning of the process can be iterated to choose a new ROFF, L1,
and RSNS value that is a closer fit. The easiest way to ap-
proach the iterative process is to change the nominal fSW
target knowing that the switching frequency varies with oper-
ating conditions anyways.
Another method for finding a standard RSNS value is to change
the VADJ value. However, this would require an external volt-
age source or a resistor from the IADJ pin to GND as ex-
plained in the Theory of Operation section of this datasheet.
www.national.com 16
LM3409/LM3409HV/LM3409Q/LM3409QHV
4. OUTPUT CAPACITANCE
A minimum output capacitance (CO-MIN) may be necessary to
reduce ΔiLED-PP below ΔiL-PP. With the specified ΔiLED-PP and
the known dynamic resistance (rD) of the LED string, solve for
the required impedance (ZC) for CO-MIN:
Solve for CO-MIN:
5. INPUT CAPACITANCE
Set the input voltage ripple (ΔvIN-PP) by solving for the re-
quired minimum capacitance (CIN-MIN):
The necessary RMS input current rating (IIN-RMS) is:
6. PFET
The PFET voltage rating should be at least 15% higher than
the maximum input voltage (VIN-MAX) and current rating should
be at least 10% higher than the average PFET current (IT):
Given a PFET with on-resistance (RDS-ON), solve for the RMS
transistor current (IT-RMS) and power dissipation (PT):
7. DIODE
The Schottky diode needs a voltage rating similar to the
PFET. Higher current diodes with a lower forward voltage are
suggested. Given a diode with forward voltage (VD), solve for
the average diode current (ID) and power dissipation (PD):
8. INPUT UVLO
Input UVLO is set with the turn-on threshold voltage (VTURN-
ON) and the desired hysteresis (VHYS). To set VHYS, solve for
RUV2:
To set VTURN-ON, solve for RUV1:
9. IADJ CONNECTION METHOD
The IADJ pin controls the high-side current sense threshold
in three ways outlined in the Theory of Operation section.
Method #1: Leave IADJ pin open and ILED is calculated as in
the Average LED Current section of the Design Guide.
Method #2: Apply an external voltage (VADJ) to the IADJ pin
between 0 and 1.24V to analog dim or to reduce ILED as fol-
lows:
Keep in mind that analog dimming will eventually push the
converter in to DCM and the inductor current ripple will no
longer be constant causing a divergence from linear dimming
at low levels.
A 0.1µF capacitor connected from the IADJ pin to GND is
recommended when using this method. It may also be nec-
essary to have a 1k series resistor with the capacitor to
create an RC filter. The filter will help remove high frequency
noise created by other connected circuitry.
Method #3: Connect an external resistor or potentiometer to
GND (REXT) and the internal 5µA current source will set the
voltage. Again, a 0.1µF capacitor connected from the IADJ
pin to GND is recommended. To set ILED, solve for REXT:
10. PWM DIMMING METHOD
There are two methods to PWM dim using the LM3409/09HV:
Method #1: Apply an external PWM signal to the EN terminal.
Method #2: Perform external parallel FET shunt dimming as
detailed in the External Parallel FET PWM Dimming section.
17 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
Design Example #1
EN PIN PWM DIMMING APPLICATION FOR 10 LEDS
30085618
SPECIFICATIONS
fSW = 525kHz
VIN = 48V; VIN-MAX = 75V
VO = 35V
ILED = 2A
ΔiLED-PP = ΔiL-PP = 1A
ΔvIN-PP = 1.44V
VTURN-ON = 10V; VHYS = 1.1V
η = 0.95
1. NOMINAL SWITCHING FREQUENCY
Assume COFF = 470pF and η = 0.95. Solve for ROFF:
The closest 1% tolerance resistor is 24.9 k therefore the
actual tOFF and target fSW are:
The chosen components from step 1 are:
2. INDUCTOR RIPPLE CURRENT
Solve for L1:
The closest standard inductor value is 15 µH therefore the
actual ΔiL-PP is:
The chosen component from step 2 is:
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LM3409/LM3409HV/LM3409Q/LM3409QHV
3. AVERAGE LED CURRENT
Determine IL-MAX:
Assume VADJ = 1.24V and solve for RSNS:
The closest 1% tolerance resistor is 0.1 therefore the ILED
is:
The chosen component from step 3 is:
4. OUTPUT CAPACITANCE
No output capacitance is necessary.
5. INPUT CAPACITANCE
Determine tON:
Solve for CIN-MIN:
Choose CIN:
Determine IIN-RMS:
The chosen components from step 5 are:
6. PFET
Determine minimum Q1 voltage rating and current rating:
A 100V, 3.8A PFET is chosen with RDS-ON = 190m and Qg
= 20nC. Determine IT-RMS and PT:
The chosen component from step 6 is:
7. DIODE
Determine minimum D1 voltage rating and current rating:
A 100V, 3A diode is chosen with VD = 750mV. Determine
PD:
The chosen component from step 7 is:
19 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
8. INPUT UVLO
Solve for RUV2:
The closest 1% tolerance resistor is 49.9 k therefore VHYS
is:
Solve for RUV1:
The closest 1% tolerance resistor is 6.98 k therefore VTURN-
ON is:
The chosen components from step 8 are:
9. IADJ CONNECTION METHOD
The IADJ pin is left open forcing VADJ = 1.24V.
10. PWM DIMMING METHOD
PWM dimming signal pair is applied to the EN pin and GND
at fDIM = 1 kHz.
Design #1 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3409HV/
LM3409QHV
Buck controller NSC LM3409HVMY/
LM3409QHVMY
2 CIN1, CIN2 2.2µF X7R 10% 100V MURATA GRM43ER72A225KA01
L
1 CF1.0µF X7R 10% 16V TDK C1608X7R1C105K
1 COFF 470pF X7R 10% 50V TDK C1608X7R1H471K
1 Q1 PMOS 100V 3.8A ZETEX ZXMP10A18KTC
1 D1 Schottky 100V 3A VISHAY SS3H10-E3/57T
1 L1 15 µH 20% 4.2A TDK SLF12565T-150M4R2
1 ROFF 24.9kΩ 1% VISHAY CRCW060324K9FKEA
1 RUV1 6.98kΩ 1% VISHAY CRCW06036K98FKEA
1 RUV2 49.9kΩ 1% VISHAY CRCW060349K9FKEA
1 RSNS 0.1Ω 1% 1W VISHAY WSL2512R1000FEA
www.national.com 20
LM3409/LM3409HV/LM3409Q/LM3409QHV
Design Example #2
ANALOG DIMMING APPLICATION FOR 4 LEDS
30085619
SPECIFICATIONS
fSW = 500kHz
VIN = 24V; VIN-MAX = 42V
VO = 14V
ILED = 1A
ΔiL-PP = 450mA; ΔiLED-PP = 50mA
ΔvIN-PP = 1V
VTURN-ON = 10V; VHYS = 1.1V
η = 0.90
1. NOMINAL SWITCHING FREQUENCY
Assume COFF = 470pF and η = 0.90. Solve for ROFF:
The closest 1% tolerance resistor is 15.4 k therefore the
actual tOFF and target fSW are:
The chosen components from step 1 are:
2. INDUCTOR RIPPLE CURRENT
Solve for L1:
The closest standard inductor value is 22 µH therefore the
actual ΔiL-PP is:
The chosen component from step 2 is:
21 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
3. AVERAGE LED CURRENT
Determine IL-MAX:
Assume VADJ = 1.24V and solve for RSNS:
The closest 1% tolerance resistor is 0.2 therefore ILED is:
The chosen component from step 3 is:
4. OUTPUT CAPACITANCE
Assume rD = 2 Ω and determine ZC:
Solve for CO-MIN and :
Choose CO:
The chosen component from step 5 is:
5. INPUT CAPACITANCE
Determine tON:
Solve for CIN-MIN:
Choose CIN:
Determine IIN-RMS:
The chosen component from step 5 is:
6. PFET
Determine minimum Q1 voltage rating and current rating:
A 70V, 5.7A PFET is chosen with RDS-ON = 190m and Qg =
20nC. Determine IT-RMS and PT:
The chosen component from step 6 is:
7. DIODE
Determine minimum D1 voltage rating and current rating:
A 60V, 5A diode is chosen with VD = 750mV. Determine PD:
The chosen component from step 7 is:
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LM3409/LM3409HV/LM3409Q/LM3409QHV
8. INPUT UVLO
Solve for RUV2:
The closest 1% tolerance resistor is 49.9 k therefore VHYS
is:
Solve for RUV1:
The closest 1% tolerance resistor is 6.98 k therefore VTURN-
ON is:
The chosen components from step 8 are:
9. IADJ CONNECTION METHOD
The IADJ pin is connected to an external voltage source and
varied from 0 – 1.24V to dim. An RC filter (RF2 = 1 k and
CF2 = 0.1µF) is used as recommended.
10. PWM DIMMING METHOD
No PWM dimming is necessary.
Design #2 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3409/LM3409Q Buck controller NSC LM3409MY/LM3409QMY
2 CIN1 4.7µF X7R 10% 50V MURATA GRM55ER71H475MA01L
1 CF1.0µF X7R 10% 16V TDK C1608X7R1C105K
1 CF2 0.1µF X7R 10% 16V TDK C1608X7R1C104K
1 COFF 470pF X7R 10% 50V TDK C1608X7R1H471K
1 CO2.2µF X7R 10% 50V MURATA GRM43ER71H225MA01L
1 Q1 PMOS 70V 5.7A ZETEX ZXMP7A17KTC
1 D1 Schottky 60V 5A COMCHIP CDBC560-G
1 L1 22 µH 20% 4.2A TDK SLF12575T-220M4R0
1 RF2 1.0kΩ 1% VISHAY CRCW06031K00FKEA
1 ROFF 15.4kΩ 1% VISHAY CRCW060315K4FKEA
1 RUV1 6.98kΩ 1% VISHAY CRCW06036K98FKEA
1 RUV2 49.9kΩ 1% VISHAY CRCW060349K9FKEA
1 RSNS 0.2Ω 1% 1W VISHAY WSL2512R2000FEA
23 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
Applications Information
DESIGN #3: EXTERNAL PARALLEL FET PWM DIMMING APPLICATION FOR 10 LEDS
30085623
Design #3 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3409HV/
LM3409QHV
Buck controller NSC LM3409HVMY/
LM3409QHVMY
2 CIN1, CIN2 2.2µF X7R 10% 100V MURATA GRM43ER72A225KA01L
1 CF1.0µF X7R 10% 16V TDK C1608X7R1C105K
1 COFF 470pF X7R 10% 50V TDK C1608X7R1H471K
1 C1 2200pF X7R 10% 50V MURATA GRM188R71H222KA01D
1 Q1 PMOS 100V 3.8A ZETEX ZXMP10A18KTC
1 Q2 CMOS 30V 2A FAIRCHILD FDC6333C
1 Q3 NMOS 100V 7.5A FAIRCHILD FDS3672
1 D1 Schottky 100V 3A VISHAY SS3H10-E3/57T
1 L1 15 µH 20% 4.2A TDK SLF12565T-150M4R2
2 R1, R2 1Ω 1% VISHAY CRCW06031R00FNEA
1 R3 10kΩ 1% VISHAY CRCW060310K0FKEA
1 REXT 100Ω 1% VISHAY CRCW0603100RFKEA
1 ROFF 24.9kΩ 1% VISHAY CRCW060324K9FKEA
1 RUV1 6.98kΩ 1% VISHAY CRCW06036K98FKEA
1 RUV2 49.9kΩ 1% VISHAY CRCW060349K9FKEA
1 RSNS 0.1Ω 1% 1W VISHAY WSL2512R1000FEA
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LM3409/LM3409HV/LM3409Q/LM3409QHV
DESIGN #4: SINGLE POTENTIOMETER ANALOG DIMMING APPLICATION FOR 6 LEDS
30085622
Design #4 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3409/LM3409Q Buck controller NSC LM3409MY/LM3409QMY
2 CIN1, CIN2 2.2µF X7R 10% 50V MURATA GRM43ER71H225MA01L
1 CF1.0µF X7R 10% 16V TDK C1608X7R1C105K
1 CF2 0.1µF X7R 10% 16V TDK C1608X7R1C104K
1 COFF 470pF X7R 10% 50V TDK C1608X7R1H471K
1 CO1.0µF X7R 10% 50V MURATA GRM32RR71H105KA01L
1 Q1 PMOS 60V 3A ZETEX ZXMP6A17GTA
1 D1 Schottky 60V 2A ST-MICRO STPS2L60A
1 L1 68 µH 20% 2A TDK SLF12565T-680M2R0
1 ROFF 25.5kΩ 1% VISHAY CRCW060325K5FKEA
1 RUV1 6.98kΩ 1% VISHAY CRCW06036K98FKEA
1 RUV2 49.9kΩ 1% VISHAY CRCW060349K9FKEA
1 RSNS 0.3Ω 1% 1W VISHAY WSL2512R3000FEA
1 RADJ 250k potentiometer BOURNS 3352P-1-254
25 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
DESIGN #5: 75°C THERMAL FOLDBACK APPLICATION FOR 16 LEDS
30085624
Design #5 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3409HV/
LM3409QHV
Buck controller NSC LM3409HVMY/LM3409QHVMY
1 U1 Analog Temperature Sensor NSC LM94022
2 CIN1, CIN2 2.2µF X7R 10% 100V MURATA GRM43ER72A225KA01L
1 CF1.0µF X7R 10% 16V TDK C1608X7R1C105K
1 CF2 0.1µF X7R 10% 16V TDK C1608X7R1C104K
1 COFF 470pF X7R 10% 50V TDK C1608X7R1H471K
1 Q1 PMOS 100V 3.8A ZETEX ZXMP10A18KTC
1 D1 Schottky 100V 3A COMCHIP SS3H10-E3/57T
1 L1 15 µH 20% 4.7A TDK SLF12575T-150M4R7
1 ROFF 24.9kΩ 1% VISHAY CRCW060324K9FKEA
1 RUV1 6.98kΩ 1% VISHAY CRCW06036K98FKEA
1 RUV2 49.9kΩ 1% VISHAY CRCW060349K9FKEA
1 RSNS 0.07Ω 1% 1W VISHAY WSL2512R0700FEA
*U2 could be replaced with a 500k NTC thermistor connected from IADJ to GND.
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LM3409/LM3409HV/LM3409Q/LM3409QHV
DESIGN #6: HIGH CURRENT APPLICATION FOR 4 LEDS
300856f4
Design #6 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3409/LM3409Q Buck controller NSC LM3409MY/LM3409QMY
2 CIN1 10µF X7R 10% 50V TDK C5750X7R1H106K
1 CF1.0µF X7R 10% 16V TDK C1608X7R1C105K
1 CF2 0.1µF X7R 10% 16V TDK C1608X7R1C104K
1 COFF 470pF X7R 10% 50V TDK C1608X7R1H471K
1 CO1.0µF X7R 10% 50V MURATA GRM32RR71H105KA01L
1 Q1 PMOS 30V 24A ST-MICRO STD30PF03LT4
1 D1 Schottky 30V 5A VISHAY SSC53L-E3/57T
1 L1 15 µH 20% 7.5A COILCRAFT DO5022P-153ML
1 RF2 1.0kΩ 1% VISHAY CRCW06031K00FKEA
1 ROFF 23.2kΩ 1% VISHAY CRCW060323K2FKEA
1 RUV1 6.98kΩ 1% VISHAY CRCW06036K98FKEA
1 RUV2 49.9kΩ 1% VISHAY CRCW060349K9FKEA
1 RSNS 0.05Ω 1% 1W VISHAY WSL2512R0500FEA
*U2 could be replaced with a 500k NTC thermistor connected from IADJ to GND.
27 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
Physical Dimensions inches (millimeters) unless otherwise noted
10-Lead Exposed Pad Plastic eMSOP Package
NS Package Number MUC10A
www.national.com 28
LM3409/LM3409HV/LM3409Q/LM3409QHV
Notes
29 www.national.com
LM3409/LM3409HV/LM3409Q/LM3409QHV
Notes
LM3409 / LM3409HV / LM3409Q / LM3409QHV PFET Buck Controller for High Power LED Drivers
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