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1. General description
The HEF4093B-Q100 is a quad two-input NAND gate. Each input has a Schmitt trigger
circuit. The gate switches a t dif ferent points for positive-going and negative-going signals.
The difference between the positive voltage (VT+) and the negative voltage (VT) is
defined as hysteresis voltage (VH).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to V SS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Schmitt trigger input discrimination
Fully static operation
5 V, 10 V, and 15 V para metric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
4. Ordering information
HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
Rev. 1 — 12 July 2012 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +125
C
Type number Package
Name Description Version
HEF4093BT-Q100 SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 2 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
5. Functional diagram
6. Pinning information
6.1 Pinning
Fig 1. Functional di ag ram Fig 2. Logic diagram (one ga te)
001aag104
1
1A
2
1B
5
2A
6
2B
8
3A
9
3B
12
4A
13
4B
3
4
10
11
1Y
2Y
3Y
4Y
001aag105
nA
nB
nY
Fig 3. Pin configuratio n
HEF4093B-Q100
1A VDD
1B 4B
1Y 4A
2Y 4Y
2A 3Y
2B 3B
VSS 3A
aaa-003547
1
2
3
4
5
6
78
10
9
12
11
14
13
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 3 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
[1] For SO14 package: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
Table 2. Pin description
Symbol Pin Description
1A to 4A 1, 5, 8, 12 input
1B to 4B 2, 6, 9, 13 input
1Y to 4Y 3, 4, 10, 11 output
VDD 14 supply voltage
VSS 7 ground (0 V)
Table 3. Function table[1]
Input Output
nA nB nY
LLH
LHH
HLH
HHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI<0.5 V or VI>V
DD + 0.5 V - 10 mA
VIinput voltage 0.5 VDD + 0.5 V
IOK output clamping curre nt VO<0.5 V or VO>V
DD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +125 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO14 [1] -500mW
P power di ssipation per output - 100 mW
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 4 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 3 15 V
VIinput voltage 0 VDD V
Tamb ambient temperature in free air 40 +125 C
Table 6. Static characteristics
VSS = 0 V; VI=V
SS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 CUnit
Min Max Min Max Min Max Min Max
VOH HIGH-level
output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level
output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
IOH HIGH-level
output cur r en t VO = 2.5 V 5 V 1.7 - 1.4 - 1.1 - 1.1 - mA
VO = 4.6 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA
VO = 9.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 13.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
IOL LOW-level
output cur r en t VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0 .3 6 - mA
VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
IIinput leakage
current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A
IDD supply current all valid input
combinations;
IO=0A
5 V - 0.25 - 0.25 - 7.5 - 7.5 A
10 V - 0.5 - 0.5 - 15.0 - 15.0 A
15 V - 1.0 - 1.0 - 30.0 - 30.0 A
CIinput
capacitance ---7.5-- - -pF
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 5 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
[1] Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 7. Dy namic characteristics
Tamb = 25
C; CL = 50 pF; tr = tf
20 ns; wave forms see Figure 4; test circuit see Figure 5; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW
propagation delay nA or nB to nY 5 V 63 ns + (0.55 ns/pF)CL- 90 185 ns
10 V 29 ns + (0.23 ns/pF)CL-4080ns
15 V 22 ns + (0.16 ns/pF)CL-3060ns
tPLH LOW to HIGH
propagation delay nA or nB to nY 5 V 58 ns + (0.55 ns/pF)CL- 85 170 ns
10 V 29 ns + (0.23 ns/pF)CL-4080ns
15 V 22 ns + (0.16 ns/pF)CL-3060ns
tTHL HIGH to LOW output
transition time nY to LOW 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns
10 V 9 ns + (0.42 ns/pF)C L-3060ns
15 V 6 ns + (0.28 ns/pF)C L-2040ns
tTLH LOW to HIGH output
transition time nA or nB to
HIGH 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns
10 V 9 ns + (0.42 ns/pF)C L-3060ns
15 V 6 ns + (0.28 ns/pF)C L-2040ns
Table 8. Dynamic po wer dissipation
VSS = 0 V; tr = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula where:
PDdynamic power
dissipation 5V P
D = 1300 fi + (fo CL) VDD2 (W) fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.
10 V PD = 6400 fi + (fo CL) VDD2 (W)
15 V PD = 18700 fi + (fo CL) VDD2 (W)
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 6 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
12. Waveforms
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
tr, tf = input rise and fall times.
Fig 4. Prop agation delay a nd ou tpu t transition time
001aag197
input
output
tPLH
tPHL
0 V
VI
VM
VM
VOH
VOL tTLH
tTHL
90 %
10 %
10 %
90 %
trtf
Table 9. Measurement points
Supply voltage Input Output
VDD VMVM
5 V to 15 V 0.5VDD 0.5VDD
Test data given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL= load capacitance including jig and probe capacitance.
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 5. Test circuit
VDD
VIVO
001aag182
DUT
CL
RT
G
Table 10. Test data
Supply voltage Input Load
VDD VItr, tfCL
5 V to 15 V VSS or VDD 20 ns 50 pF
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 7 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
13. Transfer characteristics
Table 11. Tran sfer ch aracteristics
VSS =0V; T
amb = 25
C; see Figure 6 and Figure 7.
Symbol Parameter Conditions VDD Min Typ Max Unit
VT+ positive-going threshold voltage 5 V 1.9 2.9 3.5 V
10 V 3.6 5.2 7 V
15 V 4.7 7.3 11 V
VTnegative-going threshold voltage 5 V 1.5 2.2 3.1 V
10 V 3 4.2 6.4 V
15 V 4 6.0 10.3 V
VHhysteresis voltage 5 V 0.4 0.7 - V
10 V 0.6 1.0 - V
15 V 0.7 1.3 - V
Fig 6. Transfer characteristic Fig 7. Waveforms showing definition of VT+ and VT
(between limits at 30 % and 70 %) and VH
001aag107
VO
VI
VHVT+
VT−
001aag108
VO
VIVH
VT+
VT−
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 8 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
a. VDD = 5 V; Tamb = 25 Cb.V
DD = 10 V; Tamb = 25 C
c. VDD = 15 V; Tamb = 25 C
Fig 8. Typical drain current as a function of input
VI (V)
02010
001aag111
2000
1000
IDD
(μA)
0
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 9 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
14. Application information
Some examples of applications for the HEF4093B-Q100 are:
•Wave and pulse shapers
•Astable multivibrators
•Monostable multivibrators
If a Schmitt trigger is driven via a high-impedance (R > 1 k), then it is necessary to
incorporate a capacitor C with a value of ; otherwise oscillation can occur
on the edges of a pulse.
Cp is the external parasitic capacitance betwe en inp uts and output; the value depends on
the circuit board layout.
Remark: The two inputs may be connected together, but this will result in a larger
through-current at the moment of switching.
Tamb = 25 C.
Fig 9. Typical switchin g le ve ls as a function of supply voltage
VDD (V)
2.5 17.512.57.551510
001aag112
5
10
VI
(V)
0
VT+
VT−
Fig 10. Astable multivibrator Fig 11. Schmitt trigg e r dr iv en via a
high-impedance input
001aag113
V
DD
V
DD
1
23
7
14
Cp
R
C
001aag114
V
DD
V
DD
1
23
7
14
C
CP
------ VDD VSS
–
VH
------------------------->
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 10 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
15. Package outline
Fig 12. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 11 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
16. Abbreviations
17. Revision history
Table 12. Abbreviations
Acronym Description
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Model
MIL Military
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4093B_Q100 v.1 20120712 Product specification - -
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 12 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
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Limited warr a nty and liability — Information in this document is believed to
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representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
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changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — T his NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, t he product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
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products planned, as well as fo r the planned application and use of
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applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the appl ication or use by customer’s
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Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
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applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] dat a sheet Production This document contains the product specification.
HEF4093B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 12 July 2012 13 of 14
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
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Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4093B-Q100
Quad 2-input NAND Schmitt trigger
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 July 2012
Document identifier: HEF4093B_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
13 Transfer characteristics . . . . . . . . . . . . . . . . . . 7
14 Application information. . . . . . . . . . . . . . . . . . . 9
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
19 Contact information. . . . . . . . . . . . . . . . . . . . . 13
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14