In-Circuit Test Support with MAX 7000 Devices
Technical Brief 58 December 1999, ver. 1
M-TB-058-01
Altera Corporation 1
Introduction
Altera
®
MAX
®
7000S, MAX 7000A, and MAX 7000B devices support in-system
programming with in-circuit test (ICT) equipment, offering significant time and cost
benefits by integrating programmable logic devices (PLDs) into board-level testing. Altera
provides software and device support that easily integrates in-system programmability
(ISP) into test flows. This technical brief outlines ICT support and ISP methods for
MAX 7000 devices.
ISP via In-Circuit Testers
ISP via in-circuit testers is accomplished with either an adaptive or constant algorithm. An
adaptive algorithm reads information from a device and adapts subsequent programming
steps to achieve the fastest possible programming time for that specific device. A constant
algorithm uses a pre-defined (non-adaptive) programming sequence. Some tester platforms
are well-suited to support adaptive algorithms while others are not. MAX 7000 devices can
use adaptive or constant algorithms and work with either tester platform.
SVF vs. Jam STAPL
Serial Vector Format (
.svf
) files do not support adaptive programming algorithms.
Consequently, testers using SVF files must program at the device’s worst-case
programming pulse width. For example, SVF-based testers program MAX 7000AE and
MAX 7000B devices at their worst-case programming pulse width of 20 ms, yielding fast
programming times. However, SVF-based testers program MAX 7000S devices at their
worst-case programming pulse width of 200 ms, yielding less than optimal programming
times.
To minimize SVF-based tester programming times for MAX 7000S devices, Altera offers
MAX 7000S devices with a fixed programming pulse width of only 30 ms. These fixed
programming devices have an “F” at the end of their ordering codes and are called “F”
devices. To obtain production-worthy in-system programming times when using SVF-
based testers such as HP 3070 and GenRad 228X, designers must use fixed programming
MAX 7000S devices. Since MAX 7000AE and MAX 7000B devices have a worst-case
programming pulse width of 20 ms, they do not require a fixed programming algorithm to
achieve production-worthy programming times.
Unlike SVF, the Jam
TM
Standard Test and Programming Language (STAPL), JEDEC
standard JESD-71, uses an adaptive algorithm, offering the ability to program devices faster
than their worst-case programming pulse width. Jam STAPL allows each device to be
programmed at its optimal programming pulse width. Moreover, testers that support the
Jam STAPL format use smaller file sizes and have faster programming times than those that
do not.
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
https://websupport.altera.com