74VHC245MTC - Fairchild Semiconductor

November 1992

Revised April 2005

74VHC245 Octal Bidirectional Transceiver with 3-STATE Outputs

74VHC245

Octal Bidirecti onal Transceiver with 3-STATE Outputs

General Descript ion

The VHC 245 is an advanced hi gh speed CMOS octal bus

transceiver fabricated with silicon gate CMOS technology.

It achieves high speed operation similar to equivalent Bipo-

lar Schottky TTL while maintaining the CMOS low power

dissipation. T he VHC245 is i nte nde d fo r b idi re ction al asyn-

chronous com munic ation b etween da ta busses. Th e dire c-

tion of data transmission is determined by th e level of the

T/R input. The enable input can be used to disable the

device so that the busses are effectively isolated. All inputs

are equipped with protection circuits against static dis-

charge.

Features

■High Speed: tPD

4.0 ns (typ) at VCC

■High Noise Immunity: VNIH

VNIL

28% VCC (Min)

■Power Down Protection is provided on all inputs

■Low Noise: VOLP

0.9V (typ)

■Low Power Dissipatio n:

ICC

A (Max) @ TA

■Pin and Function Compatible with 74HC245

Ordering Code:

Surface m ount pack ages are also avai lable on Tape and R eel. Specify by ap pending th e s uffix let t er “X” to the o rdering code.

Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

IEEE/IEC

Pin Description

Connection Diagram

Truth Table

HIGH Voltage Leve l L

LOW Voltage Leve l X

Immaterial

Any unused bus terminals during HIGH-Z State must be held HIGH or

LOW.

Order Number Package Number Package Description

74VHC245M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC245SJ M20D Pb-Free 20-Lead Small Outlin e Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Description

Names

OE Output Enable Input

T/R Transmit/Receive Input

A0–A7Side A Inputs or 3-STATE Outputs

B0–B7Side B Inputs or 3-STATE Outputs

Inputs Outputs

OE T/R

L L Bus B Data to Bus A

L H Bus A Data to Bus B

H X HIGH-Z S tate

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74VHC245

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: Absolute Maximum Ratings are values beyond which the device

may be damaged or have its useful life impaired. The databook specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 2: Unused inputs or I/O pins must be held HIGH or LOW. They may

not float.

DC Electrical Characteristi cs

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Voltage (VIN) (T/R, OE)



0.5V to 7.0V

DC Output Voltage (VOUT)



0.5V to VCC



0.5V

Input Diode Current (IIK) (T/R, OE)



20 mA

Output Diode Current (IOK)

20 mA

DC Output Curren t (IOUT)

25 mA

DC VCC/GND Current (ICC)

75 mA

Storage Tem per atu re (TSTG)



C to



150

Lead Temperature (TL)

(Soldering, 10 seconds) 260

Supply Voltage (VCC) 2.0V to 5.5V

Input Voltage (VIN)(T/R, OE)0V to 5.5V

Output Voltage (VOUT) 0V to VCC

Operati ng Temper ature (TOPR)



C to



Input Rise and Fall Time (tr, tf)

VCC

3.3V

0.3V 0

100 ns/V

VCC

5.0V

0.5V 0

20 ns/V

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Min Typ Max Min Max

VIH HIGH Level 2.0 1.50 1.50 V

Input V oltage 3.0



5.5 0.7 VCC 0.7 VCC

VIL LOW Level 2.0 0.50 0.50 V

Input V oltage 3.0



5.5 0.3 VCC 0.3 VCC

VOH HIGH Level 2.0 1.9 2.0 1.9 VIN

VIH IOH



Output Voltage 3.0 2.9 3.0 2.9 V or VIL

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH



4 mA

4.5 3.94 3.80 IOH



8 mA

VOL LOW Level 2.0 0.0 0.1 0.1 VIN

VIH IOL

Output Voltage 3.0 0.0 0.1 0.1 V or VIL

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL

4 mA

4.5 0.36 0.44 IOL

8 mA

IOZ 3-STAT E Output VIN

VCC or GND

Off-State Current 5.5

0.25

2.5

OUT

VCC or GND

VIN OE

VIH or VIL

IIN Input Leakage 0



5.5

0.1

1.0

5.5V or GND

(T/R, OE) Current

ICC Quiescent Supply Current 5.5 4.0 40.0

VCC or GND

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74VHC245

Noise Characteri stics

Note 3: Parameter guaranteed by design.

AC Electrical Characteristics

Note 4: Parameter guaranteed by design. tOSLH

|tPLH max



tPLH min|; tOSHL

|tPHL max



tPHL min|

Note 5: CPD is defined as the value of t he internal equivalent ca pac ita nc e w hich is c alculate d f rom the o perating c urrent consum pt ion without load. Average

operati ng c urrent ca n be obtained by the eq uat ion: ICC (opr.)

CPD * VCC * fIN



ICC/8 (per Bit).

Symbol Parameter VCC TA

CUnits Conditions

(V) Typ Limits

VOLP Quiet Output Maximum 5.0 0.9 1.2 V CL

50 pF

(Note 3) Dynamic VOL

VOLV Quiet Output Minimum 5.0



0.9



1.2 V CL

50 pF

(Note 3) Dynamic VOL

VIHD Minimum HIGH Level 5.0 3.5 V CL

50 pF

(Note 3) Dynamic Input Voltage

VILD Maximum LOW Level 5.0 1.5 V CL

50 pF

(Note 3) Dynamic Input Voltage

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Min Typ Max Min Max

tPLH Propagation Delay 3.3

0.3 5.8 8.4 1.0 10.0 ns CL

15 pF

tPHL Time 8.3 11.9 1.0 13.5 CL

50 pF

5.0

0.5 4.0 5.5 1.0 6.5 ns CL

15 pF

5.5 7.5 1.0 8.5 CL

50 pF

tPZL 3-STATE Output 3.3

0.3 8.5 13.2 1.0 15.5 ns RL

1 k

15 pF

tPZH Enable Time 11.0 16.7 1.0 19.0 CL

50 pF

5.0

0.5 5.8 8.5 1.0 10.0 ns CL

15 pF

7.3 10.6 1.0 12.0 CL

50 pF

tPLZ 3-STAT E Output 3.3

0.3 11.5 15.8 1.0 18.0 ns RL

1 k

50 pF

tPHZ Disable Time 5.0

0.5 7.0 9.7 1.0 11.0 CL

50 pF

tOSLH Output to Output 3.3

0.3 1.5 1.5 ns (Note 4) CL

50 pF

tOSHL Skew 5.0

0.5 1.0 1.0 CL

50 pF

CIN Input Capacit ance 4 10 10 pF VCC

Open

(T/R, OE)

CI/O Output Capacitance 8 pF VCC

5.0V

CPD Power Dissipation 21 pF (Note 5)

Capacitance

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74VHC245

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

5 www.fairchildsemi.com

74VHC245

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74VHC245

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

7 www.fairchildsemi.com

74VHC245 Octal Bidirectional Transceiver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.