CS19-12HO1S - Zilog - Pdf.Support

CS19-12ho1S

Single Thyristor

High Efficiency Thyristor

4/2 1

3

Part number

CS19-12ho1S

Backside: anode

TAV

T

VV1.31

RRM

20

1200

=

V= V

I= A

Features / Ad vantages: Applications: Package:

● Thyristor for line frequency

● Planar passivated chip

● Long-term stability

● Line rectifying 50/60 Hz

● Softstart AC motor control

● DC Motor control

● Power converter

● AC power control

● Lighting and temperature control

TO-263 (D2Pak)

● Industry standard outline

● RoHS compliant

● Epoxy meets UL 94V-0

IXYS reserves the right to change limits, conditions and dimensions. 20130321bData according to IEC 60747and per semiconductor unless otherwise specified

CS19-12ho1S

V = V

A²s

Symbol Definition

Ratings

typ. max.

I

V

IA

V

T

1.32

R0.7 K/W

min.

20

VV

50T = 25°C

VJ

T = °C

VJ

mA1V = V

T = 25°C

VJ

I = A

T

V

T = °C

C

110

P

tot

170 WT = 25°C

C

20

1200

forward voltage drop

total power dissipation

Conditions Unit

1.65

T = 25°C

VJ

125

V

T0

V0.86T = °C

VJ

125

r

T

22 mΩ

V1.31T = °C

VJ

I = A

T

V

20

1.73

I = A40

threshold voltage

slope resistance for power loss calculation only

µA

125

VV1200T = 25°C

VJ

IA31

P

GM

Wt = 30 µs 5

max. gate power dissipation

P

T = °C

C

125

Wt = 2.5

P

GAV

W0.5

average gate power dissipation

C

J

9

j

unction capacitance V = V230 T = 25°Cf = 1 MHz

RVJ

pF

I

TSM

t = 10 ms; (50 Hz), sine T = 45°C

VJ

max. forward surge current

T = °C

VJ

125

I²t T = 45°C

value for fusing

T = °C125

V = 0 V

R

V = 0 V

R

V = 0 V

t = 8,3 ms; (60 Hz), sine

t = 10 ms; (50 Hz), sine

t = 8,3 ms; (60 Hz), sine

t = 10 ms; (50 Hz), sine

t = 8,3 ms; (60 Hz), sine

t = 10 ms; (50 Hz), sine

t = 8,3 ms; (60 Hz), sine

VJ

R

VJ

R

thJC

thermal resistance junction to case

T = °C

VJ

125

180

195

120

115

A

155

165

160

1200

300 µs

RMS forward current

T(RMS)

TAV

180° sine

average forward current

(di/dt)

cr

A/µs

150repetitive, I =T

VJ

= 150°C; f = 50 Hz

critical rate of rise of current

V

GT

gate trigger voltage V= 6 V T = °C25

(dv/dt) T=150°C

critical rate of rise of voltage

A/µs500

V/µs

t = µs;

IA;V = ⅔ V

R = ∞; method 1 (linear voltage rise)

VJ

DVJ

60 A

T

P

G

=0.15

di /dt A/µs;

G

=0.15

DDRM

cr

V = ⅔ V

D DRM

GK

500

1.5 V

T= °C-40

VJ

I

GT

gate trigger current V= 6 V T = °C25

DVJ

28 mA

T= °C-40

VJ

2.5 V

50 mA

V

GD

gate non-trigger voltage T= °C

VJ

0.2 V

I

GD

gate non-trigger current 3mA

V = ⅔ V

D DRM

150

latching current T= °C

VJ

75 mAI

L

25tµs

p

=10

IA;

G

= 0.1 di /dt A/µs

G

=0.1

holding current T= °C

VJ

50 mAI

H

25V= 6 V

D

R = ∞

GK

gate controlled delay tim e T= °C

VJ

2µst

gd

25

IA;

G

= 0.1 di /dt A/µs

G

=0.1

V = ½ V

D DRM

turn-off time T= °C

VJ

150 µst

q

di/dt = A/µs;10 dv/dt = V/µs;20

V =

R

100 V; I A;

T

=20 V = ⅔ V

D DRM

tµs

p

= 200

non-repet., I = 20 A

T

125

R

thCH

0.50

thermal resistance case to heatsink K/W

Thyristor

1300

RRM/DRM

RSM/DSM

max. non-repetitive reverse/forward blocking voltage

max. re pe titive reverse/forward bl ocking volt a ge

R/D

reverse current, drain current

T

R/D

200

IXYS reserves the right to change limits, conditions and dimensions. 20130321bData according to IEC 60747and per semiconductor unless otherwise specified

CS19-12ho1S

Ratings

Product M

a

r

k

i

n

g

Date Code

Part No.

Logo

Assembly Code

XXXXXXXXX

IXYS

yywwz

000000

Assembly Line

CS19-08ho1 TO-220AB (3) 800

Package

T

VJ

°C

T

stg

°C150

storage temperature -55

Weight g2

Symbol Definition typ. max.min.Conditions

virt ua l j un ctio n temp eratu re

Unit

F

C

N60

mount ing for ce w i th cli p 20

I

RMS

RMS current 35 A

per terminal

125-40

CS19-08ho1S TO-263AB (D2Pak) (2) 800

TO-263

(

D2Pak

)

Similar Part Package Voltage class

CS19-12ho1 TO-220AB (3) 1200

Delivery Mode Quantity Code No.Part Number Marking on ProductOrdering

CS19-12ho1S 501313Tape & Reel 800CS19-12ho1SStandard

threshold voltage V0.86

mΩ

V

0 max

R

0 max

slope resistance * 19

Equivalent Circuits for Simulation

T =

VJ

IV

0

R

0

Thyristor

125°C

* on die level

IXYS reserves the right to change limits, conditions and dimensions. 20130321bData according to IEC 60747and per semiconductor unless otherwise specified

CS19-12ho1S

W

c2

A

A1

c

L

E

2x e

L1

D

321

3.81

(0.150)

1.78

(0.07)

2.54 (0.100)

3.05

(0.120)

10.92

(0.430)

9.02

(0.355)

mm (Inches)

Recommended min. foot print

3x b2

E1

2x b

H

D1

Supplier

Option

L2

4

minmaxminmax

A 4.06 4.83 0.160 0.190

A1

A2

b 0.51 0.99 0.020 0.039

b2 1.14 1.40 0.045 0.055

c 0.40 0.74 0.016 0.029

c2 1.14 1.40 0.045 0.055

D 8.38 9.40 0.330 0.370

D1 8.00 8.89 0.315 0.350

D2

E 9.65 10.41 0.380 0.410

E1 6.22 8.50 0.245 0.335

e

e1

H 14.61 15.88 0.575 0.625

L 1.78 2.79 0.070 0.110

L1 1.02 1.68 0.040 0.066

Wtyp.

0.02 0.040 typ.

0.0008 0.002

Dim. Millimeter Inches

typ. 0.10 typ. 0.004

2.41 0.095

0.098

4.28 0.169

All dimensions conform with

and/or within JEDEC standard.

2,54 BSC 0,100 BSC

2.5

4/2 1

3

Outlines TO-263 (D2Pak)

IXYS reserves the right to change limits, conditions and dimensions. 20130321bData according to IEC 60747and per semiconductor unless otherwise specified

CS19-12ho1S

0.01 0.1 1

60

80

100

120

140

160

0.5 1.0 1.5 2.0 2.5

0

20

40

60

10

0

10

1

10

2

10

3

10

4

0.0

0.2

0.4

0.6

0.8

ITSM

[A]

IT

[A]

VT [V]

t[ms]

ZthJC

[K/W]

23456789011

10

100

1000

I2t

[A2s]

t[ms]

IT(AV)M

[A]

TC[°C]

0 25 50 75 100 125 150 175

0

10

20

30

40

Fig. 1 Forward characteristics Fig. 3 I2t versus time (1-10 ms)

t[s]

Fig. 6 Max. forward current

at case temperature

Fig. 2 Surge overload current

Fig. 8 Transient thermal impedance

T

VJ

=25°C

T

VJ

=125°C

T

VJ

= 45°C

50 Hz, 80% V

RRM

T

VJ

=125°C

T

VJ

= 45°C

V

R

= 0 V

125°C

150°C

01020

0

10

20

30

40

IF(AV) [A]

P(AV)

[W]

Fig. 7a Power dissipation versus direct output current

Fi

g

. 7b and ambient tem

p

erature

050100150

Tamb [°C]

dc =

1

0.5

0.4

0.33

0.17

0.08

10 100 1000

1

10

100

1000

1 10 100 1000

0.1

1

10

100

IG[mA]

VG

[V]

tgd

[μs]

IG[mA]

typ. Limit

T

VJ

=125°C

Fig. 4 Gate trigger characteristics Fig. 5 Gate controlled delay time

1: I

GD

,T

VJ

=150°C

2: I

GT

,T

VJ

=25°C

3: I

GT

,T

VJ

=-40°C

dc =

1

0.5

0.4

0.33

0.17

0.08

2

1

3

6

4

5

R

thHA

0.6

0.8

1.0

2.0

4.0

8.0

R

thi

[K/W] t

i

[s]

0.1 0.01

0.08 0.0011

0.18 0.025

0.17 0.32

0.17 0.09

I

GD

,T

VJ

=125°C

4: P

GAV

=0.5W

5: P

GM

=2.5W

6: P

GM

=5W

Thyristor

IXYS reserves the right to change limits, conditions and dimensions. 20130321bData according to IEC 60747and per semiconductor unless otherwise specified