General Description
The GD16571 is a high performance low
power 2.5 Gbit/s Laser Driver with
optional on chip retiming of data.
The GD16571 is designed to meet and
exceed ITU-T STM-16 or SONET OC-48
fiberoptic communication systems re-
quirements.
The GD16571 is designed to sink a
Modulation Current into the IOUT pin and
a Pre-Bias Current into the IPRE pin. The
Modulation Current is adjustable up to
70 mA by means of the pin VMOD. The
Pre-Bias Current may be adjusted up to
50 mA by means of the VPRE pin.
Retiming of the data signal connected to
the pins DIN, DINQ is made by means of
a DFF clocked by an external clock sig-
nal at the data rate fed to the pins CKIN
and CKINQ.
A Mark-Space monitor is available on the
pins MARKP and MARKN. Together with
the symmetry adjustment pin (SYM) this
may be used to control the mark space
ratio of the output signal.
The GD16571 is implemented in a Sili-
con Bipolar process and requires a single
+5 V supply or a single -5.2 V supply.
The circuit is available in a thermally
enhanced 32-pin TQFP plastic package.
an Intel company
Data Sheet Rev.: 10
Preliminary
Features
lComplies with ITU-T STM-16 and
SONET OC-48 standards.
lIntended for driving a 25 Wload,
e.g. a laser diode with 25 Winput
impedance.
lClocked or non-clocked operation.
lLarge modulation current adjustment
range from 5 mA to 70 mA.
lOutput voltage over / under shoot
less than ±2 % respectively ±5%.
lRise / fall times less than 100 ps.
lLaser diode pre-bias adjustable up to
50 mA.
lMark-Space monitor.
lSymmetry adjustment.
lInternal 50 Wtermination of data and
clock inputs.
lOperates up to 3.5 Gbit/s.
lPower dissipation: 0.38 W.
Excluding Modulation Current and
Pre-bias Current.
lSilicon Bipolar process.
l32 pin thermally enhanced TQFP
plastic package.
Applications
lTele Communication:
–SDH STM-16
–SONET OC-48
lDatacom up to 3.125 Gbit/s.
lElectro Absorption laser driver.
lDirect Modulation laser driver.
2.5 Gbit/s
Retiming
Laser Driver
GD16571
D
Q
Input
Buffer
Input
Buffer
DIN
CKSEL
CKIN
DINQ
CKINQ
DINT
CKINT
MARKP
VEEB
VEER
VEEP
VEE
IOUTN
IOUT
VDDCONT
VDDR
VDD
IPRE
VPREVMOD VADJBUFVADJEF
50
50
50
50
MARKN
SYM
Modulation
Current
Control
Pre-Bias
Current
Control
Output
Driver
Mark/Space
Monitor
MUX
Functional Details
GD16571 is a 2.5 Gbit/s laser driver with
an optional retiming of the data signal. It
is capable of driving high power laser di-
odes, typically having input impedance of
25 W, at a maximum modulation current
of 70 mA and a maximum pre-bias cur-
rent of 50 mA.
Data (DIN, DINQ) is input to GD16571
and retimed within a DFF clocked by an
external clock (CKIN, CKINQ). Optionally
the retiming may be bypassed controlled
by a select pin (CKSEL).
Both the differential data (DIN, DINQ)
and clock inputs (CKIN, CKINQ) are in-
ternally terminated to 50 W. Termination
is made with a 50 Wresistor from the two
differential inputs to a common pin called
DINT and CKINT respectively. The input
sensitivity when driven with a single
ended signal is better than 150 mV on
both clock and data inputs.
The output pin (IOUT) is an open collec-
tor output designed for driving external
loads with 25 Wcharacteristic imped-
ance. Because of the nature of an open
collector the output therefore may be re-
garded as a current switch, with infinite
output impedance. The characteristic im-
pedance through the package is approxi-
mately 25 W. Optimum performance of
GD16571 therefore is achieved if the out-
put is terminated into a 25 Wimpedance.
Figure 1. Application Diagram
The output modulation current is con-
trolled by the pin VMOD and can be con-
trolled in the range from 0 mA to 70 mA,
however the specifications is only valid in
the range from 5 mA to 70 mA. The out-
put voltage swing across the external
load may be varied accordingly. The
modulation current control on pin VMOD
is implemented as a current mirror and
therefore sinks a current proportional to
the modulation current. The current sink
into the VMOD pin is approximately 3/80
of the modulation current. Two additional
pins (VADJBUF and VADJEF) are avail-
able in order to optimise the performance
of the output signal quality, specifically
with respect to overshoot and under-
shoot. Typically best performance is ob-
tained if these pins are connected to
VMOD.
The pre-bias current is controlled by the
pin VPRE and can be controlled from
0 mA to 50 mA. The pre-bias current
control on pin VPRE is implemented as a
current mirror and therefore sinks a cur-
rent proportional to the pre-bias current.
The current sink into the VPRE pin is ap-
proximately 3/500 of the pre-bias current.
An important parameter for laser drivers
is voltage overshoot on the output pin
(IOUT), because it determines the extinc-
tion ratio. GD16571 has been designed
with special emphasis on achieving a
very small voltage overshoot. For
GD16571 the voltage overshoot is less
than 2 % across the full modulation cur-
rent range, when driving a 25 Wload.
Similarly the voltage undershoot is less
than 5 %.
A mark-space monitor is provided
through the pins MARKP and MARKN.
These may be connected as shown in
the application diagram below, with a ca-
pacitor across the two outputs and a
comparator (or Op-amp) to determine the
mark density. Symmetry input (SYM) is
available which may be used to control
the mark-space ratio.
AC Coupled Output
When DC coupled the output swing will
be limited by IOUT output voltage speci-
fied to -2 V. For maximum output voltage
swing the output should be AC coupled.
Figure 2. AC Coupled Output
Data Sheet Rev.: 10 GD16571 Page 2 of 7
Input
Buffer
Input
Buffer
DIN/27
CKIN / 31
DINQ / 26
CKINQ / 32
DINT / 28
CKINT / 30
Differential or
Single-ended
Clock Signal
Differential or
Single-ended
Data Signal
Control Voltage from
Modulation Current
Control System
Control Voltage from
Pre-Bias Current
Control System Laser Diode Equivalent
25 Input ImpedanceW
MARKP / 7
VEEP / 18
IOUTN / 11, 12
IOUT / 13, 14
IPRE / 19
VPRE / 16VMOD / 20
50
25
25
VDD
VDD
VDD
VDD
25
50
50
50
50
50
50
50
100n
100n
C
C
L
L
Negative
Supply
Ref.
+
-
100n
MARKN / 6
Modulation
Current
Control
Pre-Bias
Current
Control
Output
Driver
Mark/Space
Monitor
L1
220uH
L3
220uH
L2
IOUT
IOUTN
L4
100nF
100nF
25W
VDDVDD
VDD
L1 and L3 = Siemens Chip
Inductors (B82432A1224K).
L2 and L4 = Siemens ferrite
cores B64290-A36-X33 with
8 turns of 0.22mm Cu-Wire.
Pin List
Mnemonic: Pin No.: Pin Type: Description:
DIN
DINQ
27
26
AC IN Data inputs. Internally terminated in 50 Wto DINT.
Internally biased to -1.3 V
DINT 28 ANL IN Termination voltage for DIN and DINQ.
CKIN
CKINQ
31
32
AC IN Clock inputs. Internally terminated in 50 Wto CKINT.
Internally biased to -1.3 V.
CKINT 30 ANL IN Termination voltage for CKIN and CKINQ.
IOUT
IOUTN
13, 14
11, 12
OPEN
COLLECTOR
Laser Driver Output (2.5 Gbit/s). IOUT and IOUTN sink a modula-
tion current, which is controlled by the pin VMOD. The current into
IOUT is high when data is high on DIN.
IPRE 19 OPEN
COLLECTOR
Pre-bias current output. IPRE sinks a current, which is controlled
by the pin VPRE.
VMOD 20 ANL IN Modulation current control input. The control system is made as a
current mirror. VMOD sinks a current proportional to the modula-
tion current. This current is approximately 3/80 times “The modu-
lation current”.
VPRE 16 ANL IN Pre-bias current control input. The control system is made as a
current mirror. VPRE sinks a current proportional to the pre-bias
current. This current is approximately 3/500 times “The pre-bias
current”.
CKSEL 1 ECL IN When CKSEL is low data is retimed. Otherwise data is bypassed
the retiming.
SYM 24 ANL IN SYM controls the mark-space ratio of the output. Decreasing the
voltage of the SYM pin decreases the pulse width of a current
high into the IOUT pin.
MARKP
MARKN
7
6
ANL OUT Mark-space monitor outputs. High impedance CML outputs. The
output voltage of the MARKP pin is the same as the voltage on
the DIN input.
VADJBUF
VADJEF
22
21
ANL IN Pins used to optimise the performance of the output in terms of
overshoot and undershoot. Typically optimum performance will be
achieved when shorted to VMOD.
VDD 2, 4, 10, 15 PWR Ground pins for laser driver part.
VDDCONT 3 PWR Ground pin for modulation current control system.
VDDR 29 PWR Ground pin for retiming part.
VEE 5, 8, 23 PWR Negative supply pins for laser driver part.
VEEP 18 PWR Negative supply pin for output driver.
VEEB 17 PWR Negative supply pin for pre-bias circuitry.
VEER 25 PWR Negative supply pin for retiming part.
NC 9 Not Connected.
Heat sink Package back Connected to VEE.
Data Sheet Rev.: 10 GD16571 Page 3 of 7
Package Pinout
Figure 3. Package 32 TQFP, Top View
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages in table are referred to VDD.
All currents in table are defined positive out of the pin.
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
VEE Power Supply -6 0 V
VOApplied Voltage (All Outputs) VEE -0.5 2 V
VIApplied Voltage (All Inputs) VEE -0.5 0.5 V
IIAC IN Input Current (AC IN) -1 1 mA
IIVMOD Input Current (VMOD) -4 1 mA
IIVPRE Input Current (VPRE, VADJBUF and VADJEF) Note 1 -1 1 mA
TOOperating Temperature Base -55 +125 °C
TSStorage Temperature -65 +165 °C
Note 1: Voltage and/or current should be externally limited to specified range.
Data Sheet Rev.: 10 GD16571 Page 4 of 7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CKINQ
CKIN
CKINT
VDDR
DINT
DIN
DINQ
VEER
SYM
VEE
VADJBUF
VADJEF
VMOD
IPRE
VEEP
VEEB
VPRE
VDD
IOUT
IOUT
IOUTN
IOUTN
VDD
NC
VEE
MARKP
MARKN
VEE
VDD
VDDCONT
VDD
CKSEL
DC Characteristics
TCASE = -40 °Cto85°C, appropriate heat sinking may be required.
All voltages in table are referred to VDD.
All currents in table are defined positive out of the pin.
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
VEE Power Supply -5.5 -5.2 -4.7 V
IEE Negative Supply Current IOUT = 0 A 75 mA
PDISS Power Dissipation VEE =-5.0 V,
IOUT =0A,
IPRE =0A
0.38 0.5 W
Vpp AN IN Peak-peak Voltage when Input is Driven Single
ended.
VVTH=-1.3 V 150 800 mV
VVMOD Voltage Range for VMOD VEE VDD V
IVMOD Sink Current into Pin VMOD -40mA
VIN NN Input Voltage Range for VPRE, VADJBUF,
VADJEF and SYM
VEE VDD V
ISINK NN Sink Current into pin VPRE, VADJBUF,
VADJEF and SYM
-10mA
VIN SYM Input Voltage Range for SYM VEE VDD V
ILEAK SYM Leakage Current for CKSEL -11mA
VIN CKSEL Input Voltage Range for CKSEL VEE VDD V
ILEAK CKSEL Leakage Current for SYM -11mA
VLO MARK Low Output Voltage for Mark-Space Monitor -2.0 V
ROMARK Output Impedance for Mark-Space Monitor 4.0 kW
VOIPRE IPRE Output Voltage -2.0 V
IIPRE IPRE Current -50 0 mA
VOIOUT IOUT Output Voltage Note 1 -2.0 V
IMod,HI IOUT IOUT High Modulation Current Note 1,2 -70 0 mA
IMod,LO IOUT IOUT Low Modulation Current Note 1,3 -3 1 mA
Note 1: RLOAD =25Wto VDD connected to pin IOUT. Sink current is controlled by the VMOD pin, and may be adjusted in the
range as specified. Notice that high modulation current means that the output voltage level is low.
Note 2: The AC parameters are only specified in the range from -70 mA to -5 mA. However at TCASE =0°Cto70°C AC parame-
ters are specified from -80 mA to -5 mA.
Note 3: This is a leakage current. Max leakage current is present at max modulation current (i.e. at 70 mA modulation current).
The leakage current decreases for smaller leakage currents.
Data Sheet Rev.: 10 GD16571 Page 5 of 7
AC Characteristics
TCASE = -40 °Cto85°C, appropriate heat sinking may be required.
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
fMAX OUT Data Output Frequency 2500 Mbit/s
Jpp OUT Added Output Jitter Note 1 20 ps
tRISE OUT Output Rise Time Note 1 100 ps
tFALL OUT Output Fall Time Note 1 100 ps
tPM Phase Margin Clock to Data 300 ps
tSData Set-up Time 60 30 ps
tHData Hold Time 20 5 ps
DCROSS_OVER Output Cross Over Control Range Note 1 ±30 %
Note 1: RLOAD =25Wto VDD connected to pin IOUT. ILD = 70 mA. Rise/Fall times at 20 –80 % of HI/LO voltage levels.
Package Outline
Figure 4. Package 32 pin. All dimensions are in mm.
Data Sheet Rev.: 10 GD16571 Page 6 of 7
Device Marking
Figure 5. Device Marking, Top View.
Ordering Information
To order, please specify as shown below:
Product Name: Intel Order Number:Package Type: Temperature Range:
GD16571-32BA FAGD1657132BA
MM#: 836125
32L TQFP EDQUAD -40..85 °C
GD16571, Data Sheet Rev.: 10 - Date: 24 July 2001
The information herein is assumed to be
reliable. GIGA assumes no responsibility
for the use of this information, and all such
information shall be at the users own risk.
Prices and specifications are subject to
change without notice. No patent rights or
licenses to any of the circuits described
herein are implied or granted to any third
party. GIGA does not authorise or warrant
any GIGA Product for use in life support
devices and/or systems.
Mileparken 22, DK-2740 Skovlunde
Denmark
Phone : +45 7010 1062
Fax : +45 7010 1063
E-mail : sales@giga.dk
Web site : http://www.intel.com/ixa
Please check our Internet web site
for latest version of this data sheet.
Distributor:
Copyright © 2001 GIGA ApS
An Intel company
All rights reserved
an Intel company
GD16571
<1> - <2> - <3>
<4> - YYWW
<1> = Wafer ID
<2> = Design ID
<3> = Wafer Lot#
<4> = Assembly Lot#
Pin 1 - Mark
