CH7101B
Brief Datasheet
209-1000-130 Rev 1.1 2017-7-18 1
Chrontel
CH7101B HDMI to VGA Converter
FEATURES
GENERAL DESCRIPTION
HDMI Receiver compliant with HDMI 1.4 specification
Analog RGB output for VGA with Triple 9-bit DAC up
to 200MHz pixel rate. Sync signals can be provided in
separated or composite manner. Support VESA and
CEA timing standards up to WUXGA 1920x1200@60
Hz with reduced blanking and 1920x1080@60Hz
On-chip Audio encoder which support 2 channel IIS/
S/PDIF audio output
VGA output is compliant with VESA VSIS v1r2
specification
MCCS bypass support
MCU embedded to handle the control logic
Support device boot up by automatically loading
firmware from on-chip flash
Integrated EDID Buffer
Crystal Free architecture
VGA connection detection supported
HDMI input detection supported
Support Auto Power Saving mode and low stand-by
current
Support YCC to RGB conversion in ITU-R BT.601 and
709 color space
IIC slave interface and HDMI DDC interface are
available for debug and firmware update.
Low power architecture
RoHS compliant and Halogen free package
Offered in 40-Pin QFN package (5 x 5 mm)
APPLICATION
Notbook/Ultrabook
Tablet Device
Handheld/Portable Device
Digital Video Systems
HDMI to VGA Adapter/Docking Station
Car Infotainment Device
Chrontel’s CH7101B is a low-cost, low-power
semiconductor device that consists of HDMI receiver,
three separate 9-bit video Digital-to-Analog Converters
(DACs) and audio encoder, which can convert HDMI
signals into VGA outputs at a maximum conversion rate
of 200 MHz with IIS or SPDIF audio output.
The HDMI Receiver integrated is compliant with HDMI
1.4b. The DACs are based on current source architecture.
And the VGA output meet VESA VSIS v1r2 clock jitter
target. With sophisticated MCU and the on-chip flash,
CH7101B supports auto-boot and EDID buffer.
Leveraging the firmware auto loaded from the embedded
flash, CH7101B can support HDMI input detection, DAC
connection detection and determine to enter into Power
saving mode automatically.
CHRONTEL CH7101B
2 209-1000-130 Rev 1.1 2017-7-18
IIS /
SPDIF
H/V
Sync
Analog
RGB
DDC_HDMI DDC_VGA
HPD
TMDS
HPD
Generator
HDMI
1.4 RX
Sync Generator
CSC
Video FIFO
Audio FIFO
DAC
Audio Encoder
MCU & EDID Buffer On Chip Flash
SPC/SPD
GPIOs
Equalizer
Figure 1: CH7101B Functional Block Diagram
CHRONTEL CH7101B
209-1000-130 Rev 1.1 2017-7-18 3
1.0 PIN-OUT
1.1 Package Diagram
1
CHRONTEL
CH7101B
QFN40
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
31
32
33
34
35
36
37
38
39
40
VDDPLL
DDC_SCL
DDC_SDA
MCLK
RB
DVDD
DGND
SD/SPDIF
WS
SCLK
SPD0
GPIO0
GPIO1
VO
VGA_SCL
HO/CSYNC
DVDD
DGND
SPC0
AVCC
VGA_SDA
BDAC
AVCC_DAC
NC
RBIAS
RDAC
GDAC
AVCC_DAC
NC
HPD
RD2P
RD2N
RD1N
AVDD
AVCC
RD0P
RCP
RCN
RD0N
RD1P
Figure 2: CH7101B 40-pin QFN pin out
CHRONTEL CH7101B
4 209-1000-130 Rev 1.1 2017-7-18
1.2 Pin Description
Table 1: Pin Name Descriptions
Pin #
Type
Symbol
Description
4
In
DDC_SCL
Serial Port Clock to HDMI/DVI Transmitter
This pin functions as the clock bus of the serial port to HDMI or DVI
DDC transmitter. This pin requires a pull-up 47 kΩ resistor to the
desired voltage level.
5
In/out
DDC_SDA
Serial Port Data to HDMI/DVI Transmitter
This pin functions as the data bus of the serial port to HDMI or DVI
DDC transmitter. This pin requires a pull-up 47 kΩ resistor to the
desired voltage level.
6
Out
SD/SPDIF
I2S Serial Data or SPDIF Output
7
Out
WS
I2S Word Select
8
Out
SCLK
I2S Continuous Serial Clock
9
Out
MCLK
I2S System Clock
10
In
RB
Chip Reset
Low to 0V for reset. Typical High level is 3.3V
12
In
SPC0
Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull-up
6.8 K resister is required
13
In/out
SPD0
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port.
External pull-up 6.8 K resister is required
14,15
In/Out
GPIO
General Purpose Input/Output
16
Out
VO
Vertical Sync Signal Output
The amplitude of this pin is from 0 to AVCC
17
Out
HO/CSYNC
Horizontal Sync Signal Output
The amplitude of this pin is from 0 to AVCC
It also functions as a Composite sync output
20
Out
VGA_SCL
Serial Port Clock Output to VGA Receiver
The pin should be connected to clock signal of VGA DDC. This pin
requires a pull-up 10 kΩ resistor to the desired voltage level
21
In/Out
VGA_SDA
Serial Port Data to VGA Receiver
The pin should be connected to data signal of VGA DDC. This pin
requires a pull-up 10 kΩ resistor to the desired voltage level
22
In
XI
Crystal Input
A parallel resonance crystal should be attached between this pin and
XO.
23
Out
XO
Crystal Output
A parallel resonance crystal should be attached between this pin and
XI. If an external CMOS clock is injected to XI, XO should be left
open.
25
Out
BDAC
VGA Blue Component DAC output
26
Out
GDAC
VGA Green Component DAC output
28
Out
RDAC
VGA Red Component DAC output
29
In
RBIAS
Current Set Resistor Input
This pin sets the DAC current. A10 K, 1% tolerance resistor should
be connected between this pin and AVSS using short and wide traces
30
Out
HPD
HDMI Receiver Hot Plug output
31,32,33,
34,36,37,
In
RD[2:0]P/N
RCP/N
HDMI TMDS Input
HDMI differential clock and data input pairs
CHRONTEL CH7101B
209-1000-130 Rev 1.1 2017-7-18 5
39,40
1
Power
VDDPLL
PLL Power Supply (1.2V)
2,18
Power
DVDD
Digital IO Power Supply (1.2V)
3,19
Power
DGND
Digital Ground
11, 38
Power
AVCC
Analog Power Supply (3.3V)
24,27
Power
AVCC_DAC
Analog DAC Power Supply (3.3V)
35
Power
AVDD
HDMI Receiver Analog Power Supply (1.2V)
Pad
Power
GND
Power Supply Ground
CHRONTEL CH7101B
6 209-1000-130 Rev 1.1 2017-7-18
2.0 PACKAGE DIMENSION
Figure 3: 40 Pin VQFN Package
Table 2: Table of Dimensions
No. of Leads
SYMBOL
40 (5 X 5 mm)
A
B
C
D
E
F
G
H
I
Milli-
meters
MIN
4.90
3.20
3.20
0.4
0.15
0.35
0.70
0
0.203
REF
MAX
5.10
3.40
3.40
0.25
0.45
0.80
0.05
Notes:
1. Conforms to JEDEC standard JESD-30 MO-220.
CHRONTEL CH7101B
209-1000-130 Rev 1.1 2017-7-18 7
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. CHRONTEL warrants each part to be
free from defects in material and workmanship for a period of one (1) year from date of shipment. Chrontel assumes
no liability for errors contained within this document. The customer should make sure that they have the most recent
data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe
upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist
others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number
Package Type
Operating Temperature Range
Minimum Order Quantity
CH7101B-BF
40 QFN, Lead-free
Commercial : -20 to 70C
490/Tray
CH7101B-BFI
40 QFN, Lead-free
Industrial : -40 to 85C
490/Tray
Chrontel
Chrontel International Limited
129 Front Street, 5th floor,
Hamilton, Bermuda HM12
www.chrontel.com
E-mail: sales@chrontel.com
2017 Chrontel - All Rights Reserved.
