Quad High-Speed Precision
Difet
® OPERATIONAL AMPLIFIER
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
Difet
®, Burr-Brown Corp.
BIFET®, National Semiconductor Corp.
FEATURES
● WIDE BANDWIDTH: 6.4MHz
● HIGH SLEW RATE: 35V/µs
● LOW OFFSET: ±750µV max
● LOW BIAS CURRENT: ±4pA max
● LOW SETTLING: 1.5µs to 0.01%
● STANDARD QUAD PINOUT
DESCRIPTION
The OPA404 is a high performance monolithic
Difet
®(dielectrically-isolated FET) quad operational
amplifier. It offers an unusual combination of very-
low bias current together with wide bandwidth and
fast slew rate.
Noise, bias current, voltage offset, drift, and speed are
superior to BIFET® amplifiers.
Laser-trimming of thin-film resistors gives very low
offset and drift—the best available in a quad FET op
amp.
The OPA404's input cascode design allows high pre-
cision input specifications and uncompromised high-
speed performance.
Standard quad op amp pin configuration allows up-
grading of existing designs to higher performance
levels. The OPA404 is unity-gain stable.
OPA404
APPLICATIONS
● PRECISION INSTRUMENTATION
● OPTOELECTRONICS
● SONAR, ULTRASOUND
● PROFESSIONAL AUDIO EQUIPMENT
● MEDICAL EQUIPMENT
● DETECTOR ARRAYS
Cascode
+In
–In
Output
OPA404 Simplified Circuit
(Each Amplifier)
+V
CC
–V
CC
© 1986 Burr-Brown Corporation PDS-677F Printed in U.S.A. August 1995
SBOS149
2
®
OPA404
SPECIFICATIONS
ELECTRICAL
At VCC = ±15VDC and TA = +25°C unless otherwise noted.
OPA404AG, KP, KU (1) OPA404BG OPA404SG
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
INPUT
NOISE
Voltage: fO = 10Hz 32 * * nV/√Hz
fO = 100Hz 19 * * nV/√Hz
fO = 1kHz 15 * * nV/√Hz
fO = 10kHz 12 * * nV/√Hz
fB = 10Hz to 10kHz 1.4 * * µVrms
fB = 0.1Hz to 10Hz 0.95 * * µVp-p
Current: fB = 0.1Hz to 10Hz 12 * * fA, p-p
fO = 0.1Hz thru 20kHz 0.6 * * fA/√Hz
OFFSET VOLTAGE
Input Offset Voltage VCM = 0VDC ±260 ±1mV * ±750 * * µV
KP, KU ±750 ±2.5mV µV
Average Drift TA = TMIN to TMAX ±3**µV/°C
KP, KU ±5µV/°C
Supply Rejection ±VCC = 12V to 18V 80 100 86 * * * dB
KP, KU 76 100 dB
Channel Separation 100Hz, RL = 2kΩ125 * * dB
BIAS CURRENT
Input Bias Current VCM = 0VDC ±1±8*±4**pA
KP, KU ±1±12 pA
OFFSET CURRENT
Input Offset Current VCM = 0VDC 0.5 8 * 4 * * pA
KP, KU 0.5 12 pA
IMPEDANCE
Differential 1013 || 1 * * Ω || pF
Common-Mode 1014 || 3 * * Ω || pF
VOTAGE RANGE
Common-Mode Input Range ±10.5 +13, –11 * * * * V
Common-Mode Rejection VIN = ±10VDC 88 100 92 * * * dB
KP, KU 84 100 dB
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain RL ≥ 2kΩ88 100 92 * * * dB
FREQUENCY RESPONSE
Gain Bandwidth Gain = 100 4 6.4 5 * * * MHz
Full Power Response 20Vp-p, RL = 2kΩ570 * * kHz
Slew Rate VO = ±10V, RL = 2kΩ24 35 28 * * * V/µs
Settling Time: 0.1% Gain = –1, RL = 2kΩ0.6 * * µs
0.01% CL = 100 pF, 10V Step 1. 5 * * µs
RATED OUTPUT
Voltage Output RL = 2kΩ±11.5 +13.2, –13.8 * * * * V
Current Output VO = ±10VDC ±5±10 * * * * mA
Output Resistance 1MHz, Open Loop 80 * * Ω
Load Capacitance Stability Gain = +1 1000 * * pF
Short Circuit Current ±10 ±27 ±40 * * * * * * mA
POWER SUPPLY
Rated Voltage ±15 * * VDC
Voltage Range,
Derated Performance ±5±18 * * * * VDC
Current, Quiescent IO = 0mADC 9 10 * * * * mA
TEMPERATURE RANGE
Specification Ambient Temperature –25 +85 * * –55 +125 °C
KP, KU 0 +70 °C
Operating Ambient Temperature –55 +125 * * * * °C
KP, KU –25 +85 °C
Storage Ambient Temperature –65 +150 * * * * °C
KP, KU –40 +125 °C
θ
Junction-Ambient 100 * * °C/W
KP, KU 120/100 °C/W
*Specifications same as OPA404AG.
NOTE: (1) OPA404KU may be marked OPA404U.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3
®
OPA404
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted.
OPA404AG, KP, KU OPA404BG OPA404SG
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
TEMPERATURE RANGE
Specification Range Ambient Temperature –25 +85 * * –55 +125 °C
KP, KU 0 +70 °C
INPUT
OFFSET VOLTAGE
Input Offset Voltage VCM = 0VDC ±450 2mV * ±1.5mV ±550 ±2.5mV µV
KP KU ±1±3.5 mV
Average Drift ±3* *µV/°C
KP, KU ±5µV/°C
Supply Rejection 75 96 80 * 70 93 dB
BIAS CURRENT
Input Bias Current VCM = 0VDC ±32 ±200 * ±100 ±500 ±5nA pA
OFFSET CURRENT
Input Offset Current VCM = 0VDC 17 100 * 50 260 2.5nA pA
VOLTAGE RANGE
Common-Mode Input Range ±10 ±12.7, –10.6 * * ±10 +12.6, –10.5 V
Common-Mode Rejection VIN = ±10VDC 82 99 86 * 80 88 dB
KP, KU 80 99 dB
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain RL ≥ 2kΩ82 94 86 * 80 88 dB
RATED OUTPUT
Voltage Output RL = 2kΩ±11.5 ±12.9, –13.8 * * ±11 +12.7, –13.8 V
Current Output VO = ±10VDC ±5±9** *±8mA
Short Circuit Current VO = 0VDC ±8±20 ±50****** mA
POWER SUPPLY
Current, Quiescent IO = 0mADC 9.3 10.5 * * 9.4 11 mA
* Specification same as OPA404AG.
ORDERING INFORMATION
TEMPERATURE
MODEL PACKAGE RANGE
OPA404KP 14-Pin Plastic DIP 0°C to +70°C
OPA404KU(1) 16-Pin Plastic SOIC 0°C to +70°C
OPA404AG 14-Pin Ceramic DIP –25°C to +85°C
OPA404BG 14-Pin Ceramic DIP –25°C to +85°C
OPA404SG 14-Pin Ceramic DIP –55°C to +125°C
NOTE: (1) OPA404KU may be marked OPA404U.
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL PACKAGE NUMBER(1)
OPA404KP 14-Pin Plastic DIP 010
OPA404KU(2) 16-Pin Plastic SOIC 211
OPA404AG 14-Pin Ceramic DIP 169
OPA404BG 14-Pin Ceramic DIP 169
OPA404SG 14-Pin Ceramic DIP 169
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book. (2) OPA404KU may be
marked OPA404U.
PIN CONFIGURATION Top View “U” (SOIC) Package
Top View “G” or “P” (DIP) Package
ABSOLUTE MAXIMUM RATINGS
Supply .............................................................................................±18VDC
Internal Power Dissipation(1) ......................................................... 1000mW
Differential Input Voltage(2) .............................................................±36VDC
Input Voltage Range(2) ...................................................................±18VDC
Storage Temperature Range... P, U = –40°C/+125°C, G = –65°C/+150°C
Operating Temperature Range .. P, U = –25°C/+85°C, G = –55°C/+125°C
Lead Temperature (soldering, 10s) .................................................... 300°C
SOIC (soldering, 3s) ..................................................................... +260°C
Output Short-Circuit Duration(3) ................................................. Continuous
Junction Temperature....................................................................... +175°C
NOTES: (1) Packages must be derated based on
θ
JC = 30°C/W or
θ
JA = 120°C/W. (2) For supply voltages less than ±18VDC the absolute maximum input voltage is equal
to: 18V > VIN > –VCC – 8V. See Figure 2. (3) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ.
A
B
D
C
1
2
3
4
5
6
7
Out A
–In A
+ In A
+ V
CC
+In B
– In B
Out B
14
13
12
11
10
9
8
Out D
–In D
+In D
–V
CC
+In C
–In C
Out C
A
B
D
C
1
2
3
4
5
6
7
8
Out A
–In A
+ In A
+ V
CC
+In B
– In B
Out B
NC
16
15
14
13
12
11
10
9
Out D
–In D
+In D
–V
CC
+In C
–In C
Out C
NC
4
®
OPA404
DICE INFORMATION
PAD FUNCTION
8 Output C
9 –Input C
10 +Input C
11 –VCC
12 +Input D
13 –Input D
14 Output D
PAD FUNCTION
1 Output A
2 –Input A
3 +Input A
4+V
CC
5 +Input B
6 –Input B
7 Output B
MECHANICAL INFORMATION
MILS (0.001") MILLIMETERS
Die Size 108 x 108 ±5 2.74 x 2.74 ±0.13
Die Thickness 20 ±3 0.51 ±0.08
Min. Pad Size 4 x 4 0.10 x 0.10
Backing None
Substrate Bias: –VCC
NC: No connection
12
3
4
NC
89
10
11
NC
12
NC
13
14
NC
NC
5
67NC
OPA404 DIE TOPOGRAPHY
TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC = ±15VDC unless otherwise noted.
1 10 100 1k 10k 100k 1M
Frequency (Hz)
0.1
100
10
1
Current Noise (fA/ Hz)
INPUT CURRENT NOISE SPECTRAL DENSITY
100 1k 10k 100k 1M 10M 100M
Source Resistance ( )
1
1k
100
10
Voltage Noise, E
O
(nV/ Hz)
TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY
AT 1kHz vs SOURCE RESISTANCE
Ω
OPA404 + Resistor
E
O
S
R
Resistor noise only
–75 –50 0 +25 +50 +100 +125
Temperature (°C)
90
110
105
95
CMR and PSR (dB)
POWER SUPPLY REJECTION AND COMMON-MODE
REJECTION vs TEMPERATURE
100
–25 +75
PSR
CMR
–50 +25–25 0 +50 +75 +100 +125
Ambient Temperature (°C)
0.1
1
10
100
1nA
10nA
Bias Current (pA)
BIAS AND OFFSET CURRENT
vs TEMPERATURE
0.1
1
10
100
1nA
10nA
Offset Current (pA)
Bias Current
Offset Current
5
®
OPA404
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15VDC unless otherwise noted.
–15 –10 –5 0 +5 +10 +15
Common-Mode Voltage (V)
0.01
10
1
0.1
Bias Current (pA)
BIAS AND OFFSET CURRENT
vs INPUT COMMON-MODE VOLTAGE
0.01
10
1
0.1
Offset Current (pA)
Offset Current
Bias Current
11k10 100 10k 100k 1M 10M
Frequency (Hz)
0
20
40
60
80
100
120
140
Common-Mode Rejection (dB)
COMMON-MODE REJECTION
vs FREQUENCY
11k10 100 10k 100k 1M 10M
Frequency (Hz)
0
20
40
60
80
100
120
140
Voltage Gain (dB)
OPEN-LOOP FREQUENCY RESPONSE
–180
–135
–90
–45
Phase Shift (Degrees)
Ø
A
OL
R
L
= 2kΩ
C
L
= 100pF
11k10 100 10k 100k 1M 10M
Frequency (Hz)
0
20
40
60
80
100
120
140
Power Supply Rejection (dB)
POWER SUPPLY REJECTION
vs FREQUENCY
+
–
–15 –10 0 +5 +10 +15
Common-Mode Voltage (V)
70
120
80
Common-Mode Rejection (dB)
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
90
–5
100
110
–75 –50 0 +25 +50 +100 +125
Ambient Temperature (°C)
2
10
8
4
Gain Bandwidth (MHz)
GAIN BANDWIDTH AND SLEW RATE
vs TEMPERATURE
6
–25 +75
33
40
36
34
Slew Rate (V/µs)
35
GBW
Slew Rate
6
®
OPA404
01020
Supply Voltage (±V
CC
)
5
8
6
GAIN-BANDWIDTH AND SLEW RATE
vs SUPPLY VOLTAGE
7
515
32
38
34
Gain Bandwidth (MHz)
36
GBW
Slew Rate
R
L
= 10kΩ
A
V
= +1
Slew Rate (V/µs)
–75 –50 0 +25 +50 +100 +125
Ambient Temperature (°C)
80
120
110
90
Voltage Gain (dB)
OPEN-LOOP GAIN vs TEMPERATURE
100
–25 +75
SMALL SIGNAL TRANSIENT RESPONSE
Time(µs)
012
Output Voltage (mV)
0
–50
–100
100
–150
50
150
LARGE SIGNAL TRANSIENT RESPONSE
Time(µs)
01234 5
Output Voltage (V)
10
0
–10
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15VDC unless otherwise noted.
10k 100k 10M
Frequency (Hz)
0
30
20
10
MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY
1M
R
L
= 2kΩ
Output Voltage (Vp-p)
–1 –10 –1k
Closed-Loop Gain (V/V)
0
5
1
SETTLING TIME vs CLOSED-LOOP GAIN
–100
Settling Time (µs)
2
3
4
0.01%
C
L
= 100pF
R
L
= 2kΩ
0.1%
7
®
OPA404
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15VDC unless otherwise noted.
10 100 100k
Frequency (Hz)
150
140
130
120
110
0
CHANNEL SEPARATION vs FREQUENCY
10k
Channel Separation (dB)
1k
R
L
= 2kΩ
R
L
= ∞
0.1 1 10 100 1k 10k 100k
Frequency (Hz)
1
0.1
0.01
0.001
THD + N (% rms)
TOTAL HARMONIC DISTORTION vs FREQUENCY
6.5Vrms
40.2kΩ
2kΩ
402Ω
A
V
= +101V/V
A
V
= +101V/V
A
V
= +1V/V
Test
Limit
01020
Supply Voltage (±V
CC
)
92
104
96
OPEN-LOOP GAIN vs SUPPLY VOLTAGE
100
515
Voltage Gain
1 10 100 1k 10k 100k 1M
Frequency (Hz)
1k
100
10
1
Voltage Noise (nV/ Hz)
INPUT VOLTAGE NOISE SPECTRAL DENSITY
–75 –50 0 +25 +50 +100 +125
Ambient Temperature (°C)
11
10
9
8
7
Supply Current (mA)
–25 +75
SUPPLY CURRENT vs TEMPERATURE
8
®
OPA404
APPLICATIONS INFORMATION
OFFSET VOLTAGE ADJUSTMENT
The OPA404 offset voltage is laser-trimmed and will require
no further trim for most applications. If desired, offset volt-
age can be trimmed by summing (see Figure 1). With this
trim method there will be no degradation of input offset drift.
GUARDING AND SHIELDING
As in any situation where high impedances are involved,
careful shielding is required to reduce “hum” pickup in input
leads. If large feedback resistors are used, they should also
be shielded along with the external input circuitry.
Leakage currents across printed circuit boards can easily
exceed the bias current of the OPA404. To avoid leakage,
utmost care must be used in planning the board layout. A
“guard” pattern should completely surround the high imped-
ance input leads and should be connected to a low-impedance
point which is at the signal input potential. (See Figure 3).
FIGURE 2. Input Current vs Input Voltage with ±VCC Pins
Grounded.
–15 –10 –5 0 +5 +10 +15
Input Voltage (V)
–2
+2
+1
–1
Input Current (mA)
INPUT CURRENT vs INPUT VOLTAGE
WITH ±V
CC
PINS GROUNDED
0
Maximum Safe Current
Maximum Safe Current
I
IN
V
FIGURE 3. Connection of Input Guard.
HANDLING AND TESTING
Measuring the unusually low bias current of the OPA404 is
difficult without specialized test equipment; most commer-
cial benchtop testers cannot accurately measure the OPA404
bias current. Low-leakage test sockets and special test
fixtures are recommended if incoming inspection of bias
current is to be performed.
To prevent surface leakage between pins, the DIP package
should not be handled by bare fingers. Oils and salts from
fingerprints or careless handling can create leakage currents
that exceed the specified OPA404 bias currents.
If necessary, DIP packages and PC board assemblies can be
cleaned with Freon TF®, baked for 30 minutes at 85°C,
rinsed with de-ionized water, and baked again for 30 min-
utes at 85°C. Surface contamination can be prevented by the
application of a high-quality conformal coating to the cleaned
PC board assembly.
–15V
+15V
±2mV
Offset
Trim
150kΩ
100kΩ
In Out
20Ω
1/4
OPA404
FIGURE 1. Offset Voltage Trim.
INPUT PROTECTION
Conventional monolithic FET operational amplifiers require
external current-limiting resistors to protect their inputs against
destructive currents that can flow when input FET gate-to-
substrate isolation diodes are forward-biased. Most BIFET
amplifiers can be destroyed by the loss of –VCC.
Unlike BIFET amplifiers, the
Difet
OPA404 requires input
current limiting resistors only if its input voltage is greater
than 8 volts more negative than –VCC. A 10kΩ series resistor
will limit the input current to a safe value with up to ±15V
input levels even if both supply voltages are lost. (See Figure
2 and Absolute Maximum Ratings).
Static damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device.
In precision operational amplifiers (both bipolar and FET
types), this may cause a noticeable degradation of offset
voltage and drift.
Static protection is recommended when handling any preci-
sion IC operational amplifier.
In
Out
Non-Inverting
In
Out
Buffer
In
Out
Inverting
For input guarding,
guard top and bottom of board.
9
®
OPA404
BIAS CURRENT CHANGE
vs COMMON-MODE VOLTAGE
The input bias currents of most popular BIFET operational
amplifiers are affected by common-mode voltage (Figure 4).
Higher input FET gate-to-drain voltage causes leakage and
ionization (bias) currents to increase. Due to its cascode
input stage, the extremely low bias current of the OPA404 is
not compromised by common-mode voltage.
APPLICATIONS CIRCUITS
Figures 5 through 11 are circuit diagrams of various appli-
cations for the OPA404.
In Out
Zero
1MΩ
2
31
6
75
Polypropylene
1µF
Gain = –100
V
OS
< 10µV
Drift ≈ 0.05µV/°C
Zero Droop ≈ 1µV/s
Referred to Input
1/4
OPA404
100kΩ
10kΩ
100kΩ
100Ω
Operate
1/4
OPA404
–10 –5 0 +5 +10
–20
–10
0
10
20
30
40
50
60
70
80
Input Bias Current (pA)
LF155
OP-15/16/17
AD547
LF156/157
AD547
OPA404
LF156/157
T
A
= +25°C; curves taken from
mfg. published typical data
Common-Mode Voltage (VDC)
–15 +15
LF155
OPA404
FIGURE 4. Input Bias Current vs Common-Mode Voltage. FIGURE 5. Auto-Zero Amplifier.
FIGURE 6. Low-Droop Positive Peak Detector.
Input
Output
67
5
2
31
10kΩ
IN914 1MΩ
2N4117 0.01µF Polstyrene
Droop ≈ 0.1mV/s
≈10pF
1/4
OPA404
1/4
OPA404
IN914
(1)
(1) (1)
NOTE: (1) Reverse polarity for negative peak detection.
10
®
OPA404
FIGURE 7. Voltage-Controlled Microamp Current Source.
FIGURE 9. FET Instrumentation Amplifier with Shield Driver.
FIGURE 8. Sensitive Photodiode Amplifier.
E
1
E
1
Output = 1µA/V
I
O
12
3
1MΩ
R
6
5
3
2
INA105
Differential
Input
1
I
O
= (E
1
– E
2
) /R
Load
1/4
OPA404
+15V
Output
0.01µF
Guard
Pin Photodiode
UDT Pin-040A
2
3
8
4
1
–15V
<1pF to prevent gain peaking
5 x 88 V/W
0.1µF
0.01µF
1/4
OPA404
Circuit must be well shielded.
1000MΩ
1000MΩ
12
13
3
1
2
6
7
5
10
9
814
1/4
OPA404
1/4
OPA404
1/4
OPA404
1/4
OPA404
Input
+
–
Guard
20kΩ20kΩ
Guard
R
F
10kΩ
R
F
10kΩ
20kΩ20kΩ
A
V
= 101µV/V
I ≈ 1pA
R ≈ 10
13
Ω
BW ≈ 100kHz
Differential Voltage Gain = 1+ (2R
F
/R
G
)
B
IN
R
G
/2
100Ω
R
G
/2
100Ω
11
®
OPA404
FIGURE 10. 8-Pole 10Hz Low-Pass Filter.
FIGURE 11. Wide-Band Amplifier.
Gain = +1V/V
48dB/Octave, 10Hz LPF
Butterworth Response
0.47µF
57.6kΩ
9.53kΩ
2
31
A
0.47µF
44.2kΩ
12.1kΩ
4
57
B
0.22µF
61.9kΩ
18.7kΩ
9
10 8
C
0.033µF
127kΩ
60.4kΩ
13
12 14
D
1µF
1µF
1µF 1µF
Out
In
1kΩ1kΩ1kΩ1kΩ
A Out
B C D
4.02kΩ4.02kΩ4.02kΩ4.02kΩ
A
V
= +635
BW ≈ 650kHz
Gain-Bandwidth ≈ 410MHz
In
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
OPA404AG NRND CDIP SB JD 14 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
OPA404BG NRND CDIP SB JD 14 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
OPA404KP ACTIVE PDIP N 14 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
OPA404KPG4 ACTIVE PDIP N 14 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
OPA404KU ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA404KU/1K ACTIVE SOIC DW 16 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA404KU/1KE4 ACTIVE SOIC DW 16 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA404KUG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA404SG NRND CDIP SB JD 14 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-May-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA404KU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA404KU/1K SOIC DW 16 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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