LM3448MA/NOPB - NATIONAL SEMICONDUCTOR

LM3448

LM3448 Phase Dimmable Offline LED Driver with Integrated FET

Literature Number: SNOSB51B

LM3448

November 8, 2011

Phase Dimmable Offline LED Driver with Integrated FET

General Description

The LM3448 is an adaptive constant off-time AC/DC buck

(step-down) constant current LED regulator designed to be

compatible with TRIAC dimmers. The LM3448 provides a

constant current for illuminating high power LEDs and in-

cludes a phase angle dim decoder. The dim decoder allows

wide range LED dimming using standard forward and reverse

phase TRIAC dimmers. The integrated high-voltage and low

Rdson MOSFET reduces design complexity while improving

LED driver efficiency. The integrated and patented architec-

ture facilitates implementation of small form factor LED

drivers suitable for integrated LED lamps with very low exter-

nal component count. The LM3448 also provides the flexibility

required to implement both isolated and non-isolated solu-

tions based on the Flyback, Buck or Buck-Boost topology

using either active or passive power factor correction (Valley-

Fill) circuits. Additional features include thermal shutdown,

current limit and VCC under-voltage lockout.

Features

■Input phase angle dim decoder circuit for LED dimming

■Integrated, vertical 600V MOSFET with superior

avalanche energy capability

■Application voltage range 85VAC – 265VAC

■Adjustable switching frequency

■Adaptive programmable off-time allows for constant ripple

current

■No 120Hz flicker possible

■Low quiescent current

■Thermal shutdown

■Low profile 16-pin Narrow SOIC package

■Wave solder capable

Applications

■Retrofit TRIAC Dimming

■Solid State Lighting

■Industrial and Commercial Lighting

■Residential Lighting

Typical LM3448 LED Driver Application Circuit

301258a0

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

LM3448 Phase Dimmable Offline LED Driver with Integrated FET

Connection Diagram

Top View

30125873

16-Lead Narrow SOIC Package

NS Package Drawing M16A

Ordering Information

Order Number Spec. Package Type NSC Package

Drawing Supplied As

LM3448MA NOPB Narrow SOIC-16 M16A 48 Units, Rails

LM3448MAX NOPB Narrow SOIC-16 M16A 2500 Units, Tape and Reel

Pin Descriptions

Pin(s) Name Description

1, 2, 15, 16 SW Drain connection of internal 600V MOSFET.

3, 14 NC No connect. Provides clearance between high voltage and low voltage pins. Do not tie to GND.

4 BLDR Bleeder pin. Provides the input signal to the angle detect circuitry. A 230Ω internal resistor ensures BLDR is

pulled down for proper angle sense detection.

5, 12 GND Circuit ground connection.

6 VCC Input voltage pin. This pin provides the power for the internal control circuitry and gate driver. Connect a 22uF

(minimum) bypass capacitor to ground.

7 ASNS PWM output of the TRIAC dim decoder circuit. Outputs a 0 to 4V PWM signal with a duty cycle proportional

to the TRIAC dimmer on-time.

8 FLTR1 First filter input. The 120Hz PWM signal from ASNS is filtered to a DC signal and compared to a 1 to 3V, 5.85

kHz ramp to generate a higher frequency PWM signal with a duty cycle proportional to the TRIAC dimmer

firing angle. Pull above 4.9V (typical) to TRI-STATE® DIM.

9 DIM Input/output dual function dim pin. This pin can be driven with an external PWM signal to dim the LEDs. It

may also be used as an output signal and connected to the DIM pin of other LM3448/LM3445 devices or

LED drivers to dim multiple LED circuits simultaneously.

10 COFF OFF time setting pin. A user set current and capacitor connected from the output to this pin sets the constant

OFF time of the switching controller.

11 FLTR2 Second filter input. A capacitor tied to this pin filters the PWM dimming signal to supply a DC voltage to control

the LED current. Could also be used as an analog dimming input.

13 ISNS LED current sense pin (internally connected to MOSFET source). Connect a resistor from ISNS to GND to

set the maximum LED current.

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LM3448

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

SW to GND -0.3V to +600V

BLDR to GND -0.3V to +17V

VCC, FLTR1 to GND -0.3V to +14V

ISNS to GND -0.3V to +2.5V

ASNS, DIM, FLTR2, COFF to

GND -0.3V to +7.0V

SW FET Drain Current:

Peak 1.2A

Continuous Limited by TJ-MAX

Continuous Power Dissipation

(Note 2)

Internally Limited

ESD Susceptibility:

HBM (Note 3) 2 kV

Junction Temperature (TJ-MAX) 125°C

Storage Temperature Range -65°C to +150°C

Maximum Lead Temperature

(Solder and Reflow) 260°C

Operating Conditions (Note 1)

VCC 8V to 12V

Junction Temperature Range −40°C to +125°C

Electrical Characteristics (Note 1)

VCC = 12V unless otherwise noted. Limits in standard type face are for TJ = 25°C and those with boldface type apply over the full

Operating Temperature Range ( TJ = −40°C to +125°C). Minimum and Maximum limits are guaranteed through test, design, or

statistical correlation. Typical values represent the most likely parametric norm at TJ = +25ºC and are provided for reference

purposes only.

Symbol Parameter Conditions Min

(Note 4)

Typ

(Note 5)

Max

(Note 4)Units

BLEEDER

RBLDR Bleeder resistance to GND IBLDR = 10mA 230 325 Ω

VCC SUPPLY

IVCC Operating supply current Non-switching 2.00 2.85 mA

VCC-UVLO Rising threshold 7.4 7.7 V

Falling threshold 6.0 6.4

Hysterisis 1

COFF

VCOFF Time out threshold 1.225 1.276 1.327 V

RCOFF Off timer sinking

impedance

33 60 Ω

tCOFF Restart timer 180 µs

CURRENT LIMIT

VISNS ISNS limit threshold 1.174 1.269 1.364 V

tISNS Leading edge blanking time 125 ns

Current limit reset delay 180 µs

INTERNAL PWM RAMP

fRAMP Frequency 5.85 kHz

VRAMP Valley voltage 0.96 1.00 1.04 V

Peak voltage 2.85 3.00 3.08

DRAMP Maximum duty cycle 96.5 98.0 %

DIM DECODER

VANG_DET Angle detect rising

threshold

Observed on BLDR pin 6.79 7.21 7.81 V

VASNS ASNS filter delay 4 µs

ASNS VMAX 3.81 3.96 4.11 V

IASNS ASNS drive capability sink VASNS = 2V -7.6 mA

ASNS drive capability

source

VASNS = 2V 4.3

IDIM DIM low sink current VDIM = 1V -2.80 -1.65

DIM high source current VDIM = 4V 3.00 4.00

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LM3448

Symbol Parameter Conditions Min

(Note 4)

Typ

(Note 5)

Max

(Note 4)Units

VDIM DIM low voltage PWM input voltage threshold 0.9 1.33 V

DIM high voltage 2.33 3.15

VTSTH TRI-STATE threshold

voltage

Apply to FLTR1 pin 4.87 5.25 V

RDIM DIM comparator TRI-

STATE impedance

10 MΩ

CURRENT SENSE COMPARATOR

VFLTR2 FLTR2 open circuit voltage 720 750 780 mV

RFLTR2 FLTR2 impedance 420 kΩ

OUTPUT MOSFET (SW FET)

VBVDS SW to ISNS breakdown

voltage

600 660 V

IDS SW to ISNS leakage

current (Note 8)

SW - ISNS = 600V 1 µA

RON SW to ISNS switch on

resistance

3.6 Ω

THERMAL SHUTDOWN

TSD Thermal shutdown

temperature

(Note 6) 165 °C

Thermal shutdown

hysteresis

THERMAL RESISTANCE

RθJA Junction to Ambient (Note 6, Note 7) 95 °C/W

Note 1: Absolute Maximum Ratings are limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of

the device is guaranteed and do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical

Characteristics table. All voltages are with respect to the potential at the GND pin unless otherwise specified.

Note 2: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at approximately TJ = 165°C (typ.) and

disengages at approximately TJ = 145°C (typ).

Note 3: Human Body Model, applicable std. JESD22-A114-C.

Note 4: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%

production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used

to calculate Average Outgoing Quality Level (AOQL).

Note 5: Typical numbers are at 25°C and represent the most likely norm.

Note 6: These electrical parameters are guaranteed by design and are not verified by test.

Note 7: This RθJA typical value determined using JEDEC specifications JESD51-1 to JESD51-11. However junction-to-ambient thermal resistance is highly board-

layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues during board design. In

high-power dissipation applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the

maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient

thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

Note 8: High voltage devices such as the LM3448 are susceptible to increased leakage currents when exposed to high humidity and high pressure operating

environments. Users of this device are cautioned to satisfy themselves as to the suitability of this product in the intended end application and take any necessary

precautions (e.g. system level HAST/HALT testing, conformal coating, potting, etc.) to ensure proper device operation.

Note 9: Data used for this plot taken from Design #3.

Note 10: Data used for this plot taken from Design #2.

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LM3448

Typical Performance Characteristics TJ = 25°C and VCC = 12V unless otherwise specified.

Efficiency vs. Input Line Voltage (Note 9)

80 90 100 110 120 130 140

EFFICIENCY (%)

INPUT VOLTAGE (VRMS)

7 LEDs

9 LEDs

30125881

Power Factor vs. Input Line Voltage (Note 9)

80 90 100 110 120 130 140

0.93

0.94

0.95

0.96

0.97

0.98

POWER FACTOR

INPUT VOLTAGE (VRMS)

9 LEDs

7 LEDs

30125882

LED Current vs. Input Line Voltage (Note 10)

80 90 100 110 120 130 140

140

160

180

200

220

240

LED CURRENT (mA)

INPUT VOLTAGE (VRMS)

8 LEDs

10 LEDs

12 LEDs

30125884

fSW vs. Input Line Voltage (Note 10)

80 90 100 110 120 130 140

SWITCHING FREQUENCY (kHz)

INPUT VOLTAGE (VRMS)

8 LEDs

12 LEDs

10 LEDs

30125883

Min On-Time (tON) vs. Temperature

-50 -25 0 25 50 75 100 125 150

150

160

170

180

190

200

MIN ON-TIME (ns)

TEMPERATURE (°C)

30125833

BLDR Resistor vs. Temperature

-50 -25 0 25 50 75 100 125 150

200

220

240

260

280

300

BLDR RESISTOR (Ω)

TEMPERATURE (°C)

30125802

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LM3448

VCC UVLO vs. Temperature

-50 -25 0 25 50 75 100 125 150

6.0

6.5

7.0

7.5

8.0

UVLO THRESHOLD (V)

TEMPERATURE (°C)

UVLO (VCC) Rising

UVLO (VCC) Falling

30125814

VCOFF Threshold vs. Temperature

-50 -25 0 25 50 75 100 125 150

1.25

1.26

1.27

1.28

1.29

1.30

VCOFF THRESHOLD (V)

TEMPERATURE (°C)

30125837

Angle Detect Threshold vs. Temperature

-50 -30 -10 10 30 50 70 90 110 130 150

6.6

6.8

7.0

7.2

7.4

7.6

7.8

ANGLE DETECT THRESHOLD (V)

TEMPERATURE (°C)

30125842

Leading Edge Blanking Variation Over Temperature

30125872

DIM Pin Duty Cycle vs. FLTR1 Voltage (Note 9)

1.0 1.3 1.5 1.8 2.0 2.3 2.5 2.8 3.0

100

DIM PIN DUTY CYCLE (%)

FLTR1 VOLTAGE (V)

30125862

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LM3448

Simplified Internal Block Diagram

30125811

Theory of Operation

The LM3448 contains all the necessary circuitry to build a line-

powered (mains powered) constant current LED driver whose

output current can be controlled with a conventional TRIAC

dimmer.

OVERVIEW OF PHASE CONTROL DIMMING

A basic "phase controlled" TRIAC dimmer circuit is shown in

Figure 1.

30125812

FIGURE 1. Basic TRIAC Dimmer

An RC network consisting of R1, R2, and C1 delay the turn

on of the TRIAC until the voltage on C1 reaches the trigger

voltage of the diac. Increasing the resistance of the poten-

tiometer (wiper moving downward) increases the turn-on de-

lay which decreases the on-time or "conduction angle" of the

TRIAC (θ). This reduces the average power delivered to the

load.

30125813

FIGURE 2. Line Voltage and Dimming Waveforms

Voltage waveforms for a simple TRIAC dimmer are shown in

Figure 2. Figure 2(a) shows the full sinusoid of the input volt-

age. Even when set to full brightness, few dimmers will pro-

vide 100% on-time (i.e. the full sinusoid). Figure 2(b) shows

a theoretical waveform from a dimmer. The on-time is often

referred to as the "conduction angle" and may be stated in

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LM3448

degrees or radians. The off-time represents the delay caused

by the RC circuit feeding the TRIAC. The off-time can be re-

ferred to as the "firing angle" and is simply (180° - θ).

Figure 2(c) shows a waveform from a reverse phase dimmer,

sometimes referred to as an electronic dimmer. These typi-

cally are more expensive, microcontroller based dimmers that

use switching elements other than TRIACs. Note that the

conduction starts from the zero-crossing and terminates

some time later. This method of control reduces the noise

spike at the transition. Since the LM3448 has been designed

to assess the relative on-time and control the LED current

accordingly, most phase control dimmers both forward and

reverse phase may be used with success.

A bridge rectifier converts the line (mains) voltage of (b) into

a series of half-sines as shown in (a).

30125815

FIGURE 3. Voltage Waveforms After Bridge Rectifier

Without TRIAC Dimming

(b) and (a) show typical TRIAC dimmed voltage waveforms

before and after the bridge rectifier.

30125816

FIGURE 4. Voltage Waveforms After Bridge Rectifier With

TRIAC Dimming

SENSING THE RECTIFIED TRIAC WAVEFORM

An external series pass regulator (R2, D1, and Q1) translates

the rectified line voltage to a level where it can be sensed by

the BLDR pin on the LM3448 as shown in Figure 5.

30125817

FIGURE 5. AC Line Sense Circuitry

D1 is typically a 15V zener diode which forces transistor Q1

to “stand-off” most of the rectified line voltage. Having no ca-

pacitance on the source of Q1 allows the voltage on the BLDR

pin to rise and fall with the rectified line voltage as the line

voltage drops below zener voltage D1 (see the section on

Angle Detect).

A diode-capacitor network (D2, C5) is used to maintain the

voltage on the VCC pin while the voltage on the BLDR pin

goes low. This provides the supply voltage to operate the

LM3448.

Resistor R5 is used to bleed charge out of any stray capaci-

tance on the BLDR node and may be used to provide the

necessary holding current for the dimmer when operating at

light output currents.

ANGLE DETECT

The Angle Detect circuit uses a comparator with a fixed

threshold voltage of 7.21V to monitor the BLDR pin to deter-

mine whether the TRIAC is on or off. The output of the

comparator drives the ASNS buffer and also controls the

bleeder circuit. A 4s delay line on the output is used to filter

out noise that could be present on this signal.

The output of the Angle Detect circuit is limited to a 0V to 4.0V

swing by the buffer and presented to the ASNS pin. R1 and

C3 comprise a low-pass filter with a bandwidth on the order

of 1.0Hz.

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LM3448

The Angle Detect circuit and its filter produce a DC level which

corresponds to the duty cycle (relative on-time) of the TRIAC

dimmer. As a result, the LM3448 will work equally well with

50Hz or 60Hz line voltages.

BLEEDER

While the BLDR pin is below the 7.21V threshold, the internal

bleeder MOSFET is on to place a small load (230Ω) on the

series pass regulator. This additional load is necessary to

complete the circuit through the TRIAC dimmer so that the

dimmer delay circuit can operate correctly. Above 7.21V, the

bleeder resistor is removed to increase efficiency.

FLTR1 PIN

The FLTR1 pin has two functions. Normally it is fed by ASNS

through filter components R1 and C3 and drives the dim de-

coder. However if the FLTR1 pin is tied above 4.9V ( e.g., to

VCC) the ramp comparator is at TRI-STATE disabling the dim

decoder.

DIM DECODER

The ramp generator produces a 5.85 kHz saw tooth wave with

a minimum of 1.0V and a maximum of 3.0V. The filtered ASNS

signal enters pin FLTR1 where it is compared against the

output of the Ramp Generator. The output of the ramp com-

parator will have an on-time which is inversely proportional to

the average voltage level at pin FLTR1. However since the

FLTR1 signal can vary between 0V and 4.0V (the limits of the

ASNS pin), and the ramp generator signal only varies be-

tween 1.0V and 3.0V, the output of the ramp comparator will

be on continuously for VFLTR1 < 1.0V and off continuously for

VFLTR1 > 3.0V. This allows a decoding range from 45° to 135°

to provide a 0 – 100% dimming range.

The output of the ramp comparator drives both a common

source N-channel MOSFET through a Schmitt trigger and the

DIM pin. The MOSFET drain is pulled up to 750 mV by a

50kΩ resistor.

Since the MOSFET inverts the output of the ramp comparator,

the drain voltage of the MOSFET is proportional to the duty

cycle of the line voltage that comes through the TRIAC dim-

mer. The amplitude of the ramp generator causes this pro-

portionality to "hard limit" for duty cycles above 75% and

below 25%.

FLTR2

The MOSFET drain signal next passes through an RC filter

comprised of an internal 370kΩ resistor and an external ca-

pacitor on pin FLTR2. This forms a second low pass filter to

further reduce the ripple in this signal which is used as a ref-

erence by the PWM comparator. This RC filter is generally set

to 10Hz.

The net effect is that the output of the dim decoder is a DC

voltage whose amplitude varies from near 0V to 750 mV as

the duty cycle of the dimmer varies from 25% to 75%. This

corresponds to conduction angles of 45° to 135°.

The output voltage of the dim decoder directly controls the

peak current that will be delivered by the internal SW FET.

As the TRIAC fires beyond 135°, the DIM decoder no longer

controls the dimming. At this point the LEDs will dim gradually

for one of two reasons:

•The voltage at VBUCK decreases and the buck converter

runs out of headroom and causes LED current to decrease

as VBUCK decreases.

•Minimum on-time is reached which fixes the duty-cycle

and therefore reduces the voltage at VBUCK.

The transition from dimming with the DIM decoder to head-

room or minimum on-time dimming is seamless. LED currents

from full load to as low as 0.5mA can be easily achieved.

COFF AND CONSTANT OFF-TIME CONTROL OVERVIEW

The LM3448 is a buck regulator that uses a proprietary con-

stant off-time method to maintain constant current through a

string of LEDs as shown in Figure 6.

30125823

FIGURE 6. Simplified Buck Regulation Circuit

Constant off-time control architecture operates by simply

defining the off-time and allowing the on-time, and therefore

the switching frequency, to vary as either VIN or VO changes.

The output voltage is equal to the LED string voltage (VLED),

and should not change significantly for a given application.

The input voltage or VBUCK in this analysis will vary as the

input line varies. The length of the on-time is determined by

the sensed inductor current through a resistor to a voltage

reference at a comparator. During the on-time denoted by

tON, the SW FET is on causing the inductor current to increase

(see Figure 7). During the on-time, current flows from VBUCK

through the LEDs, L2, the LM3448's internal SW FET and

finally through R3 to ground. At some point in time the inductor

current reaches a maximum (IL2-PK) determined by the voltage

at the ISNS pin. This sensed voltage across R3 is compared

against the dim decoder voltage on FLTR2 at which point the

SW FET is turned off by the regulator. During the off-period

denoted by tOFF, the current through L2 continues to flow

through the LEDs via D10. Capacitor C12 eliminates most of

the ripple current seen in the inductor. Resistor R4, capacitor

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LM3448

C11 and transistor Q3 provide a linear current ramp that in

conjunction with the COFF comparator threshold sets the

constant off-time for a given output voltage.

30125825

FIGURE 7. Inductor Current Waveform in CCM

VCC BIAS SUPPLY

The LM3448 requires a supply voltage at the VCC pin in the

range of 8V to 12V. The device has VCC under-voltage lockout

(UVLO) with rising and falling thresholds of 7.4V and 6.4V

respectively. Methods for supplying the VCC voltage are dis-

cussed in the “Design Considerations” section of this

datasheet.

THERMAL SHUTDOWN

Thermal shutdown limits total power dissipation by turning off

the internal SW FET when the IC junction temperature ex-

ceeds 165°C. After thermal shutdown occurs, the SW FET will

not turn on until the junction temperature drops to approxi-

mately 145°C.

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LM3448

Design Considerations

VALLEY-FILL POWER FACTOR CORRECTION

For the non-isolated buck converter, a valley-fill power factor

correction (PFC) circuit shown in Figure 8 provides a simple

means of improving the converter’s power factor perfor-

mance.

30125818

FIGURE 8. Two Stage Valley Fill Circuit

The valley-fill circuit allows the buck regulator to draw power

throughout a larger portion of the AC line. This allows the ca-

pacitance needed at VBUCK to be lower than if there were no

valley-fill circuit and adds passive power factor correction

(PFC) to the application. Besides better power factor correc-

tion, a valley-fill circuit allows the buck converter to operate

while separate circuitry translates the dimming information.

This allows for dimming that isn’t subject to 120Hz flicker that

can possibly be perceived by the human eye.

VBUCK supplies the power which drives the LED string. Diode

D3 allows VBUCK to remain high while V+ cycles on and off.

VBUCK has a relatively small hold capacitor C10 which reduces

the voltage ripple when the valley-fill capacitors are being

charged. However, the network of diodes and capacitors

shown between D3 and C10 make up a "valley-fill" circuit. The

valley-fill circuit can be configured with two or three stages.

The most common configuration is two stages which is illus-

trated in Figure 8.

When the “input line is high”, power is derived directly through

D3. The term “input line is high” can be explained as follows.

The valley-fill circuit charges capacitors C7 and C9 in series

when the input line is high (see Figure 9).

30125819

FIGURE 9. Two stage Valley-Fill Circuit when AC Line is

High

The peak voltage of a two stage valley-fill capacitor is:

As the AC line decreases from its peak value every cycle,

there will be a point where the voltage magnitude of the AC

line is equal to the voltage that each capacitor is charged. At

this point diode D3 becomes reversed biased, and the ca-

pacitors are placed in parallel to each other (see Figure 10)

and VBUCK equals the capacitor voltage.

30125821

FIGURE 10. Two stage Valley-Fill Circuit when AC Line is

Low

The valley-fill circuit can be optimized for power factor, volt-

age hold-up and overall application size and cost. The

LM3448 will operate with a single stage or a three stage val-

ley-fill circuit as well. Resistor R8 functions as a current

limiting resistor during start-up and during the transition from

series to parallel connection. Resistors R6 and R7 are 1MΩ

bleeder resistors and may or may not be necessary for each

application.

FLTR2 LINE-INJECTION

The technique of line-injection is another very effective means

of improving power factor performance. When using this

method, the valley-fill circuit can be eliminated which results

in a much simpler driver design. The trade off will be an in-

crease of 120Hz ripple on the LED current.

Different FLTR2 circuits are shown in Figure 11. Figure 11(a)

shows how to set up FLTR2 when a passive PFC circuit (e.g.

valley-fill) is already being used and no line-injection is uti-

lized. If passive PFC is not being implemented, then the

“direct line-injection” of Figure 11(b) or “AC line-injection” of

Figure 11(c) can be used.

Direct line-injection involves injecting a small portion (750mV

to 1.00V) of rectified AC line voltage (i.e. V+) into the FLTR2

pin. The result is that current shaping of the input current will

yield power factor values greater than 0.94.

AC coupled line-injection goes one step further by adding a

capacitor C14 between R15 and C11. This improves LED line

regulation but does so by trading out a small portion of the

power factor improvement from the direct-injection circuit. For

example with AC coupled line-injection, LED current regula-

tion of up to +/- 3% is possible for an input voltage range of

105VAC to 135VAC when operating at a nominal 120VAC.

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LM3448

30125886

FIGURE 11. (a) No line-injection, (b) Direct line-injection, (c) AC-coupled line injection

DIRECT LINE-INJECTION FOR FLYBACK TOPOLOGY

For flyback converters using the LM3448, direct-line injection

can result in power factors greater than 0.95. Using this tech-

nique, the LM3448 circuit is essentially turned into a constant

power flyback converter operating in discontinuous conduc-

tion mode (DCM). The LM3448 normally works as a constant

off-time regulator, but by injecting a 1.0VPK rectified AC volt-

age into the FLTR2 pin, the on-time can be made to be

constant. With a DCM flyback converter the primary side cur-

rent, i, needs to increase as the rectified input voltage, V+,

increases as shown in the following equations,

or,

Therefore a constant on-time (since inductor L is constant)

can be obtained.

By using the line voltage injection technique, the FLTR2 pin

has the voltage wave shape shown in Figure 12 on it with no

TRIAC dimmer in-line. Peak voltage at the FLTR2 pin should

be kept below 1.25V otherwise current limit will be tripped.

Capacitor C11 is chosen small enough so as not to distort the

AC signal but just add a little filtering.

Although the on-time is probably never truly constant, it can

be observed in Figure 13 how (by injecting the rectified volt-

age) the on-time is adjusted.

30125895

FIGURE 12. FLTR2 Waveform with No Dimmer

30125896

FIGURE 13. Typical Operation of Direct Line-Injection into FLTR2 Pin

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LM3448

TRIAC DIMMER HOLDING CURRENT

In order to emulate an incandescent light bulb (essentially a

resistor) with any LED driver, the existing TRIAC will require

a small amount of holding current throughout the AC line cy-

cle. As shown in Figure 14, a simple circuit consisting of R3,

D1, Q1 and R4 can accomplish this. With R4 placed on the

source of Q1, additional holding current can be pulled from

the TRIAC. Most TRIAC dimmers only require a few milliamps

of current to hold them on. A few “less expensive” TRIACs

sold on the market will require a bit more current. The value

of resistor R4 will depend on the type of TRIAC being used

and how many light fixtures are running off the TRIAC.

With a single LM3448 circuit on a common TRIAC dimmer, a

holding current resistor between 3kΩ and 5kΩ will be re-

quired. As the number of LM3448 circuits added to a single

dimmer increases, R4’s resistance can also be increased. A

few TRIAC dimmers will require a resistor as low as 1kΩ or

smaller for a single LM3448 circuit. Therefore the trade-off will

be dimming performance versus efficiency. As the holding

resistor R4 is increased, the overall system efficiency will also

increase.

30125885

FIGURE 14. Basic holding current circuit

OPTIMIZING THE HOLDING CURRENT

For optimal system performance and efficiency, only enough

holding current should be applied at the right time in the cycle

to keep the TRIAC operating properly. This will ensure no

variation or ‘flicker’ is seen in the LED light output while im-

proving the circuit efficiency. Circuits that do this are outlined

individually as blocks in Figure 15. These circuits are de-

signed to identify the type of phase dimmer in-line with the

LM3448, add holding current for different dimming conditions,

or to discharge parasitic capacitances. The objective is to only

add enough holding current as needed regardless if the dim-

mer is of a forward or reverse phase type. This allows the

lighting manufacturer to optimize efficiency and gain Energy

Star approval if desired.

30125878

FIGURE 15. TRIAC holding current circuits

13 www.ti.com

LM3448

Linear Hold Insertion Circuit

This circuit adds holding current during low TRIAC conduction

angles. A variable voltage between 0 and 5 volts is generated

at the Q6 gate by averaging the square wave output signal on

the DIM pin. The duty cycle of this square wave varies with

the TRIAC firing angle. As the LEDs are dimmed, the voltage

at the Q6 gate will rise pulling a “holding current” equal to the

Q6 source voltage divided by resistor R19.

Valley-Fill Holding Current Circuit

As described in the section on valley-fill PFC operation, when

the valley-fill capacitors are in parallel there is a brief period

of time where the output load is being supplied by these two

capacitors. Therefore there is minimal or no line current being

drawn from the AC line and the minimum holding current re-

quirement is not met. The TRIAC may turn off at this time

which causes phase dimming decode issues. A circuit can be

added that detects when the valley-fill capacitors are in par-

allel. The result is that the gate of Q4 is pulled low, allowing

additional hold current to be sourced through resistor R10.

TRIAC Edge Detect Circuit

During initial turn on (forward phase) or turn off (reverse

phase) of a phase dimmer, a little extra holding current is

sometimes required to latch the phase dimmer on or dis-

charge any parasitic capacitances on the AC line. In order to

determine which dimmer is being used, a TRIAC edge detect

circuit is needed.

When the TRIAC fires, a sharp edge is created that can be

captured by a properly sized R-C circuit. The combination of

C3 and R6 creates a positive pulse on R7 for a forward phase

dimmer or a negative pulse on R7 for a reverse phase dim-

mer. The pulse polarity determines whether the forward or

reverse phase holding current circuit will be used. The value

of R7 can be adjusted to vary the sensitivity of the edge detect

circuit.

Forward Phase Holding Current Circuit

This circuit adds holding current when a forward phase TRIAC

edge is detected. The TRIAC edge detect R-C circuit creates

a positive pulse on the base of Q3 each cycle when a forward

phase dimmer is present and dimming. The positive pulse

turns on Q3 which results in additional holding current being

pulled through R9.

Reverse Phase Holding Current Circuit

This circuit adds holding current when a reverse phase TRIAC

edge is detected. The TRIAC edge detect R-C circuit creates

a negative pulse on the emitter of Q2 each cycle when a re-

verse phase dimmer is present and dimming. This turns on

Q8 and connects R23 to the Q1 pass MOSFET, adding hold-

ing current and sharpening the turn-off of the reverse phase

dimmer.

START-UP AND BIAS SUPPLY

Figure 16 shows how to generate the necessary VCC bias

supply at start-up. Since the AC line peak voltage is always

higher than the rating of the regulator, all designs require an

N-channel MOSFET (passFET). The passFET (Q1) is con-

nected with its drain attached to the rectified AC. The gate of

Q1 is connected to a zener diode (D1) which is then biased

from the rectified AC line through series resistance (R3). The

source of Q1 is held at a VGS below the zener voltage and

current flows through Q1 to charge up whatever capacitance

is present. If the capacitance is large enough, the source volt-

age will remain relatively constant over the line cycle and this

becomes the input bias supply at VCC. This bias circuit also

enables instant turn-on.

However once the circuit is operational, it can be desirable to

bootstrap VCC to an auxiliary winding of the inductor or trans-

former as shown in Figure 17. The two bias paths are each

connected to VCC through a diode to ensure the higher of the

two is providing VCC current. This bootstrapping greatly im-

proves efficiency while still maintaining quick start-up re-

sponse.

30125885

FIGURE 16. VCC start-up circuit

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LM3448

30125887

FIGURE 17. VCC auxiliary winding bias circuit

COFF CURRENT SOURCE CIRCUITS

There are a few different current source circuits that can be

used for establishing the LM3448 constant-off time control as

shown in Figure 18.

Figure 18(a) shows the simplest current source circuit. Ca-

pacitor COFF will be charged with a constant current from

VCC through resistor ROFF.

If there is large noise or ripple on the VCC pin, then the pre-

viously described circuit will fluctuate and the off-time will not

be constant. The circuit of Figure 18(b) addresses this by us-

ing a zener diode D1 across ROFF which establishes a stable

voltage reference for the current source with inherent VCC rip-

ple rejection.

LED loads can exhibit voltage drift due to self-heating or ex-

ternal thermal conditions. A change in the LED stack voltage

will result in the LED current to drift as well. Figure 18(c) ad-

dresses this issue by having the COFF current source refer-

enced to the LED stack voltage using Q1 and ROFF and

thereby compensating for LED voltage drift. Another benefit

is that the number of series LEDs in the LED string can be

changed while still maintaining the same output drive current.

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LM3448

30125888

FIGURE 18. COFF Current Source Circuits

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LM3448

Design Guide

30125801

FIGURE 19. Typical Non-Isolated Buck Converter with Valley-Fill PFC

The following design guide is an example of how to design

the LM3448 as a non-isolated buck converter with valley-fill

PFC as shown in Figure 19.

DETERMINING DUTY-CYCLE (D)

Duty cycle (D) approximately equals:

With efficiency considered:

For simplicity, choose efficiency between 75% and 85%.

CALCULATING OFF-TIME

The “Off-Time” of the LM3448 is set by the user and remains

fairly constant as long as the voltage of the LED stack remains

constant. Calculating the off-time is the first step in determin-

ing the switching frequency (fSW) of the converter, which is

integral in determining some external component values.

PNP transistor Q3, resistor R4, and the LED string voltage

define a charging current into capacitor C11. A constant cur-

rent into a capacitor creates a linear charging characteristic.

17 www.ti.com

LM3448

Resistor R4, capacitor C11 and the current through resistor

R4 (iCOLL), which is approximately equal to VLED/R4, are all

fixed. Therefore, dv is fixed and linear, and dt (i.e. tOFF) can

now be calculated.

Common equations for determining duty cycle and switching

frequency in any buck converter:

Therefore:

With efficiency of the buck converter in mind:

Substitute equations and rearrange:

Off-time and switching frequency can now be calculated using

the equations above.

SETTING THE SWITCHING FREQUENCY

Selecting the switching frequency for nominal operating con-

ditions is based on tradeoffs between efficiency (better at low

frequency) and solution size/cost (smaller at high frequency).

The input voltage to the buck converter (VBUCK) changes with

both line variations and over the course of each half-cycle of

the input line voltage. The voltage across the LED string will,

however, remain constant and therefore the off-time remains

constant.

The on-time (tON) and therefore the switching frequency, will

vary as the VBUCK voltage changes with line voltage. A good

design practice is to choose a desired nominal switching fre-

quency knowing that the switching frequency will decrease as

the line voltage drops and increase as the line voltage in-

creases.

The off-time of the LM3448 can be programmed for switching

frequencies ranging from 30 kHz to over 1MHz. A trade-off

between efficiency and solution size must be considered

when designing the LM3448 application.

The maximum switching frequency attainable is limited only

by the minimum on-time requirement (200 ns).

Worst case scenario for minimum on time is when VBUCK is at

its maximum voltage (AC high line) and the LED string voltage

(VLED) is at its minimum value.

The maximum voltage seen by the Buck Converter is:

INDUCTOR SELECTION

The controlled off-time architecture of the LM3448 regulates

the average current through the inductor (L2), and therefore

the LED string current (see Figure 20). The input voltage to

the buck converter (VBUCK) changes with line variations and

over the course of each half-cycle of the input line voltage.

The voltage across the LED string is relatively constant, and

therefore the current through R4 is constant. This current sets

the off-time of the converter and therefore the output volt-

second product (VLED x off-time) remains constant. A constant

volt-second product makes it possible to keep the ripple

through the inductor constant as the voltage at VBUCK varies.

30125840

FIGURE 20. Simplified LM3448 Buck Converter

The equation for an ideal inductor is:

www.ti.com 18

LM3448

Given a fixed inductor value, L, this equation states that the

change in the inductor current over time is proportional to the

voltage applied across the inductor.

During the on-time, the voltage applied across the inductor is,

Since the voltage across the SW FET (VDS) is relatively small

as is the voltage across sense resistor R3, we can simplify

this as approximately,

During the off-time, the voltage seen by the inductor is ap-

proximately,

The value of VL(OFF-TIME) will be relatively constant, because

the LED stack voltage will remain constant. If we rewrite the

equation for an inductor inserting what we know about the

circuit during the off-time, we get,

Re-arranging this gives,

From this we can see that the ripple current (Δi) is proportional

to off-time (tOFF) multiplied by a voltage which is dominated

by VLED divided by a constant inductance (L2).

These equations can be rearranged to calculate the desired

value for inductor L2.

where,

and finally,

Refer to “Design Example” section of the datasheet to better

understand the design process.

SETTING THE LED CURRENT

Figure 21 shows the inductor current waveform (IL2) when

operating in continuous conduction mode (CCM). The

LM3448 constant off-time control loop regulates the peak in-

ductor current (IL2-PK). Since the average inductor current

equals the average LED current (IAVE), LED current is con-

trolled by regulating the peak inductor current.

30125825

FIGURE 21. Inductor Current Waveform in CCM

Knowing the desired average LED current (IAVE) and the nom-

inal inductor current ripple (ΔiL), the peak current for an ap-

plication running in CCM is defined as follows:

Or, the maximum (i.e. un-dimmed) LED current would then

be,

This is important to calculate because this peak current mul-

tiplied by the sense resistor R3 will determine when the

internal comparator is tripped. The internal comparator turns

the SW FET off once the peak sensed voltage reaches 750

mV.

CURRENT LIMIT

Under normal circumstances, the trip voltage on the PWM

comparator would be less than or equal to 750 mV depending

on the amount of dimming. However if there is a short circuit

or an excessive load on the output, higher than normal switch

currents will cause a voltage above 1.27V on the ISNS pin

which will trip the I-LIM comparator. The I-LIM comparator will

reset the RS latch, turning off the internal SW FET. It will also

inhibit the Start Pulse Generator and the COFF comparator

by holding the COFF pin low. A delay circuit will prevent the

start of another cycle for 180µs.

VALLEY FILL CAPACITORS

The maximum voltage seen by the valley-fill capacitors is,

This assumes that the capacitors chosen have identical ca-

pacitance values and split the line voltage equally. Often a

20% difference in capacitance could be observed between

19 www.ti.com

LM3448

like capacitors. Therefore a voltage rating margin of 25% to

50% should be considered.

The valley-fill capacitors should be sized to supply energy to

the buck converter (VBUCK) when the input line is less than its

peak divided by the number of stages used in the valley-fill.

The capacitance value should be calculated when the TRIAC

is not firing (i.e. when full LED current is being drawn by the

LED string). The maximum power is delivered to the LED

string at this time and therefore the most capacitance will be

needed.

30125852

FIGURE 22. Two Stage Valley-Fill VBUCK Voltage with no

TRIAC Dimming

From Figure 22 and the equation for current in a capacitor,

the amount of capacitance needed at VBUCK can be calculated

using the following method.

At 60Hz and a valley-fill circuit of two stages, the hold-up time

(tX) required at VBUCK is calculated as follows. The total angle

of an AC half cycle is 180° and the total time of a half AC line

cycle is 8.33ms. When the angle of the AC waveform is at 30°

and 150°, the voltage of the AC line is exactly ½ of its peak.

With a two stage valley-fill circuit, this is the point where the

LED string switches from power being derived from AC line

to power being derived from the hold-up capacitors (C7 and

C9). At 60° out of 180° of the cycle or 1/3 of the cycle, the

power is derived from the hold-up capacitors (1/3 x 8.33 ms

= 2.78 ms). This is equal to the hold-up time (dt) from the

above equation, and dv is the amount of voltage the circuit is

allowed to droop. From the next section (“Determining Maxi-

mum Number of Series Connected LEDs Allowed”) we know

the minimum VBUCK voltage will be about 45V for a 90VAC to

135VAC line. At a 90VAC low line operating condition input,

½ of the peak voltage is 64V. Therefore with some margin the

voltage at VBUCK cannot droop more than about 15V (dv). (i)

is equal to (POUT/ VBUCK), where POUT is equal to (VLED x

ILED). Total capacitance (C7 in parallel with C9) can now be

calculated. See “ Design Example" section for further calcu-

lations of the valley-fill capacitors.

MAXIMUM NUMBER OF SERIES CONNECTED LEDS

A buck converter topology requires that the input voltage

(VBUCK) of the output circuit must be greater than the voltage

of the LED stack (VLED) for proper regulation. One must de-

termine what the minimum voltage observed by the buck

converter will be before the maximum number of series LEDs

allowed can be determined. Two variables will have to be de-

termined in order to accomplish this.

1. AC line operating voltage. This is usually 90VAC to

135VAC for North America. Although the LM3448 can

operate at much lower and higher input voltages a range

is needed to illustrate the design process.

2. Number of stages being implemented in the valley-fill

circuit.

In this example a two-stage valley-fill circuit will be used.

Figure 23 shows three TRIAC dimmed waveforms. One can

easily see that the peak voltage (VPEAK) from 0° to 90° will

always be,

Once the TRIAC is firing at an angle greater than 90° the peak

voltage will lower and be equal to,

The voltage at VBUCK with a valley-fill stage of two will look

similar to the waveforms of Figure 24. The purpose of the

valley-fill circuit is to allow the buck converter to pull power

directly off of the AC line when the line voltage is greater than

its peak voltage divided by two (for a two stage valley-fill cir-

cuit). During this time, the capacitors within the valley-fill

circuit (C7 and C9) are charged up to the peak of the AC line

voltage. Once the line drops below its peak divided by two,

the two capacitors are placed in parallel and deliver power to

the buck converter. One can now see that if the peak of the

AC line voltage is lowered due to variations in the line voltage,

or if the TRIAC is firing at an angle above 90°, the DC offset

(VDC) will lower. VDC is the lowest value that voltage VBUCK

will encounter.

Example:

Line voltage = 90VAC to 135VAC

Valley-fill stages = 2

Depending on what type and value of capacitors are used,

some derating should be used for voltage droop when the

capacitors are delivering power to the buck converter. When

the TRIAC is firing at 135° the current through the LED string

will be small. Therefore the droop should be small at this point

and a 5% voltage droop should be a sufficient derating. With

this derating, the lowest voltage the buck converter will see is

about 42.5V in this example.

To determine how many LEDs can be driven, take the mini-

mum voltage the buck converter will see (42.5V) and divide it

by the worst case forward voltage drop of a single LED.

Example:

42.5V/3.7V = 11.5 LEDs (11 LEDs with margin)

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LM3448

30125855

FIGURE 23. VBUCK Waveforms with Various TRIAC Firing Angles

30125856

FIGURE 24. Two Stage Valley-Fill VBUCK Waveforms with Various TRIAC Firing Angles

OUTPUT CAPACITOR

A capacitor placed in parallel with the LED or array of LEDs

can be used to reduce the LED current ripple while keeping

the same average current through both the inductor and the

LED array. With a buck topology the output inductance (L2)

can now be lowered, making the magnetics smaller and less

expensive. With a well designed converter, you can assume

that all of the ripple will be seen by the capacitor and not the

LEDs. One must ensure that the capacitor you choose can

handle the RMS current of the inductor. Refer to

manufacture’s datasheets to ensure compliance. Usually an

X5R or X7R capacitor between 1µF and 10µF of the proper

voltage rating will be sufficient.

RE-CIRCULATING DIODE

The LM3448 Buck converter requires a re-circulating diode

D10 to carry the inductor current during the off-time of the

internal SW FET. The most efficient choice for D10 is a diode

with a low forward drop and near-zero reverse recovery time

that can withstand a reverse voltage of the maximum voltage

seen at VBUCK. For a common 110VAC ± 20% line, the re-

verse voltage could be as high as 190V.

The current rating must be at least,

or,

Another consideration when choosing a diode is to make sure

that the diode’s reverse recovery time is much greater than

the leading edge blanking time for proper operation.

21 www.ti.com

LM3448

Design Calculation Example

The following design example illustrates the process of actu-

ally calculating external component values for a LM3448 non-

isolated buck converter with valley-fill PFC according to the

following specifications.

SPECIFICATIONS:

1. Input voltage range (90VAC – 135VAC)

2. Nominal input voltage = 115VAC

3. Number of LEDs in series = 7

4. Forward voltage drop of a single LED = 3.6V

5. LED stack voltage = (7 x 3.6V) = 25.2V

CHOSEN VALUES:

1. Target nominal switching frequency, fSW = 250kHz

2. ILED(AVE) = 400mA

3. POUT = (25.2V) x (400mA) = 10.1W

4. Ripple current Δi (usually 15% - 30% of ILED(AVE)) = (0.30

x 400mA) = 120mA

5. Valley fill stages = 2

6. Assumed minimum efficiency = 80%

CALCULATIONS:

1. Calculate minimum voltage VBUCK equals:

2. Calculate maximum voltage VBUCK voltage,

3. Calculate tOFF at VBUCK nominal line voltage,

4. Calculate tON(MIN) at high line to ensure that

tON(MIN) > 200ns,

5. Calculate C11 and R4:

6. Choose current through R4 (between 50µA and 100µA):

70µA

Calculate R4,

7. Choose a standard value of 365kΩ

8. Calculate C11,

10. Choose standard value of 120pF.

11. Calculate inductor value at tOFF = 3µs,

12. Choose C10 = 1.0µF, 200V.

13. Calculate valley-fill capacitor values,

VAC low line = 90VAC, VBUCK minimum equals 45V (no

TRIAC dimming at maximum LED current). Set droop for

20V maximum at full load and low line.

Since "i" equals POUT/VBUCK = 224mA, "dV" equals 20V,

"dt" equals 2.78ms, and then CTOTAL equals 31µF.

Therefore choose C7 = C9 = 15µF.

www.ti.com 22

LM3448

Applications Information

DESIGN #1: 7W, 120VAC Non-isolated Buck LED Driver with Valley-Fill PFC

SPECIFICATIONS:

•AC Input Voltage: 120VAC nominal (85VAC – 135VAC)

•Output Voltage: 21.1VDC

•LED Output Current: 342mA

This TRIAC dimmer compatible design incorporates the following features:

•Passive valley-fill PFC for improved power factor performance,

•Comprehensive TRIAC holding current coverage,

•Standard VCC start-up and bias circuit,

•Constant-off time control with LED voltage drift compensation.

23 www.ti.com

LM3448

30125877

www.ti.com 24

LM3448

DESIGN #1 BILL OF MATERIALS

Part ID Description Manufacturer Part Number

U1 IC LED Driver National Semiconductor LM3448MA

BR1 Bridge Rectifier Vr = 400V, Io = 0.8A, Vf = 1V Diodes Inc. HD04-T

C2 Ceramic, 0.01uF, X7R, 25V, 10% MuRata GRM188R71E103KA01D

C3 Ceramic, 1000pF 500V X7R 1206 Kemet C1206C102KCRACTU

C12 .01uF KEMIT C1808C103KDRACTU

C6, C10 CAP 33uF 100V ELECT NHG RADIAL Panasonic-ECG ECA-2AHG330

C7 22uF, Ceramic, X5R, 25V, 10% MuRata GRM32ER61E226KE15L

C8 DNP - -

C9 4.7uF C3216X7R1E475K

C11 DNP - -

C13 Ceramic, 1.0uF 100V X7R 1206 Murata GRM31CR72A105KA01

C14 Ceramic, X7R, 16V, 10% MuRata GRM188R71C474KA88D

C15 Ceramic, 0.1uF, X7R, 16V, 10% MuRata GRM188R71C104KA01D

C16 Ceramic, 0.22uF, X7R, 16V, 10% Murata GRM188R71E224KA88D

C17 Ceramic, 330pF 100V C0G 0603 Murata GCM1885C2A331JA16D

D1 DIODE ZENER 225MW 15V SOT23 ON Semiconductor BZX84C15LT1G

D2, D3, D5, D6, D7 DIODE FAST REC 200V 1A Rohm Semiconductor RF071M2STR

D4 DIODE SWITCH SS DUAL 70V SOT323 Fairchild BAV99WT1G

D8 DIODE SUPER FAST 200V 1A SMB Diodes Inc MURS120-13-F

F1 FUSE 1A 125V FAST Cooper/Bussman 6125FA1A

L2 10mH, FERRITE CHIP POWER 160 OHM Steward HI1206T161R-10

L3 1mH, Shielded Drum Core, Coilcraft Inc. MSS1260-105

Q1 MOSFET N-CHAN 250V 4.4A DPAK Fairchild FDD6N25

Q2, Q3 TRANS NPN 350MW 40V SMD SOT23 Diodes Inc MMBT4401-7-F

Q4 MOSFET P-CH 50V 130MA SOT-323 Diodes Inc BSS84W-7-F

Q5 TRANS HIVOLT PNP AMP SOT-23 Fairchild MMBTA92

Q6 MOSFET N-CHANNEL 100V SOT323 Diodes Inc BSS123W-7-F

Q8 TRANS PNP LP 100MA 30V SOT23 ON Semiconductor BC858CLT1G

R2 4.75M, 0805, 1%, 0.125W Vishay-Dale CRCW08054M75FKEA

R3 1%, 0.25W Vishay-Dale CRCW1206332kFKEA

R4 DNP - -

R5, R16 RES 49.9K OHM, 0.1W, 1% 0603 Vishay-Dale CRCW060349k9FKEA

R6 RES 100K OHM, 0.25W1%, 1206 Vishay-Dale CRCW1206100kFKEA

R7 RES 7.50K OHM, 0.1W, 1% 0603 Vishay-Dale CRCW06037k50FKEA

R8 RES 10.0K OHM, 0.1W, 1% 0603 Vishay-Dale CRCW060310k0FKEA

R9 RES 100 OHM, 0.25W1%, 1206 Vishay-Dale CRCW1206100RFKEA

R10 RES 124 OHM, 0.25W1%, 1206 Vishay-Dale CRCW1206124RFKEA

R11 RES 200K OHM, 0.125W, 1%, 0805 Vishay-Dale CRCW0805200kFKEA

R12, R13 RES 1.0M OHM, 0.125W, 1%, 0805 Vishay-Dale CRCW08051M00FKEA

R14 RES 576K OHM, 1/10W 1% 0603 Vishay-Dale CRCW0603576kFKEA

R15 RES 280K OHM, 1/10W 1% 0603 Vishay-Dale CRCW0603280kFKEA

R17 DNP - -

R18 RES 301 OHM, 0.25W1%, 1206 Vishay-Dale CRCW1206301RFKEA

R19 RES 49.9 OHM, 0.125W, 1%, 0805 Vishay-Dale CRCW080549R9FKEA

R21 RES 12.1 OHM, 0.25W1%, 1206 Vishay-Dale CRCW120612R1FKEA

R22 RES 1.8 OHM 1/3W 5% 1210 Vishay-Dale CRCW12101R80JNEA

R23 RES 499 OHM, 0.25W1%, 1206 Vishay-Dale CRCW1206499RFKEA

RT1 CURRENT LIM INRUSH 60OHM 20% Canterm MF72-060D5

25 www.ti.com

LM3448

DESIGN #2: 6.5W, 120VAC Non-isolated “A19 Edison” Retrofit with AC-Coupled Line Injection

SPECIFICATIONS:

•AC Input Voltage: 120VAC nominal (85VAC – 135VAC)

•Output Voltage: 35.7VDC

•LED Output Current: 181mA

This TRIAC dimmer compatible design incorporates the following features:

•AC coupled line-injection for improved power factor performance and LED current regulation,

•Standard VCC start-up and bias circuit,

•VCC derived COFF current source.

NOTE: Refer to LM3448 Application Note, AN-2127, for additional information and BOM regarding this design.

30125874

www.ti.com 26

LM3448

DESIGN #3: 6W, 120VAC Isolated Flyback LED Driver with Direct Line Injection

SPECIFICATIONS:

•AC Input Voltage: 120VAC nominal (85VAC – 135VAC)

•Flyback Output Voltage: 27.1VDC

•LED Output Current: 228mA

This TRIAC dimmer compatible design incorporates the following features:

•Direct line-injection for improved power factor performance,

•Standard VCC start-up with auxiliary winding bias circuit for improved system efficiency,

•Zener diode derived COFF current source for improved VCC ripple rejection,

•Additional TRIAC holding current circuit for improved dimmer performance at low conduction angles,

•Output overvoltage protection (OVP).

NOTE: Refer to LM3448 Application Note, AN-2090, for additional information and BOM regarding this design.

30125875

27 www.ti.com

LM3448

DESIGN #4: 6W, 230VAC Isolated Flyback LED Driver with Direct Line Injection

SPECIFICATIONS:

•AC Input Voltage: 230VAC nominal (180VAC – 265VAC)

•Flyback Output Voltage: 27.0VDC

•LED Output Current: 226mA

This TRIAC dimmer compatible design incorporates the following features:

•Direct line-injection for improved power factor performance

•Standard VCC start-up with auxiliary winding bias circuit for improved system efficiency,

•VCC derived COFF current source,

•Additional TRIAC holding current circuit for improved dimmer performance at low conduction angles,

•Output overvoltage protection (OVP).

NOTE: Refer to LM3448 Application Note, AN-2091, for additional information and BOM regarding this design.

30125876

www.ti.com 28

LM3448

Physical Dimensions inches (millimeters) unless otherwise noted

Narrow SOIC-16 Pin Package

For Ordering, Refer to Ordering Information Table

NS Package Number M16A

29 www.ti.com

LM3448

Notes

LM3448 Phase Dimmable Offline LED Driver with Integrated FET

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