Data Sheet
V1.0 2013-10
Microcontrollers
XMC4100 / XMC4200
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex™-M4
32-bit processor core
Edition 2013-10
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
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characteristics. With respect to any examples or hints given herein , any typical values stated herein and/or any
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For further information on technology, delivery terms and conditions and prices, please contact the nearest
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Infineon Technologies components may be used in life-support devices or systems only with the express written
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of that life-suppo rt device or system or to af fect the safety or effectiveness of that device or system. Life support
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be endangered.
Data Sheet
V1.0 2013-10
Microcontrollers
XMC4100 / XMC4200
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex™-M4
32-bit processor core
XMC4100 / XMC4200
XMC4000 Family
Data Sheet V1.0, 2013-10
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited.
Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace
Buffer™ are trademarks of ARM, Limited.
Synopsys™ is a trademark of Synopsys, Inc.
XMC4[12]00 Data Sheet
Revision History: V1.0 2013-10
Previous Versions:
V0.6 2012-11
Page Subjects
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Please send your proposal (including a reference to this document) to:
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Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Table of Contents
Data Sheet 5 V1.0, 2013-10
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Pin Configuration and Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2.1 Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.4 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.2 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.3 Digital to Analog Converters (DACx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.4 Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2.5 High Resolution PWM (HRPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2.5.1 HRC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2.5.2 CMP and 10-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.2.5.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.2.6 Low Power Analog Comparator (LPAC) . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2.7 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2.8 USB Device Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.9 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.10 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2.11 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.2 Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.4 Phase Locked Loop (PLL) Characteristi cs . . . . . . . . . . . . . . . . . . . . . . 71
Table of Contents
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Table of Contents
Data Sheet 6 V1.0, 2013-10
3.3.5 Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.7 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 76
3.3.8 Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 77
3.3.8.2 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.3.8.3 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.3.9 USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
About this Document
Data Sheet 7 V1.0, 2013-10
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of th e XMC4[12]00 series devices.
The document describes the characteristics of a superset of the XMC4[12]00 series
devices. For simplicity, the various device types are referred to by the collective term
XMC4[12]00 throughout this manual.
XMC4000 Family User Documentation
The set of user documentation includes:
•Reference Manu al
– decribes the functionality of the superset of devices.
•Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
•Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions
of those documents.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 8 V1.0, 2013-10
1 Summary of Features
The XMC4[12]00 devices are members of the XMC4000 Family of microcontrollers
based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high
performance and energy efficient microco ntrolle rs optimized for Industrial Connecti vity,
Industrial Control, Power Conversion, Sense & Control.
Figure 1 System Block Diagram
CPU Subsystem
•CPU Core
– High Performance 32-bit ARM Cortex-M4 CPU
– 16-bit and 32-bit Thumb2 instruction set
– DSP/MAC instructions
– System timer (SysTick) for Operating System support
• Floating Point Unit
• Memory Protection Unit
• Nested Vectored Interrupt Controller
• OneGeneral Purpose DMA with up-to 8 channels
• Event Request Unit (ERU) for programmable processing of external and internal
service requests
• Flexible CRC Engine (FCE) for multiple bit error detection
PMU
ROM & Flash
Bus Matri x
CPU
ARM®CortexTM-M4
DSRAM1PSRAM
FCE
GPDMA0 USB
Device
DCodeSystem ICode
Perip herals 0 Peripherals 1
PBA0
Data Code
WDT
RTC
ERU0
SCU
ERU1 VADC POSIF0 CCU40 CCU41
USIC0 CCU80 LEDTS0 PORTS DAC
USIC1 CAN
System
Masters System
Slaves
PBA1
HRPWM
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 9 V1.0, 2013-10
On-Chip Memories
• 16 KB on-chip boot ROM
• up to 16 KB on-chip high-speed program memory
• up to 24 KB on-chip high speed data memory
• up to 256 KB on-chip Flash Memory with 1 KB instruction cache
Communication Peripherals
• Universal Serial Bus, USB 2.0 device, with integrated PHY
• Controller Area Network i nterface (Mu lt iCAN), Ful l-CAN/Basic-CAN with two nodes,
64 message objects, data rate up to 1 MBit/s
• Four Universal Serial Interface Channels (USIC), providing four serial channels,
usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces
• LED and Touch-Sense Controller (LEDTS) fo r Human-Machine interface
Analog Frontend Periphera ls
• Two Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with
input out-of-range comparators
• Digital-Analog Converter (DAC) with two channels of 12-bit resolution
Industrial Control Peripherals
• Two Capture/Compare Units 4 (CCU4) for use as general purpose timers
• One Capture/Compare Units 8 (CCU8) for motor control and power conversion
• Four High Resoultion PWM (HRPWM) channels
• One Position Interface (POSIF) for servo motor positioning
• Window Watchdog Timer (WDT) for safety sensitive applications
• Die Temperature Sensor (DTS)
• Real Time Clock module with alarm support
• System Control Unit (SCU) for system configuration and control
Input/Output Li ne s
• Programmable port driver control module (PORTS)
• Individual bit addressability
• Tri-stated in input mode
• Push/pull or open drain output mode
• Boundary scan test support over JTAG interface
On-Chip Debug Suppo rt
• Full support for debug features: 8 breakpoints, CoreSight, trace
• Various interfaces: ARM-JTAG, SWD, single wire trace
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 10 V1.0, 2013-10
1.1 Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:
• <DDD> the derivatives function set
• <Z> the package variant
–E: LFBGA
–F: LQFP
–Q: VQFN
• <PPP> package pin count
• <T> the temperature range:
– F: -40°C to 85°C
– K: -40°C to 125°C
• <FFFF> the Fla sh me mo ry size.
For ordering codes for the XMC4[12]00 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC4100 and XMC4200 series,
some descriptions may not apply to a specific product. Please see Table 1.
For simplicity the term XMC4[12]00 is used for all derivatives throughout this document.
1.2 Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1 Synopsis of XMC4[12]00 Device Types
Derivative1)
1) x is a placeholder for the supportedtemperature range.
Package Flash
Kbytes SRAM
Kbytes
XMC4200-F64x256 PG-LQFP-64 256 40
XMC4200-Q48x256 PG-VQFN-48 256 40
XMC4100-F64x128 PG-LQFP-64 128 20
XMC4100-Q48x128 PG-VQFN-48 128 20
XMC4104-F64x64 PG-LQFP-64 64 20
XMC4104-Q48x64 PG-VQFN-48 64 20
XMC4104-F64x128 PG-LQFP-64 128 20
XMC4104-Q48x128 PG-VQFN-48 128 20
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 11 V1.0, 2013-10
1.3 Device Type Features
The following table lists the available features per device type.
1.4 Definition of Feature Variants
The XMC4[12]00 types are offered with seve ral memory sizes and nu mber of availabl e
VADC channels. Table 4 describes the location of the available Flash memory, Table 5
describes the location of the available SRAMs, Table 6 the available VADC channels.
Table 2 Features of XMC4[12]0 0 Device Types
Derivative1)
1) x is a placeholder for the supported temperature range.
LEDTS Intf. USB Intf. USIC Chan. MultiCAN
Nod./Msg.
XMC4200-F64x256 1 1 2 x 2 2 / 64
XMC4200-Q48x256 1 1 2 x 2 2 / 64
XMC4100-F64x128 1 1 2 x 2 2 / 64
XMC4100-Q48x128 1 1 2 x 2 2 / 64
XMC4104-F64x64 1 −2 x 2 −
XMC4104-Q48x64 1 −2 x 2 −
XMC4104-F64x128 1 −2 x 2 −
XMC4104-Q48x128 1 −2 x 2 −
Table 3 Features of XMC4[12]0 0 Device Types
Derivative1)
1) x is a placeholder for the supported temperature range.
ADC
Chan. DAC
Chan. CCU4
Slice CCU8
Slice POSIF
Intf. HRPWM
Intf.
XMC4200-F64x256 10 2 2 x 4 1 x 4 1 1
XMC4200-Q48x256 9 2 2 x 4 1 x 4 1 1
XMC4100-F64x128 10 2 2 x 4 1 x 4 1 1
XMC4100-Q48x128 9 2 2 x 4 1 x 4 1 1
XMC4104-F64x64 10 2 2 x 4 1 x 4 1 1
XMC4104-Q48x64 9 2 2 x 4 1 x 4 1 1
XMC4104-F64x128 10 2 2 x 4 1 x 4 1 1
XMC4104-Q48x128 9 2 2 x 4 1 x 4 1 1
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 12 V1.0, 2013-10
1.5 Identification Registers
The identificati on registers allow software to identify the marking.
Table 4 Flash Memory Ranges
Total Flash Size Cached Range Uncached Range
256 Kbytes 0800 0000H −
0803 FFFFH
0C00 0000H −
0C03 FFFFH
128 Kbytes 0800 0000H −
0801 FFFFH
0C00 0000H −
0C01 FFFFH
64 Kbytes 0800 0000H −
0800 FFFFH
0C00 0000H −
0C00 FFFFH
Table 5 SRAM Memory R anges
Total SRAM Size Program SRAM System Data SRAM
40 Kbytes 1FFF C000H −
1FFF FFFFH
2000 0000H −
2000 5FFFH
20 Kbytes 1FFF E000H −
1FFF FFFFH
2000 0000H −
2000 2FFFH
Table 6 AD Converter Channels1)
1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port
I/O Function tab l e.
Package VADC G0 VADC G1
PG-LQFP-64 CH0,
CH3..CH7 CH0, CH1, CH3, CH6
PG-VQFN-48 CH0,
CH3..CH7 CH0, CH1, CH3
Table 7 XMC4200 Identification Registers
Register Name Value Marking
SCU_IDCHIP 0004 2001HEES-AA, ES-AA
SCU_IDCHIP 0004 2002HES-AB, AB
JTAG IDCODE 101D D083HEES-AA, ES-AA
JTAG IDCODE 201D D083HES-AB, AB
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Data Sheet 13 V1.0, 2013-10
Table 8 XMC4100 Identification Registers
Register Name Value Marking
SCU_IDCHIP 0004 1001HEES-AA, ES-AA
SCU_IDCHIP 0004 2002HES-AB, AB
JTAG IDCODE 101D D083HEES-AA, ES-AA
JTAG IDCODE 201D D083HES-AB, AB
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 14 V1.0, 2013-10
2 General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1 Logic Symbols
Figure 2 XMC4[12]00 Logic Symbol PG-LQFP-64
Port 0
12 bit
Port 1
10 bit
Port 2
12 bit
VAGND
VSSA
(1)
VAREF
VDDA
(1) VDDP
(3)
JTAG
3 bit
TCK SWD
1 bit
VDDC
(2)
XTAL1
XTAL2
USB_DP
USB_DM
Port 14
9 bit
TMS
PORST
via Port Pins
RTC_XTAL1
RTC_XTAL2
HIB_IO_0
VBAT (1 )
(1) VSSO
Exp. Die Pad
(VSS)
VSS
(1)
Port 3
1 bit
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 15 V1.0, 2013-10
Figure 3 XMC4[12]00 Logic Symbol PG-VQFN-48
Port 0
9 bit
Port 1
6 bit
Port 2
6 bit
VAGND
VSSA
(1)
VAREF
VDDA
(1) VDDP
(3)
JTAG
3 bit
TCK SWD
1 bit
VDDC
(2)
XTAL1
XTAL2
USB_DP
USB_DM
Port 14
8 bit
TMS
PORST
via Port Pins
RTC_XTAL1
RTC_XTAL2
HIB_IO_0
VBAT (1 ) Exp. Die Pad
(VSS)
VSS
(1)
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 16 V1.0, 2013-10
2.2 Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
Figure 4 XMC4[12]00 PG-LQFP-64 Pin Configuration (top view)
2P0.0 1P0.1
64 P0.2
63 P0.3
62 P0.4
61 P0.5
60 P0.6
58 P0.7
57 P0.8
4P0.9 3P0.10
59 P0.11
52 P1.0
51 P1.1
50 P1.2
49 P1.3
48 P1.4
47 P1.5
55 P1.7
54 P1.8
53 P1.9
46 P1.15
34 P2.0
33 P2.1
32P2.2 31P2.3 30P2.4 29P2.5
36 P2.6
35 P2.7
28P2.8 27P2.9 26P2.14 25P2.15
5P3.0
20P14.0 19P14.3 18P14.4 17P14.5
16P14.6 15P14.7
24P14.8 23P14.9
14P14.14
10HIB_IO_0
43 PORST
11RTC_XTAL1 12RTC_XTAL2
45 TCK
44 TMS
6USB_DM 7USB_DP
13VBAT
22VDDA/VAREF
9VDDC
42 VDDC
8VDDP
38 VDDP
56 VDDP
37 VSS
21VSSA/VAGND
41 VSSO
39 XTAL1
40 XTAL2
XMC4[12]00
(Top View)
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 17 V1.0, 2013-10
Figure 5 XMC4[12]00 PG-VQFN-48 Pin Configuration (top view)
2
P0.0 1P0.1
48 P0.2
47 P0.3
46 P0.4
45 P0.5
44 P0.6
42 P0.7
41 P0.8
4
3
43
P1.0
P1.1
P1.2
P1.3
36 P1.4
35 P1.5
39
38
37
34
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
24
23
22
21
5
16P14.0 15P14.3 14P14.4 13P14.5
P14.6
P14.7
20P14.8 19P14.9
10
HIB_IO_0 31 PORST
11
RTC_XTAL1
12
RTC_XTAL2
33 TCK
32 TMS
6
USB_DM
7
USB_DP
VBAT
18VDDA/VAREF
9
VDDC 30 VDDC
8
VDDP
26
VDDP
40 VDDP
25
VSS
17VSSA/VAGND
29
27
XTAL1
28
XTAL2
XMC4[12]00
(Top View)
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 18 V1.0, 2013-10
2.2.1 Package Pin Summary
The following general scheme is used to describe each pin:
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the dedicated pins (i.e. PORST) and supply pins.
The following columns, title d with the supported package variants, lists the pa ckage pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type (A1, A1+, special=special pad,
In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about
the pad properties are defined in the Electrical Parameters.
In the “Notes”, special information to the res pective pin/fu nction is given, i.e. deviatio ns
from the default configuration after reset.
Table 9 Package Pin Mapping Description
Function Package A Package B ... Pad
Type Notes
Name N Ax ... A1+
Table 10 Package Pin Mapping
Function LQFP-64 VQFN-48 Pad Type Notes
P0.022A1+
P0.111A1+
P0.2 64 48 A1+
P0.3 63 47 A1+
P0.4 62 46 A1+
P0.5 61 45 A1+
P0.6 60 44 A1+
P0.7 58 43 A1+ After a system reset, via
HWSEL this pin selects the
DB.TDI function.
P0.8 57 42 A1+ After a system reset, via
HWSEL this pin selects the
DB.TRST function, with a
weak pull-down active.
P0.9 4 - A1+
P0.10 3 - A1+
P0.11 59 - A1+
P1.0 52 40 A1+
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 19 V1.0, 2013-10
P1.1 51 39 A1+
P1.2 50 38 A1+
P1.3 49 37 A1+
P1.4 48 36 A1+
P1.5 47 35 A1+
P1.7 55 - A1+
P1.8 54 - A1+
P1.9 53 - A1+
P1.15 46 - A1+
P2.0 34 26 A1+
P2.1 33 25 A1+ After a system reset, via
HWSEL this pin selects the
DB.TDO function.
P2.2 32 24 A1+
P2.3 31 23 A1+
P2.4 30 22 A1+
P2.5 29 21 A1+
P2.6 36 - A1+
P2.7 35 - A1+
P2.8 28 - A1+
P2.9 27 - A1+
P2.14 26 - A1+
P2.15 25 - A1+
P3.0 5 - A1+
P14.02016AN/DIG_IN
P14.31915AN/DIG_IN
P14.41814AN/DIG_IN
P14.51713AN/DIG_IN
P14.61612AN/DIG_IN
P14.71511AN/DIG_IN
P14.8 24 20 AN/DAC/DIG_I
N
P14.9 23 19 AN/DAC/DIG_I
N
Table 10 Package Pin Mapping (cont’d)
Function LQFP-64 VQFN-48 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 20 V1.0, 2013-10
P14.14 14 - AN/DIG_IN
USB_DP 7 4 special
USB_DM 6 3 special
HIB_IO_0 10 7 A1 special At the first power-up and with
every reset of the hibernate
domain this pin is configured
as open-drain output and
drives "0".
As output the medium driver
mode is active.
TCK 45 34 A1 Weak pull-down active.
TMS 44 33 A1+ Weak pull-up active.
As output the strong-soft
driver mode is active.
PORST 43 32 special Strong pull-down controlled
by EVR.
Weak pull-up active while
strong pull-down is not
active.
XTAL1 39 29 clock_IN
XTAL2 40 30 clock_O
RTC_XTAL1 11 8 clock_IN
RTC_XTAL2 12 9 clock_O
VBAT 13 10 Power When VDDP is supplied VBAT
has to be supplied as well.
VDDA/VAREF 22 18 AN_Power/AN
_Ref Shared analog supply and
reference voltage pin.
VSSA/VAGND 21 17 AN_Power/AN
_Ref Shared analog supply and
reference ground pin.
VDDC 9 6 Power
VDDC 42 31 Power
VDDP 8 5 Power
VDDP 38 28 Power
VDDP 56 41 Power
VSS 37 27 Power
Table 10 Package Pin Mapping (cont’d)
Function LQFP-64 VQFN-48 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 21 V1.0, 2013-10
VSSO 41 - Power
VSS Exp. Pad Exp. Pad Power Exposed Die Pad
The exposed die pad is
connected internally to VSS.
For proper operation, it is
mandatory to connect the
exposed pad to the board
ground.
For thermal aspects, please
refer to the Data Sheet.
Board layout examples are
given in an application note.
Table 10 Package Pin Mapping (cont’d)
Function LQFP-64 VQFN-48 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
General Device Information
Data Sheet 22 V1.0, 2013-10
2.2.2 Port I/O Functions
The following general scheme is used to describe each PORT pin:
Figure 6 Simp li fie d Port Structure
Pn.y is the port pin name , d efinin g the con t rol and data bi ts/registers associ ated with i t.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin,
selected by Pn_IOCR.PC. The output value is directly drive n by the respective module,
with the pin characteristics controlled by the port registers (within the limits of the
connected pad).
The port pin input can be connected to mult iple peripherals. Most peripherals have an
input multip lexer to select between differen t po ssi b le input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
By Pn_HWSEL it is possible to select between different hardware “masters”
(HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control
overrules settings in the respective port pin registers.
Table 11 Port I/O Functi on Description
Function Outputs Inputs
ALT1 ALTn HWO0 HWI0 Input Input
P0.0 MODA.OUT MODB.OUT MODB.INA MODC.INA
Pn.y MODA.OUT MODA.INA MODC.INB
XMC4000
Pn.y
VDDP
GND
Pn.y
ALT1
...
ALTn
HWO0
HWO1
SW
Control Logic
Input 0
Input n
... PAD
HWI0
HWI1
MODB.OUT
MODB
MODA
MODA.INA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Data Sheet 26 V1.0, 2013-10
2.3 Power Connection Scheme
Figure 7. shows a referen ce power connection scheme for the XMC4[12]00.
Figure 7 Power Connection Scheme
Every power supply pin needs to b e connected. Different pins of the same supp ly need
also to be externally connected. As example, all VDDP pins must be connected externally
to one VDDP net. In this reference scheme one 100 nF capacitor is connected at each
supply pin against VSS. An additional 10 µF capacitor is connected to the VDDP nets and
an additional 4.7uF capacitor to the VDDC nets.
VBAT
M x VDDC
N x VDDP
VSS
VDDA / VAREF
Hibernate domai n
RTC Hibernate
control
Retention
Memory
32 kHz
Clock
Core Domain
CPU
Dig.
Peripherals
Analog Domain
ADC DAC
GPIOs
Out-of-range comparator
PAD Domain
Level
shift.
FLASH
RAMs
100 nF x M
4.7 µF x 1
100 nF
3.3V
XMC4000
EVR
VSSA / VAGND
Exp. Die Pad
VSS
GND
GND
GND
GND
100 nF x N
10 µF x 1
3.3V
2.0...3.6 V
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Data Sheet 27 V1.0, 2013-10
The XMC4[12]00 has a common ground concept, all VSS, VSSA and VSSO pins share the
same ground potential. In packages with an exposed die pad it must be connected to the
common ground as well.
There are no dedicated connections for the analog reference VAREF and VAGND. Instead,
they share the same pins as the analog supply pins VDDA and VSSA.Some analog
channels can optionally serve as “Alternate Reference”; further details on this operating
mode are described in the Reference Manual.
When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g.
battery) is connected to VBAT, the VBAT pin can also be connected directly to VDDP.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 28 V1.0, 2013-10
3 Electrical Parameters
3.1 General Parameters
3.1.1 Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the
XMC4[12]00 and partly its requirements on the system. To aid interpreting the
parameters easily when evaluating them for a design, they are marked with an two-letter
abbreviation in column “Symbol”:
•CC
Such parameters indicate Controller Characte ristics, which are a distinctive feature
of the XMC4[12]00 and must be regarded for system design.
•SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC4[12]00 is designed in.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 29 V1.0, 2013-10
3.1.2 Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 13 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
Storage temperature TST SR -65 – 150 °C–
Junction temperature TJ SR -40 −150 °C –
Voltage at 3.3 V power supply
pins with respect to VSS
VDDP SR – – 4.3 V –
Voltage on any Class A and
dedicated input pin with
respect to VSS
VIN SR -1.0 – VDDP + 1.0
or max. 4.3 V whichever
is lower
Voltage on any analog input
pin with respect to VAGND
VAIN
VAREF SR -1.0 – VDDP + 1.0
or max. 4.3 V whichever
is lower
Input current on any pin
during overload condition IIN SR -10 – +10 mA
Absolute maximum sum of all
input circuit currents for one
port group during overload
condition1)
1) The port groups are defined in Table 17.
ΣIIN SR -25 – +25 mA
Absolute maximum sum of all
input circuit currents during
overload condition
ΣIIN SR -100 – +100 mA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 30 V1.0, 2013-10
Figure 8 explains the input voltage ranges of VIN and VAIN and its dependency to the
supply level of VDDP.The input voltage must not exceed 4.3 V, and it must not be more
than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the
overload conditions in Section 3.1.3.
Figure 8 Absolute Maximum Input Voltage Ranges
V
4.3
V
SS
-1.0
A
A
B
Abs. max. input voltage V
IN
with V
DDP
> 3.3 V
Abs. max. input voltage V
IN
with V
DDP
≤ 3.3 V
V
V
DDP
+ 1.0
V
SS
-1.0
V
DDP
B
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 31 V1.0, 2013-10
3.1.3 Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 14 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
• full operation life-time is not exceeded
•Operating Co nditions are met for
– pad supply levels (VDDP or VDDA)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
parameters, then the parameters functionality of this pin as stated in the Operating
Conditions can no longer be guaranteed. Operation is still possible in most cases but
with relaxed parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations li ke short to battery.
Figure 9 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Table 14 Overload Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin
during overload condition IOV SR -5 – 5 mA
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
1) The port groups are defined in Table 17.
IOVG SR – – 20 mA Σ|IOVx|, for all
IOVx <0mA
––20mAΣ|IOVx|, for all
IOVx >0mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR – – 80 mA ΣIOVG
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 32 V1.0, 2013-10
Figure 9 Input Overload Current via ESD structur es
Table 15 and Table 16 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as de fined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 15 PN-Junction Characteris itics for positive Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ=150°C
A1 / A1+ VIN =VDDP +1.0V VIN =VDDP +0.75V
AN/DIG_IN VIN =VDDP +1.0V VIN =VDDP +0.75V
Table 16 PN-Junction Characterisiti cs for negative Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ=150°C
A1 / A1+ VIN =VSS -1.0V VIN =VSS -0.75V
AN/DIG_IN VIN =VDDP -1.0V VIN =VDDP -0.75V
Table 17 Port Groups for Overl oad and Short-Circuit Curren t Sum
Parameters
Group Pins
1 P0.[12:0], P3.0
2 P14.[8:0]
3 P2.[15:0]
4 P1.[15:0]
Pn.y IOVx
GND
ESD Pad
GND
VDDP
VDDP
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 33 V1.0, 2013-10
3.1.4 Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 3.2.1.
Figure 10 Output Slopes with different Pad Driver Modes
Figure 10 is a qualitative display of the resulting output slope performance with
different output driver modes. The detailed input and output characteristics are listed in
Section 3.2.1.
Table 18 Pad Driver and Pad Classes Overview
Class Power
Supply Type Sub-Class Speed
Grade Load Termination
A3.3 V LVTTL
I/O,
LVTTL
outputs
A1
(e.g. GPIO) 6 MHz 100 pF No
A1+
(e.g. serial I/Os) 25 MHz 50 pF Series termination
recommended
V
VDDP
VSS
VOH
VOL
t
CDEF
C
D
E
F
Output High Voltage
Output Low Voltage
Weak drive strength
Medium drive strength
Stro ng – sl ow dri v e stre ngt h
Strong – soft drive strength
C D E F Class A1+ Pads
E F Class A1 Pads
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 34 V1.0, 2013-10
3.1.5 Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC4[12]00. All parameters specified in the following
tables refer to these operating conditions, unless noted otherwise.
Table 19 Operating Conditions Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Ambient Temperature TA SR -40 −85 °C Temp. Range F
-40 −125 °C Temp. Range K
Digital supply voltage VDDP SR 3.131)
1) See also the Supply Monitoring thresholds, Section 3.3.2.
3.3 3.632)
2) Voltage overshoot to 4.0 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h over lifetime.
V
Core Supply Voltage VDDC
CC −1) 1.3 −V Generated
internally
Digital ground voltage VSS SR 0 −−V
ADC analog supply
voltage VDDA SR 3.0 3.3 3.62) V
Analog ground voltage for
VDDA
VSSA SR -0.1 0 0.1 V
Battery Supply Voltage for
Hibernate Domain3)
3) Different limits apply for LPAC operation, Section 3.2.6
VBAT SR 1.95 −3.63 V When VDDP is
supplied VBAT
has to be
supplied as
well.
System Frequency fSYS SR −−80 MHz
Short circuit current of
digital outputs ISC SR -5 −5mA
Absolute sum of short
circuit currents per pin
group4)
4) The port groups are defined in Table 17.
ΣISC_PG
SR −−20 mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
SR −−100 mA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 35 V1.0, 2013-10
3.2 DC Parameters
3.2.1 Input/Output Pins
The digital input stage of the shared analog/digital input pins is identical to the input
stage of the standard digital input/o utput pins.
Table 20 Standard Pad Parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Max.
Pin capacitance (digital
inputs/outputs) CIO CC −10 pF
Pull-down current |IPDL|
CC 150 −μA1)VIN ≥0.6 × VDDP
1) Current required to override the pull device with the opposite logic level (“force current ”).
With active pull device, at load currents between force and keep current the input state is undefined.
−10 μA2)VIN ≤0.36 × VDDP
2) Load current at which the pull device still maintains th e va lid logic level (“keep current”).
With active pull device, at load currents between force and keep current the input state is undefined.
Pull-Up current |IPUH|
CC −10 μA2)VIN ≥0.6 × VDDP
100 −μA1)VIN ≤0.36 × VDDP
Input Hysteresis for
pads of all A classes3)
3) Hysteresis is implemented to avoid metastable stat es and swit ch ing due to int ernal g roun d bo unce. I t can n ot
be guaranteed that it suppresses switch ing due to external system noise.
HYSA
CC 0.1 ×
VDDP
−V
PORST spike filter
always blocked pulse
duration
tSF1 CC −10 ns
PORST spike filter
pass-through pulse
duration
tSF2 CC 100 −ns
PORST pull-down
current |IPPD|
CC 13 −mA Vi=1.0 V
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 36 V1.0, 2013-10
Figure 1 1 Pull Device Input Characteristics
Figure 11 visualizes the input characteristics with an active internal pull device:
• in the cases “A” the internal pull device is overridden by a strong external driver;
• in the cases “B” the internal pull device defines the input logical state against a weak
external load.
XMC4000 IN
I
PDL
AI
PDL
≥150 μA
BI
PDL
≤10 μA
V
DDP
GND
V
V
DDP
V
SS
0.6 x V
DDP
A
0.36 x V
DDP
B
Va lid High
Va lid Low
Inva lid di gi tal i nput
XMC4000
IN
I
PUH
AI
PUH
≥ 100 μA
BI
PUH
≤10 μA
V
V
DDP
V
SS
0.6 x V
DDP
B
0.36 x V
DDP
A
Va lid High
Va lid Low
Inva lid di gi tal i nput
Pull -down active
Pull-up active
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 37 V1.0, 2013-10
Table 21 Standard Pads Class_A1
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZA1 CC -500 500 nA 0 V ≤VIN ≤VDDP
Input high voltage VIHA1 SR 0.6 × VDDP VDDP + 0.3 V max . 3.6 V
Input low voltage VILA1 SR -0.3 0.36 × VDDP V
Output high voltage,
POD1) = weak VOHA1
CC VDDP - 0.4 −VIOH ≥-400 μA
2.4 −VIOH ≥-500 μA
Output high voltage,
POD1) = medium VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output low voltage VOLA1
CC −0.4 V IOL ≤500 μA;
POD1) = weak
−0.4 V IOL ≤2mA;
POD1) = medium
Fall time tFA1 CC −150 ns CL=20pF;
POD1) = weak
1) POD = Pin Out Driver
−50 ns CL=50pF;
POD1) = medium
Rise time tRA1 CC −150 ns CL=20pF;
POD1) = weak
−50 ns CL=50pF;
POD1) = medium
Table 22 Standard Pads Class_A1 +
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZA1+ CC -1 1 μA0V≤VIN ≤VDDP
Input high voltage VIHA1+ SR 0.6 × VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA1+ SR -0.3 0.36 × VDDP V
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 38 V1.0, 2013-10
Output high voltage,
POD1) = weak VOHA1+
CC VDDP - 0.4 −VIOH ≥-400 μA
2.4 −VIOH ≥-500 μA
Output high voltage,
POD1) = medium VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output high voltage,
POD1) = strong VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output low voltage VOLA1+
CC −0.4 V IOL ≤500 μA;
POD1) = weak
−0.4 V IOL ≤2mA;
POD1) = medium
−0.4 V IOL ≤2mA;
POD1) = strong
Fall time tFA1+ CC −150 ns CL=20pF;
POD1) = weak
−50 ns CL=50pF;
POD1) = medium
−28 ns CL=50pF;
POD1) = strong;
edge = slow
−16 ns CL=50pF;
POD1) = strong;
edge = soft;
Rise time tRA1+ CC −150 ns CL=20pF;
POD1) = weak
−50 ns CL=50pF;
POD1) = medium
−28 ns CL=50pF;
POD1) = strong;
edge = slow
−16 ns CL=50pF;
POD1) = strong;
edge = soft
1) POD = Pin Out Driver
Table 22 Standard Pads Class_A1 + (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 39 V1.0, 2013-10
Table 23 HIB_IO Class_A1 special Pads
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZHIB
CC -500 500 nA 0 V ≤VIN ≤VBAT
Input high voltage VIHHIB
SR 0.6 × VBAT VBAT + 0.3 V max. 3. 6 V
Input low voltage VILHIB
SR -0.3 0.36 × VBAT V
Input Hysteresis for
HIB_IO pins1)
1) Hysteresis is implemente d to avoi d meta st able stat es and switchin g due to interna l gro und bounce. It can not
be guaranteed that it suppresses switch ing due to external system noise.
HYSHIB
CC 0.1 × VBAT −VVBAT ≥3.13 V
0.06 ×
VBAT
−VVBAT <3.13 V
Output high voltage,
POD1) = medium VOHHIB
CC VBAT - 0.4 −VIOH ≥-1.4 mA
Output low voltage VOLHIB
CC −0.4 V IOL ≤2mA
Fall time tFHIB CC −50 ns VBAT ≥3.13 V
CL=50pF
−100 ns VBAT <3.13 V
CL=50pF
Rise time tRHIB CC −50 ns VBAT ≥3.13 V
CL=50pF
−100 ns VBAT <3.13 V
CL=50pF
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 40 V1.0, 2013-10
3.2.2 Analog to Digital Converters (ADCx)
Table 24 ADC Parameters (Operating Condition s ap ply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Analog reference voltage VAREF
SR −−−VVAREF =VDDA
shared analog
supply and
reference input
pin
Alternate reference
voltage5) VAREF
SR VAGND
+ 1 −VDDA +
0.051) V
Analog reference ground VAGND
SR −−−VVAGND =VSSA
shared analog
supply and
reference input
pin
Alternate reference
voltage range2)5) VAREF -
VAGND
SR
1−VDDA +
0.1 V
Analog input voltage VAIN SR VAGND −VDDA V
Input leakage at analog
inputs3) IOZ1 CC -100 −200 nA 0.03 × VDDA <
VAIN <0.97 × VDDA
-500 −100 nA 0 V ≤VAIN ≤ 0.03
× VDDA
-100 −500 nA 0.97 × VDDA
≤VAIN ≤VDDA
Internal ADC clock fADCI CC 2 −30 MHz VDDA = 3.3 V
Switched capacitance at
the analog voltage inputs4) CAINSW
CC −720 pF
Total capacitan ce of an
analog input CAINTOT
CC −25 30 pF
Switched capacitance at
the alternate reference
voltage input5)6)
CAREFSW
CC −15 30 pF
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 41 V1.0, 2013-10
Total capacitan ce of the
alternate reference
inputs5)
CAREFTOT
CC −20 40 pF
Total Unadjusted Error TUE CC -6 −6 LSB 12-bit resolu tion;
VDDA = 3.3 V;
VAREF = VDDA7)
Differential Non-Linearity
Error8) EADNL
CC -4.5 −4.5 LSB
Gain Error8) EAGAIN
CC -6 −6LSB
Integral Non-Linearity8) EAINLCC -4.5 −4.5 LSB
Offset Error8) EAOFF
CC -6 −6LSB
Worst case ADC VDDA
power supply current per
active converter
IDDAA
CC −1.5 2 mA during conversion
VDDP =3.6V,
TJ= 150 oC
Charge consumption on
alternate reference per
conversion5)
QCONV
CC −30 −pC 0 V ≤VAREF
≤VDDA9)
ON resistance of the
analog input path RAIN CC −700 1 700 Ohm
ON resistance for the ADC
test (pull down for AIN7) RAIN7T
CC 180 550 900 Ohm
1) A running conversion may become imprecise in case the no rmal conditions are violated (voltage overshoot).
2) If the analog refer ence voltage is below VDDA, then the ADC converter e rrors increase. If the referen ce voltage
is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offse t errors increase also by the factor 1/k.
3) The leakage current defin ition i s a contin uous functi on , as shown in figure ADCx Analog Input s Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation -
they do not define step funct i on (see Figure 14).
4) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements, the volt age measured at AINx can deviate from VAREF/2.
5) Applies to AINx, when used as alternate reference input.
6) This represents an equivalent switched capacitance. This capacitance is not switched to the re ference voltage
at once. Instead, smaller capacitances are successively switched to th e reference voltage.
7) For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16.
Never less than ±1 LSB.
8) The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unad justed error TUE.
Table 24 ADC Parameters (Operating Condition s apply) (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 42 V1.0, 2013-10
Figure 1 2 VADC Reference Voltage Range
9) The resulting current for a conversion ca n be calculated with IAREF =QCONV /tc.
The fastest 12-bit post-calibrated conversion of tc= 566 ns results in a typical average current of
IAREF =53µA.
Minimum VAREF - VAGND is 1 V
V
VDDA + 0.05
VAGND + 1
VAGND
Valid VAREF
VDDA
e.g. VAREF = 4/5 of VDDA
Conversion error
increases by 5/4
Precise co nversion range ( 12 bit)
t
VAREF
VSSA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 43 V1.0, 2013-10
The power-up calibration of the ADC requires a maximum number of 4 352 fADCI cycles.
Figure 13 ADCx Input Circuits
Figure 14 ADCx Analog Input Leakage Current
Reference Voltage Input Circuitry
Analog Input Circuitry
Analog_InpRefDiag
REXT
=
VAIN CEXT
RAIN, On
CAINTOT - CAINSW
CAINSW
ANx
VAREF
RAREF, On
CAREFTOT - CAREFSW CAREFSW
VAGNDx
VAREFx
RAIN7T
VAGNDx
ADC-Leakage.vsd
V
IN
[% V
DDA
]
200 nA
500 nA
3% 100%97%
I
OZ1
100 nA
-500 nA
-100 nA
Singl e AD C Input
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 44 V1.0, 2013-10
Conversion Time
• STC defines additional clock cycles to extend the sample time
• PC adds two cycles if post-calibration is enabled
• DM adds one cycle for an extended conversion time of the MSB
Conversion Time Examples
System assumptions (max. fADC):
fADC = 80 MHz i.e. tADC = 12.5 ns, DIVA = 2, fADCI = 26.7 MHz i.e. tADCI = 37.5 ns
According to the given formulas the following minimum conversion times can be
achieved (STC = 0, DM = 0):
12-bit post-calibrated conversion (PC = 2):
tCN12C = (2 + 12 + 2) × tADCI + 2 × tADC = 16 × 37.5 ns + 2 × 12.5 ns = 625 ns
12-bit uncalibrated conversion:
tCN12 = (2 + 12) × tADCI + 2 × tADC = 14 × 37.5 ns + 2 × 12.5 ns = 550 ns
10-bit uncalibrated conversion:
tCN10 = (2 + 10) × tADCI + 2 × tADC = 12 × 37.5 ns + 2 × 12.5 ns = 475 ns
8-bit uncalib rated:
tCN8 = (2 + 8) × tADCI + 2 × tADC = 10 × 37.5 ns + 2 × 12.5 ns = 400 ns
System assumptions (max. fADCI):
fADC = 60 MHz i.e. tADC = 16.67 ns, DIVA = 1, fADCI = 30 MHz i.e. tADCI = 33.33 ns
12-bit post-calibrated conversion (PC = 2):
tCN12C = (2 + 12 + 2) × tADCI + 2 × tADC = 16 × 33.33 ns + 2 × 16.67 ns = 566 ns
Table 25 Conversion Time (Operating Conditions apply)
Parameter Symbol Values Unit Note
Conversion
time tCCC 2 ×TADC +
(2+N+STC+PC+DM)× TADCI
μs N = 8, 10, 12 for
N-bit conversion
TADC =1/fPERIPH
TADCI =1/fADCI
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 45 V1.0, 2013-10
3.2.3 Digital to Analog Converters (DACx)
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 26 DAC Parameters (Operating Condition s ap ply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
RMS supply current IDD CC −2.5 4 mA per active DAC
channel,
without load
currents of DAC
outputs
Resolution RES CC −12 −Bit
Update rate fURATE_ACC −2 Msam
ple/s data rate, where
DAC can follow
64 LSB code jumps
to ± 1LSB accuracy
Update rate fURATE_F CC −5 Msam
ple/s data rate, where
DAC can follow
64 LSB code jumps
to ± 4 LSB accuracy
Settling time tSETTLE CC −12 μs at full scale jump,
output voltage
reaches target
value ± 20 LSB
Slew rate SR CC 2 5 −V/μs
Minimum output
voltage VOUT_MIN
CC −0.3 −V code value
unsigned: 000H;
signed: 800H
Maximum output
voltage VOUT_MAX
CC −2.5 −V code value
unsigned: FFFH;
signed: 7FFH
Integral non-
linearity1) INL CC -5.5 ±2.5 5.5 LSB RL ≥ 5kOhm,
CL ≤ 50 pF
Differential non-
linearity DNL CC -2 ±1 2 LSB RL ≥ 5kOhm,
CL ≤ 50 pF
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 46 V1.0, 2013-10
Conversion Calculation
Unsigned:
DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN)
Signed:
DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) - 2048
Offset error EDOFF CC ±20 mV
Gain error EDG_IN CC -5 0 5 %
Startup time tSTARTUP CC −15 30 μs time from output
enabling till code
valid ±16 LSB
3dB Bandwidth of
Output Buffer fC1 CC 2.5 5 −MHz verified by design
Output sourcing
current IOUT_SOURCE
CC −-30 −mA
Output sinking
current IOUT_SINK
CC −0.6 −mA
Output resistance ROUT CC −50 −Ohm
Load resistance RL SR 5 −− kOhm
Load capacitance CL SR −−50 pF
Signal-to-Noise
Ratio SNR CC −70 −dB examination
bandwidth < 25 kHz
Total Harmonic
Distortion THD CC −70 −dB examination
bandwidth < 25 kHz
Power Supply
Rejection Ratio PSRR CC −56 −dB to VDDA
verified by desig n
1) According to best straight line method.
Table 26 DAC Parameters (Operating Condition s apply) (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 47 V1.0, 2013-10
Figure 1 5 DAC Conversion Examples
DAC output
VOUT_MIN
VOUT_MAX
64 LSBs
+/- 4LSB
fURATE_F (max)
64 LSBs
+/- 1LSB
fURATE_A (max)
DAC output
VOUT_MIN
VOUT_MAX 20 LSBs
tSETTLE
20 LSB s
tSETTLE
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 48 V1.0, 2013-10
3.2.4 Out-of-Range Comparator (ORC)
The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the
analog reference1) (VAREF) on selected input pins (GxORCy) and generates a service
request trigger (GxORCOUTy).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The parameters in Table 27 apply for the maximum reference voltage
VAREF =VDDA +50mV.
1) Always the standard VA DC ref erence, alternate references do not apply to the ORC.
Table 27 ORC Parameters (Operating Conditio ns apply)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
DC Switching Level VODC CC 100 125 200 mV VAIN ≥ VAREF + VODC
Hysteresis VOHYS CC 50 −VODC mV
Detection Delay of a
persistent
Overvoltage
tODD CC 55 −450 ns VAIN ≥ VAREF + 200 mV
45 −105 ns VAIN ≥ VAREF + 400 mV
Always detected
Overvoltage Pulse tOPDD CC 440 −− ns VAIN ≥ VAREF + 200 mV
90 −− ns VAIN ≥ VAREF + 400 mV
Never detected
Overvoltage Pulse tOPDN CC −−49 ns VAIN ≥ VAREF + 200 mV
−−30 ns VAIN ≥ VAREF + 400 mV
Release Delay tORD CC 65 −105 ns VAIN ≤ VAREF
Enable Delay tOED CC −100 200 ns
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 49 V1.0, 2013-10
Figure 16 GxORCOUTy Trigger Generation
Figure 17 ORC Detection Ranges
VSS
VAREF
tORD
VODC
VOHYS
tODD
GxORCOUTy
GxORCy
VAIN (V)
VAREF + 400 mV
t
VAREF + 200 mV
Overvoltage
may be
detected
(level uncertain)
Never
detected
Overvoltage
Pulse
(Too short)
T < tOPDN tOPDN < T < tOPDD
Overvoltage
may be
detected
T > tOPDD
Always detected
Overvoltage Pulse
T < tOPDN
Never
detected
Overvoltage
Pulse
(Too short)
tOPDN < T < tOPDD T > tOPDD
Always detected
Overvoltage Pulse
VAREF + 100 mV
Overvoltage
may be
detected
T > tOPDN
Never
detected
Overvoltage
Pulse
(To o low)
VAREF
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 50 V1.0, 2013-10
3.2.5 High Resolution PWM (HRPWM)
The following chapters describe the operating conditions, characteristics and timing
requirements, for all the components inside the HRPWM module. Each description is
given for just one sub unit, e.g., one CSG or one HRC.
All the timing information is related to the module clock, fhrpwm.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.2.5.1 HRC characteristics
Table 28 summarizes the characteristics of the HRC units.
3.2.5.2 CMP and 10-bit DAC characteristics
The Table 29 summarizes the characteristics of the CSG unit.
The specified characteristics require that the setup of the HRPWM follows the
initialization sequence as docume nted in the Reference Manual.
Table 28 HRC characteristics (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
High resolution step
size1)2)
1) The step size for clock frequencies equal to 180, 120 and 80 MHz is 150 ps.
2) The step size for clock frequencies different from 180, 120 and 80 MHz but within the range from 180 to 64
MHz can be between 118 to 180 ps (fixed over process and operating conditions)
tHRS CC – 150 – ps
Startup time (after reset
release) tstart CC – – 2 μs
Table 29 CMP an d 10-bit DAC chara cteristics (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DAC Resolution RES
CC 10 bits
DAC differential
nonlinearity DNL
CC -1 – 1.5 LSB Monotonic
behavior,
See Figure 18
DAC integral nonlinearity INL CC -3 – 3 LSB See Figure 18
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 51 V1.0, 2013-10
CSG Output Jitter DCSG
CC ––1clk
Bias startup time tstart CC – – 98 us
Bias supply current IDDbias
CC ––400μA
CSGy startup time tCSGS
CC ––2μs
Input operation current1) IDDCIN
CC -10 – 33 μASee Figure 19
High Speed Mode
DAC output voltage range VDOUT
CC VSS –VDDP V
DAC propagation delay -
Full scale tFShs
CC – – 80 ns See Figure 20
Input Selector propagation
delay - Full scale tDhs CC – – 100 ns See Figure 20
Comparator bandwidth tDhs CC 20 – – ns
DAC CLK frequency fclk SR – – 30 MHz
Supply current IDDhs
CC ––940μA
Low Speed Mode
DAC output voltage range VDOUT
CC 0.1 ×
VDDP2) –VDDP V
DAC propagation delay -
Full Scale tFSls CC – – 160 ns See Figure 20
Input Selector propagation
delay - Full Scale tDls CC – – 200 ns See Figure 20
Comparator bandwidth tDls CC 20 – – ns
DAC CLK frequency fclk SR – – 30 MHz
Supply current IDDls
CC ––300μA
1) Typical input resistance RCIN = 100kOhm.
2) The INL error increases for DAC output voltages below this limit.
Table 29 CMP an d 10-bit DAC chara cteristics (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 52 V1.0, 2013-10
Figure 18 CSG DAC INL and DNL example
Figure 19 Input operation current
Output
DAC
code
FS
INL
Best Fit Straight Line
Output
DAC
code
FS
Idea l DAC
DNL=1.5LSBs
DNL= -0.5LSBs
DAC Curve
INL
DNL= -1LSB
CMP Input Selector
CSGy
+
-
CMP
DAC
HRPWMx.CyINA
HRPWMx.CyINB Control
logic
HRPWMx.CyINA/
HRPWMx.CyINB IDDcin
CMP Input
Selector
Rcin
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 53 V1.0, 2013-10
Figure 20 DAC and Input Selector Propagation Delay
3.2.5.3 Clocks
HRPWM DAC Conversion Clock
The DAC conversion clock can be generated internally or it can be controlled via a
HRPWM module pin.
CSG External Clock
It is possible to select an external source, that can be used as a clock for the slope
generation, HRPWMx.ECLKy. This clock is synchronized internally with the module
clock and therefore the external clock needs to meet the criterion described on Table 31.
Table 30 External DAC conversion trigger operating conditions
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
Frequency fetrg SR – – 302) MHz
ON time tonetrg SR 2Tccu1)2)
1) 50% duty cycle is not obligatory
2) Only valid if the signal was n ot previously synchronized/generated wit h the fccu clock (or a synchronous clock)
–– ns
OFF time toffetrg SR 2Tccu1)2) –– ns
0x000
FS
tfshs/tsishs
t
tfshs/tsishs
CSGy
CMP Input
Selector
0 V
3.3 V
CSGy
+
-
CMP
DAC
0x000
FS
tsishs
tfshs
Output
+
-
CMP
DAC
1LSB
1LSB
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 54 V1.0, 2013-10
3.2.6 Low Power Analog Comparator (LPAC)
The Low Power Analog Comparator (LPAC) triggers a wake-up event from Hibernate
state or an interrupt trigger during normal operation. It does so by comparing VBAT or
another external sensor voltage VLPS with a pre-programmed th reshold voltage.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 31 External clock operating conditions
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
Frequency feclk SR – – fhrpwm/4 MHz
ON time toneclk SR 2Tccu1)2)
1) Only valid if the signal was no t previously synchronized/generat ed with the fccu clock (or a synchron ous clock)
2) 50% duty cycle is not obligatory
–– ns
OFF time toffeclk SR 2Tccu1)2) – – ns Only the
rising
edge is
used
Table 32 Low Power Analog Comp arator Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
VBAT supply voltage range for
LPAC operation VBAT SR 2.1 −3.6 V
Sensor voltage range VLPCS
CC 0−1.2 V
Threshold step size Vth CC −18.75 −mV
Threshold trigger accuracy
Δ
Vth CC −−±10 % for Vth >0.4V
Conversion time tLPCC CC −−250 μs
Average current consumption
over time ILPCAC
CC −−15 μA for a conversion
interval of
10 ms
Current consumption during
conversion ILPCC CC −150 −μA
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 55 V1.0, 2013-10
3.2.7 Die Temperature Sensor
The Die Temperature Sensor (DTS) measures the junction temperature TJ.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
Temperature TDTS = (RESULT - 605) / 2.05 [°C]
This formula and the values defined in Table 33 apply with the following calibration
values:
• DTSCON.BGTRIM = 8H
• DTSCON.REFTRIM = 4H
Table 33 Die Temperature Sensor Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Temperature sensor range TSR SR -40 −150 °C
Linearity Error
(to the below d efined formula)
Δ
TLE CC −±1 −°C per
Δ
TJ≤30 °C
Offset Error
Δ
TOE CC −±6 −°C
Δ
TOE = TJ - TDTS
VDDP ≤3.3 V1)
1) At VDDP_max = 3.63 V the typical offset error increases by an additional
Δ
TOE =±1°C.
Measurement time tMCC −−100 μs
Start-up time after reset
inactive tTSST SR −−10 μs
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 56 V1.0, 2013-10
3.2.8 USB Device Interface DC Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification.
High-Speed Mode is not supported .
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 34 USB Device Data Line (USB_DP, USB_DM) Parameters (Operating
Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input low voltage VIL SR −−0.8 V
Input high voltage
(driven) VIH SR 2.0 −− V
Input high voltage
(floating) 1)
1) Measured at A-connector with 1. 5 kOhm ± 5% to 3. 3 V ± 0.3 V connected to USB_DP or USB_DM and at B-
connector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM.
VIHZ SR 2.7 −3.6 V
Differential input
sensitivity VDIS CC 0.2 −− V
Differential common
mode range VCM CC 0.8 −2.5 V
Output low voltage VOL CC 0.0 −0.3 V 1.5 kOhm pull-
up to 3.6 V
Output high voltage VOH CC 2.8 −3.6 V 15 kOhm pull-
down to 0 V
DP pull-up resistor (idle
bus) RPUI CC 900 −1 575 Ohm
DM pull-up resistor
(upstream port
receiving)
RPUA CC 1 425 −3 090 Ohm
Input impedance DP,
DM ZINP CC 300 −− kOhm 0 V ≤ VIN ≤ VDDP
Driver output resistance
DP, DM ZDRV CC 28 −44 Ohm
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 57 V1.0, 2013-10
3.2.9 Oscillator Pins
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The oscillator pins can be operated with an external crystal (see Figure 21) or in direct
input mode (see Figure 22).
Figure 21 Oscillator in Crystal Mode
XTAL1
XTAL2
f
OSC
Damping resistor
may be needed for
some crystals
V
PPX
V
PPX_min
≤V
PPX
≤V
PPX_max
t
V
V
PPX_min
t
OSCS
GND
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 58 V1.0, 2013-10
Figure 22 Oscillator in Direct Input Mode
V
VIHBX_max
VSS
t
Input High Voltage
Input Low Voltage
Input High Voltage
XTAL1
XTAL2
not connected
External Clock
Source
Direct Input Mode
VIHBX_min
VILBX_max
VILBX_min
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 59 V1.0, 2013-10
Table 35 OSC_XTAL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input frequency fOSC SR 4 −40 MHz Direct Input Mode
selected
4−25 MHz External Crystal
Mode selected
Oscillator start-up
time1)2)
1) tOSCS is defined from the moment the oscillator is enable d wih SCU_OSCHPCTRL.MODE until the oscillations
reach an amplitude at XTAL1 of 0.4 * VDDP.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
tOSCS
CC −−10 ms
Input voltage at XTAL1 VIX SR -0.5 −VDDP +
0.5 V
Input amplitude (peak-
to-peak) at XTAL12)3)
3) If the shaper unit is enabled and not bypassed.
VPPX SR 0.4 ×
VDDP
−VDDP +
1.0 V
Input high voltage at
XTAL14)
4) If the shaper unit is bypassed, dedicated DC-th resholds have to be met.
VIHBXSR 1.0 −VDDP +
0.5 V
Input low voltage at
XTAL14) VILBX SR -0.5 −0.4 V
Input leakage current at
XTAL1 IILX1 CC -100 −100 nA Oscillator power
down
0V ≤ VIX ≤VDDP
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 60 V1.0, 2013-10
Table 36 RTC_XTAL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input frequency fOSC SR −32.768 −kHz
Oscillator start-up
time1)2)3)
1) tOSCS is defined from the moment the o scillator is enabled by the user with SCU_OSCULCTRL.MODE until the
oscillations reach an amplitude at RTC_XTAL1 of 0.2 * VBAT.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) For a reliable start of the oscillation in crystal mode it is required that VBAT ≥3.0 V. A running oscillation is
maintained across the full VBAT voltage range.
tOSCS
CC −−5s
Input voltage at
RTC_XTAL1 VIX SR -0.3 −VBAT +
0.3 V
Input amplitude (peak-
to-peak) at
RTC_XTAL12)4)
4) If the shaper unit is enabled and not bypassed.
VPPX CC 0.2 ×
VBAT
−VBAT +
0.6 V
Input high voltage at
RTC_XTAL15)
5) If the shaper unit is bypassed, dedicated DC-th resholds have to be met.
VIHBXSR 0.6 ×
VBAT
−VBAT +
0.3 V
Input low voltage at
RTC_XTAL15) VILBX SR -0.3 −0.36 ×
VBAT
V
Input Hysteresis for
RTC_XTAL15)6)
6) Hysteresis is implemente d to avoid metastab le state s and switching due to in te rnal ground bo unce. It can n ot
be guaranteed that it suppresses switch ing due to external system noise.
VHYSX
CC 0.1 ×
VBAT
−V3.0V ≤
VBAT <3.6V
0.03 ×
VBAT
−VVBAT <3.0V
Input leakage current at
RTC_XTAL1 IILX1 CC -100 −100 nA Oscillator power
down
0V ≤ VIX ≤VBAT
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 61 V1.0, 2013-10
3.2.10 Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lowe r than those given in the followi ng tables,
and depend on the custo mer's system operat ing condi tions (e.g . thermal connecti on or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
If not stated otherwise, the operating conditions for the parameters in the following table
are:
VDDP = 3.3 V, TA = 25 oC
Table 37 Power Supply Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Active supply current1)
Peripherals enabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPA CC −80 −mA 80 / 80 / 80
−75 −80 / 40 / 40
−73 −40 / 40 / 80
−59 −24 / 24 / 24
−50 −1/1/1
Active supply current
Code execution from RAM
Flash in Sleep mode
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPA CC −24 −mA 80 / 80 / 80
−19 −80 / 40 / 40
Active supply current2)
Peripherals disabled
Frequency:
fCPU / fPERIPH in MHz
IDDPA CC −63 −mA 80 / 80 / 80
−62 −80 / 40 / 40
−60 −40 / 40 / 80
−54 −24 / 24 / 24
−50 −1/1/1
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 62 V1.0, 2013-10
Sleep supply current3)
Peripherals enabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPS CC −76 −mA 80 / 80 / 80
−73 −80 / 40 / 40
−70 −40 / 40 / 80
−56 −24 / 24 / 24
−47 −1/1/1
fCPU / fPERIPH / fCCU in kHz −46 −100 / 100 / 100
Sleep supply current4)
Peripherals disabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPS CC −59 −mA 80 / 80 / 80
−58 −80 / 40 / 40
−57 −40 / 40 / 80
−51 −24 / 24 / 24
−46 −1/1/1
fCPU / fPERIPH / fCCU in kHz −46 −100 / 100 / 100
Deep Sleep supply
current5)
Flash in Sleep mode
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPD CC −6.9 −mA 24 / 24 / 24
−4.3 −4/4/4
−3.8 −1/1/1
fCPU / fPERIPH / fCCU in kHz −4.5 −100 / 100 / 100
6)
Hibernate supply current
RTC on7) IDDPH CC −10.8 −μAVBAT =3.3V
−8.0 −VBAT =2.4V
−6.8 −VBAT =2.0V
Hibernate supply current
RTC off8) IDDPH CC −10.3 −μAVBAT =3.3V
−7.5 −VBAT =2.4V
−6.3 −VBAT =2.0V
Worst case active supply
current9) IDDPA CC −−140
10) mA VDDP =3.6V,
TJ=150oC
VDDA power supply current IDDA CC −−−
11) mA
IDDP current at PORST Lo w IDDP_PORST
CC −−24 mA VDDP =3.6V,
TJ=150oC
Table 37 Power Supply Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 63 V1.0, 2013-10
Power Dissipation PDISS CC −−1WVDDP =3.6V,
TJ=150oC
Wake-up time from Sleep to
Active mode tSSA CC −6−cycles
Wake-up time from Deep
Sleep to Active mode −−−ms Defined by the
wake-up of the
Flash module,
see
Section 3.2.11
Wake-up time from
Hibernate mode −−−ms Wake-up via
power-on reset
event, see
Section 3.3.2
1) CPU executing code from Flash, all peripherals idle.
2) CPU executing code from Flash. USB and CCU clock off.
3) CPU in sleep, all peripherals idle, Flash in Active mode.
4) CPU in sleep, Flash in Active mode.
5) CPU in sleep, peripherals disabled, after wake-up code execution from RAM.
6) To wake-up the Flash from its Sleep mode, fCPU ≥ 1 MHz is required.
7) OSC_ULP operating with external crystal on RTC_XTAL
8) OSC_ULP off, Hibernate domain operating with OSC_SI clock
9) Test Power Loop: fSYS = 80 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer mode,
all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in 500kHz
internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE, DTS
measurements and FPU calculations.
The power consumption of each customer applicatio n will most probably be lower than this value, but must be
evaluated separately.
10) IDDP decreases typically by 3.5 mA when fSYS decreases by 10 MHz, at constant TJ
11) Sum of currents of all active converters (ADC and DAC)
Table 37 Power Supply Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 64 V1.0, 2013-10
Peripheral Idle Currents
Test conditions:
•fsys and derived clocks at 80 MHz
•VDDP =3.3V, Ta=25 °C
• all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit
of the SCU)
• the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control
Unit of the SCU
• no I/O activity
• the given values are a result of differential measurements with asserted and
deasserted peripheral reset and enabled clock of the peripheral under test
The tested peripheral is left in the state after the peripheral reset is deasserted, no further
initialisation or configuration is done. E.g. no timer is running in the CCUs, no
communication active in the USICs, etc.
Table 38 Peripheral Idle Currents
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
PORTS
USB
FCE
WDT
POSIFx
IPER CC −≤0.3 −mA
MultiCAN
ERU
LEDTSCU0
CCU4x
CCU8x
−≤1.0 −
DAC (digital)1)
1) The current consumption of the analog components are given in the dedicated Data Sheet sections of the
respective peripher al.
−1.3 −
USICx −3.0 −
VADC (digital)1) −4.5 −
DMAx −6.0 −
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 65 V1.0, 2013-10
3.2.11 Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 39 Flash Memory Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Erase Time per 256
Kbyte Sector tERP CC −55.5s
Erase Time per 64 Kbyte
Sector tERP CC −1.2 1.4 s
Erase Time per 16 Kbyte
Logical Sector tERP CC −0.3 0.4 s
Program time per page1)
1) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes an additional time of 5.5 ms.
tPRP CC −5.5 11 ms
Erase suspend delay tFL_ErSusp
CC −−15 ms
Wait time after margin
change tFL_Margin
Del CC 10 −−μs
Wake-up time tWU CC −−270 μs
Read access time ta CC 20 −−ns For operation
with 1 / fCPU < ta
wait states must
be configured2)
2) The following formula applies to the wait sta te configuration: FCON.WSPFLASH × (1 / fCPU) ≥ ta.
Data Retention Time,
Physical Sector3)4)
3) Storage and inactive time included.
tRET CC 20 −−years Max. 1000
erase/program
cycles
Data Retention Time,
Logical Sector3)4) tRETL CC 20 −−years Max. 100
erase/program
cycles
Data Retention Time,
User Configuration Block
(UCB)3)4)
tRTU CC 20 −−years Max. 4
erase/program
cycles per UCB
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 66 V1.0, 2013-10
4) Values given are valid for an average weighted junction temperature of TJ = 110°C. Further lifetime
dependency values are give in the Quality Declarations.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 67 V1.0, 2013-10
3.3 AC Parameters
3.3.1 Testing Waveforms
Figure 2 3 Rise/Fall Time Parameter s
Figure 24 Testing Waveform, Output Delay
Figure 25 Testing Waveform, Output High Impedance
AC_Rise-Fall-Times.vsd
10%
90%
V
SS
V
DDP
t
R
t
F
10%
90%
AC_TestPoints.vsd
V
DDP
/ 2 V
DDP
/ 2
V
DDP
V
SS
Test Points
AC_HighImp.vsd
V
LOAD
+ 0.1 V Tim ing
Reference
Points
V
LOAD
-0.1V
V
OH
-0.1V
V
OL
+ 0.1V
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 68 V1.0, 2013-10
3.3.2 Power-Up and Supply Monitoring
PORST is always asserted when VDDP and/or VDDC violate the respective thresholds.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 26 PORST Circuit
Table 40 Supply Monitoring Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Digital supply voltage reset
threshold VPOR CC 2.791)
1) Minimum threshold for reset assertion.
−3.052) V3)
Core supply voltage reset
threshold VPV CC −−1.17 V
VDDP voltage to ensure
defined pad states VDDPPA
CC −1.0 −V
PORST rise time tPR SR −−2μs
Startup time from power-on
reset with code execution
from Flash
tSSW CC −2.5 3.5 ms Time to the first
user code
instruction
VDDC ramp up time tVCR CC −550 −μs Ramp up after
power-on or
after a reset
triggered by a
violation of
VPOR or VPV
VDDP
PORST
GND
PORESET
VDDP
GND
XMC4000
RPORST
(optional)
External
reset
trigger Supply
Monitoring
IPPD
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 69 V1.0, 2013-10
Figure 27 Power-Up Behavior
3.3.3 Power Sequencing
While starting up and shutting down as well as when switching power modes of the
system it is important to limit the current load steps. A typical cause for such load steps
is changing the CPU frequency fCPU. Load steps exceeding the below defined values
may cause a power on reset triggered by the supply monitor.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
2) Maximum threshold for reset deassertion.
3) The VDDP monitoring has a typical hysteresis of VPORHYS =180mV.
as pr ogr am m ed
V
POR
V
PV
V
DDP
V
DDC
Pads
PORST
V
DDPPA
Undefined H igh-i mpedance or p ul l -device active
3.3 V
1.3 V
t
SSW
t
VCR
t
PR
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 70 V1.0, 2013-10
Positive Load Step Examples
System assumptions:
fCPU = fSYS, target frequency fCPU = 80 MHz, main PLL fVCO = 480 MHz, stepping done by
K2 divider, tPLSS between individual steps:
24 MHz - 48 MHz - 80 MHz (K2 steps 20 - 10 - 6)
24 MHz - 60 MHz - 80 MHz (K2 steps 20 - 8 - 6)
Table 41 Power Sequencing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Positive Load Step Current
Δ
IPLS SR - −50 mA Load increase
on VDDP
Δ
t ≤ 10 ns
Negative Load Step
Current
Δ
INLS SR - −150 mA Load decrease
on VDDP
Δ
t ≤ 10 ns
VDDC Voltage Over-
/ Und ershoot from Load
Step
Δ
VLS CC - −±100 mV For maximum
positive or
negative load
step
Positive Load Step Settling
Time tPLSS SR 50 −-μs
Negative Load Step
Settling Time tNLSS SR 100 −-μs
External Buffer Capacitor
on VDDC
CEXT SR 3 4.7 6 μF In addition
C= 100 nF
capacitor on
each VDDC pin
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 71 V1.0, 2013-10
3.3.4 Phase Locked Loop (PLL) Characteris tics
Main and USB PLL
Table 42 PLL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Accumulated Jitter DP CC −−±5 ns accumulated
over 300 cycles
fSYS =80MHz
Duty Cycle1)
1) 50% for even K2 divider values, 50±(10/ K2) for odd K2 divider values.
DDC CC 46 50 54 % Low pul se to
total period,
assuming an
ideal input clock
source
PLL base frequency fPLLBASE
CC 30 −140 MHz
VCO input frequency fREF CC 4 −16 MHz
VCO frequency range fVCO CC 260 −520 MHz
PLL lock-in time tL CC −−400 μs
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 72 V1.0, 2013-10
3.3.5 Internal Clock Source Characteristics
Fast Internal Clock Source
Table 43 Fast Internal Clock Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Nominal frequency fOFINC
CC −36.5 −MHz not calibrated
−24 −MHz calibrated
Accuracy
Δ
fOFI
CC -0.5 −0.5 % automatic
calibration1)2)
1) Error in addition to the accuracy of the reference clock.
2) Automatic calibration compensates variations of the temperature and in t he VDDP supply voltage.
-15 −15 % factory
calibration,
VDDP =3.3V
-25 −25 % no calibration,
VDDP =3.3V
-7 −7 % Variation over
voltage range3)
3.13 V ≤VDDP ≤
3.63 V
3) Deviations from the nominal VDDP voltage induce an additional error to the uncalibrated and/or factory
calibrated oscillator frequency.
Start-up time tOFIS CC −50 −μs
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 73 V1.0, 2013-10
Slow Internal Clock Source
Table 44 Slow Internal Clock Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Nominal frequency fOSI CC −32.768 −kHz
Accuracy
Δ
fOSI
CC -4 −4%VBAT = const.
0°C≤TA≤
85 °C
-5 −5%
VBAT = const.
TA<0°C or
TA>85 °C
-5 −5%2.4V≤VBAT,
TA=25°C
-10 −10 % 1.95 V ≤
VBAT <2.4V,
TA=25°C
Start-up time tOSIS CC −50 −μs
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 74 V1.0, 2013-10
3.3.6 JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditio ns ap p l y.
Table 45 JTAG Interface Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCK clock period t1SR 30 – – ns For CL=20pF
on TDO
TCK clock period t1SR 40 – – ns For CL=50pF
on TDO
TCK high time t2SR 10 – – ns
TCK low time t3SR 10 – – ns
TCK clock rise time t4SR––4ns
TCK clock fall time t5SR––4ns
TDI/TMS setup
to TCK rising edge t6SR6––ns
TDI/TMS hold
after TCK rising edge t7SR6––ns
TDO valid after TCK falling
edge1) (propagation delay)
1) The falling edge on TCK is used to generate the TDO timing.
t8CC––17nsC
L=50pF
3––nsC
L=20pF
TDO hold after TCK falling
edge1) t18 CC2––ns
TDO high imped. to valid
from TCK falli n g ed g e1)2)
2) The setup time for TDO is given implicitly by the TCK cycle time.
t9CC––14nsC
L=50pF
TDO valid to high imped.
from TCK falli n g ed g e1) t10 CC – – 13.5 ns CL=50pF
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 75 V1.0, 2013-10
Figure 28 Test Clock Timing (TCK)
Figure 29 JTAG Timing
JTAG_TCK.vsd
0.9
VDDP
0.5
VDDP
TCK
t
1
t
2
0.1
VDDP
t
3
t
5
t
4
JTAG_IO.vsd
t
6
t
7
t
6
t
7
t
9
t
8
t
10
TCK
TMS
TDI
TDO t
18
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 76 V1.0, 2013-10
3.3.7 Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditio ns ap p l y.
Figure 30 SWD Timing
Table 46 SWD Interface Timing Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SWDCLK clock period tSC SR 25 – – ns CL=30pF
40 – – ns CL=50pF
SWDCLK high time t1 SR 10 – 500000 ns
SWDCLK low time t2 SR 10 – 500000 ns
SWDIO input setup
to SWDCLK rising edge t3 SR 6 – – ns
SWDIO input hold
after SWDCLK rising edge t4 SR 6 – – ns
SWDIO output valid time
after SWDCLK rising edge t5 CC – – 17 ns CL=50pF
– – 13 ns CL=30pF
SWDIO output hold time
from SWDCLK rising edge t6 CC 3 – – ns
SWDCLK
SWDIO
(Output)
t1t2
t6
t5
tSC
SWDIO
(Input)
t3t4
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 77 V1.0, 2013-10
3.3.8 Peripheral Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditio ns ap p l y.
3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 47 USIC SSC Master Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SCLKOUT master clock
period tCLK CC 40 −− ns
Slave select output SELO
active to first SCLKOUT
transmit edg e
t1 CC tSYS -
6.51)
1) tSYS = 1 / fPB
−− ns
Slave select output SELO
inactive afte r last
SCLKOUT receive edge
t2 CC tSYS -
8.51) −− ns
Data output DOUT[3:0]
valid time t3 CC -6 −8ns
Receive data input
DX0/DX[5:3] setup time to
SCLKOUT receive edge
t4 SR 23 −− ns
Data input DX0/DX[5:3]
hold time from SCLKOU T
receive edg e
t5 SR 1 −− ns
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 78 V1.0, 2013-10
Table 48 USIC SSC Slave Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DX1 slave clock period tCLK SR 66.6 −− ns
Select input DX2 setup to
first clock input DX1 transmit
edge1)
1) These input timing are valid for asyn chronou s input sign al handling of slave select inpu t, sh ift cl ock input, and
receive data input (bits DXnCR.DSEN = 0).
t10 SR 3 −− ns
Select input DX2 hold after
last clock input DX1 receive
edge1)
t11 SR 4 −− ns
Receive data input
DX0/DX[5:3] setup time to
shift clock receive edge1)
t12 SR 6 −− ns
Data input DX0/DX[5:3] hold
time from clock input DX1
receive edg e1)
t13 SR 4 −− ns
Data output DOUT[3:0] valid
time t14 CC 0 −24 ns
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 79 V1.0, 2013-10
Figure 3 1 USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
t
2
t
1
USIC_SSC_TMGX.VSD
Clock O utput
SCLKOUT
Data Output
DOUT[3:0]
t
3
t
3
t
5
Data
valid
t
4
First Transmit
Edge
Data Input
DX0/DX[5:3]
Sel ect Ou tput
SELOx
Active
Master Mode Ti m ing
S l ave Mode Tim i ng
t
11
t
10
Clock I nput
DX1
Data Output
DOUT[3:0]
t
14
t
14
Data
valid
Data Input
DX0/DX[5:3]
Select Input
DX2
Active
t
13
t
12
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, rec e ive data at recei ve data input is latc h ed.
Receive
Edge Last Receive
Edge
InactiveInactive
Trans mit
Edge
InactiveInactive
Firs t Transm it
Edge Receive
Edge Transm it
Edge Last Receive
Edge
t
5
Data
valid
t
4
Data
valid
t
12
t
13
Drawn for BRGH.SCLK CFG = 00B. Also val id for for SCLKCFG = 01B wi th inverted SCLKOUT s ignal.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 80 V1.0, 2013-10
3.3.8.2 Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 49 USIC IIC Standard Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open -drain mode. The high level on th ese lines must be held by an extern al pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL t1
CC/SR --300ns
Rise time of both SDA and
SCL t2
CC/SR - - 1000 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 250 - - ns
LOW period of SCL clock t5
CC/SR 4.7 - - µs
HIGH period of SCL clock t6
CC/SR 4.0 - - µs
Hold time for (repeated)
START condition t7
CC/SR 4.0 - - µs
Set-up time for repeated
START condition t8
CC/SR 4.7 - - µs
Set-up time for STOP
condition t9
CC/SR 4.0 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 4.7 - - µs
Capacitive load for each
bus line Cb SR - - 400 pF
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 81 V1.0, 2013-10
Table 50 USIC IIC Fast Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open -drain mode. The high level on th ese lines must be held by an extern al pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL t1
CC/SR 20 +
0.1*Cb
2)
2) Cb refers to the total capacitance of one bus line in pF.
- 300 ns
Rise time of both SDA and
SCL t2
CC/SR 20 +
0.1*Cb
2)
- 300 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 100 - - ns
LOW period of SCL clock t5
CC/SR 1.3 - - µs
HIGH period of SCL clock t6
CC/SR 0.6 - - µs
Hold time for (repeated)
START condition t7
CC/SR 0.6 - - µs
Set-up time for repeated
START condition t8
CC/SR 0.6 - - µs
Set-up time for STOP
condition t9
CC/SR 0.6 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 1.3 - - µs
Capacitive load for each
bus line Cb SR - - 400 pF
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 82 V1.0, 2013-10
Figure 32 USIC IIC Stand and Fast Mode Timin g
3.3.8.3 Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 51 USIC IIS Ma ster Transmi tte r Tim ing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t1 CC 33.3 −−ns
Clock high time t2 CC 0.35 x
t1min
−−ns
Clock low time t3 CC 0.35 x
t1min
−−ns
Hold time t4 CC 0 −−ns
Clock rise time t5 CC −−0.15 x
t1min
ns
SCL
SDA
SCL
SDA
t
1
t
2
t
1
t
2
t
10
t
9
t
7
t
8
t
7
t
3
t
4
t
5
t
6
PSSr
S
70%
30%
9
th
clock
9
th
clock
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 83 V1.0, 2013-10
Figure 33 USIC IIS Ma ster Transmi tte r Tim ing
Figure 34 USIC IIS Slave Receiver Timing
Table 52 USIC IIS Slave Receiver Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t6 SR 66.6 −−ns
Clock high time t7 SR 0.35 x
t6min
−−ns
Clock low time t8 SR 0. 35 x
t6min
−−ns
Set-up time t9 SR 0.2 x
t6min
−−ns
Hold time t10 SR 0 −−ns
SCK
WA/
DOUT
t
1
t
5
t
3
t
2
t
4
SCK
WA/
DIN
t
6
t
10
t
8
t
7
t
9
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Data Sheet 84 V1.0, 2013-10
3.3.9 USB Interface Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification.
High-Speed Mode is not supported .
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 35 USB Signal Timing
Table 53 USB Timing Parameters (operating cond itions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Rise time tRCC 4 – 20 ns CL=50pF
Fall time tFCC 4 – 20 ns CL=50pF
Rise/Fall time matching tR/tFCC 90 – 111.11 % CL=50pF
Crossover voltage VCRS CC 1.3 – 2.0 V CL=50pF
USB_Rise-Fall-Times.vsd
10%
90%
D-
D+
t
R
t
F
10%
90%
V
CRS
V
SS
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Package and Reliability
Data Sheet 85 V1.0, 2013-10
4 Package and Reliability
The XMC4[12]00 is a member of the XMC4000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Die Pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1 Package Parameters
Table 54 provides th e thermal characteristics of the packages used in XMC4[12]00.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSS, independent of EMC and thermal requirements.
4.1.1 Thermal Considerations
When operating the XMC4[12]00 in a system, the total heat generated in the chip must
be dissipated to the ambient environment to prevent overheating and the resulting
thermal damage.
The maximum heat that can be dissipated depend s on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
Table 54 Thermal Characteristics of the Packages
Parameter Symbol Limit Values Unit Package Types
Min. Max.
Exposed Die Pad
Dimensions Ex × Ey
CC -5.8×5.8 mm PG-LQFP-64-19
-5.2×5.2 mm PG-VQFN-48-53
Thermal resistance
Junction-Ambient RΘJA
CC - 30 K/W PG-LQFP-64-191)
- 34.8 K/W PG-VQFN-48-531)
1) Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; expo sed pad soldered.
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Package and Reliability
Data Sheet 86 V1.0, 2013-10
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
• Reduce VDDP, if possible in the system
• Reduce the system frequency
• Reduce the number of output pins
• Reduce the load on active output drivers
4.2 Package Outl ines
Figure 36 PG-LQFP-64-19 (Plastic Green Low Profile Quad Flat Package)
D
12
H
0.2 A-B D4x
A-B0.2 64x
D
B
12
1
64 64
1
Index Marking Index Marking
0.5
7.5
+0.07
0.2
-0.03
PG-LQFP-64-6, -8, -12, -22-PO V13
0.08
M
A-B D
CCOPLANARITYSEATING
PLANE
C
0.08
±0.05
0.1
STAND OFF
±0.05
1.4
1.6 MAX.
±0.15
0.6
H
A
-0.06
+0.05
0.15
0˚...7˚
64x
64x
C
10
0.5 x 45˚
1)
10
1)
1) Does not include plastic or metal protrusion of 0.25 max. per side
Bottom View
Exposed Diepad
Ox
Oy
Ex
Ey
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Package and Reliability
Data Sheet 87 V1.0, 2013-10
Figure 37 PG-VQFN-48-53 (Plastic Green Very Thin Profile Flat Non Leaded
Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
0.9 MAX.
SEATING PLANE
Index Marking
+0.03
0.4 x 45˚
(0.65)
Index Marking
1312
2425
48
1
(5.2)
37
36
7
±0.1
A
6.8
6.8
48x0.08
(0.2)
0.05 MAX.
C
7
±0.1
B
11 x 0.5 = 5.5
0.5
0.5
11 x 0.5 = 5.5
0.4
±0.07
(6.2)
(6.2)
(5.2)
0.23
0.26
0.15
M
±0.05
±0.03
48x0.1 A B C
PG-VQFN-48-15, -19, -20, -22, -24, -48, -51, -52, -53, -54, -55, -56, -57-PO V12
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Quality Declarations
Data Sheet 88 V1.0, 2013-10
5 Quality Declarations
The qualification of the XMC4[12]00 is executed according to the JEDEC standard
JESD47H.
Note: For automotive applications refer to the Infineon automotive microcontrol lers.
Table 55 Quality Parameters
Parameter Sy mbol Values Unit Note /
Test Condition
Min. Typ. Max.
Operation lifetime tOP CC 20 −− aTJ ≤ 109°C,
device permanent
on
ESD susceptibility
according to Human Body
Model (HBM)
VHBM
SR −−2 000 V EIA/JESD22-
A114-B
ESD susceptibility
according to Charged
Device Model (CDM)
VCDM
SR −−500 V Conforming to
JESD22-C101-C
Moisture sensitivity level MSL
CC −−3−JEDEC
J-STD-020C
Subject to Agreement on the Use of Product Information
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Published by Infineon Technologies AG