AT89C51-12LM/883 - Atmel Corporation

8-Bit

Microcontroller

with 4 Kbytes

Flash

AT89C51

Features

•Compatible with MCS-51 Products

•4 Kbytes of In-System Reprogrammable Flas h Me mory

Endura nc e: 1, 00 0 Write/Erase Cycle s

•Full y Stati c Ope ration: 0 Hz to 24 MHz

•Three -Le ve l Prog ram Memory Lock

•128 x 8-Bit Inte rnal RAM

•32 Programmable I/O Lines

•Two 16-Bit Timer/Counters

•Six Interrupt Sources

•Program ma bl e Seri al Channel

•Low Power Id le and Power Down Modes

P1.0 V

P1.1 P0.0 (AD0)

P1.2

()P3.2INT0

ALE/PROG

()P3.7RD P2.3 (A11)

(TXD) P3.1

EA/VPP

()P3.6WR P2.4 (A12)

(RXD) P3.0 P0.7 (AD7)

(T1) P3.5 P2.6 (A14)

RST P0.6 (AD6)

P1.7 P0.5 (AD5)

P1.6 P0.4 (AD4)

P1.5 P0.3 (AD3)

P1.4 P0.2 (AD2)

P1.3 P0.1 (AD1)

()P3.3INT1

PSEN

XTAL2 P2.2 (A10)

(T0) P3.4 P2.7 (A15)

XTAL1 P2.1 (A9)

GND P2.0 (A8)

P2.5 (A13)

Pin Configurations PDIP/Cerdip

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4

Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The

device is manufactured using Atmel’s high density nonvolatile memory technology

and is compatible with the industry standard MCS-51 instruction set and pinout.

The on-chip Flash allows the progr am memory to be repr ogrammed in-system or by

a conventional nonvolatile memory pr ogrammer. By combining a vers atile 8-bit CPU

with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer

which provides a highly flex ible and cost effective solution to many embedded control

applications.

(continued)

INDEX

CORNER

P1.0

VCC

P1.1

P1.2

P1.4

P1.3

43 40

18192021

P1.7

P1.6

P1.5

NC 7

121314151617

3837

3635 33

PSEN

XTAL1

GND

XTAL2

GND

P0.0 (AD0)

ALE/PROG

()P3.7RD

EA/VPP

()P3.6WR

(RXD) P3.0 P0.7 (AD7)

P2.6 (A14)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P0.2 (AD2)

P0.1 (AD1)

()P3.2INT0

(TXD) P3.1

(T1) P3.5

()P3.3INT1

(T0) P3.4 P2.7 (A15)

(A11) P2.3

(A12) P2.4

(A10) P2.2

(A9) P2.1

(A8) P2.0

RST

P2.5 (A13)

PQFP/TQFP

P1.0

VCC

P1.1

P0.0 (AD0)

P1.2

ALE/PROG

()P3.7RD

XTAL1

EA/VPP

()P3.6WR

GND

(RXD) P3.0 P0.7 (AD7)

P2.6 (A14)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P1.4

P0.2 (AD2)

P1.3

P0.1 (AD1)

PSEN

XTAL2

()P3.2INT0

(TXD) P3.1

(T1) P3.5

()P3.3INT1

(T0) P3.4 P2.7 (A15)

(A11) P2.3

(A12) P2.4

(A10) P2.2

(A9) P2.1

(A8) P2.0

RST

P1.7

P1.6

P1.5

INDEX

CORNER

P2.5 (A13)

34 NC

43 40

65444

25 28

20 24

17 29

PLCC/LCC

0265E

PORT 2 DRIVERS

PORT 2

LATCH

P2.0 - P2.7

FLASH

PORT 0

LATCH

RAM

PROGRAM

ADDRESS

BUFFER

INCREMENTER

PROGRAM

COUNTER

DPTR

RAM ADDR.

INSTRUCTION

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

STACK

POINTER

ACC

TMP2 TMP1

ALU

PSW

TIMING

AND

CONTROL

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

OSC

GND

PSEN

ALE/PROG

EA / V

RST

PORT 0 DRIVERS

P0.0 - P0.7

Block Diagra m

2AT89C51

Pin Desc ription

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an

output port each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-im-

pedance inputs.

Port 0 may also be configured to be the multiplexed low-

order address/data bus during accesses to external pro-

gram and data memory. In this mode P0 has internal pul-

lups.

Port 0 also receives the code bytes during F lash program-

ming, and outputs the code bytes during program ver ifica-

tion. External pullups are required during program verifica-

tion.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs .

When 1s are written to Port 1 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during

Flash programming and program verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs .

When 1s are written to Port 2 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX

The AT89C51 provides the following standard features : 4

Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16- bit

timer/counters, a five vector two-level interrupt architec-

ture, a full duplex serial port, on-chip oscillator and clock

circuitry. In addition, the AT89C51 is designed with static

logic for operation down to zero frequency and supports

two software selectable power saving modes. The Idle

Mode stops the CPU while allowing the RAM, timer/count-

ers, serial port and interrupt system to continue function-

ing. The Power Down Mode sa ves the RAM contents but

freezes the oscillator disabling all other chip functions until

the next hardware reset.

Description (Continued) @ DPTR). In this application it us es strong internal pullups

when emitting 1s. During accesses to external data mem-

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits

the contents of the P2 Special Function Register.

Port 2 also receives the high- order addres s bits and some

control signals during Flash programming and verific ation.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs .

When 1s are written to Port 3 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

current (IIL) because of the pullups.

Port 3 also serves the functions of various special features

of the AT89C51 as listed below:

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (extenal interrupt 0)

P3.3 INT1 (extenal interrupt 1)

P3.4 T0 (timer 0 extenal input)

P3.5 T1 (timer 1 external input)

P3.6 WR (extenal data memory write strobe)

P3.7 RD (external data memory read strobe)

Port 3 also receives some control signals for Flash pro-

gramming and programming verification.

RST

Reset input. A high on this pin for two machine cycles

while the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low

byte of the address during accesses to external memory.

This pin is also the program pulse input (PROG) during

Flash programming.

In normal operation ALE is emitted at a constant rate of

1/6 the oscillator frequency, and may be used for exter nal

timing or clocking purposes. Note, however , that one ALE

pulse is skipped during each access to external Data

Memory.

If desired, ALE operation can be disabled by setting bit 0

of SFR location 8EH. With the bit set, ALE is active only

during a MOVX or MOVC instruc tion. Otherwise, the pin is

weakly pulled high. Setting the A LE-disable bit has no ef-

fect if the microcrontroller is in external execution mode.

PSEN

Program Store Enable is the read s trobe to external pro-

gram memory.

(continued)

AT89C51

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier which can be configured for use

as an on-chip oscillator, as shown in Figure 1. Either a

quartz crystal or ceramic res onator may be used. To driv e

the device from an external clock source, XTAL2 should

be left unconnected while XTAL1 is driven as shown in

Figure 2. There are no requirements on the duty cycle of

the external clock signal, since the input to the internal

clocking circuitry is through a divide-by-two flip-flop, but

minimum and maximum voltage high and low time specifi-

cations must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on- chip RAM and all the spe-

cial functions registers remain unchanged during this

Figure 2. External Clock Drive Configuration

C2 XTAL2

GND

XTAL1

Figure 1. Oscillator Connections

Notes: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Cera mi c Res on ators

Status of Exte rnal Pins During Idle and P owe r Down

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power Down Internal 0 0 Data Data Data Data

Power Down External 0 0 Float Data Data Data

When the AT89C51 is executing code from external pro-

gram memory, PSEN is activated twice each machine cy-

cle, except that two PSEN activations are skipped during

each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from exter nal pro-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is pr ogrammed, EA will be

internally latched on reset.

EA should be strapped to VCC for internal program execu-

tions.

This pin also receives the 12-volt programming enable

voltage (VPP) during Flas h progr amming, for parts that re-

quire 12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Pin Desc ription (Continued) mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

It should be noted that when idle is terminated by a hard-

ware reset, the device normally resumes program execu-

tion, from where it left off, up to two machine cycles before

the internal reset algorithm takes control. On-chip hard-

4AT89C51

ware inhibits access to internal RAM in this event, but ac-

cess to the port pins is not inhibited. To eliminate the pos-

sibility of an unexpected write to a port pin when Idle is

terminated by reset, the instruction following the one that

invokes Idle should not be one that writes to a port pin or

to external memory.

Power Down Mode

In the power down mode the os cillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardwar e reset.

Reset redefines the SFRs but does not change the on-

chip RAM. The reset should not be activated before VCC

is restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and

stabilize.

Progra m Me mory Lock Bits

On the chip are three lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the ad-

ditional features listed in the table below:

When lock bit 1 is programmed, the logic level at the EA

pin is sampled and latched during reset. If the device is

powered up without a reset, the latch initializes to a ran-

dom value, and holds that value until reset is activated. It

is necessary that the latched value of EA be in agreement

with the current logic level at that pin in order for the device

to function properly.

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash

memory array in the erased state (that is, contents = FFH)

and ready to be programmed. The programming interfac e

accepts either a high-voltage (12-volt) or a low-voltage

(VCC) program enable signal. The low voltage program-

ming mode provides a convenient way to program the

AT89C51 inside the user’s system, while the high-voltage

programming mode is compatible with conventional third

party Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or

low-voltage programming mode enabled. The respective

top-side marking and device signature codes are listed in

the following table.

VPP = 12 V VPP = 5 V

Top-Side Mark AT89C51 AT89C51

xxxx xxxx-5

yyww yyww

Signature (030H)=1EH (030H)=1EH

(031H)=51H (031H)=51H

(032H)=FFH (032H)=05H

The AT89C51 code memory array is programmed byte-

by-byte in either programming mode.

To program any

non-blank byte in the on-chip Flash Memory, the entire

memory must be erased using the Chip Erase Mode.

Programming Algorithm: Before programming the

AT89C51, the address, data and control signals should be

set up according to the Flash programming mode table

and Figures 3 and 4. To program the AT89C51, take the

following steps.

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12 V for the high-voltage program-

ming mode.

5. Pulse ALE/PROG once to program a byte in the Flash

array or the lock bits. The byte-write cycle is self-timed and

typically takes no more than 1.5 ms. Repeat steps 1

through 5, changing the address and data for the entire

array or until the end of the object file is reached.

Data Polling: The AT89C51 features Data Polling to indi-

cate the end of a write cycle. During a write cycle, an at-

(

continued

)

Lock Bit P r ote ction Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features.

2PUU

MOVC instructions executed from external program memory are disabled from

fetching code bytes from internal memory, EA is sampled and latched on reset, and

further programming of the Flash is disabled.

3 P P U Same as mode 2, also verify is disabled.

4 P P P Same as mode 3, also external execution is disabled.

AT89C51

tempted read of the last byte written will result in the com-

plement of the written datum on PO.7. Once the write cy-

cle has been completed, true data are valid on all outputs,

and the next cycle may begin. Data Polling may begin any

time after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can

also be monitored by the RDY/BSY output signal. P3.4 is

pulled low after ALE goes high during programming to in-

dicate BUSY. P3.4 is pulled high again when program-

ming is done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read

back via the address and data lines for verification. The

lock bits cannot be verified directly. Verification of the lock

bits is achieved by observing that their features are en-

abled.

Chip Erase: The entire Flash array is erased electrically

by using the proper combination of control signals and by

holding ALE/PROG low for 10 ms. The code array is writ-

ten with all “1"s. The chip erase operation must be exe-

cuted before the code memory can be re-programmed.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 030H,

031H, and 032H, except that P3.6 and P3.7 must be

pulled to a logic low. The values returned are as follows.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 51H indicates 89C51

(032H) = FFH indicates 12 V programming

(032H) = 05H indicates 5 V programming

Progra mming Interfa ce

Every code byte in the Flash array can be written and the

entire array can be erased by using the appropriate com-

bination of control signals. The write operation cycle is

self-timed and once initiated, will automatically time itself

to completion.

All major programming vendors offer worldwide support

for the Atmel microcontroller series. Please contact your

local programming vendor for the appropr iate software re-

vision.

Flash Pr ogr a mm i ng Modes

Mode RST PSEN ALE/ EA/

VPP P2.6 P2.7 P3.6 P3.7

PROG

Write Code Data H L H/12V(1) LHHH

Read Code Data H L H H L L H H

Write Lock Bit - 1 H L H/12V H H H H

Bit - 2 H L H/12V H H L L

Bit - 3 H L H/12V H L H L

Chip Erase H L H/12V H L L L

Read Signature

Byte H L H H L L L L

Notes: 1. The signature byte at location 032H designates

whether VPP = 12 V or VPP = 5 V should be used to

enabl e pro gramming.

2. Chip Erase requires a 10 ms PROG pulse.

(2)

Programming the Flash (Continued)

6AT89C51

Flash Pr ogramm ing and V er if i ca ti on Cha rac teristics

TA = 21°C to 27°C, VCC = 5.0 ± 10%

Symbol Parameter Min Max Units

VPP(1) Programming Enable Voltage 11.5 12.5 V

IPP(1) Programming Enable Current 1.0 mA

1/tCLCL Oscillator Frequency 4 24 MHz

tAVGL Address Setup to PROG Low 48tCLCL

tGHAX Address Hold After PROG 48tCLCL

tDVGL Data Setup to PROG Low 48tCLCL

tGHDX Data Hold After PROG 48tCLCL

tEHSH P2.7 (ENABLE) High to VPP 48tCLCL

tSHGL VPP Setup to PROG Low 10 µs

tGHSL(1) VPP Hold After PROG 10 µs

tGLGH PROG Width 1 110 µs

tAVQV Address to Data Valid 48tCLCL

tELQV ENABLE Low to Data Valid 48tCLCL

tEHQV Data Float After ENABLE 0 48tCLCL

tGHBL PROG High to BUSY Low 1.0 µs

tWC Byte Write Cycle Time 2.0 ms

Note: 1. Only used in 12-volt programming mode.

P2.6

P3.6

P2.0 - P2.3

A0 - A7

ADDR.

OOOOH/0FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

4-24 MHz

A8 - A11 P0

+5V

P2.7

PGM DATA

(USE 10K

PULLUPS)

VIH

ALE

P3.7

XTAL 2 EA

RST

PSEN

XTAL 1

GND

AT89C51

Figure 4. Verifying the Flash

P2.6

P3.6

P2.0 - P2.3

A0 - A7

ADDR.

OOOOH/OFFFH

SEE FLASH

PROGRAMMING

MODES TABLE

4-24 MHz

A8 - A11 P0

+5V

P2.7

PGM

DATA

PROG

V/V

IH PP

VIH

ALE

P3.7

XTAL 2 EA

RST

PSEN

XTAL 1

GND

VCC

AT89C51

Figure 3. Programming the Flash

AT89C51

tGLGH

tAVGL

tSHGL

tDVGL tGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7

P2.0 - P2.3

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/V

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

Flash Pr ogr amming and V er ification Waveform s - Low V ol ta ge Mode

tGLGH tGHSL

tAVGL

tSHGL

tDVGL tGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7

P2.0 - P2.3

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/V

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

Flash Progr amming and V erifica ti on Wa ve for m s - Hi gh Vol tage Mode

8AT89C51

D.C. Characteristics

TA = -40°C to 85°C, VCC = 5.0 V ± 20% (unless otherwise noted)

Symbol Parameter Condition Min Max Units

VIL Inpu t Low Volt ag e (Excep t EA) -0.5 0.2 VCC-0.1 V

VIL1 Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V

VIH Inpu t High Voltage (Excep t XTAL 1, RST) 0.2 VCC+0.9 VCC+0.5 V

VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V

VOL Output Low Voltage(1)

(Ports 1,2,3) IOL = 1.6 mA 0.4 5 V

VOL1 Output Low Voltage(1)

(Port 0, ALE, PSEN) IOL = 3.2 mA 0.4 5 V

VOH Output High Voltage

(Ports 1,2,3, AL E, PSEN)

IOH = -60 µA, VCC = 5 V ± 10 % 2.4 V

IOH = -25 µA 0.75 VCC V

IOH = -10 µA 0.9 VCC V

VOH1 Outpu t High Vol ta ge

(Port 0 in External Bus Mo de )

IOH = -800 µA, VCC = 5 V ± 10% 2.4 V

IOH = -300 µA 0.75 VCC V

IOH = -80 µA 0.9 VCC V

IIL Logica l 0 Input Current

(Ports 1,2,3) VIN = 0.45 V -50 µA

ITL Logical 1 to 0 Transition

Current (Ports 1,2,3) VIN = 2 V -6 50 µA

ILI Inpu t Le akage Current

(Port 0, EA) 0.45 < VIN < VCC ±10 µA

RRST Reset Pulldown Resistor 50 300 KΩ

CIO Pin Capacitance Test F req . = 1 MHz, T A = 25°C 10 pF

ICC Power Supply Current Active Mode, 12 MHz 20 mA

Idle Mode, 12 MHz 5 mA

Power Down Mode(2) VCC = 6 V 100 µA

VCC = 3 V 40 µA

Operating Temperature...................-55°C to +125°C

Storage Temperature......................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground ................... -1.0 V to +7.0 V

Maximum Operating Voltage ............................6.6 V

DC Output Current.......................................15.0 mA

*NOTICE: Stresses beyo nd those liste d unde r “Absolu te Maxi-

mum Ratings ” may cau se permanent dama ge to th e de vi ce.

This is a stress rating only and functional operation of the

device at these or any other conditions beyond those indi-

cated in the operational sections of this specification is not

implie d. Exposure to abs olute ma xi mu m rating co nd itions

for extended periods may affect device reliability.

Absolute Ma ximum Ra ti ngs *

Notes: 1. Under steady state (non-transient) conditions, IOL

must be externally limited as follows:

Maxi mum IOL per port pin:10 mA

Maxi mum IOL per 8-bit port:

Port 0:26 mA

Ports 1, 2, 3: 1 5 mA

Maximum total IOL for all out put pi ns:7 1 mA

If IOL exceeds the test condition, VOL may exceed the

related specification. Pins are not guaranteed to sink

curre nt greater t ha n th e listed t es t co nd itions .

2. Minimum VCC for Power Down is 2 V.

AT89C51

External Program and Da ta Memory Characte ristics

Symbol Parameter 12 MHz Oscillator 16 to 24 MHz Oscillator Units

Min Max Min Max

1/tCLCL Oscillator Frequency 0 24 MHz

tLHLL ALE Pulse Width 127 2tCLCL-40 ns

tAVLL Address Valid to ALE Low 28 tCLCL-13 ns

tLLAX Address Hold After ALE Low 48 tCLCL-20 ns

tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns

tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns

tPLPH PSEN Pulse Width 205 3tCLCL-20 ns

tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-45 ns

tPXIX Input Instruction Hold After PSEN 0 0 ns

tPXIZ Input Instruction Float After PSEN 59 tCLCL-10 ns

tPXAV PSEN to Address Valid 75 tCLCL-8 ns

tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns

tPLAZ PSEN Low to Address Float 10 10 ns

tRLRH RD Pulse Width 400 6tCLCL-100 ns

tWLWH WR Pulse Width 400 6tCLCL-100 ns

tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns

tRHDX Data Hold After RD 0 0 ns

tRHDZ Data Float After RD 97 2tCLCL-28 ns

tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns

tAVDV Address to Valid Data In 585 9tCLCL-165 ns

tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns

tAVWL Address to RD or WR Low 203 4tCLCL-75 ns

tQVWX Data Valid to WR Transition 23 tCLCL-20 ns

tQVWH Data Valid to WR High 433 7tCLCL-120 ns

tWHQX Data Hold After WR 33 tCLCL-20 ns

tRLAZ RD Low to Address Float 0 0 ns

tWHLH RD or WR High to ALE High 43 123 tCLCL-20 tCLCL+25 ns

A.C. Characteristics

(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all

other outputs = 80 pF)

10 AT89C51

LHLL

LLDV

LLWL

LLAX

WHLH

AVLL

RLRH

AVDV

AVWL

RLAZ

RHDX

RLDV

RHDZ

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA IN INSTR IN

External Data Mem ory Read Cy cle

LHLL

LLIV

PLIV

LLAX

PXIZ

PLPH

PLAZ

PXAV

AVLL

LLPL

AVIV

PXIX

ALE

PSEN

PORT 0

PORT 2

A8 - A15

A0 - A7 A0 - A7

A8 - A15

INSTR IN

External Progr am Memor y Read Cycl e

AT89C51

External Cloc k Dr ive

Symbol Parameter Min Max Units

1/tCLCL Oscillator Frequency 0 24 MHz

tCLCL Clock Period 41.6 ns

tCHCX High Time 15 ns

tCLCX Low Time 15 ns

tCLCH Rise Time 20 ns

tCHCL Fall Time 20 ns

CHCX

CLCX

CLCL

CHCL

CLCH

V - 0.5V

0.45V 0.2 V - 0.1V

0.7 VCC

External Cloc k Dr ive Wave forms

LHLL

LLWL

LLAX

WHLH

AVLL

WLWH

AVWL

QVWX

QVWH

WHQX

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA OUT INSTR IN

External Data Memory Cy cle

12 AT89C51

XHDV

QVXH

XLXL

XHDX

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID VALIDVALID VALIDVALID VALIDVALID VALID

Shift Register Mode Timing Waveforms

0.45V

TEST POINTS

V - 0.5V

0.2 V + 0.9V

0.2 V - 0.1V

AC Testing Input /Out put Wa ve for ms (1)

Note: 1. AC Inputs during testing are driven at V CC - 0.5 V for a

logic 1 and 0.4 5 V for a lo gi c 0. Timing meas ure -

ments are made at VIH min. for a logi c 1 an d VIL

max. for a logic 0.

Serial Port Timing: Shift Register Mode Test Condi tions

(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)

Symbol Parameter 12 MHz Osc Variable Oscillator Units

Min Max Min Max

tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs

tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns

tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-33 ns

tXHDX Input Data Hold After Clock Rising Edge 0 0 ns

tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

LOAD+ 0.1V

Timing Reference

Points

LOAD- 0.1V

LOAD

OL+ 0.1V

OL - 0.1V

Float Wavefor ms (1)

Note: 1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs.

A por t pin be gi ns to fl oat whe n a 100 mV ch ange

from the loaded VOH/VOL leve l occu rs .

AT89C51

Ordering Information

Speed

(MHz) Power

Supply Ordering Code Package Operation Range

12 5 V ± 20% AT89C51-12AC 44A Commercial

AT89C51-12JC 44J (0°C to 70°C)

AT89C51-12PC 40P6

AT89C51-12QC 44Q

AT89C51-12AI 44A Industrial

AT89C51-12JI 44J (-40°C to 85°C)

AT89C51-12PI 40P6

AT89C51-12QI 44Q

AT89C51-12AA 44A Automotive

AT89C51-12JA 44J (-40°C to 125°C)

AT89C51-12PA 40P6

AT89C51-12QA 44Q

5 V ± 10% AT89C51-12DM 40D6 Military

AT89C51-12LM 44L (-55°C to 125°C)

AT89C51-12DM/883 40D6 Military/883C

AT89C51-12LM/883 44L Class B, Fully Compliant

(-55°C to 125°C)

16 5 V ± 20% AT89C51-16AC 44A Commercial

AT89C51-16JC 44J (0°C to 70°C)

AT89C51-16PC 40P6

AT89C51-16QC 44Q

AT89C51-16AI 44A Industrial

AT89C51-16JI 44J (-40°C to 85°C)

AT89C51-16PI 40P6

AT89C51-16QI 44Q

AT89C51-16AA 44A Automotive

AT89C51-16JA 44J (-40°C to 125°C)

AT89C51-16PA 40P6

AT89C51-16QA 44Q

20 5 V ± 20% AT89C51-20AC 44A Commercial

AT89C51-20JC 44J (0°C to 70°C)

AT89C51-20PC 40P6

AT89C51-20QC 44Q

AT89C51-20AI 44A Industrial

AT89C51-20JI 44J (-40°C to 85°C)

AT89C51-20PI 40P6

AT89C51-20QI 44Q

14 AT89C51

Ordering Information

Package Type

44A 44 Lead, Thi n Pla stic Gull Win g Qua d Flat pa ck (TQFP)

40D6 40 Lead, 0.6 00 " Wi de, Non-Wind owed, Ceramic Dual Inlin e Pac ka ge (Cerdip)

44J 44 Lead, Plasti c J-L ea de d Chi p Carrier (PLCC)

44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

40P6 40 Lead, 0.6 00" Wi de , Pla stic Dual Inlin e Pac kage (PDIP)

44Q 44 Lead, Plastic Gul l Wing Quad Flatp ack (PQFP)

Speed

(MHz) Power

Supply Ordering Code Package Operation Range

24 5 V ± 20% AT89C51-24AC 44A Commercial

AT89C51-24JC 44J (0°C to 70°C)

AT89C51-24PC 44P6

AT89C51-24QC 44Q

AT89C51-24AI 44A Industrial

AT89C51-24JI 44J (-40°C to 85°C)

AT89C51-24PI 44P6

AT89C51-24QI 44Q

AT89C51